1 /* 2 * SPDX-License-Identifier: MIT 3 * 4 * Copyright � 2003-2018 Intel Corporation 5 */ 6 7 #ifndef _INTEL_GPU_COMMANDS_H_ 8 #define _INTEL_GPU_COMMANDS_H_ 9 10 /* 11 * Instruction field definitions used by the command parser 12 */ 13 #define INSTR_CLIENT_SHIFT 29 14 #define INSTR_MI_CLIENT 0x0 15 #define INSTR_BC_CLIENT 0x2 16 #define INSTR_RC_CLIENT 0x3 17 #define INSTR_SUBCLIENT_SHIFT 27 18 #define INSTR_SUBCLIENT_MASK 0x18000000 19 #define INSTR_MEDIA_SUBCLIENT 0x2 20 #define INSTR_26_TO_24_MASK 0x7000000 21 #define INSTR_26_TO_24_SHIFT 24 22 23 /* 24 * Memory interface instructions used by the kernel 25 */ 26 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 27 /* Many MI commands use bit 22 of the header dword for GGTT vs PPGTT */ 28 #define MI_GLOBAL_GTT (1<<22) 29 30 #define MI_NOOP MI_INSTR(0, 0) 31 #define MI_USER_INTERRUPT MI_INSTR(0x02, 0) 32 #define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0) 33 #define MI_WAIT_FOR_OVERLAY_FLIP (1<<16) 34 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 35 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 36 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 37 #define MI_FLUSH MI_INSTR(0x04, 0) 38 #define MI_READ_FLUSH (1 << 0) 39 #define MI_EXE_FLUSH (1 << 1) 40 #define MI_NO_WRITE_FLUSH (1 << 2) 41 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ 42 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ 43 #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ 44 #define MI_REPORT_HEAD MI_INSTR(0x07, 0) 45 #define MI_ARB_ON_OFF MI_INSTR(0x08, 0) 46 #define MI_ARB_ENABLE (1<<0) 47 #define MI_ARB_DISABLE (0<<0) 48 #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) 49 #define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0) 50 #define MI_SUSPEND_FLUSH_EN (1<<0) 51 #define MI_SET_APPID MI_INSTR(0x0e, 0) 52 #define MI_OVERLAY_FLIP MI_INSTR(0x11, 0) 53 #define MI_OVERLAY_CONTINUE (0x0<<21) 54 #define MI_OVERLAY_ON (0x1<<21) 55 #define MI_OVERLAY_OFF (0x2<<21) 56 #define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0) 57 #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) 58 #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) 59 #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) 60 /* IVB has funny definitions for which plane to flip. */ 61 #define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19) 62 #define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19) 63 #define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19) 64 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) 65 #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) 66 #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) 67 /* SKL ones */ 68 #define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8) 69 #define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8) 70 #define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8) 71 #define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8) 72 #define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8) 73 #define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8) 74 #define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8) 75 #define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8) 76 #define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8) 77 #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ 78 #define MI_SEMAPHORE_GLOBAL_GTT (1<<22) 79 #define MI_SEMAPHORE_UPDATE (1<<21) 80 #define MI_SEMAPHORE_COMPARE (1<<20) 81 #define MI_SEMAPHORE_REGISTER (1<<18) 82 #define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */ 83 #define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */ 84 #define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */ 85 #define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */ 86 #define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */ 87 #define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */ 88 #define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */ 89 #define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */ 90 #define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */ 91 #define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */ 92 #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */ 93 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ 94 #define MI_SEMAPHORE_SYNC_INVALID (3<<16) 95 #define MI_SEMAPHORE_SYNC_MASK (3<<16) 96 #define MI_SET_CONTEXT MI_INSTR(0x18, 0) 97 #define MI_MM_SPACE_GTT (1<<8) 98 #define MI_MM_SPACE_PHYSICAL (0<<8) 99 #define MI_SAVE_EXT_STATE_EN (1<<3) 100 #define MI_RESTORE_EXT_STATE_EN (1<<2) 101 #define MI_FORCE_RESTORE (1<<1) 102 #define MI_RESTORE_INHIBIT (1<<0) 103 #define HSW_MI_RS_SAVE_STATE_EN (1<<3) 104 #define HSW_MI_RS_RESTORE_STATE_EN (1<<2) 105 #define MI_SEMAPHORE_SIGNAL MI_INSTR(0x1b, 0) /* GEN8+ */ 106 #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) 107 #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ 108 #define MI_SEMAPHORE_POLL (1<<15) 109 #define MI_SEMAPHORE_SAD_GTE_SDD (1<<12) 110 #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) 111 #define MI_STORE_DWORD_IMM_GEN4 MI_INSTR(0x20, 2) 112 #define MI_MEM_VIRTUAL (1 << 22) /* 945,g33,965 */ 113 #define MI_USE_GGTT (1 << 22) /* g4x+ */ 114 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 115 #define MI_STORE_DWORD_INDEX_SHIFT 2 116 /* 117 * Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM: 118 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw 119 * simply ignores the register load under certain conditions. 120 * - One can actually load arbitrary many arbitrary registers: Simply issue x 121 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold! 122 */ 123 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) 124 #define MI_LRI_FORCE_POSTED (1<<12) 125 #define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1) 126 #define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2) 127 #define MI_SRM_LRM_GLOBAL_GTT (1<<22) 128 #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ 129 #define MI_FLUSH_DW_STORE_INDEX (1<<21) 130 #define MI_INVALIDATE_TLB (1<<18) 131 #define MI_FLUSH_DW_OP_STOREDW (1<<14) 132 #define MI_FLUSH_DW_OP_MASK (3<<14) 133 #define MI_FLUSH_DW_NOTIFY (1<<8) 134 #define MI_INVALIDATE_BSD (1<<7) 135 #define MI_FLUSH_DW_USE_GTT (1<<2) 136 #define MI_FLUSH_DW_USE_PPGTT (0<<2) 137 #define MI_LOAD_REGISTER_MEM MI_INSTR(0x29, 1) 138 #define MI_LOAD_REGISTER_MEM_GEN8 MI_INSTR(0x29, 2) 139 #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) 140 #define MI_BATCH_NON_SECURE (1) 141 /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ 142 #define MI_BATCH_NON_SECURE_I965 (1<<8) 143 #define MI_BATCH_PPGTT_HSW (1<<8) 144 #define MI_BATCH_NON_SECURE_HSW (1<<13) 145 #define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0) 146 #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ 147 #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) 148 #define MI_BATCH_RESOURCE_STREAMER (1<<10) 149 150 /* 151 * 3D instructions used by the kernel 152 */ 153 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags)) 154 155 #define GEN9_MEDIA_POOL_STATE ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4) 156 #define GEN9_MEDIA_POOL_ENABLE (1 << 31) 157 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24)) 158 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 159 #define SC_UPDATE_SCISSOR (0x1<<1) 160 #define SC_ENABLE_MASK (0x1<<0) 161 #define SC_ENABLE (0x1<<0) 162 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16)) 163 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 164 #define SCI_YMIN_MASK (0xffff<<16) 165 #define SCI_XMIN_MASK (0xffff<<0) 166 #define SCI_YMAX_MASK (0xffff<<16) 167 #define SCI_XMAX_MASK (0xffff<<0) 168 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 169 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 170 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 171 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 172 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 173 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 174 #define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 175 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 176 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 177 178 #define COLOR_BLT_CMD (2<<29 | 0x40<<22 | (5-2)) 179 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 180 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 181 #define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5) 182 #define BLT_WRITE_A (2<<20) 183 #define BLT_WRITE_RGB (1<<20) 184 #define BLT_WRITE_RGBA (BLT_WRITE_RGB | BLT_WRITE_A) 185 #define BLT_DEPTH_8 (0<<24) 186 #define BLT_DEPTH_16_565 (1<<24) 187 #define BLT_DEPTH_16_1555 (2<<24) 188 #define BLT_DEPTH_32 (3<<24) 189 #define BLT_ROP_SRC_COPY (0xcc<<16) 190 #define BLT_ROP_COLOR_COPY (0xf0<<16) 191 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */ 192 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */ 193 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 194 #define ASYNC_FLIP (1<<22) 195 #define DISPLAY_PLANE_A (0<<20) 196 #define DISPLAY_PLANE_B (1<<20) 197 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) 198 #define PIPE_CONTROL_FLUSH_L3 (1<<27) 199 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */ 200 #define PIPE_CONTROL_MMIO_WRITE (1<<23) 201 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) 202 #define PIPE_CONTROL_CS_STALL (1<<20) 203 #define PIPE_CONTROL_TLB_INVALIDATE (1<<18) 204 #define PIPE_CONTROL_MEDIA_STATE_CLEAR (1<<16) 205 #define PIPE_CONTROL_QW_WRITE (1<<14) 206 #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) 207 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 208 #define PIPE_CONTROL_WRITE_FLUSH (1<<12) 209 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ 210 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */ 211 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */ 212 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 213 #define PIPE_CONTROL_NOTIFY (1<<8) 214 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */ 215 #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) 216 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 217 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 218 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 219 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 220 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 221 #define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */ 222 223 /* 224 * Commands used only by the command parser 225 */ 226 #define MI_SET_PREDICATE MI_INSTR(0x01, 0) 227 #define MI_ARB_CHECK MI_INSTR(0x05, 0) 228 #define MI_RS_CONTROL MI_INSTR(0x06, 0) 229 #define MI_URB_ATOMIC_ALLOC MI_INSTR(0x09, 0) 230 #define MI_PREDICATE MI_INSTR(0x0C, 0) 231 #define MI_RS_CONTEXT MI_INSTR(0x0F, 0) 232 #define MI_TOPOLOGY_FILTER MI_INSTR(0x0D, 0) 233 #define MI_LOAD_SCAN_LINES_EXCL MI_INSTR(0x13, 0) 234 #define MI_URB_CLEAR MI_INSTR(0x19, 0) 235 #define MI_UPDATE_GTT MI_INSTR(0x23, 0) 236 #define MI_CLFLUSH MI_INSTR(0x27, 0) 237 #define MI_REPORT_PERF_COUNT MI_INSTR(0x28, 0) 238 #define MI_REPORT_PERF_COUNT_GGTT (1<<0) 239 #define MI_LOAD_REGISTER_REG MI_INSTR(0x2A, 0) 240 #define MI_RS_STORE_DATA_IMM MI_INSTR(0x2B, 0) 241 #define MI_LOAD_URB_MEM MI_INSTR(0x2C, 0) 242 #define MI_STORE_URB_MEM MI_INSTR(0x2D, 0) 243 #define MI_CONDITIONAL_BATCH_BUFFER_END MI_INSTR(0x36, 0) 244 245 #define PIPELINE_SELECT ((0x3<<29)|(0x1<<27)|(0x1<<24)|(0x4<<16)) 246 #define GFX_OP_3DSTATE_VF_STATISTICS ((0x3<<29)|(0x1<<27)|(0x0<<24)|(0xB<<16)) 247 #define MEDIA_VFE_STATE ((0x3<<29)|(0x2<<27)|(0x0<<24)|(0x0<<16)) 248 #define MEDIA_VFE_STATE_MMIO_ACCESS_MASK (0x18) 249 #define GPGPU_OBJECT ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x4<<16)) 250 #define GPGPU_WALKER ((0x3<<29)|(0x2<<27)|(0x1<<24)|(0x5<<16)) 251 #define GFX_OP_3DSTATE_DX9_CONSTANTF_VS \ 252 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x39<<16)) 253 #define GFX_OP_3DSTATE_DX9_CONSTANTF_PS \ 254 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x3A<<16)) 255 #define GFX_OP_3DSTATE_SO_DECL_LIST \ 256 ((0x3<<29)|(0x3<<27)|(0x1<<24)|(0x17<<16)) 257 258 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS \ 259 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x43<<16)) 260 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS \ 261 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x44<<16)) 262 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS \ 263 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x45<<16)) 264 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS \ 265 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x46<<16)) 266 #define GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS \ 267 ((0x3<<29)|(0x3<<27)|(0x0<<24)|(0x47<<16)) 268 269 #define MFX_WAIT ((0x3<<29)|(0x1<<27)|(0x0<<16)) 270 271 #define COLOR_BLT ((0x2<<29)|(0x40<<22)) 272 #define SRC_COPY_BLT ((0x2<<29)|(0x43<<22)) 273 274 #endif /* _INTEL_GPU_COMMANDS_H_ */ 275
