1 /* SPDX-License-Identifier: ISC */
2 /*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018 The Linux Foundation. All rights reserved.
6 */
7
8 #ifndef _CE_H_
9 #define _CE_H_
10
11 #include "hif.h"
12
13 #define CE_HTT_H2T_MSG_SRC_NENTRIES 8192
14
15 /* Descriptor rings must be aligned to this boundary */
16 #define CE_DESC_RING_ALIGN 8
17 #define CE_SEND_FLAG_GATHER 0x00010000
18
19 /*
20 * Copy Engine support: low-level Target-side Copy Engine API.
21 * This is a hardware access layer used by code that understands
22 * how to use copy engines.
23 */
24
25 struct ath10k_ce_pipe;
26
27 #define CE_DESC_FLAGS_GATHER (1 << 0)
28 #define CE_DESC_FLAGS_BYTE_SWAP (1 << 1)
29 #define CE_WCN3990_DESC_FLAGS_GATHER BIT(31)
30
31 #define CE_DESC_ADDR_MASK GENMASK_ULL(34, 0)
32 #define CE_DESC_ADDR_HI_MASK GENMASK(4, 0)
33
34 /* Following desc flags are used in QCA99X0 */
35 #define CE_DESC_FLAGS_HOST_INT_DIS (1 << 2)
36 #define CE_DESC_FLAGS_TGT_INT_DIS (1 << 3)
37
38 #define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask
39 #define CE_DESC_FLAGS_META_DATA_LSB ar->hw_values->ce_desc_meta_data_lsb
40
41 #define CE_DDR_RRI_MASK GENMASK(15, 0)
42 #define CE_DDR_DRRI_SHIFT 16
43
44 struct ce_desc {
45 __le32 addr;
46 __le16 nbytes;
47 __le16 flags; /* %CE_DESC_FLAGS_ */
48 };
49
50 struct ce_desc_64 {
51 __le64 addr;
52 __le16 nbytes; /* length in register map */
53 __le16 flags; /* fw_metadata_high */
54 __le32 toeplitz_hash_result;
55 };
56
57 #define CE_DESC_SIZE sizeof(struct ce_desc)
58 #define CE_DESC_SIZE_64 sizeof(struct ce_desc_64)
59
60 struct ath10k_ce_ring {
61 /* Number of entries in this ring; must be power of 2 */
62 unsigned int nentries;
63 unsigned int nentries_mask;
64
65 /*
66 * For dest ring, this is the next index to be processed
67 * by software after it was/is received into.
68 *
69 * For src ring, this is the last descriptor that was sent
70 * and completion processed by software.
71 *
72 * Regardless of src or dest ring, this is an invariant
73 * (modulo ring size):
74 * write index >= read index >= sw_index
75 */
76 unsigned int sw_index;
77 /* cached copy */
78 unsigned int write_index;
79 /*
80 * For src ring, this is the next index not yet processed by HW.
81 * This is a cached copy of the real HW index (read index), used
82 * for avoiding reading the HW index register more often than
83 * necessary.
84 * This extends the invariant:
85 * write index >= read index >= hw_index >= sw_index
86 *
87 * For dest ring, this is currently unused.
88 */
89 /* cached copy */
90 unsigned int hw_index;
91
92 /* Start of DMA-coherent area reserved for descriptors */
93 /* Host address space */
94 void *base_addr_owner_space_unaligned;
95 /* CE address space */
96 dma_addr_t base_addr_ce_space_unaligned;
97
98 /*
99 * Actual start of descriptors.
100 * Aligned to descriptor-size boundary.
101 * Points into reserved DMA-coherent area, above.
102 */
103 /* Host address space */
104 void *base_addr_owner_space;
105
106 /* CE address space */
107 dma_addr_t base_addr_ce_space;
108
109 char *shadow_base_unaligned;
110 struct ce_desc_64 *shadow_base;
111
112 /* keep last */
113 void *per_transfer_context[0];
114 };
115
116 struct ath10k_ce_pipe {
117 struct ath10k *ar;
118 unsigned int id;
119
120 unsigned int attr_flags;
121
122 u32 ctrl_addr;
123
124 void (*send_cb)(struct ath10k_ce_pipe *);
125 void (*recv_cb)(struct ath10k_ce_pipe *);
126
127 unsigned int src_sz_max;
128 struct ath10k_ce_ring *src_ring;
129 struct ath10k_ce_ring *dest_ring;
130 const struct ath10k_ce_ops *ops;
131 };
132
133 /* Copy Engine settable attributes */
134 struct ce_attr;
135
136 struct ath10k_bus_ops {
137 u32 (*read32)(struct ath10k *ar, u32 offset);
138 void (*write32)(struct ath10k *ar, u32 offset, u32 value);
139 int (*get_num_banks)(struct ath10k *ar);
140 };
141
ath10k_ce_priv(struct ath10k * ar)142 static inline struct ath10k_ce *ath10k_ce_priv(struct ath10k *ar)
143 {
144 return (struct ath10k_ce *)ar->ce_priv;
145 }
146
147 struct ath10k_ce {
148 /* protects CE info */
149 spinlock_t ce_lock;
150 const struct ath10k_bus_ops *bus_ops;
151 struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
152 u32 *vaddr_rri;
153 dma_addr_t paddr_rri;
154 };
155
156 /*==================Send====================*/
157
158 /* ath10k_ce_send flags */
159 #define CE_SEND_FLAG_BYTE_SWAP 1
160
161 /*
162 * Queue a source buffer to be sent to an anonymous destination buffer.
163 * ce - which copy engine to use
164 * buffer - address of buffer
165 * nbytes - number of bytes to send
166 * transfer_id - arbitrary ID; reflected to destination
167 * flags - CE_SEND_FLAG_* values
168 * Returns 0 on success; otherwise an error status.
169 *
170 * Note: If no flags are specified, use CE's default data swap mode.
171 *
172 * Implementation note: pushes 1 buffer to Source ring
173 */
174 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
175 void *per_transfer_send_context,
176 dma_addr_t buffer,
177 unsigned int nbytes,
178 /* 14 bits */
179 unsigned int transfer_id,
180 unsigned int flags);
181
182 int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
183 void *per_transfer_context,
184 dma_addr_t buffer,
185 unsigned int nbytes,
186 unsigned int transfer_id,
187 unsigned int flags);
188
189 void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe);
190
191 int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe);
192
193 /*==================Recv=======================*/
194
195 int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe);
196 int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx,
197 dma_addr_t paddr);
198 void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries);
199
200 /* recv flags */
201 /* Data is byte-swapped */
202 #define CE_RECV_FLAG_SWAPPED 1
203
204 /*
205 * Supply data for the next completed unprocessed receive descriptor.
206 * Pops buffer from Dest ring.
207 */
208 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
209 void **per_transfer_contextp,
210 unsigned int *nbytesp);
211 /*
212 * Supply data for the next completed unprocessed send descriptor.
213 * Pops 1 completed send buffer from Source ring.
214 */
215 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
216 void **per_transfer_contextp);
217
218 int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
219 void **per_transfer_contextp);
220
221 /*==================CE Engine Initialization=======================*/
222
223 int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
224 const struct ce_attr *attr);
225 void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id);
226 int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
227 const struct ce_attr *attr);
228 void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id);
229
230 /*==================CE Engine Shutdown=======================*/
231 /*
232 * Support clean shutdown by allowing the caller to revoke
233 * receive buffers. Target DMA must be stopped before using
234 * this API.
235 */
236 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
237 void **per_transfer_contextp,
238 dma_addr_t *bufferp);
239
240 int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state,
241 void **per_transfer_contextp,
242 unsigned int *nbytesp);
243
244 /*
245 * Support clean shutdown by allowing the caller to cancel
246 * pending sends. Target DMA must be stopped before using
247 * this API.
248 */
249 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
250 void **per_transfer_contextp,
251 dma_addr_t *bufferp,
252 unsigned int *nbytesp,
253 unsigned int *transfer_idp);
254
255 /*==================CE Interrupt Handlers====================*/
256 void ath10k_ce_per_engine_service_any(struct ath10k *ar);
257 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
258 int ath10k_ce_disable_interrupts(struct ath10k *ar);
259 void ath10k_ce_enable_interrupts(struct ath10k *ar);
260 void ath10k_ce_dump_registers(struct ath10k *ar,
261 struct ath10k_fw_crash_data *crash_data);
262 void ath10k_ce_alloc_rri(struct ath10k *ar);
263 void ath10k_ce_free_rri(struct ath10k *ar);
264
265 /* ce_attr.flags values */
266 /* Use NonSnooping PCIe accesses? */
267 #define CE_ATTR_NO_SNOOP BIT(0)
268
269 /* Byte swap data words */
270 #define CE_ATTR_BYTE_SWAP_DATA BIT(1)
271
272 /* Swizzle descriptors? */
273 #define CE_ATTR_SWIZZLE_DESCRIPTORS BIT(2)
274
275 /* no interrupt on copy completion */
276 #define CE_ATTR_DIS_INTR BIT(3)
277
278 /* no interrupt, only polling */
279 #define CE_ATTR_POLL BIT(4)
280
281 /* Attributes of an instance of a Copy Engine */
282 struct ce_attr {
283 /* CE_ATTR_* values */
284 unsigned int flags;
285
286 /* #entries in source ring - Must be a power of 2 */
287 unsigned int src_nentries;
288
289 /*
290 * Max source send size for this CE.
291 * This is also the minimum size of a destination buffer.
292 */
293 unsigned int src_sz_max;
294
295 /* #entries in destination ring - Must be a power of 2 */
296 unsigned int dest_nentries;
297
298 void (*send_cb)(struct ath10k_ce_pipe *);
299 void (*recv_cb)(struct ath10k_ce_pipe *);
300 };
301
302 struct ath10k_ce_ops {
303 struct ath10k_ce_ring *(*ce_alloc_src_ring)(struct ath10k *ar,
304 u32 ce_id,
305 const struct ce_attr *attr);
306 struct ath10k_ce_ring *(*ce_alloc_dst_ring)(struct ath10k *ar,
307 u32 ce_id,
308 const struct ce_attr *attr);
309 int (*ce_rx_post_buf)(struct ath10k_ce_pipe *pipe, void *ctx,
310 dma_addr_t paddr);
311 int (*ce_completed_recv_next_nolock)(struct ath10k_ce_pipe *ce_state,
312 void **per_transfer_contextp,
313 u32 *nbytesp);
314 int (*ce_revoke_recv_next)(struct ath10k_ce_pipe *ce_state,
315 void **per_transfer_contextp,
316 dma_addr_t *nbytesp);
317 void (*ce_extract_desc_data)(struct ath10k *ar,
318 struct ath10k_ce_ring *src_ring,
319 u32 sw_index, dma_addr_t *bufferp,
320 u32 *nbytesp, u32 *transfer_idp);
321 void (*ce_free_pipe)(struct ath10k *ar, int ce_id);
322 int (*ce_send_nolock)(struct ath10k_ce_pipe *pipe,
323 void *per_transfer_context,
324 dma_addr_t buffer, u32 nbytes,
325 u32 transfer_id, u32 flags);
326 void (*ce_set_src_ring_base_addr_hi)(struct ath10k *ar,
327 u32 ce_ctrl_addr,
328 u64 addr);
329 void (*ce_set_dest_ring_base_addr_hi)(struct ath10k *ar,
330 u32 ce_ctrl_addr,
331 u64 addr);
332 int (*ce_completed_send_next_nolock)(struct ath10k_ce_pipe *ce_state,
333 void **per_transfer_contextp);
334 };
335
ath10k_ce_base_address(struct ath10k * ar,unsigned int ce_id)336 static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
337 {
338 return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
339 }
340
341 #define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) (((COPY_ENGINE_BASE_ADDRESS) \
342 - CE0_BASE_ADDRESS) / (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
343
344 #define CE_SRC_RING_TO_DESC(baddr, idx) \
345 (&(((struct ce_desc *)baddr)[idx]))
346
347 #define CE_DEST_RING_TO_DESC(baddr, idx) \
348 (&(((struct ce_desc *)baddr)[idx]))
349
350 #define CE_SRC_RING_TO_DESC_64(baddr, idx) \
351 (&(((struct ce_desc_64 *)baddr)[idx]))
352
353 #define CE_DEST_RING_TO_DESC_64(baddr, idx) \
354 (&(((struct ce_desc_64 *)baddr)[idx]))
355
356 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
357 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
358 (((int)(toidx) - (int)(fromidx)) & (nentries_mask))
359
360 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
361 #define CE_RING_IDX_ADD(nentries_mask, idx, num) \
362 (((idx) + (num)) & (nentries_mask))
363
364 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
365 ar->regs->ce_wrap_intr_sum_host_msi_lsb
366 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
367 ar->regs->ce_wrap_intr_sum_host_msi_mask
368 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
369 (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
370 CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
371 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
372 #define CE_INTERRUPT_SUMMARY (GENMASK(CE_COUNT_MAX - 1, 0))
373
ath10k_ce_interrupt_summary(struct ath10k * ar)374 static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar)
375 {
376 struct ath10k_ce *ce = ath10k_ce_priv(ar);
377
378 if (!ar->hw_params.per_ce_irq)
379 return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
380 ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
381 CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
382 else
383 return CE_INTERRUPT_SUMMARY;
384 }
385
386 /* Host software's Copy Engine configuration. */
387 #define CE_ATTR_FLAGS 0
388
389 /*
390 * Configuration information for a Copy Engine pipe.
391 * Passed from Host to Target during startup (one per CE).
392 *
393 * NOTE: Structure is shared between Host software and Target firmware!
394 */
395 struct ce_pipe_config {
396 __le32 pipenum;
397 __le32 pipedir;
398 __le32 nentries;
399 __le32 nbytes_max;
400 __le32 flags;
401 __le32 reserved;
402 };
403
404 /*
405 * Directions for interconnect pipe configuration.
406 * These definitions may be used during configuration and are shared
407 * between Host and Target.
408 *
409 * Pipe Directions are relative to the Host, so PIPEDIR_IN means
410 * "coming IN over air through Target to Host" as with a WiFi Rx operation.
411 * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
412 * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
413 * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
414 * over the interconnect.
415 */
416 #define PIPEDIR_NONE 0
417 #define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
418 #define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
419 #define PIPEDIR_INOUT 3 /* bidirectional */
420
421 /* Establish a mapping between a service/direction and a pipe. */
422 struct service_to_pipe {
423 __le32 service_id;
424 __le32 pipedir;
425 __le32 pipenum;
426 };
427
428 #endif /* _CE_H_ */
429
