1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Please try to maintain the following order within this file unless it makes
24 * sense to do otherwise. From top to bottom:
25 * 1. typedefs
26 * 2. #defines, and macros
27 * 3. structure definitions
28 * 4. function prototypes
29 *
30 * Within each section, please try to order by generation in ascending order,
31 * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
32 */
33
34 #ifndef __I915_GEM_GTT_H__
35 #define __I915_GEM_GTT_H__
36
37 #include <linux/io-mapping.h>
38 #include <linux/mm.h>
39 #include <linux/pagevec.h>
40
41 #include "i915_request.h"
42 #include "i915_selftest.h"
43 #include "i915_timeline.h"
44
45 #define I915_GTT_PAGE_SIZE_4K BIT(12)
46 #define I915_GTT_PAGE_SIZE_64K BIT(16)
47 #define I915_GTT_PAGE_SIZE_2M BIT(21)
48
49 #define I915_GTT_PAGE_SIZE I915_GTT_PAGE_SIZE_4K
50 #define I915_GTT_MAX_PAGE_SIZE I915_GTT_PAGE_SIZE_2M
51
52 #define I915_GTT_MIN_ALIGNMENT I915_GTT_PAGE_SIZE
53
54 #define I915_FENCE_REG_NONE -1
55 #define I915_MAX_NUM_FENCES 32
56 /* 32 fences + sign bit for FENCE_REG_NONE */
57 #define I915_MAX_NUM_FENCE_BITS 6
58
59 struct drm_i915_file_private;
60 struct drm_i915_fence_reg;
61 struct i915_vma;
62
63 typedef u32 gen6_pte_t;
64 typedef u64 gen8_pte_t;
65 typedef u64 gen8_pde_t;
66 typedef u64 gen8_ppgtt_pdpe_t;
67 typedef u64 gen8_ppgtt_pml4e_t;
68
69 #define ggtt_total_entries(ggtt) ((ggtt)->vm.total >> PAGE_SHIFT)
70
71 /* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
72 #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
73 #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
74 #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
75 #define GEN6_PTE_CACHE_LLC (2 << 1)
76 #define GEN6_PTE_UNCACHED (1 << 1)
77 #define GEN6_PTE_VALID (1 << 0)
78
79 #define I915_PTES(pte_len) ((unsigned int)(PAGE_SIZE / (pte_len)))
80 #define I915_PTE_MASK(pte_len) (I915_PTES(pte_len) - 1)
81 #define I915_PDES 512
82 #define I915_PDE_MASK (I915_PDES - 1)
83 #define NUM_PTE(pde_shift) (1 << (pde_shift - PAGE_SHIFT))
84
85 #define GEN6_PTES I915_PTES(sizeof(gen6_pte_t))
86 #define GEN6_PD_SIZE (I915_PDES * PAGE_SIZE)
87 #define GEN6_PD_ALIGN (PAGE_SIZE * 16)
88 #define GEN6_PDE_SHIFT 22
89 #define GEN6_PDE_VALID (1 << 0)
90
91 #define GEN7_PTE_CACHE_L3_LLC (3 << 1)
92
93 #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
94 #define BYT_PTE_WRITEABLE (1 << 1)
95
96 /* Cacheability Control is a 4-bit value. The low three bits are stored in bits
97 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
98 */
99 #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
100 (((bits) & 0x8) << (11 - 3)))
101 #define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
102 #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
103 #define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
104 #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
105 #define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
106 #define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
107 #define HSW_PTE_UNCACHED (0)
108 #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
109 #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
110
111 /* GEN8 32b style address is defined as a 3 level page table:
112 * 31:30 | 29:21 | 20:12 | 11:0
113 * PDPE | PDE | PTE | offset
114 * The difference as compared to normal x86 3 level page table is the PDPEs are
115 * programmed via register.
116 */
117 #define GEN8_3LVL_PDPES 4
118 #define GEN8_PDE_SHIFT 21
119 #define GEN8_PDE_MASK 0x1ff
120 #define GEN8_PTE_SHIFT 12
121 #define GEN8_PTE_MASK 0x1ff
122 #define GEN8_PTES I915_PTES(sizeof(gen8_pte_t))
123
124 /* GEN8 48b style address is defined as a 4 level page table:
125 * 47:39 | 38:30 | 29:21 | 20:12 | 11:0
126 * PML4E | PDPE | PDE | PTE | offset
127 */
128 #define GEN8_PML4ES_PER_PML4 512
129 #define GEN8_PML4E_SHIFT 39
130 #define GEN8_PML4E_MASK (GEN8_PML4ES_PER_PML4 - 1)
131 #define GEN8_PDPE_SHIFT 30
132 /* NB: GEN8_PDPE_MASK is untrue for 32b platforms, but it has no impact on 32b page
133 * tables */
134 #define GEN8_PDPE_MASK 0x1ff
135
136 #define PPAT_UNCACHED (_PAGE_PWT | _PAGE_PCD)
137 #define PPAT_CACHED_PDE 0 /* WB LLC */
138 #define PPAT_CACHED _PAGE_PAT /* WB LLCeLLC */
139 #define PPAT_DISPLAY_ELLC _PAGE_PCD /* WT eLLC */
140
141 #define CHV_PPAT_SNOOP (1<<6)
142 #define GEN8_PPAT_AGE(x) ((x)<<4)
143 #define GEN8_PPAT_LLCeLLC (3<<2)
144 #define GEN8_PPAT_LLCELLC (2<<2)
145 #define GEN8_PPAT_LLC (1<<2)
146 #define GEN8_PPAT_WB (3<<0)
147 #define GEN8_PPAT_WT (2<<0)
148 #define GEN8_PPAT_WC (1<<0)
149 #define GEN8_PPAT_UC (0<<0)
150 #define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
151 #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8))
152
153 #define GEN8_PPAT_GET_CA(x) ((x) & 3)
154 #define GEN8_PPAT_GET_TC(x) ((x) & (3 << 2))
155 #define GEN8_PPAT_GET_AGE(x) ((x) & (3 << 4))
156 #define CHV_PPAT_GET_SNOOP(x) ((x) & (1 << 6))
157
158 #define GEN8_PDE_IPS_64K BIT(11)
159 #define GEN8_PDE_PS_2M BIT(7)
160
161 struct sg_table;
162
163 struct intel_rotation_info {
164 struct intel_rotation_plane_info {
165 /* tiles */
166 unsigned int width, height, stride, offset;
167 } plane[2];
168 } __packed;
169
assert_intel_rotation_info_is_packed(void)170 static inline void assert_intel_rotation_info_is_packed(void)
171 {
172 BUILD_BUG_ON(sizeof(struct intel_rotation_info) != 8*sizeof(unsigned int));
173 }
174
175 struct intel_partial_info {
176 u64 offset;
177 unsigned int size;
178 } __packed;
179
assert_intel_partial_info_is_packed(void)180 static inline void assert_intel_partial_info_is_packed(void)
181 {
182 BUILD_BUG_ON(sizeof(struct intel_partial_info) != sizeof(u64) + sizeof(unsigned int));
183 }
184
185 enum i915_ggtt_view_type {
186 I915_GGTT_VIEW_NORMAL = 0,
187 I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
188 I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
189 };
190
assert_i915_ggtt_view_type_is_unique(void)191 static inline void assert_i915_ggtt_view_type_is_unique(void)
192 {
193 /* As we encode the size of each branch inside the union into its type,
194 * we have to be careful that each branch has a unique size.
195 */
196 switch ((enum i915_ggtt_view_type)0) {
197 case I915_GGTT_VIEW_NORMAL:
198 case I915_GGTT_VIEW_PARTIAL:
199 case I915_GGTT_VIEW_ROTATED:
200 /* gcc complains if these are identical cases */
201 break;
202 }
203 }
204
205 struct i915_ggtt_view {
206 enum i915_ggtt_view_type type;
207 union {
208 /* Members need to contain no holes/padding */
209 struct intel_partial_info partial;
210 struct intel_rotation_info rotated;
211 };
212 };
213
214 enum i915_cache_level;
215
216 struct i915_vma;
217
218 struct i915_page_dma {
219 struct page *page;
220 int order;
221 union {
222 dma_addr_t daddr;
223
224 /* For gen6/gen7 only. This is the offset in the GGTT
225 * where the page directory entries for PPGTT begin
226 */
227 u32 ggtt_offset;
228 };
229 };
230
231 #define px_base(px) (&(px)->base)
232 #define px_page(px) (px_base(px)->page)
233 #define px_dma(px) (px_base(px)->daddr)
234
235 struct i915_page_table {
236 struct i915_page_dma base;
237 unsigned int used_ptes;
238 };
239
240 struct i915_page_directory {
241 struct i915_page_dma base;
242
243 struct i915_page_table *page_table[I915_PDES]; /* PDEs */
244 unsigned int used_pdes;
245 };
246
247 struct i915_page_directory_pointer {
248 struct i915_page_dma base;
249 struct i915_page_directory **page_directory;
250 unsigned int used_pdpes;
251 };
252
253 struct i915_pml4 {
254 struct i915_page_dma base;
255 struct i915_page_directory_pointer *pdps[GEN8_PML4ES_PER_PML4];
256 };
257
258 struct i915_vma_ops {
259 /* Map an object into an address space with the given cache flags. */
260 int (*bind_vma)(struct i915_vma *vma,
261 enum i915_cache_level cache_level,
262 u32 flags);
263 /*
264 * Unmap an object from an address space. This usually consists of
265 * setting the valid PTE entries to a reserved scratch page.
266 */
267 void (*unbind_vma)(struct i915_vma *vma);
268
269 int (*set_pages)(struct i915_vma *vma);
270 void (*clear_pages)(struct i915_vma *vma);
271 };
272
273 struct pagestash {
274 spinlock_t lock;
275 struct pagevec pvec;
276 };
277
278 struct i915_address_space {
279 struct drm_mm mm;
280 struct drm_i915_private *i915;
281 struct device *dma;
282 /* Every address space belongs to a struct file - except for the global
283 * GTT that is owned by the driver (and so @file is set to NULL). In
284 * principle, no information should leak from one context to another
285 * (or between files/processes etc) unless explicitly shared by the
286 * owner. Tracking the owner is important in order to free up per-file
287 * objects along with the file, to aide resource tracking, and to
288 * assign blame.
289 */
290 struct drm_i915_file_private *file;
291 u64 total; /* size addr space maps (ex. 2GB for ggtt) */
292 u64 reserved; /* size addr space reserved */
293
294 bool closed;
295
296 struct mutex mutex; /* protects vma and our lists */
297
298 struct i915_page_dma scratch_page;
299 struct i915_page_table *scratch_pt;
300 struct i915_page_directory *scratch_pd;
301 struct i915_page_directory_pointer *scratch_pdp; /* GEN8+ & 48b PPGTT */
302
303 /**
304 * List of objects currently involved in rendering.
305 *
306 * Includes buffers having the contents of their GPU caches
307 * flushed, not necessarily primitives. last_read_req
308 * represents when the rendering involved will be completed.
309 *
310 * A reference is held on the buffer while on this list.
311 */
312 struct list_head active_list;
313
314 /**
315 * LRU list of objects which are not in the ringbuffer and
316 * are ready to unbind, but are still in the GTT.
317 *
318 * last_read_req is NULL while an object is in this list.
319 *
320 * A reference is not held on the buffer while on this list,
321 * as merely being GTT-bound shouldn't prevent its being
322 * freed, and we'll pull it off the list in the free path.
323 */
324 struct list_head inactive_list;
325
326 /**
327 * List of vma that have been unbound.
328 *
329 * A reference is not held on the buffer while on this list.
330 */
331 struct list_head unbound_list;
332
333 struct pagestash free_pages;
334
335 /* Some systems require uncached updates of the page directories */
336 bool pt_kmap_wc:1;
337
338 /* Some systems support read-only mappings for GGTT and/or PPGTT */
339 bool has_read_only:1;
340
341 /* FIXME: Need a more generic return type */
342 gen6_pte_t (*pte_encode)(dma_addr_t addr,
343 enum i915_cache_level level,
344 u32 flags); /* Create a valid PTE */
345 /* flags for pte_encode */
346 #define PTE_READ_ONLY (1<<0)
347 int (*allocate_va_range)(struct i915_address_space *vm,
348 u64 start, u64 length);
349 void (*clear_range)(struct i915_address_space *vm,
350 u64 start, u64 length);
351 void (*insert_page)(struct i915_address_space *vm,
352 dma_addr_t addr,
353 u64 offset,
354 enum i915_cache_level cache_level,
355 u32 flags);
356 void (*insert_entries)(struct i915_address_space *vm,
357 struct i915_vma *vma,
358 enum i915_cache_level cache_level,
359 u32 flags);
360 void (*cleanup)(struct i915_address_space *vm);
361
362 struct i915_vma_ops vma_ops;
363
364 I915_SELFTEST_DECLARE(struct fault_attr fault_attr);
365 I915_SELFTEST_DECLARE(bool scrub_64K);
366 };
367
368 #define i915_is_ggtt(V) (!(V)->file)
369
370 static inline bool
i915_vm_is_48bit(const struct i915_address_space * vm)371 i915_vm_is_48bit(const struct i915_address_space *vm)
372 {
373 return (vm->total - 1) >> 32;
374 }
375
376 static inline bool
i915_vm_has_scratch_64K(struct i915_address_space * vm)377 i915_vm_has_scratch_64K(struct i915_address_space *vm)
378 {
379 return vm->scratch_page.order == get_order(I915_GTT_PAGE_SIZE_64K);
380 }
381
382 /* The Graphics Translation Table is the way in which GEN hardware translates a
383 * Graphics Virtual Address into a Physical Address. In addition to the normal
384 * collateral associated with any va->pa translations GEN hardware also has a
385 * portion of the GTT which can be mapped by the CPU and remain both coherent
386 * and correct (in cases like swizzling). That region is referred to as GMADR in
387 * the spec.
388 */
389 struct i915_ggtt {
390 struct i915_address_space vm;
391
392 struct io_mapping iomap; /* Mapping to our CPU mappable region */
393 struct resource gmadr; /* GMADR resource */
394 resource_size_t mappable_end; /* End offset that we can CPU map */
395
396 /** "Graphics Stolen Memory" holds the global PTEs */
397 void __iomem *gsm;
398 void (*invalidate)(struct drm_i915_private *dev_priv);
399
400 bool do_idle_maps;
401
402 int mtrr;
403
404 struct drm_mm_node error_capture;
405 };
406
407 struct i915_hw_ppgtt {
408 struct i915_address_space vm;
409 struct kref ref;
410
411 unsigned long pd_dirty_rings;
412 union {
413 struct i915_pml4 pml4; /* GEN8+ & 48b PPGTT */
414 struct i915_page_directory_pointer pdp; /* GEN8+ */
415 struct i915_page_directory pd; /* GEN6-7 */
416 };
417
418 void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
419 };
420
421 struct gen6_hw_ppgtt {
422 struct i915_hw_ppgtt base;
423
424 struct i915_vma *vma;
425 gen6_pte_t __iomem *pd_addr;
426 gen6_pte_t scratch_pte;
427
428 unsigned int pin_count;
429 bool scan_for_unused_pt;
430 };
431
432 #define __to_gen6_ppgtt(base) container_of(base, struct gen6_hw_ppgtt, base)
433
to_gen6_ppgtt(struct i915_hw_ppgtt * base)434 static inline struct gen6_hw_ppgtt *to_gen6_ppgtt(struct i915_hw_ppgtt *base)
435 {
436 BUILD_BUG_ON(offsetof(struct gen6_hw_ppgtt, base));
437 return __to_gen6_ppgtt(base);
438 }
439
440 /*
441 * gen6_for_each_pde() iterates over every pde from start until start+length.
442 * If start and start+length are not perfectly divisible, the macro will round
443 * down and up as needed. Start=0 and length=2G effectively iterates over
444 * every PDE in the system. The macro modifies ALL its parameters except 'pd',
445 * so each of the other parameters should preferably be a simple variable, or
446 * at most an lvalue with no side-effects!
447 */
448 #define gen6_for_each_pde(pt, pd, start, length, iter) \
449 for (iter = gen6_pde_index(start); \
450 length > 0 && iter < I915_PDES && \
451 (pt = (pd)->page_table[iter], true); \
452 ({ u32 temp = ALIGN(start+1, 1 << GEN6_PDE_SHIFT); \
453 temp = min(temp - start, length); \
454 start += temp, length -= temp; }), ++iter)
455
456 #define gen6_for_all_pdes(pt, pd, iter) \
457 for (iter = 0; \
458 iter < I915_PDES && \
459 (pt = (pd)->page_table[iter], true); \
460 ++iter)
461
i915_pte_index(u64 address,unsigned int pde_shift)462 static inline u32 i915_pte_index(u64 address, unsigned int pde_shift)
463 {
464 const u32 mask = NUM_PTE(pde_shift) - 1;
465
466 return (address >> PAGE_SHIFT) & mask;
467 }
468
469 /* Helper to counts the number of PTEs within the given length. This count
470 * does not cross a page table boundary, so the max value would be
471 * GEN6_PTES for GEN6, and GEN8_PTES for GEN8.
472 */
i915_pte_count(u64 addr,u64 length,unsigned int pde_shift)473 static inline u32 i915_pte_count(u64 addr, u64 length, unsigned int pde_shift)
474 {
475 const u64 mask = ~((1ULL << pde_shift) - 1);
476 u64 end;
477
478 GEM_BUG_ON(length == 0);
479 GEM_BUG_ON(offset_in_page(addr | length));
480
481 end = addr + length;
482
483 if ((addr & mask) != (end & mask))
484 return NUM_PTE(pde_shift) - i915_pte_index(addr, pde_shift);
485
486 return i915_pte_index(end, pde_shift) - i915_pte_index(addr, pde_shift);
487 }
488
i915_pde_index(u64 addr,u32 shift)489 static inline u32 i915_pde_index(u64 addr, u32 shift)
490 {
491 return (addr >> shift) & I915_PDE_MASK;
492 }
493
gen6_pte_index(u32 addr)494 static inline u32 gen6_pte_index(u32 addr)
495 {
496 return i915_pte_index(addr, GEN6_PDE_SHIFT);
497 }
498
gen6_pte_count(u32 addr,u32 length)499 static inline u32 gen6_pte_count(u32 addr, u32 length)
500 {
501 return i915_pte_count(addr, length, GEN6_PDE_SHIFT);
502 }
503
gen6_pde_index(u32 addr)504 static inline u32 gen6_pde_index(u32 addr)
505 {
506 return i915_pde_index(addr, GEN6_PDE_SHIFT);
507 }
508
509 static inline unsigned int
i915_pdpes_per_pdp(const struct i915_address_space * vm)510 i915_pdpes_per_pdp(const struct i915_address_space *vm)
511 {
512 if (i915_vm_is_48bit(vm))
513 return GEN8_PML4ES_PER_PML4;
514
515 return GEN8_3LVL_PDPES;
516 }
517
518 /* Equivalent to the gen6 version, For each pde iterates over every pde
519 * between from start until start + length. On gen8+ it simply iterates
520 * over every page directory entry in a page directory.
521 */
522 #define gen8_for_each_pde(pt, pd, start, length, iter) \
523 for (iter = gen8_pde_index(start); \
524 length > 0 && iter < I915_PDES && \
525 (pt = (pd)->page_table[iter], true); \
526 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDE_SHIFT); \
527 temp = min(temp - start, length); \
528 start += temp, length -= temp; }), ++iter)
529
530 #define gen8_for_each_pdpe(pd, pdp, start, length, iter) \
531 for (iter = gen8_pdpe_index(start); \
532 length > 0 && iter < i915_pdpes_per_pdp(vm) && \
533 (pd = (pdp)->page_directory[iter], true); \
534 ({ u64 temp = ALIGN(start+1, 1 << GEN8_PDPE_SHIFT); \
535 temp = min(temp - start, length); \
536 start += temp, length -= temp; }), ++iter)
537
538 #define gen8_for_each_pml4e(pdp, pml4, start, length, iter) \
539 for (iter = gen8_pml4e_index(start); \
540 length > 0 && iter < GEN8_PML4ES_PER_PML4 && \
541 (pdp = (pml4)->pdps[iter], true); \
542 ({ u64 temp = ALIGN(start+1, 1ULL << GEN8_PML4E_SHIFT); \
543 temp = min(temp - start, length); \
544 start += temp, length -= temp; }), ++iter)
545
gen8_pte_index(u64 address)546 static inline u32 gen8_pte_index(u64 address)
547 {
548 return i915_pte_index(address, GEN8_PDE_SHIFT);
549 }
550
gen8_pde_index(u64 address)551 static inline u32 gen8_pde_index(u64 address)
552 {
553 return i915_pde_index(address, GEN8_PDE_SHIFT);
554 }
555
gen8_pdpe_index(u64 address)556 static inline u32 gen8_pdpe_index(u64 address)
557 {
558 return (address >> GEN8_PDPE_SHIFT) & GEN8_PDPE_MASK;
559 }
560
gen8_pml4e_index(u64 address)561 static inline u32 gen8_pml4e_index(u64 address)
562 {
563 return (address >> GEN8_PML4E_SHIFT) & GEN8_PML4E_MASK;
564 }
565
gen8_pte_count(u64 address,u64 length)566 static inline u64 gen8_pte_count(u64 address, u64 length)
567 {
568 return i915_pte_count(address, length, GEN8_PDE_SHIFT);
569 }
570
571 static inline dma_addr_t
i915_page_dir_dma_addr(const struct i915_hw_ppgtt * ppgtt,const unsigned n)572 i915_page_dir_dma_addr(const struct i915_hw_ppgtt *ppgtt, const unsigned n)
573 {
574 return px_dma(ppgtt->pdp.page_directory[n]);
575 }
576
577 static inline struct i915_ggtt *
i915_vm_to_ggtt(struct i915_address_space * vm)578 i915_vm_to_ggtt(struct i915_address_space *vm)
579 {
580 GEM_BUG_ON(!i915_is_ggtt(vm));
581 return container_of(vm, struct i915_ggtt, vm);
582 }
583
584 #define INTEL_MAX_PPAT_ENTRIES 8
585 #define INTEL_PPAT_PERFECT_MATCH (~0U)
586
587 struct intel_ppat;
588
589 struct intel_ppat_entry {
590 struct intel_ppat *ppat;
591 struct kref ref;
592 u8 value;
593 };
594
595 struct intel_ppat {
596 struct intel_ppat_entry entries[INTEL_MAX_PPAT_ENTRIES];
597 DECLARE_BITMAP(used, INTEL_MAX_PPAT_ENTRIES);
598 DECLARE_BITMAP(dirty, INTEL_MAX_PPAT_ENTRIES);
599 unsigned int max_entries;
600 u8 clear_value;
601 /*
602 * Return a score to show how two PPAT values match,
603 * a INTEL_PPAT_PERFECT_MATCH indicates a perfect match
604 */
605 unsigned int (*match)(u8 src, u8 dst);
606 void (*update_hw)(struct drm_i915_private *i915);
607
608 struct drm_i915_private *i915;
609 };
610
611 const struct intel_ppat_entry *
612 intel_ppat_get(struct drm_i915_private *i915, u8 value);
613 void intel_ppat_put(const struct intel_ppat_entry *entry);
614
615 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915);
616 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915);
617
618 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
619 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
620 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
621 void i915_ggtt_enable_guc(struct drm_i915_private *i915);
622 void i915_ggtt_disable_guc(struct drm_i915_private *i915);
623 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv);
624 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv);
625
626 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv);
627 void i915_ppgtt_release(struct kref *kref);
628 struct i915_hw_ppgtt *i915_ppgtt_create(struct drm_i915_private *dev_priv,
629 struct drm_i915_file_private *fpriv);
630 void i915_ppgtt_close(struct i915_address_space *vm);
i915_ppgtt_get(struct i915_hw_ppgtt * ppgtt)631 static inline void i915_ppgtt_get(struct i915_hw_ppgtt *ppgtt)
632 {
633 if (ppgtt)
634 kref_get(&ppgtt->ref);
635 }
i915_ppgtt_put(struct i915_hw_ppgtt * ppgtt)636 static inline void i915_ppgtt_put(struct i915_hw_ppgtt *ppgtt)
637 {
638 if (ppgtt)
639 kref_put(&ppgtt->ref, i915_ppgtt_release);
640 }
641
642 int gen6_ppgtt_pin(struct i915_hw_ppgtt *base);
643 void gen6_ppgtt_unpin(struct i915_hw_ppgtt *base);
644
645 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv);
646 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv);
647 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv);
648
649 int __must_check i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
650 struct sg_table *pages);
651 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
652 struct sg_table *pages);
653
654 int i915_gem_gtt_reserve(struct i915_address_space *vm,
655 struct drm_mm_node *node,
656 u64 size, u64 offset, unsigned long color,
657 unsigned int flags);
658
659 int i915_gem_gtt_insert(struct i915_address_space *vm,
660 struct drm_mm_node *node,
661 u64 size, u64 alignment, unsigned long color,
662 u64 start, u64 end, unsigned int flags);
663
664 /* Flags used by pin/bind&friends. */
665 #define PIN_NONBLOCK BIT(0)
666 #define PIN_MAPPABLE BIT(1)
667 #define PIN_ZONE_4G BIT(2)
668 #define PIN_NONFAULT BIT(3)
669 #define PIN_NOEVICT BIT(4)
670
671 #define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */
672 #define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */
673 #define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */
674 #define PIN_UPDATE BIT(8)
675
676 #define PIN_HIGH BIT(9)
677 #define PIN_OFFSET_BIAS BIT(10)
678 #define PIN_OFFSET_FIXED BIT(11)
679 #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE)
680
681 #endif
682
