1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2016 Realtek Corporation. 5 * 6 * Contact Information: 7 * wlanfae <wlanfae@realtek.com> 8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 9 * Hsinchu 300, Taiwan. 10 * 11 * Larry Finger <Larry.Finger@lwfinger.net> 12 * 13 *****************************************************************************/ 14 15 #ifndef __ODM_INTERFACE_H__ 16 #define __ODM_INTERFACE_H__ 17 18 #define INTERFACE_VERSION "1.1" /*2015.07.29 YuChen*/ 19 20 /* 21 * =========== Constant/Structure/Enum/... Define 22 */ 23 24 /* 25 * =========== Macro Define 26 */ 27 28 #define _reg_all(_name) ODM_##_name 29 #define _reg_ic(_name, _ic) ODM_##_name##_ic 30 #define _bit_all(_name) BIT_##_name 31 #define _bit_ic(_name, _ic) BIT_##_name##_ic 32 33 /* _cat: implemented by Token-Pasting Operator. */ 34 35 /*=================================== 36 * 37 * #define ODM_REG_DIG_11N 0xC50 38 * #define ODM_REG_DIG_11AC 0xDDD 39 * 40 * ODM_REG(DIG,_pdm_odm) 41 * =================================== 42 */ 43 44 #define _reg_11N(_name) ODM_REG_##_name##_11N 45 #define _reg_11AC(_name) ODM_REG_##_name##_11AC 46 #define _bit_11N(_name) ODM_BIT_##_name##_11N 47 #define _bit_11AC(_name) ODM_BIT_##_name##_11AC 48 49 #define _cat(_name, _ic_type, _func) \ 50 (((_ic_type) & ODM_IC_11N_SERIES) ? _func##_11N(_name) : \ 51 _func##_11AC(_name)) 52 53 /* _name: name of register or bit. 54 * Example: "ODM_REG(R_A_AGC_CORE1, dm)" 55 * gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", 56 * depends on support_ic_type. 57 */ 58 #define ODM_REG(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _reg) 59 #define ODM_BIT(_name, _pdm_odm) _cat(_name, _pdm_odm->support_ic_type, _bit) 60 enum phydm_h2c_cmd { 61 PHYDM_H2C_TXBF = 0x41, 62 ODM_H2C_RSSI_REPORT = 0x42, 63 ODM_H2C_IQ_CALIBRATION = 0x45, 64 ODM_H2C_RA_PARA_ADJUST = 0x47, 65 PHYDM_H2C_DYNAMIC_TX_PATH = 0x48, 66 PHYDM_H2C_FW_TRACE_EN = 0x49, 67 ODM_H2C_WIFI_CALIBRATION = 0x6d, 68 PHYDM_H2C_MU = 0x4a, 69 ODM_MAX_H2CCMD 70 }; 71 72 enum phydm_c2h_evt { 73 PHYDM_C2H_DBG = 0, 74 PHYDM_C2H_LB = 1, 75 PHYDM_C2H_XBF = 2, 76 PHYDM_C2H_TX_REPORT = 3, 77 PHYDM_C2H_INFO = 9, 78 PHYDM_C2H_BT_MP = 11, 79 PHYDM_C2H_RA_RPT = 12, 80 PHYDM_C2H_RA_PARA_RPT = 14, 81 PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, 82 PHYDM_C2H_IQK_FINISH = 17, /*0x11*/ 83 PHYDM_C2H_DBG_CODE = 0xFE, 84 PHYDM_C2H_EXTEND = 0xFF, 85 }; 86 87 enum phydm_extend_c2h_evt { 88 PHYDM_EXTEND_C2H_DBG_PRINT = 0 89 90 }; 91 92 /* 93 * =========== Extern Variable ??? It should be forbidden. 94 */ 95 96 /* 97 * =========== EXtern Function Prototype 98 */ 99 100 u8 odm_read_1byte(struct phy_dm_struct *dm, u32 reg_addr); 101 102 u16 odm_read_2byte(struct phy_dm_struct *dm, u32 reg_addr); 103 104 u32 odm_read_4byte(struct phy_dm_struct *dm, u32 reg_addr); 105 106 void odm_write_1byte(struct phy_dm_struct *dm, u32 reg_addr, u8 data); 107 108 void odm_write_2byte(struct phy_dm_struct *dm, u32 reg_addr, u16 data); 109 110 void odm_write_4byte(struct phy_dm_struct *dm, u32 reg_addr, u32 data); 111 112 void odm_set_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask, 113 u32 data); 114 115 u32 odm_get_mac_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask); 116 117 void odm_set_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask, 118 u32 data); 119 120 u32 odm_get_bb_reg(struct phy_dm_struct *dm, u32 reg_addr, u32 bit_mask); 121 122 void odm_set_rf_reg(struct phy_dm_struct *dm, enum odm_rf_radio_path e_rf_path, 123 u32 reg_addr, u32 bit_mask, u32 data); 124 125 u32 odm_get_rf_reg(struct phy_dm_struct *dm, enum odm_rf_radio_path e_rf_path, 126 u32 reg_addr, u32 bit_mask); 127 128 /* 129 * Memory Relative Function. 130 */ 131 void odm_allocate_memory(struct phy_dm_struct *dm, void **ptr, u32 length); 132 void odm_free_memory(struct phy_dm_struct *dm, void *ptr, u32 length); 133 134 void odm_move_memory(struct phy_dm_struct *dm, void *p_dest, void *src, 135 u32 length); 136 137 s32 odm_compare_memory(struct phy_dm_struct *dm, void *p_buf1, void *buf2, 138 u32 length); 139 140 void odm_memory_set(struct phy_dm_struct *dm, void *pbuf, s8 value, u32 length); 141 142 /* 143 * ODM MISC-spin lock relative API. 144 */ 145 void odm_acquire_spin_lock(struct phy_dm_struct *dm, 146 enum rt_spinlock_type type); 147 148 void odm_release_spin_lock(struct phy_dm_struct *dm, 149 enum rt_spinlock_type type); 150 151 /* 152 * ODM Timer relative API. 153 */ 154 void odm_stall_execution(u32 us_delay); 155 156 void ODM_delay_ms(u32 ms); 157 158 void ODM_delay_us(u32 us); 159 160 void ODM_sleep_ms(u32 ms); 161 162 void ODM_sleep_us(u32 us); 163 164 /* 165 * ODM FW relative API. 166 */ 167 void odm_fill_h2c_cmd(struct phy_dm_struct *dm, u8 element_id, u32 cmd_len, 168 u8 *cmd_buffer); 169 170 u8 phydm_c2H_content_parsing(void *dm_void, u8 c2h_cmd_id, u8 c2h_cmd_len, 171 u8 *tmp_buf); 172 173 u64 odm_get_current_time(struct phy_dm_struct *dm); 174 u64 odm_get_progressing_time(struct phy_dm_struct *dm, u64 start_time); 175 176 void odm_set_tx_power_index_by_rate_section(struct phy_dm_struct *dm, 177 u8 rf_path, u8 channel, 178 u8 rate_section); 179 180 u8 odm_get_tx_power_index(struct phy_dm_struct *dm, u8 rf_path, u8 tx_rate, 181 u8 band_width, u8 channel); 182 183 #endif /* __ODM_INTERFACE_H__ */ 184
