1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Comedi driver for NI PCI-MIO E series cards
4 *
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
7 */
8
9 /*
10 * Driver: ni_pcimio
11 * Description: National Instruments PCI-MIO-E series and M series (all boards)
12 * Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
13 * Herman Bruyninckx, Terry Barnaby
14 * Status: works
15 * Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
16 * PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014,
17 * PCI-6040E, PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E,
18 * PCI-6071E, PCI-6023E, PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E,
19 * PCI-6035E, PCI-6052E, PCI-6110, PCI-6111, PCI-6220, PXI-6220,
20 * PCI-6221, PXI-6221, PCI-6224, PXI-6224, PCI-6225, PXI-6225,
21 * PCI-6229, PXI-6229, PCI-6250, PXI-6250, PCI-6251, PXI-6251,
22 * PCIe-6251, PXIe-6251, PCI-6254, PXI-6254, PCI-6259, PXI-6259,
23 * PCIe-6259, PXIe-6259, PCI-6280, PXI-6280, PCI-6281, PXI-6281,
24 * PCI-6284, PXI-6284, PCI-6289, PXI-6289, PCI-6711, PXI-6711,
25 * PCI-6713, PXI-6713, PXI-6071E, PCI-6070E, PXI-6070E,
26 * PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
27 * PCI-6143, PXI-6143
28 * Updated: Mon, 16 Jan 2017 12:56:04 +0000
29 *
30 * These boards are almost identical to the AT-MIO E series, except that
31 * they use the PCI bus instead of ISA (i.e., AT). See the notes for the
32 * ni_atmio.o driver for additional information about these boards.
33 *
34 * Autocalibration is supported on many of the devices, using the
35 * comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
36 * M-Series boards do analog input and analog output calibration entirely
37 * in software. The software calibration corrects the analog input for
38 * offset, gain and nonlinearity. The analog outputs are corrected for
39 * offset and gain. See the comedilib documentation on
40 * comedi_get_softcal_converter() for more information.
41 *
42 * By default, the driver uses DMA to transfer analog input data to
43 * memory. When DMA is enabled, not all triggering features are
44 * supported.
45 *
46 * Digital I/O may not work on 673x.
47 *
48 * Note that the PCI-6143 is a simultaineous sampling device with 8
49 * convertors. With this board all of the convertors perform one
50 * simultaineous sample during a scan interval. The period for a scan
51 * is used for the convert time in a Comedi cmd. The convert trigger
52 * source is normally set to TRIG_NOW by default.
53 *
54 * The RTSI trigger bus is supported on these cards on subdevice 10.
55 * See the comedilib documentation for details.
56 *
57 * Information (number of channels, bits, etc.) for some devices may be
58 * incorrect. Please check this and submit a bug if there are problems
59 * for your device.
60 *
61 * SCXI is probably broken for m-series boards.
62 *
63 * Bugs:
64 * - When DMA is enabled, COMEDI_EV_CONVERT does not work correctly.
65 */
66
67 /*
68 * The PCI-MIO E series driver was originally written by
69 * Tomasz Motylewski <...>, and ported to comedi by ds.
70 *
71 * References:
72 * 341079b.pdf PCI E Series Register-Level Programmer Manual
73 * 340934b.pdf DAQ-STC reference manual
74 *
75 * 322080b.pdf 6711/6713/6715 User Manual
76 *
77 * 320945c.pdf PCI E Series User Manual
78 * 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
79 *
80 * ISSUES:
81 * - need to deal with external reference for DAC, and other DAC
82 * properties in board properties
83 * - deal with at-mio-16de-10 revision D to N changes, etc.
84 * - need to add other CALDAC type
85 * - need to slow down DAC loading. I don't trust NI's claim that
86 * two writes to the PCI bus slows IO enough. I would prefer to
87 * use udelay().
88 * Timing specs: (clock)
89 * AD8522 30ns
90 * DAC8043 120ns
91 * DAC8800 60ns
92 * MB88341 ?
93 */
94
95 #include <linux/module.h>
96 #include <linux/delay.h>
97
98 #include "../comedi_pci.h"
99
100 #include <asm/byteorder.h>
101
102 #include "ni_stc.h"
103 #include "mite.h"
104
105 #define PCIDMA
106
107 /*
108 * These are not all the possible ao ranges for 628x boards.
109 * They can do OFFSET +- REFERENCE where OFFSET can be
110 * 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
111 * be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
112 * 63 different possibilities. An AO channel
113 * can not act as it's own OFFSET or REFERENCE.
114 */
115 static const struct comedi_lrange range_ni_M_628x_ao = {
116 8, {
117 BIP_RANGE(10),
118 BIP_RANGE(5),
119 BIP_RANGE(2),
120 BIP_RANGE(1),
121 RANGE(-5, 15),
122 UNI_RANGE(10),
123 RANGE(3, 7),
124 RANGE(4, 6),
125 RANGE_ext(-1, 1)
126 }
127 };
128
129 static const struct comedi_lrange range_ni_M_625x_ao = {
130 3, {
131 BIP_RANGE(10),
132 BIP_RANGE(5),
133 RANGE_ext(-1, 1)
134 }
135 };
136
137 enum ni_pcimio_boardid {
138 BOARD_PCIMIO_16XE_50,
139 BOARD_PCIMIO_16XE_10,
140 BOARD_PCI6014,
141 BOARD_PXI6030E,
142 BOARD_PCIMIO_16E_1,
143 BOARD_PCIMIO_16E_4,
144 BOARD_PXI6040E,
145 BOARD_PCI6031E,
146 BOARD_PCI6032E,
147 BOARD_PCI6033E,
148 BOARD_PCI6071E,
149 BOARD_PCI6023E,
150 BOARD_PCI6024E,
151 BOARD_PCI6025E,
152 BOARD_PXI6025E,
153 BOARD_PCI6034E,
154 BOARD_PCI6035E,
155 BOARD_PCI6052E,
156 BOARD_PCI6110,
157 BOARD_PCI6111,
158 /* BOARD_PCI6115, */
159 /* BOARD_PXI6115, */
160 BOARD_PCI6711,
161 BOARD_PXI6711,
162 BOARD_PCI6713,
163 BOARD_PXI6713,
164 BOARD_PCI6731,
165 /* BOARD_PXI6731, */
166 BOARD_PCI6733,
167 BOARD_PXI6733,
168 BOARD_PXI6071E,
169 BOARD_PXI6070E,
170 BOARD_PXI6052E,
171 BOARD_PXI6031E,
172 BOARD_PCI6036E,
173 BOARD_PCI6220,
174 BOARD_PXI6220,
175 BOARD_PCI6221,
176 BOARD_PCI6221_37PIN,
177 BOARD_PXI6221,
178 BOARD_PCI6224,
179 BOARD_PXI6224,
180 BOARD_PCI6225,
181 BOARD_PXI6225,
182 BOARD_PCI6229,
183 BOARD_PXI6229,
184 BOARD_PCI6250,
185 BOARD_PXI6250,
186 BOARD_PCI6251,
187 BOARD_PXI6251,
188 BOARD_PCIE6251,
189 BOARD_PXIE6251,
190 BOARD_PCI6254,
191 BOARD_PXI6254,
192 BOARD_PCI6259,
193 BOARD_PXI6259,
194 BOARD_PCIE6259,
195 BOARD_PXIE6259,
196 BOARD_PCI6280,
197 BOARD_PXI6280,
198 BOARD_PCI6281,
199 BOARD_PXI6281,
200 BOARD_PCI6284,
201 BOARD_PXI6284,
202 BOARD_PCI6289,
203 BOARD_PXI6289,
204 BOARD_PCI6143,
205 BOARD_PXI6143,
206 };
207
208 static const struct ni_board_struct ni_boards[] = {
209 [BOARD_PCIMIO_16XE_50] = {
210 .name = "pci-mio-16xe-50",
211 .n_adchan = 16,
212 .ai_maxdata = 0xffff,
213 .ai_fifo_depth = 2048,
214 .alwaysdither = 1,
215 .gainlkup = ai_gain_8,
216 .ai_speed = 50000,
217 .n_aochan = 2,
218 .ao_maxdata = 0x0fff,
219 .ao_range_table = &range_bipolar10,
220 .ao_speed = 50000,
221 .caldac = { dac8800, dac8043 },
222 },
223 [BOARD_PCIMIO_16XE_10] = {
224 .name = "pci-mio-16xe-10", /* aka pci-6030E */
225 .n_adchan = 16,
226 .ai_maxdata = 0xffff,
227 .ai_fifo_depth = 512,
228 .alwaysdither = 1,
229 .gainlkup = ai_gain_14,
230 .ai_speed = 10000,
231 .n_aochan = 2,
232 .ao_maxdata = 0xffff,
233 .ao_fifo_depth = 2048,
234 .ao_range_table = &range_ni_E_ao_ext,
235 .ao_speed = 10000,
236 .caldac = { dac8800, dac8043, ad8522 },
237 },
238 [BOARD_PCI6014] = {
239 .name = "pci-6014",
240 .n_adchan = 16,
241 .ai_maxdata = 0xffff,
242 .ai_fifo_depth = 512,
243 .alwaysdither = 1,
244 .gainlkup = ai_gain_4,
245 .ai_speed = 5000,
246 .n_aochan = 2,
247 .ao_maxdata = 0xffff,
248 .ao_range_table = &range_bipolar10,
249 .ao_speed = 100000,
250 .caldac = { ad8804_debug },
251 },
252 [BOARD_PXI6030E] = {
253 .name = "pxi-6030e",
254 .n_adchan = 16,
255 .ai_maxdata = 0xffff,
256 .ai_fifo_depth = 512,
257 .alwaysdither = 1,
258 .gainlkup = ai_gain_14,
259 .ai_speed = 10000,
260 .n_aochan = 2,
261 .ao_maxdata = 0xffff,
262 .ao_fifo_depth = 2048,
263 .ao_range_table = &range_ni_E_ao_ext,
264 .ao_speed = 10000,
265 .caldac = { dac8800, dac8043, ad8522 },
266 },
267 [BOARD_PCIMIO_16E_1] = {
268 .name = "pci-mio-16e-1", /* aka pci-6070e */
269 .n_adchan = 16,
270 .ai_maxdata = 0x0fff,
271 .ai_fifo_depth = 512,
272 .gainlkup = ai_gain_16,
273 .ai_speed = 800,
274 .n_aochan = 2,
275 .ao_maxdata = 0x0fff,
276 .ao_fifo_depth = 2048,
277 .ao_range_table = &range_ni_E_ao_ext,
278 .ao_speed = 1000,
279 .caldac = { mb88341 },
280 },
281 [BOARD_PCIMIO_16E_4] = {
282 .name = "pci-mio-16e-4", /* aka pci-6040e */
283 .n_adchan = 16,
284 .ai_maxdata = 0x0fff,
285 .ai_fifo_depth = 512,
286 .gainlkup = ai_gain_16,
287 /*
288 * there have been reported problems with
289 * full speed on this board
290 */
291 .ai_speed = 2000,
292 .n_aochan = 2,
293 .ao_maxdata = 0x0fff,
294 .ao_fifo_depth = 512,
295 .ao_range_table = &range_ni_E_ao_ext,
296 .ao_speed = 1000,
297 .caldac = { ad8804_debug }, /* doc says mb88341 */
298 },
299 [BOARD_PXI6040E] = {
300 .name = "pxi-6040e",
301 .n_adchan = 16,
302 .ai_maxdata = 0x0fff,
303 .ai_fifo_depth = 512,
304 .gainlkup = ai_gain_16,
305 .ai_speed = 2000,
306 .n_aochan = 2,
307 .ao_maxdata = 0x0fff,
308 .ao_fifo_depth = 512,
309 .ao_range_table = &range_ni_E_ao_ext,
310 .ao_speed = 1000,
311 .caldac = { mb88341 },
312 },
313 [BOARD_PCI6031E] = {
314 .name = "pci-6031e",
315 .n_adchan = 64,
316 .ai_maxdata = 0xffff,
317 .ai_fifo_depth = 512,
318 .alwaysdither = 1,
319 .gainlkup = ai_gain_14,
320 .ai_speed = 10000,
321 .n_aochan = 2,
322 .ao_maxdata = 0xffff,
323 .ao_fifo_depth = 2048,
324 .ao_range_table = &range_ni_E_ao_ext,
325 .ao_speed = 10000,
326 .caldac = { dac8800, dac8043, ad8522 },
327 },
328 [BOARD_PCI6032E] = {
329 .name = "pci-6032e",
330 .n_adchan = 16,
331 .ai_maxdata = 0xffff,
332 .ai_fifo_depth = 512,
333 .alwaysdither = 1,
334 .gainlkup = ai_gain_14,
335 .ai_speed = 10000,
336 .caldac = { dac8800, dac8043, ad8522 },
337 },
338 [BOARD_PCI6033E] = {
339 .name = "pci-6033e",
340 .n_adchan = 64,
341 .ai_maxdata = 0xffff,
342 .ai_fifo_depth = 512,
343 .alwaysdither = 1,
344 .gainlkup = ai_gain_14,
345 .ai_speed = 10000,
346 .caldac = { dac8800, dac8043, ad8522 },
347 },
348 [BOARD_PCI6071E] = {
349 .name = "pci-6071e",
350 .n_adchan = 64,
351 .ai_maxdata = 0x0fff,
352 .ai_fifo_depth = 512,
353 .alwaysdither = 1,
354 .gainlkup = ai_gain_16,
355 .ai_speed = 800,
356 .n_aochan = 2,
357 .ao_maxdata = 0x0fff,
358 .ao_fifo_depth = 2048,
359 .ao_range_table = &range_ni_E_ao_ext,
360 .ao_speed = 1000,
361 .caldac = { ad8804_debug },
362 },
363 [BOARD_PCI6023E] = {
364 .name = "pci-6023e",
365 .n_adchan = 16,
366 .ai_maxdata = 0x0fff,
367 .ai_fifo_depth = 512,
368 .gainlkup = ai_gain_4,
369 .ai_speed = 5000,
370 .caldac = { ad8804_debug }, /* manual is wrong */
371 },
372 [BOARD_PCI6024E] = {
373 .name = "pci-6024e",
374 .n_adchan = 16,
375 .ai_maxdata = 0x0fff,
376 .ai_fifo_depth = 512,
377 .gainlkup = ai_gain_4,
378 .ai_speed = 5000,
379 .n_aochan = 2,
380 .ao_maxdata = 0x0fff,
381 .ao_range_table = &range_bipolar10,
382 .ao_speed = 100000,
383 .caldac = { ad8804_debug }, /* manual is wrong */
384 },
385 [BOARD_PCI6025E] = {
386 .name = "pci-6025e",
387 .n_adchan = 16,
388 .ai_maxdata = 0x0fff,
389 .ai_fifo_depth = 512,
390 .gainlkup = ai_gain_4,
391 .ai_speed = 5000,
392 .n_aochan = 2,
393 .ao_maxdata = 0x0fff,
394 .ao_range_table = &range_bipolar10,
395 .ao_speed = 100000,
396 .caldac = { ad8804_debug }, /* manual is wrong */
397 .has_8255 = 1,
398 },
399 [BOARD_PXI6025E] = {
400 .name = "pxi-6025e",
401 .n_adchan = 16,
402 .ai_maxdata = 0x0fff,
403 .ai_fifo_depth = 512,
404 .gainlkup = ai_gain_4,
405 .ai_speed = 5000,
406 .n_aochan = 2,
407 .ao_maxdata = 0x0fff,
408 .ao_range_table = &range_ni_E_ao_ext,
409 .ao_speed = 100000,
410 .caldac = { ad8804_debug }, /* manual is wrong */
411 .has_8255 = 1,
412 },
413 [BOARD_PCI6034E] = {
414 .name = "pci-6034e",
415 .n_adchan = 16,
416 .ai_maxdata = 0xffff,
417 .ai_fifo_depth = 512,
418 .alwaysdither = 1,
419 .gainlkup = ai_gain_4,
420 .ai_speed = 5000,
421 .caldac = { ad8804_debug },
422 },
423 [BOARD_PCI6035E] = {
424 .name = "pci-6035e",
425 .n_adchan = 16,
426 .ai_maxdata = 0xffff,
427 .ai_fifo_depth = 512,
428 .alwaysdither = 1,
429 .gainlkup = ai_gain_4,
430 .ai_speed = 5000,
431 .n_aochan = 2,
432 .ao_maxdata = 0x0fff,
433 .ao_range_table = &range_bipolar10,
434 .ao_speed = 100000,
435 .caldac = { ad8804_debug },
436 },
437 [BOARD_PCI6052E] = {
438 .name = "pci-6052e",
439 .n_adchan = 16,
440 .ai_maxdata = 0xffff,
441 .ai_fifo_depth = 512,
442 .alwaysdither = 1,
443 .gainlkup = ai_gain_16,
444 .ai_speed = 3000,
445 .n_aochan = 2,
446 .ao_maxdata = 0xffff,
447 .ao_fifo_depth = 2048,
448 .ao_range_table = &range_ni_E_ao_ext,
449 .ao_speed = 3000,
450 /* manual is wrong */
451 .caldac = { ad8804_debug, ad8804_debug, ad8522 },
452 },
453 [BOARD_PCI6110] = {
454 .name = "pci-6110",
455 .n_adchan = 4,
456 .ai_maxdata = 0x0fff,
457 .ai_fifo_depth = 8192,
458 .alwaysdither = 0,
459 .gainlkup = ai_gain_611x,
460 .ai_speed = 200,
461 .n_aochan = 2,
462 .ao_maxdata = 0xffff,
463 .reg_type = ni_reg_611x,
464 .ao_range_table = &range_bipolar10,
465 .ao_fifo_depth = 2048,
466 .ao_speed = 250,
467 .caldac = { ad8804, ad8804 },
468 },
469 [BOARD_PCI6111] = {
470 .name = "pci-6111",
471 .n_adchan = 2,
472 .ai_maxdata = 0x0fff,
473 .ai_fifo_depth = 8192,
474 .gainlkup = ai_gain_611x,
475 .ai_speed = 200,
476 .n_aochan = 2,
477 .ao_maxdata = 0xffff,
478 .reg_type = ni_reg_611x,
479 .ao_range_table = &range_bipolar10,
480 .ao_fifo_depth = 2048,
481 .ao_speed = 250,
482 .caldac = { ad8804, ad8804 },
483 },
484 #if 0
485 /* The 6115 boards probably need their own driver */
486 [BOARD_PCI6115] = { /* .device_id = 0x2ed0, */
487 .name = "pci-6115",
488 .n_adchan = 4,
489 .ai_maxdata = 0x0fff,
490 .ai_fifo_depth = 8192,
491 .gainlkup = ai_gain_611x,
492 .ai_speed = 100,
493 .n_aochan = 2,
494 .ao_maxdata = 0xffff,
495 .ao_671x = 1,
496 .ao_fifo_depth = 2048,
497 .ao_speed = 250,
498 .reg_611x = 1,
499 /* XXX */
500 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
501 },
502 #endif
503 #if 0
504 [BOARD_PXI6115] = { /* .device_id = ????, */
505 .name = "pxi-6115",
506 .n_adchan = 4,
507 .ai_maxdata = 0x0fff,
508 .ai_fifo_depth = 8192,
509 .gainlkup = ai_gain_611x,
510 .ai_speed = 100,
511 .n_aochan = 2,
512 .ao_maxdata = 0xffff,
513 .ao_671x = 1,
514 .ao_fifo_depth = 2048,
515 .ao_speed = 250,
516 .reg_611x = 1,
517 /* XXX */
518 .caldac = { ad8804_debug, ad8804_debug, ad8804_debug },
519 },
520 #endif
521 [BOARD_PCI6711] = {
522 .name = "pci-6711",
523 .n_aochan = 4,
524 .ao_maxdata = 0x0fff,
525 /* data sheet says 8192, but fifo really holds 16384 samples */
526 .ao_fifo_depth = 16384,
527 .ao_range_table = &range_bipolar10,
528 .ao_speed = 1000,
529 .reg_type = ni_reg_6711,
530 .caldac = { ad8804_debug },
531 },
532 [BOARD_PXI6711] = {
533 .name = "pxi-6711",
534 .n_aochan = 4,
535 .ao_maxdata = 0x0fff,
536 .ao_fifo_depth = 16384,
537 .ao_range_table = &range_bipolar10,
538 .ao_speed = 1000,
539 .reg_type = ni_reg_6711,
540 .caldac = { ad8804_debug },
541 },
542 [BOARD_PCI6713] = {
543 .name = "pci-6713",
544 .n_aochan = 8,
545 .ao_maxdata = 0x0fff,
546 .ao_fifo_depth = 16384,
547 .ao_range_table = &range_bipolar10,
548 .ao_speed = 1000,
549 .reg_type = ni_reg_6713,
550 .caldac = { ad8804_debug, ad8804_debug },
551 },
552 [BOARD_PXI6713] = {
553 .name = "pxi-6713",
554 .n_aochan = 8,
555 .ao_maxdata = 0x0fff,
556 .ao_fifo_depth = 16384,
557 .ao_range_table = &range_bipolar10,
558 .ao_speed = 1000,
559 .reg_type = ni_reg_6713,
560 .caldac = { ad8804_debug, ad8804_debug },
561 },
562 [BOARD_PCI6731] = {
563 .name = "pci-6731",
564 .n_aochan = 4,
565 .ao_maxdata = 0xffff,
566 .ao_fifo_depth = 8192,
567 .ao_range_table = &range_bipolar10,
568 .ao_speed = 1000,
569 .reg_type = ni_reg_6711,
570 .caldac = { ad8804_debug },
571 },
572 #if 0
573 [BOARD_PXI6731] = { /* .device_id = ????, */
574 .name = "pxi-6731",
575 .n_aochan = 4,
576 .ao_maxdata = 0xffff,
577 .ao_fifo_depth = 8192,
578 .ao_range_table = &range_bipolar10,
579 .reg_type = ni_reg_6711,
580 .caldac = { ad8804_debug },
581 },
582 #endif
583 [BOARD_PCI6733] = {
584 .name = "pci-6733",
585 .n_aochan = 8,
586 .ao_maxdata = 0xffff,
587 .ao_fifo_depth = 16384,
588 .ao_range_table = &range_bipolar10,
589 .ao_speed = 1000,
590 .reg_type = ni_reg_6713,
591 .caldac = { ad8804_debug, ad8804_debug },
592 },
593 [BOARD_PXI6733] = {
594 .name = "pxi-6733",
595 .n_aochan = 8,
596 .ao_maxdata = 0xffff,
597 .ao_fifo_depth = 16384,
598 .ao_range_table = &range_bipolar10,
599 .ao_speed = 1000,
600 .reg_type = ni_reg_6713,
601 .caldac = { ad8804_debug, ad8804_debug },
602 },
603 [BOARD_PXI6071E] = {
604 .name = "pxi-6071e",
605 .n_adchan = 64,
606 .ai_maxdata = 0x0fff,
607 .ai_fifo_depth = 512,
608 .alwaysdither = 1,
609 .gainlkup = ai_gain_16,
610 .ai_speed = 800,
611 .n_aochan = 2,
612 .ao_maxdata = 0x0fff,
613 .ao_fifo_depth = 2048,
614 .ao_range_table = &range_ni_E_ao_ext,
615 .ao_speed = 1000,
616 .caldac = { ad8804_debug },
617 },
618 [BOARD_PXI6070E] = {
619 .name = "pxi-6070e",
620 .n_adchan = 16,
621 .ai_maxdata = 0x0fff,
622 .ai_fifo_depth = 512,
623 .alwaysdither = 1,
624 .gainlkup = ai_gain_16,
625 .ai_speed = 800,
626 .n_aochan = 2,
627 .ao_maxdata = 0x0fff,
628 .ao_fifo_depth = 2048,
629 .ao_range_table = &range_ni_E_ao_ext,
630 .ao_speed = 1000,
631 .caldac = { ad8804_debug },
632 },
633 [BOARD_PXI6052E] = {
634 .name = "pxi-6052e",
635 .n_adchan = 16,
636 .ai_maxdata = 0xffff,
637 .ai_fifo_depth = 512,
638 .alwaysdither = 1,
639 .gainlkup = ai_gain_16,
640 .ai_speed = 3000,
641 .n_aochan = 2,
642 .ao_maxdata = 0xffff,
643 .ao_fifo_depth = 2048,
644 .ao_range_table = &range_ni_E_ao_ext,
645 .ao_speed = 3000,
646 .caldac = { mb88341, mb88341, ad8522 },
647 },
648 [BOARD_PXI6031E] = {
649 .name = "pxi-6031e",
650 .n_adchan = 64,
651 .ai_maxdata = 0xffff,
652 .ai_fifo_depth = 512,
653 .alwaysdither = 1,
654 .gainlkup = ai_gain_14,
655 .ai_speed = 10000,
656 .n_aochan = 2,
657 .ao_maxdata = 0xffff,
658 .ao_fifo_depth = 2048,
659 .ao_range_table = &range_ni_E_ao_ext,
660 .ao_speed = 10000,
661 .caldac = { dac8800, dac8043, ad8522 },
662 },
663 [BOARD_PCI6036E] = {
664 .name = "pci-6036e",
665 .n_adchan = 16,
666 .ai_maxdata = 0xffff,
667 .ai_fifo_depth = 512,
668 .alwaysdither = 1,
669 .gainlkup = ai_gain_4,
670 .ai_speed = 5000,
671 .n_aochan = 2,
672 .ao_maxdata = 0xffff,
673 .ao_range_table = &range_bipolar10,
674 .ao_speed = 100000,
675 .caldac = { ad8804_debug },
676 },
677 [BOARD_PCI6220] = {
678 .name = "pci-6220",
679 .n_adchan = 16,
680 .ai_maxdata = 0xffff,
681 .ai_fifo_depth = 512, /* FIXME: guess */
682 .gainlkup = ai_gain_622x,
683 .ai_speed = 4000,
684 .reg_type = ni_reg_622x,
685 .caldac = { caldac_none },
686 },
687 [BOARD_PXI6220] = {
688 .name = "pxi-6220",
689 .n_adchan = 16,
690 .ai_maxdata = 0xffff,
691 .ai_fifo_depth = 512, /* FIXME: guess */
692 .gainlkup = ai_gain_622x,
693 .ai_speed = 4000,
694 .reg_type = ni_reg_622x,
695 .caldac = { caldac_none },
696 },
697 [BOARD_PCI6221] = {
698 .name = "pci-6221",
699 .n_adchan = 16,
700 .ai_maxdata = 0xffff,
701 .ai_fifo_depth = 4095,
702 .gainlkup = ai_gain_622x,
703 .ai_speed = 4000,
704 .n_aochan = 2,
705 .ao_maxdata = 0xffff,
706 .ao_fifo_depth = 8191,
707 .ao_range_table = &range_bipolar10,
708 .reg_type = ni_reg_622x,
709 .ao_speed = 1200,
710 .caldac = { caldac_none },
711 },
712 [BOARD_PCI6221_37PIN] = {
713 .name = "pci-6221_37pin",
714 .n_adchan = 16,
715 .ai_maxdata = 0xffff,
716 .ai_fifo_depth = 4095,
717 .gainlkup = ai_gain_622x,
718 .ai_speed = 4000,
719 .n_aochan = 2,
720 .ao_maxdata = 0xffff,
721 .ao_fifo_depth = 8191,
722 .ao_range_table = &range_bipolar10,
723 .reg_type = ni_reg_622x,
724 .ao_speed = 1200,
725 .caldac = { caldac_none },
726 },
727 [BOARD_PXI6221] = {
728 .name = "pxi-6221",
729 .n_adchan = 16,
730 .ai_maxdata = 0xffff,
731 .ai_fifo_depth = 4095,
732 .gainlkup = ai_gain_622x,
733 .ai_speed = 4000,
734 .n_aochan = 2,
735 .ao_maxdata = 0xffff,
736 .ao_fifo_depth = 8191,
737 .ao_range_table = &range_bipolar10,
738 .reg_type = ni_reg_622x,
739 .ao_speed = 1200,
740 .caldac = { caldac_none },
741 },
742 [BOARD_PCI6224] = {
743 .name = "pci-6224",
744 .n_adchan = 32,
745 .ai_maxdata = 0xffff,
746 .ai_fifo_depth = 4095,
747 .gainlkup = ai_gain_622x,
748 .ai_speed = 4000,
749 .reg_type = ni_reg_622x,
750 .has_32dio_chan = 1,
751 .caldac = { caldac_none },
752 },
753 [BOARD_PXI6224] = {
754 .name = "pxi-6224",
755 .n_adchan = 32,
756 .ai_maxdata = 0xffff,
757 .ai_fifo_depth = 4095,
758 .gainlkup = ai_gain_622x,
759 .ai_speed = 4000,
760 .reg_type = ni_reg_622x,
761 .has_32dio_chan = 1,
762 .caldac = { caldac_none },
763 },
764 [BOARD_PCI6225] = {
765 .name = "pci-6225",
766 .n_adchan = 80,
767 .ai_maxdata = 0xffff,
768 .ai_fifo_depth = 4095,
769 .gainlkup = ai_gain_622x,
770 .ai_speed = 4000,
771 .n_aochan = 2,
772 .ao_maxdata = 0xffff,
773 .ao_fifo_depth = 8191,
774 .ao_range_table = &range_bipolar10,
775 .reg_type = ni_reg_622x,
776 .ao_speed = 1200,
777 .has_32dio_chan = 1,
778 .caldac = { caldac_none },
779 },
780 [BOARD_PXI6225] = {
781 .name = "pxi-6225",
782 .n_adchan = 80,
783 .ai_maxdata = 0xffff,
784 .ai_fifo_depth = 4095,
785 .gainlkup = ai_gain_622x,
786 .ai_speed = 4000,
787 .n_aochan = 2,
788 .ao_maxdata = 0xffff,
789 .ao_fifo_depth = 8191,
790 .ao_range_table = &range_bipolar10,
791 .reg_type = ni_reg_622x,
792 .ao_speed = 1200,
793 .has_32dio_chan = 1,
794 .caldac = { caldac_none },
795 },
796 [BOARD_PCI6229] = {
797 .name = "pci-6229",
798 .n_adchan = 32,
799 .ai_maxdata = 0xffff,
800 .ai_fifo_depth = 4095,
801 .gainlkup = ai_gain_622x,
802 .ai_speed = 4000,
803 .n_aochan = 4,
804 .ao_maxdata = 0xffff,
805 .ao_fifo_depth = 8191,
806 .ao_range_table = &range_bipolar10,
807 .reg_type = ni_reg_622x,
808 .ao_speed = 1200,
809 .has_32dio_chan = 1,
810 .caldac = { caldac_none },
811 },
812 [BOARD_PXI6229] = {
813 .name = "pxi-6229",
814 .n_adchan = 32,
815 .ai_maxdata = 0xffff,
816 .ai_fifo_depth = 4095,
817 .gainlkup = ai_gain_622x,
818 .ai_speed = 4000,
819 .n_aochan = 4,
820 .ao_maxdata = 0xffff,
821 .ao_fifo_depth = 8191,
822 .ao_range_table = &range_bipolar10,
823 .reg_type = ni_reg_622x,
824 .ao_speed = 1200,
825 .has_32dio_chan = 1,
826 .caldac = { caldac_none },
827 },
828 [BOARD_PCI6250] = {
829 .name = "pci-6250",
830 .n_adchan = 16,
831 .ai_maxdata = 0xffff,
832 .ai_fifo_depth = 4095,
833 .gainlkup = ai_gain_628x,
834 .ai_speed = 800,
835 .reg_type = ni_reg_625x,
836 .caldac = { caldac_none },
837 },
838 [BOARD_PXI6250] = {
839 .name = "pxi-6250",
840 .n_adchan = 16,
841 .ai_maxdata = 0xffff,
842 .ai_fifo_depth = 4095,
843 .gainlkup = ai_gain_628x,
844 .ai_speed = 800,
845 .reg_type = ni_reg_625x,
846 .caldac = { caldac_none },
847 },
848 [BOARD_PCI6251] = {
849 .name = "pci-6251",
850 .n_adchan = 16,
851 .ai_maxdata = 0xffff,
852 .ai_fifo_depth = 4095,
853 .gainlkup = ai_gain_628x,
854 .ai_speed = 800,
855 .n_aochan = 2,
856 .ao_maxdata = 0xffff,
857 .ao_fifo_depth = 8191,
858 .ao_range_table = &range_ni_M_625x_ao,
859 .reg_type = ni_reg_625x,
860 .ao_speed = 350,
861 .caldac = { caldac_none },
862 },
863 [BOARD_PXI6251] = {
864 .name = "pxi-6251",
865 .n_adchan = 16,
866 .ai_maxdata = 0xffff,
867 .ai_fifo_depth = 4095,
868 .gainlkup = ai_gain_628x,
869 .ai_speed = 800,
870 .n_aochan = 2,
871 .ao_maxdata = 0xffff,
872 .ao_fifo_depth = 8191,
873 .ao_range_table = &range_ni_M_625x_ao,
874 .reg_type = ni_reg_625x,
875 .ao_speed = 350,
876 .caldac = { caldac_none },
877 },
878 [BOARD_PCIE6251] = {
879 .name = "pcie-6251",
880 .n_adchan = 16,
881 .ai_maxdata = 0xffff,
882 .ai_fifo_depth = 4095,
883 .gainlkup = ai_gain_628x,
884 .ai_speed = 800,
885 .n_aochan = 2,
886 .ao_maxdata = 0xffff,
887 .ao_fifo_depth = 8191,
888 .ao_range_table = &range_ni_M_625x_ao,
889 .reg_type = ni_reg_625x,
890 .ao_speed = 350,
891 .caldac = { caldac_none },
892 },
893 [BOARD_PXIE6251] = {
894 .name = "pxie-6251",
895 .n_adchan = 16,
896 .ai_maxdata = 0xffff,
897 .ai_fifo_depth = 4095,
898 .gainlkup = ai_gain_628x,
899 .ai_speed = 800,
900 .n_aochan = 2,
901 .ao_maxdata = 0xffff,
902 .ao_fifo_depth = 8191,
903 .ao_range_table = &range_ni_M_625x_ao,
904 .reg_type = ni_reg_625x,
905 .ao_speed = 350,
906 .caldac = { caldac_none },
907 },
908 [BOARD_PCI6254] = {
909 .name = "pci-6254",
910 .n_adchan = 32,
911 .ai_maxdata = 0xffff,
912 .ai_fifo_depth = 4095,
913 .gainlkup = ai_gain_628x,
914 .ai_speed = 800,
915 .reg_type = ni_reg_625x,
916 .has_32dio_chan = 1,
917 .caldac = { caldac_none },
918 },
919 [BOARD_PXI6254] = {
920 .name = "pxi-6254",
921 .n_adchan = 32,
922 .ai_maxdata = 0xffff,
923 .ai_fifo_depth = 4095,
924 .gainlkup = ai_gain_628x,
925 .ai_speed = 800,
926 .reg_type = ni_reg_625x,
927 .has_32dio_chan = 1,
928 .caldac = { caldac_none },
929 },
930 [BOARD_PCI6259] = {
931 .name = "pci-6259",
932 .n_adchan = 32,
933 .ai_maxdata = 0xffff,
934 .ai_fifo_depth = 4095,
935 .gainlkup = ai_gain_628x,
936 .ai_speed = 800,
937 .n_aochan = 4,
938 .ao_maxdata = 0xffff,
939 .ao_fifo_depth = 8191,
940 .ao_range_table = &range_ni_M_625x_ao,
941 .reg_type = ni_reg_625x,
942 .ao_speed = 350,
943 .has_32dio_chan = 1,
944 .caldac = { caldac_none },
945 },
946 [BOARD_PXI6259] = {
947 .name = "pxi-6259",
948 .n_adchan = 32,
949 .ai_maxdata = 0xffff,
950 .ai_fifo_depth = 4095,
951 .gainlkup = ai_gain_628x,
952 .ai_speed = 800,
953 .n_aochan = 4,
954 .ao_maxdata = 0xffff,
955 .ao_fifo_depth = 8191,
956 .ao_range_table = &range_ni_M_625x_ao,
957 .reg_type = ni_reg_625x,
958 .ao_speed = 350,
959 .has_32dio_chan = 1,
960 .caldac = { caldac_none },
961 },
962 [BOARD_PCIE6259] = {
963 .name = "pcie-6259",
964 .n_adchan = 32,
965 .ai_maxdata = 0xffff,
966 .ai_fifo_depth = 4095,
967 .gainlkup = ai_gain_628x,
968 .ai_speed = 800,
969 .n_aochan = 4,
970 .ao_maxdata = 0xffff,
971 .ao_fifo_depth = 8191,
972 .ao_range_table = &range_ni_M_625x_ao,
973 .reg_type = ni_reg_625x,
974 .ao_speed = 350,
975 .has_32dio_chan = 1,
976 .caldac = { caldac_none },
977 },
978 [BOARD_PXIE6259] = {
979 .name = "pxie-6259",
980 .n_adchan = 32,
981 .ai_maxdata = 0xffff,
982 .ai_fifo_depth = 4095,
983 .gainlkup = ai_gain_628x,
984 .ai_speed = 800,
985 .n_aochan = 4,
986 .ao_maxdata = 0xffff,
987 .ao_fifo_depth = 8191,
988 .ao_range_table = &range_ni_M_625x_ao,
989 .reg_type = ni_reg_625x,
990 .ao_speed = 350,
991 .has_32dio_chan = 1,
992 .caldac = { caldac_none },
993 },
994 [BOARD_PCI6280] = {
995 .name = "pci-6280",
996 .n_adchan = 16,
997 .ai_maxdata = 0x3ffff,
998 .ai_fifo_depth = 2047,
999 .gainlkup = ai_gain_628x,
1000 .ai_speed = 1600,
1001 .ao_fifo_depth = 8191,
1002 .reg_type = ni_reg_628x,
1003 .caldac = { caldac_none },
1004 },
1005 [BOARD_PXI6280] = {
1006 .name = "pxi-6280",
1007 .n_adchan = 16,
1008 .ai_maxdata = 0x3ffff,
1009 .ai_fifo_depth = 2047,
1010 .gainlkup = ai_gain_628x,
1011 .ai_speed = 1600,
1012 .ao_fifo_depth = 8191,
1013 .reg_type = ni_reg_628x,
1014 .caldac = { caldac_none },
1015 },
1016 [BOARD_PCI6281] = {
1017 .name = "pci-6281",
1018 .n_adchan = 16,
1019 .ai_maxdata = 0x3ffff,
1020 .ai_fifo_depth = 2047,
1021 .gainlkup = ai_gain_628x,
1022 .ai_speed = 1600,
1023 .n_aochan = 2,
1024 .ao_maxdata = 0xffff,
1025 .ao_fifo_depth = 8191,
1026 .ao_range_table = &range_ni_M_628x_ao,
1027 .reg_type = ni_reg_628x,
1028 .ao_speed = 350,
1029 .caldac = { caldac_none },
1030 },
1031 [BOARD_PXI6281] = {
1032 .name = "pxi-6281",
1033 .n_adchan = 16,
1034 .ai_maxdata = 0x3ffff,
1035 .ai_fifo_depth = 2047,
1036 .gainlkup = ai_gain_628x,
1037 .ai_speed = 1600,
1038 .n_aochan = 2,
1039 .ao_maxdata = 0xffff,
1040 .ao_fifo_depth = 8191,
1041 .ao_range_table = &range_ni_M_628x_ao,
1042 .reg_type = ni_reg_628x,
1043 .ao_speed = 350,
1044 .caldac = { caldac_none },
1045 },
1046 [BOARD_PCI6284] = {
1047 .name = "pci-6284",
1048 .n_adchan = 32,
1049 .ai_maxdata = 0x3ffff,
1050 .ai_fifo_depth = 2047,
1051 .gainlkup = ai_gain_628x,
1052 .ai_speed = 1600,
1053 .reg_type = ni_reg_628x,
1054 .has_32dio_chan = 1,
1055 .caldac = { caldac_none },
1056 },
1057 [BOARD_PXI6284] = {
1058 .name = "pxi-6284",
1059 .n_adchan = 32,
1060 .ai_maxdata = 0x3ffff,
1061 .ai_fifo_depth = 2047,
1062 .gainlkup = ai_gain_628x,
1063 .ai_speed = 1600,
1064 .reg_type = ni_reg_628x,
1065 .has_32dio_chan = 1,
1066 .caldac = { caldac_none },
1067 },
1068 [BOARD_PCI6289] = {
1069 .name = "pci-6289",
1070 .n_adchan = 32,
1071 .ai_maxdata = 0x3ffff,
1072 .ai_fifo_depth = 2047,
1073 .gainlkup = ai_gain_628x,
1074 .ai_speed = 1600,
1075 .n_aochan = 4,
1076 .ao_maxdata = 0xffff,
1077 .ao_fifo_depth = 8191,
1078 .ao_range_table = &range_ni_M_628x_ao,
1079 .reg_type = ni_reg_628x,
1080 .ao_speed = 350,
1081 .has_32dio_chan = 1,
1082 .caldac = { caldac_none },
1083 },
1084 [BOARD_PXI6289] = {
1085 .name = "pxi-6289",
1086 .n_adchan = 32,
1087 .ai_maxdata = 0x3ffff,
1088 .ai_fifo_depth = 2047,
1089 .gainlkup = ai_gain_628x,
1090 .ai_speed = 1600,
1091 .n_aochan = 4,
1092 .ao_maxdata = 0xffff,
1093 .ao_fifo_depth = 8191,
1094 .ao_range_table = &range_ni_M_628x_ao,
1095 .reg_type = ni_reg_628x,
1096 .ao_speed = 350,
1097 .has_32dio_chan = 1,
1098 .caldac = { caldac_none },
1099 },
1100 [BOARD_PCI6143] = {
1101 .name = "pci-6143",
1102 .n_adchan = 8,
1103 .ai_maxdata = 0xffff,
1104 .ai_fifo_depth = 1024,
1105 .gainlkup = ai_gain_6143,
1106 .ai_speed = 4000,
1107 .reg_type = ni_reg_6143,
1108 .caldac = { ad8804_debug, ad8804_debug },
1109 },
1110 [BOARD_PXI6143] = {
1111 .name = "pxi-6143",
1112 .n_adchan = 8,
1113 .ai_maxdata = 0xffff,
1114 .ai_fifo_depth = 1024,
1115 .gainlkup = ai_gain_6143,
1116 .ai_speed = 4000,
1117 .reg_type = ni_reg_6143,
1118 .caldac = { ad8804_debug, ad8804_debug },
1119 },
1120 };
1121
1122 #include "ni_mio_common.c"
1123
pcimio_ai_change(struct comedi_device * dev,struct comedi_subdevice * s)1124 static int pcimio_ai_change(struct comedi_device *dev,
1125 struct comedi_subdevice *s)
1126 {
1127 struct ni_private *devpriv = dev->private;
1128 int ret;
1129
1130 ret = mite_buf_change(devpriv->ai_mite_ring, s);
1131 if (ret < 0)
1132 return ret;
1133
1134 return 0;
1135 }
1136
pcimio_ao_change(struct comedi_device * dev,struct comedi_subdevice * s)1137 static int pcimio_ao_change(struct comedi_device *dev,
1138 struct comedi_subdevice *s)
1139 {
1140 struct ni_private *devpriv = dev->private;
1141 int ret;
1142
1143 ret = mite_buf_change(devpriv->ao_mite_ring, s);
1144 if (ret < 0)
1145 return ret;
1146
1147 return 0;
1148 }
1149
pcimio_gpct0_change(struct comedi_device * dev,struct comedi_subdevice * s)1150 static int pcimio_gpct0_change(struct comedi_device *dev,
1151 struct comedi_subdevice *s)
1152 {
1153 struct ni_private *devpriv = dev->private;
1154 int ret;
1155
1156 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s);
1157 if (ret < 0)
1158 return ret;
1159
1160 return 0;
1161 }
1162
pcimio_gpct1_change(struct comedi_device * dev,struct comedi_subdevice * s)1163 static int pcimio_gpct1_change(struct comedi_device *dev,
1164 struct comedi_subdevice *s)
1165 {
1166 struct ni_private *devpriv = dev->private;
1167 int ret;
1168
1169 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s);
1170 if (ret < 0)
1171 return ret;
1172
1173 return 0;
1174 }
1175
pcimio_dio_change(struct comedi_device * dev,struct comedi_subdevice * s)1176 static int pcimio_dio_change(struct comedi_device *dev,
1177 struct comedi_subdevice *s)
1178 {
1179 struct ni_private *devpriv = dev->private;
1180 int ret;
1181
1182 ret = mite_buf_change(devpriv->cdo_mite_ring, s);
1183 if (ret < 0)
1184 return ret;
1185
1186 return 0;
1187 }
1188
m_series_init_eeprom_buffer(struct comedi_device * dev)1189 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1190 {
1191 struct ni_private *devpriv = dev->private;
1192 struct mite *mite = devpriv->mite;
1193 resource_size_t daq_phys_addr;
1194 static const int Start_Cal_EEPROM = 0x400;
1195 static const unsigned int window_size = 10;
1196 unsigned int old_iodwbsr_bits;
1197 unsigned int old_iodwbsr1_bits;
1198 unsigned int old_iodwcr1_bits;
1199 int i;
1200
1201 /* IO Window 1 needs to be temporarily mapped to read the eeprom */
1202 daq_phys_addr = pci_resource_start(mite->pcidev, 1);
1203
1204 old_iodwbsr_bits = readl(mite->mmio + MITE_IODWBSR);
1205 old_iodwbsr1_bits = readl(mite->mmio + MITE_IODWBSR_1);
1206 old_iodwcr1_bits = readl(mite->mmio + MITE_IODWCR_1);
1207 writel(0x0, mite->mmio + MITE_IODWBSR);
1208 writel(((0x80 | window_size) | daq_phys_addr),
1209 mite->mmio + MITE_IODWBSR_1);
1210 writel(0x1 | old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1211 writel(0xf, mite->mmio + 0x30);
1212
1213 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1214 devpriv->eeprom_buffer[i] = ni_readb(dev, Start_Cal_EEPROM + i);
1215
1216 writel(old_iodwbsr1_bits, mite->mmio + MITE_IODWBSR_1);
1217 writel(old_iodwbsr_bits, mite->mmio + MITE_IODWBSR);
1218 writel(old_iodwcr1_bits, mite->mmio + MITE_IODWCR_1);
1219 writel(0x0, mite->mmio + 0x30);
1220 }
1221
init_6143(struct comedi_device * dev)1222 static void init_6143(struct comedi_device *dev)
1223 {
1224 const struct ni_board_struct *board = dev->board_ptr;
1225 struct ni_private *devpriv = dev->private;
1226
1227 /* Disable interrupts */
1228 ni_stc_writew(dev, 0, NISTC_INT_CTRL_REG);
1229
1230 /* Initialise 6143 AI specific bits */
1231
1232 /* Set G0,G1 DMA mode to E series version */
1233 ni_writeb(dev, 0x00, NI6143_MAGIC_REG);
1234 /* Set EOCMode, ADCMode and pipelinedelay */
1235 ni_writeb(dev, 0x80, NI6143_PIPELINE_DELAY_REG);
1236 /* Set EOC Delay */
1237 ni_writeb(dev, 0x00, NI6143_EOC_SET_REG);
1238
1239 /* Set the FIFO half full level */
1240 ni_writel(dev, board->ai_fifo_depth / 2, NI6143_AI_FIFO_FLAG_REG);
1241
1242 /* Strobe Relay disable bit */
1243 devpriv->ai_calib_source_enabled = 0;
1244 ni_writew(dev, devpriv->ai_calib_source | NI6143_CALIB_CHAN_RELAY_OFF,
1245 NI6143_CALIB_CHAN_REG);
1246 ni_writew(dev, devpriv->ai_calib_source, NI6143_CALIB_CHAN_REG);
1247 }
1248
pcimio_detach(struct comedi_device * dev)1249 static void pcimio_detach(struct comedi_device *dev)
1250 {
1251 struct ni_private *devpriv = dev->private;
1252
1253 mio_common_detach(dev);
1254 if (dev->irq)
1255 free_irq(dev->irq, dev);
1256 if (devpriv) {
1257 mite_free_ring(devpriv->ai_mite_ring);
1258 mite_free_ring(devpriv->ao_mite_ring);
1259 mite_free_ring(devpriv->cdo_mite_ring);
1260 mite_free_ring(devpriv->gpct_mite_ring[0]);
1261 mite_free_ring(devpriv->gpct_mite_ring[1]);
1262 mite_detach(devpriv->mite);
1263 }
1264 if (dev->mmio)
1265 iounmap(dev->mmio);
1266 comedi_pci_disable(dev);
1267 }
1268
pcimio_auto_attach(struct comedi_device * dev,unsigned long context)1269 static int pcimio_auto_attach(struct comedi_device *dev,
1270 unsigned long context)
1271 {
1272 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1273 const struct ni_board_struct *board = NULL;
1274 struct ni_private *devpriv;
1275 unsigned int irq;
1276 int ret;
1277
1278 if (context < ARRAY_SIZE(ni_boards))
1279 board = &ni_boards[context];
1280 if (!board)
1281 return -ENODEV;
1282 dev->board_ptr = board;
1283 dev->board_name = board->name;
1284
1285 ret = comedi_pci_enable(dev);
1286 if (ret)
1287 return ret;
1288
1289 ret = ni_alloc_private(dev);
1290 if (ret)
1291 return ret;
1292 devpriv = dev->private;
1293
1294 devpriv->mite = mite_attach(dev, false); /* use win0 */
1295 if (!devpriv->mite)
1296 return -ENOMEM;
1297
1298 if (board->reg_type & ni_reg_m_series_mask)
1299 devpriv->is_m_series = 1;
1300 if (board->reg_type & ni_reg_6xxx_mask)
1301 devpriv->is_6xxx = 1;
1302 if (board->reg_type == ni_reg_611x)
1303 devpriv->is_611x = 1;
1304 if (board->reg_type == ni_reg_6143)
1305 devpriv->is_6143 = 1;
1306 if (board->reg_type == ni_reg_622x)
1307 devpriv->is_622x = 1;
1308 if (board->reg_type == ni_reg_625x)
1309 devpriv->is_625x = 1;
1310 if (board->reg_type == ni_reg_628x)
1311 devpriv->is_628x = 1;
1312 if (board->reg_type & ni_reg_67xx_mask)
1313 devpriv->is_67xx = 1;
1314 if (board->reg_type == ni_reg_6711)
1315 devpriv->is_6711 = 1;
1316 if (board->reg_type == ni_reg_6713)
1317 devpriv->is_6713 = 1;
1318
1319 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1320 if (!devpriv->ai_mite_ring)
1321 return -ENOMEM;
1322 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1323 if (!devpriv->ao_mite_ring)
1324 return -ENOMEM;
1325 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1326 if (!devpriv->cdo_mite_ring)
1327 return -ENOMEM;
1328 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1329 if (!devpriv->gpct_mite_ring[0])
1330 return -ENOMEM;
1331 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1332 if (!devpriv->gpct_mite_ring[1])
1333 return -ENOMEM;
1334
1335 if (devpriv->is_m_series)
1336 m_series_init_eeprom_buffer(dev);
1337 if (devpriv->is_6143)
1338 init_6143(dev);
1339
1340 irq = pcidev->irq;
1341 if (irq) {
1342 ret = request_irq(irq, ni_E_interrupt, IRQF_SHARED,
1343 dev->board_name, dev);
1344 if (ret == 0)
1345 dev->irq = irq;
1346 }
1347
1348 ret = ni_E_init(dev, 0, 1);
1349 if (ret < 0)
1350 return ret;
1351
1352 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1353 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1354 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1355 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1356 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1357
1358 return 0;
1359 }
1360
1361 static struct comedi_driver ni_pcimio_driver = {
1362 .driver_name = "ni_pcimio",
1363 .module = THIS_MODULE,
1364 .auto_attach = pcimio_auto_attach,
1365 .detach = pcimio_detach,
1366 };
1367
ni_pcimio_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)1368 static int ni_pcimio_pci_probe(struct pci_dev *dev,
1369 const struct pci_device_id *id)
1370 {
1371 return comedi_pci_auto_config(dev, &ni_pcimio_driver, id->driver_data);
1372 }
1373
1374 static const struct pci_device_id ni_pcimio_pci_table[] = {
1375 { PCI_VDEVICE(NI, 0x0162), BOARD_PCIMIO_16XE_50 }, /* 0x1620? */
1376 { PCI_VDEVICE(NI, 0x1170), BOARD_PCIMIO_16XE_10 },
1377 { PCI_VDEVICE(NI, 0x1180), BOARD_PCIMIO_16E_1 },
1378 { PCI_VDEVICE(NI, 0x1190), BOARD_PCIMIO_16E_4 },
1379 { PCI_VDEVICE(NI, 0x11b0), BOARD_PXI6070E },
1380 { PCI_VDEVICE(NI, 0x11c0), BOARD_PXI6040E },
1381 { PCI_VDEVICE(NI, 0x11d0), BOARD_PXI6030E },
1382 { PCI_VDEVICE(NI, 0x1270), BOARD_PCI6032E },
1383 { PCI_VDEVICE(NI, 0x1330), BOARD_PCI6031E },
1384 { PCI_VDEVICE(NI, 0x1340), BOARD_PCI6033E },
1385 { PCI_VDEVICE(NI, 0x1350), BOARD_PCI6071E },
1386 { PCI_VDEVICE(NI, 0x14e0), BOARD_PCI6110 },
1387 { PCI_VDEVICE(NI, 0x14f0), BOARD_PCI6111 },
1388 { PCI_VDEVICE(NI, 0x1580), BOARD_PXI6031E },
1389 { PCI_VDEVICE(NI, 0x15b0), BOARD_PXI6071E },
1390 { PCI_VDEVICE(NI, 0x1880), BOARD_PCI6711 },
1391 { PCI_VDEVICE(NI, 0x1870), BOARD_PCI6713 },
1392 { PCI_VDEVICE(NI, 0x18b0), BOARD_PCI6052E },
1393 { PCI_VDEVICE(NI, 0x18c0), BOARD_PXI6052E },
1394 { PCI_VDEVICE(NI, 0x2410), BOARD_PCI6733 },
1395 { PCI_VDEVICE(NI, 0x2420), BOARD_PXI6733 },
1396 { PCI_VDEVICE(NI, 0x2430), BOARD_PCI6731 },
1397 { PCI_VDEVICE(NI, 0x2890), BOARD_PCI6036E },
1398 { PCI_VDEVICE(NI, 0x28c0), BOARD_PCI6014 },
1399 { PCI_VDEVICE(NI, 0x2a60), BOARD_PCI6023E },
1400 { PCI_VDEVICE(NI, 0x2a70), BOARD_PCI6024E },
1401 { PCI_VDEVICE(NI, 0x2a80), BOARD_PCI6025E },
1402 { PCI_VDEVICE(NI, 0x2ab0), BOARD_PXI6025E },
1403 { PCI_VDEVICE(NI, 0x2b80), BOARD_PXI6713 },
1404 { PCI_VDEVICE(NI, 0x2b90), BOARD_PXI6711 },
1405 { PCI_VDEVICE(NI, 0x2c80), BOARD_PCI6035E },
1406 { PCI_VDEVICE(NI, 0x2ca0), BOARD_PCI6034E },
1407 { PCI_VDEVICE(NI, 0x70aa), BOARD_PCI6229 },
1408 { PCI_VDEVICE(NI, 0x70ab), BOARD_PCI6259 },
1409 { PCI_VDEVICE(NI, 0x70ac), BOARD_PCI6289 },
1410 { PCI_VDEVICE(NI, 0x70ad), BOARD_PXI6251 },
1411 { PCI_VDEVICE(NI, 0x70ae), BOARD_PXI6220 },
1412 { PCI_VDEVICE(NI, 0x70af), BOARD_PCI6221 },
1413 { PCI_VDEVICE(NI, 0x70b0), BOARD_PCI6220 },
1414 { PCI_VDEVICE(NI, 0x70b1), BOARD_PXI6229 },
1415 { PCI_VDEVICE(NI, 0x70b2), BOARD_PXI6259 },
1416 { PCI_VDEVICE(NI, 0x70b3), BOARD_PXI6289 },
1417 { PCI_VDEVICE(NI, 0x70b4), BOARD_PCI6250 },
1418 { PCI_VDEVICE(NI, 0x70b5), BOARD_PXI6221 },
1419 { PCI_VDEVICE(NI, 0x70b6), BOARD_PCI6280 },
1420 { PCI_VDEVICE(NI, 0x70b7), BOARD_PCI6254 },
1421 { PCI_VDEVICE(NI, 0x70b8), BOARD_PCI6251 },
1422 { PCI_VDEVICE(NI, 0x70b9), BOARD_PXI6250 },
1423 { PCI_VDEVICE(NI, 0x70ba), BOARD_PXI6254 },
1424 { PCI_VDEVICE(NI, 0x70bb), BOARD_PXI6280 },
1425 { PCI_VDEVICE(NI, 0x70bc), BOARD_PCI6284 },
1426 { PCI_VDEVICE(NI, 0x70bd), BOARD_PCI6281 },
1427 { PCI_VDEVICE(NI, 0x70be), BOARD_PXI6284 },
1428 { PCI_VDEVICE(NI, 0x70bf), BOARD_PXI6281 },
1429 { PCI_VDEVICE(NI, 0x70c0), BOARD_PCI6143 },
1430 { PCI_VDEVICE(NI, 0x70f2), BOARD_PCI6224 },
1431 { PCI_VDEVICE(NI, 0x70f3), BOARD_PXI6224 },
1432 { PCI_VDEVICE(NI, 0x710d), BOARD_PXI6143 },
1433 { PCI_VDEVICE(NI, 0x716c), BOARD_PCI6225 },
1434 { PCI_VDEVICE(NI, 0x716d), BOARD_PXI6225 },
1435 { PCI_VDEVICE(NI, 0x717d), BOARD_PCIE6251 },
1436 { PCI_VDEVICE(NI, 0x717f), BOARD_PCIE6259 },
1437 { PCI_VDEVICE(NI, 0x71bc), BOARD_PCI6221_37PIN },
1438 { PCI_VDEVICE(NI, 0x72e8), BOARD_PXIE6251 },
1439 { PCI_VDEVICE(NI, 0x72e9), BOARD_PXIE6259 },
1440 { 0 }
1441 };
1442 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1443
1444 static struct pci_driver ni_pcimio_pci_driver = {
1445 .name = "ni_pcimio",
1446 .id_table = ni_pcimio_pci_table,
1447 .probe = ni_pcimio_pci_probe,
1448 .remove = comedi_pci_auto_unconfig,
1449 };
1450 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1451
1452 MODULE_AUTHOR("Comedi http://www.comedi.org");
1453 MODULE_DESCRIPTION("Comedi low-level driver");
1454 MODULE_LICENSE("GPL");
1455
