1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_DP_TYPES_H 27 #define DC_DP_TYPES_H 28 29 #include "os_types.h" 30 31 enum dc_lane_count { 32 LANE_COUNT_UNKNOWN = 0, 33 LANE_COUNT_ONE = 1, 34 LANE_COUNT_TWO = 2, 35 LANE_COUNT_FOUR = 4, 36 LANE_COUNT_EIGHT = 8, 37 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 38 }; 39 40 /* This is actually a reference clock (27MHz) multiplier 41 * 162MBps bandwidth for 1.62GHz like rate, 42 * 270MBps for 2.70GHz, 43 * 324MBps for 3.24Ghz, 44 * 540MBps for 5.40GHz 45 * 810MBps for 8.10GHz 46 */ 47 enum dc_link_rate { 48 LINK_RATE_UNKNOWN = 0, 49 LINK_RATE_LOW = 0x06, 50 LINK_RATE_HIGH = 0x0A, 51 LINK_RATE_RBR2 = 0x0C, 52 LINK_RATE_HIGH2 = 0x14, 53 LINK_RATE_HIGH3 = 0x1E 54 }; 55 56 enum dc_link_spread { 57 LINK_SPREAD_DISABLED = 0x00, 58 /* 0.5 % downspread 30 kHz */ 59 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 60 /* 0.5 % downspread 33 kHz */ 61 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 62 }; 63 64 enum dc_voltage_swing { 65 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 66 VOLTAGE_SWING_LEVEL1, 67 VOLTAGE_SWING_LEVEL2, 68 VOLTAGE_SWING_LEVEL3, 69 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 70 }; 71 72 enum dc_pre_emphasis { 73 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 74 PRE_EMPHASIS_LEVEL1, 75 PRE_EMPHASIS_LEVEL2, 76 PRE_EMPHASIS_LEVEL3, 77 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 78 }; 79 /* Post Cursor 2 is optional for transmitter 80 * and it applies only to the main link operating at HBR2 81 */ 82 enum dc_post_cursor2 { 83 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 84 POST_CURSOR2_LEVEL1, 85 POST_CURSOR2_LEVEL2, 86 POST_CURSOR2_LEVEL3, 87 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 88 }; 89 90 struct dc_link_settings { 91 enum dc_lane_count lane_count; 92 enum dc_link_rate link_rate; 93 enum dc_link_spread link_spread; 94 }; 95 96 struct dc_lane_settings { 97 enum dc_voltage_swing VOLTAGE_SWING; 98 enum dc_pre_emphasis PRE_EMPHASIS; 99 enum dc_post_cursor2 POST_CURSOR2; 100 }; 101 102 struct dc_link_training_settings { 103 struct dc_link_settings link; 104 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; 105 }; 106 107 108 union dpcd_rev { 109 struct { 110 uint8_t MINOR:4; 111 uint8_t MAJOR:4; 112 } bits; 113 uint8_t raw; 114 }; 115 116 union max_lane_count { 117 struct { 118 uint8_t MAX_LANE_COUNT:5; 119 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 120 uint8_t TPS3_SUPPORTED:1; 121 uint8_t ENHANCED_FRAME_CAP:1; 122 } bits; 123 uint8_t raw; 124 }; 125 126 union max_down_spread { 127 struct { 128 uint8_t MAX_DOWN_SPREAD:1; 129 uint8_t RESERVED:5; 130 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 131 uint8_t TPS4_SUPPORTED:1; 132 } bits; 133 uint8_t raw; 134 }; 135 136 union mstm_cap { 137 struct { 138 uint8_t MST_CAP:1; 139 uint8_t RESERVED:7; 140 } bits; 141 uint8_t raw; 142 }; 143 144 union lane_count_set { 145 struct { 146 uint8_t LANE_COUNT_SET:5; 147 uint8_t POST_LT_ADJ_REQ_GRANTED:1; 148 uint8_t RESERVED:1; 149 uint8_t ENHANCED_FRAMING:1; 150 } bits; 151 uint8_t raw; 152 }; 153 154 union lane_status { 155 struct { 156 uint8_t CR_DONE_0:1; 157 uint8_t CHANNEL_EQ_DONE_0:1; 158 uint8_t SYMBOL_LOCKED_0:1; 159 uint8_t RESERVED0:1; 160 uint8_t CR_DONE_1:1; 161 uint8_t CHANNEL_EQ_DONE_1:1; 162 uint8_t SYMBOL_LOCKED_1:1; 163 uint8_t RESERVED_1:1; 164 } bits; 165 uint8_t raw; 166 }; 167 168 union device_service_irq { 169 struct { 170 uint8_t REMOTE_CONTROL_CMD_PENDING:1; 171 uint8_t AUTOMATED_TEST:1; 172 uint8_t CP_IRQ:1; 173 uint8_t MCCS_IRQ:1; 174 uint8_t DOWN_REP_MSG_RDY:1; 175 uint8_t UP_REQ_MSG_RDY:1; 176 uint8_t SINK_SPECIFIC:1; 177 uint8_t reserved:1; 178 } bits; 179 uint8_t raw; 180 }; 181 182 union sink_count { 183 struct { 184 uint8_t SINK_COUNT:6; 185 uint8_t CPREADY:1; 186 uint8_t RESERVED:1; 187 } bits; 188 uint8_t raw; 189 }; 190 191 union lane_align_status_updated { 192 struct { 193 uint8_t INTERLANE_ALIGN_DONE:1; 194 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 195 uint8_t RESERVED:4; 196 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 197 uint8_t LINK_STATUS_UPDATED:1; 198 } bits; 199 uint8_t raw; 200 }; 201 202 union lane_adjust { 203 struct { 204 uint8_t VOLTAGE_SWING_LANE:2; 205 uint8_t PRE_EMPHASIS_LANE:2; 206 uint8_t RESERVED:4; 207 } bits; 208 uint8_t raw; 209 }; 210 211 union dpcd_training_pattern { 212 struct { 213 uint8_t TRAINING_PATTERN_SET:4; 214 uint8_t RECOVERED_CLOCK_OUT_EN:1; 215 uint8_t SCRAMBLING_DISABLE:1; 216 uint8_t SYMBOL_ERROR_COUNT_SEL:2; 217 } v1_4; 218 struct { 219 uint8_t TRAINING_PATTERN_SET:2; 220 uint8_t LINK_QUAL_PATTERN_SET:2; 221 uint8_t RESERVED:4; 222 } v1_3; 223 uint8_t raw; 224 }; 225 226 /* Training Lane is used to configure downstream DP device's voltage swing 227 and pre-emphasis levels*/ 228 /* The DPCD addresses are from 0x103 to 0x106*/ 229 union dpcd_training_lane { 230 struct { 231 uint8_t VOLTAGE_SWING_SET:2; 232 uint8_t MAX_SWING_REACHED:1; 233 uint8_t PRE_EMPHASIS_SET:2; 234 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 235 uint8_t RESERVED:2; 236 } bits; 237 uint8_t raw; 238 }; 239 240 /* TMDS-converter related */ 241 union dwnstream_port_caps_byte0 { 242 struct { 243 uint8_t DWN_STRM_PORTX_TYPE:3; 244 uint8_t DWN_STRM_PORTX_HPD:1; 245 uint8_t RESERVERD:4; 246 } bits; 247 uint8_t raw; 248 }; 249 250 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 251 enum dpcd_downstream_port_detailed_type { 252 DOWN_STREAM_DETAILED_DP = 0, 253 DOWN_STREAM_DETAILED_VGA, 254 DOWN_STREAM_DETAILED_DVI, 255 DOWN_STREAM_DETAILED_HDMI, 256 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 257 DOWN_STREAM_DETAILED_DP_PLUS_PLUS 258 }; 259 260 union dwnstream_port_caps_byte2 { 261 struct { 262 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 263 uint8_t RESERVED:6; 264 } bits; 265 uint8_t raw; 266 }; 267 268 union dp_downstream_port_present { 269 uint8_t byte; 270 struct { 271 uint8_t PORT_PRESENT:1; 272 uint8_t PORT_TYPE:2; 273 uint8_t FMT_CONVERSION:1; 274 uint8_t DETAILED_CAPS:1; 275 uint8_t RESERVED:3; 276 } fields; 277 }; 278 279 union dwnstream_port_caps_byte3_dvi { 280 struct { 281 uint8_t RESERVED1:1; 282 uint8_t DUAL_LINK:1; 283 uint8_t HIGH_COLOR_DEPTH:1; 284 uint8_t RESERVED2:5; 285 } bits; 286 uint8_t raw; 287 }; 288 289 union dwnstream_port_caps_byte3_hdmi { 290 struct { 291 uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 292 uint8_t YCrCr422_PASS_THROUGH:1; 293 uint8_t YCrCr420_PASS_THROUGH:1; 294 uint8_t YCrCr422_CONVERSION:1; 295 uint8_t YCrCr420_CONVERSION:1; 296 uint8_t RESERVED:3; 297 } bits; 298 uint8_t raw; 299 }; 300 301 /*4-byte structure for detailed capabilities of a down-stream port 302 (DP-to-TMDS converter).*/ 303 union dwnstream_portxcaps { 304 struct { 305 union dwnstream_port_caps_byte0 byte0; 306 unsigned char max_TMDS_clock; //byte1 307 union dwnstream_port_caps_byte2 byte2; 308 309 union { 310 union dwnstream_port_caps_byte3_dvi byteDVI; 311 union dwnstream_port_caps_byte3_hdmi byteHDMI; 312 } byte3; 313 } bytes; 314 315 unsigned char raw[4]; 316 }; 317 318 union downstream_port { 319 struct { 320 unsigned char present:1; 321 unsigned char type:2; 322 unsigned char format_conv:1; 323 unsigned char detailed_caps:1; 324 unsigned char reserved:3; 325 } bits; 326 unsigned char raw; 327 }; 328 329 330 union sink_status { 331 struct { 332 uint8_t RX_PORT0_STATUS:1; 333 uint8_t RX_PORT1_STATUS:1; 334 uint8_t RESERVED:6; 335 } bits; 336 uint8_t raw; 337 }; 338 339 /*6-byte structure corresponding to 6 registers (200h-205h) 340 read during handling of HPD-IRQ*/ 341 union hpd_irq_data { 342 struct { 343 union sink_count sink_cnt;/* 200h */ 344 union device_service_irq device_service_irq;/* 201h */ 345 union lane_status lane01_status;/* 202h */ 346 union lane_status lane23_status;/* 203h */ 347 union lane_align_status_updated lane_status_updated;/* 204h */ 348 union sink_status sink_status; 349 } bytes; 350 uint8_t raw[6]; 351 }; 352 353 union down_stream_port_count { 354 struct { 355 uint8_t DOWN_STR_PORT_COUNT:4; 356 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 357 /*Bit 6 = MSA_TIMING_PAR_IGNORED 358 0 = Sink device requires the MSA timing parameters 359 1 = Sink device is capable of rendering incoming video 360 stream without MSA timing parameters*/ 361 uint8_t IGNORE_MSA_TIMING_PARAM:1; 362 /*Bit 7 = OUI Support 363 0 = OUI not supported 364 1 = OUI supported 365 (OUI and Device Identification mandatory for DP 1.2)*/ 366 uint8_t OUI_SUPPORT:1; 367 } bits; 368 uint8_t raw; 369 }; 370 371 union down_spread_ctrl { 372 struct { 373 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 374 /* Bits 4 = SPREAD_AMP. Spreading amplitude 375 0 = Main link signal is not downspread 376 1 = Main link signal is downspread <= 0.5% 377 with frequency in the range of 30kHz ~ 33kHz*/ 378 uint8_t SPREAD_AMP:1; 379 uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/ 380 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 381 0 = Source device will send valid data for the MSA Timing Params 382 1 = Source device may send invalid data for these MSA Timing Params*/ 383 uint8_t IGNORE_MSA_TIMING_PARAM:1; 384 } bits; 385 uint8_t raw; 386 }; 387 388 union dpcd_edp_config { 389 struct { 390 uint8_t PANEL_MODE_EDP:1; 391 uint8_t FRAMING_CHANGE_ENABLE:1; 392 uint8_t RESERVED:5; 393 uint8_t PANEL_SELF_TEST_ENABLE:1; 394 } bits; 395 uint8_t raw; 396 }; 397 398 struct dp_device_vendor_id { 399 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 400 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 401 }; 402 403 struct dp_sink_hw_fw_revision { 404 uint8_t ieee_hw_rev; 405 uint8_t ieee_fw_rev[2]; 406 }; 407 408 /*DPCD register of DP receiver capability field bits-*/ 409 union edp_configuration_cap { 410 struct { 411 uint8_t ALT_SCRAMBLER_RESET:1; 412 uint8_t FRAMING_CHANGE:1; 413 uint8_t RESERVED:1; 414 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 415 uint8_t RESERVED2:4; 416 } bits; 417 uint8_t raw; 418 }; 419 420 union training_aux_rd_interval { 421 struct { 422 uint8_t TRAINIG_AUX_RD_INTERVAL:7; 423 uint8_t EXT_RECIEVER_CAP_FIELD_PRESENT:1; 424 } bits; 425 uint8_t raw; 426 }; 427 428 /* Automated test structures */ 429 union test_request { 430 struct { 431 uint8_t LINK_TRAINING :1; 432 uint8_t LINK_TEST_PATTRN :1; 433 uint8_t EDID_READ :1; 434 uint8_t PHY_TEST_PATTERN :1; 435 uint8_t AUDIO_TEST_PATTERN :1; 436 uint8_t RESERVED :1; 437 uint8_t TEST_STEREO_3D :1; 438 } bits; 439 uint8_t raw; 440 }; 441 442 union test_response { 443 struct { 444 uint8_t ACK :1; 445 uint8_t NO_ACK :1; 446 uint8_t EDID_CHECKSUM_WRITE:1; 447 uint8_t RESERVED :5; 448 } bits; 449 uint8_t raw; 450 }; 451 452 union phy_test_pattern { 453 struct { 454 /* DpcdPhyTestPatterns. This field is 2 bits for DP1.1 455 * and 3 bits for DP1.2. 456 */ 457 uint8_t PATTERN :3; 458 /* BY speci, bit7:2 is 0 for DP1.1. */ 459 uint8_t RESERVED :5; 460 } bits; 461 uint8_t raw; 462 }; 463 464 /* States of Compliance Test Specification (CTS DP1.2). */ 465 union compliance_test_state { 466 struct { 467 unsigned char STEREO_3D_RUNNING : 1; 468 unsigned char RESERVED : 7; 469 } bits; 470 unsigned char raw; 471 }; 472 473 union link_test_pattern { 474 struct { 475 /* dpcd_link_test_patterns */ 476 unsigned char PATTERN :2; 477 unsigned char RESERVED:6; 478 } bits; 479 unsigned char raw; 480 }; 481 482 union test_misc { 483 struct dpcd_test_misc_bits { 484 unsigned char SYNC_CLOCK :1; 485 /* dpcd_test_color_format */ 486 unsigned char CLR_FORMAT :2; 487 /* dpcd_test_dyn_range */ 488 unsigned char DYN_RANGE :1; 489 unsigned char YCBCR :1; 490 /* dpcd_test_bit_depth */ 491 unsigned char BPC :3; 492 } bits; 493 unsigned char raw; 494 }; 495 496 #endif /* DC_DP_TYPES_H */ 497
