1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7 #define _SDIO_HALINIT_C_
8
9 #include <drv_types.h>
10 #include <rtw_debug.h>
11 #include <rtl8723b_hal.h>
12
13 #include "hal_com_h2c.h"
14 /*
15 * Description:
16 *Call power on sequence to enable card
17 *
18 * Return:
19 *_SUCCESS enable success
20 *_FAIL enable fail
21 */
CardEnable(struct adapter * padapter)22 static u8 CardEnable(struct adapter *padapter)
23 {
24 u8 bMacPwrCtrlOn;
25 u8 ret = _FAIL;
26
27
28 rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
29 if (!bMacPwrCtrlOn) {
30 /* RSV_CTRL 0x1C[7:0] = 0x00 */
31 /* unlock ISO/CLK/Power control register */
32 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
33
34 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_enable_flow);
35 if (ret == _SUCCESS) {
36 u8 bMacPwrCtrlOn = true;
37 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
38 }
39 } else
40 ret = _SUCCESS;
41
42 return ret;
43 }
44
45 #ifdef CONFIG_GPIO_WAKEUP
46 /* we set it high under init and fw will */
47 /* give us Low Pulse when host wake up */
HostWakeUpGpioClear(struct adapter * Adapter)48 void HostWakeUpGpioClear(struct adapter *Adapter)
49 {
50 u32 value32;
51
52 value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL_2);
53
54 /* set GPIO 12 1 */
55 value32 |= BIT(12);/* 4+8 */
56 /* GPIO 12 out put */
57 value32 |= BIT(20);/* 4+16 */
58
59 rtw_write32(Adapter, REG_GPIO_PIN_CTRL_2, value32);
60 } /* HostWakeUpGpioClear */
61
HalSetOutPutGPIO(struct adapter * padapter,u8 index,u8 OutPutValue)62 void HalSetOutPutGPIO(struct adapter *padapter, u8 index, u8 OutPutValue)
63 {
64 if (index <= 7) {
65 /* config GPIO mode */
66 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
67
68 /* config GPIO Sel */
69 /* 0: input */
70 /* 1: output */
71 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index));
72
73 /* set output value */
74 if (OutPutValue)
75 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index));
76 else
77 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index));
78 } else {
79 /* 88C Series: */
80 /* index: 11~8 transform to 3~0 */
81 /* 8723 Series: */
82 /* index: 12~8 transform to 4~0 */
83 index -= 8;
84
85 /* config GPIO mode */
86 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
87
88 /* config GPIO Sel */
89 /* 0: input */
90 /* 1: output */
91 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index));
92
93 /* set output value */
94 if (OutPutValue)
95 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index));
96 else
97 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index));
98 }
99 }
100 #endif
101
102 static
_InitPowerOn_8723BS(struct adapter * padapter)103 u8 _InitPowerOn_8723BS(struct adapter *padapter)
104 {
105 u8 value8;
106 u16 value16;
107 u32 value32;
108 u8 ret;
109 /* u8 bMacPwrCtrlOn; */
110
111
112 /* all of these MUST be configured before power on */
113 #ifdef CONFIG_EXT_CLK
114 /* Use external crystal(XTAL) */
115 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B + 2);
116 value8 |= BIT(7);
117 rtw_write8(padapter, REG_PAD_CTRL1_8723B + 2, value8);
118
119 /* CLK_REQ High active or Low Active */
120 /* Request GPIO polarity: */
121 /* 0: low active */
122 /* 1: high active */
123 value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL + 1);
124 value8 |= BIT(5);
125 rtw_write8(padapter, REG_MULTI_FUNC_CTRL + 1, value8);
126 #endif /* CONFIG_EXT_CLK */
127
128 /* only cmd52 can be used before power on(card enable) */
129 ret = CardEnable(padapter);
130 if (!ret) {
131 RT_TRACE(
132 _module_hci_hal_init_c_,
133 _drv_emerg_,
134 ("%s: run power on flow fail\n", __func__)
135 );
136 return _FAIL;
137 }
138
139 /* Radio-Off Pin Trigger */
140 value8 = rtw_read8(padapter, REG_GPIO_INTM + 1);
141 value8 |= BIT(1); /* Enable falling edge triggering interrupt */
142 rtw_write8(padapter, REG_GPIO_INTM + 1, value8);
143 value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1);
144 value8 |= BIT(1);
145 rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8);
146
147 /* Enable power down and GPIO interrupt */
148 value16 = rtw_read16(padapter, REG_APS_FSMCO);
149 value16 |= EnPDN; /* Enable HW power down and RF on */
150 rtw_write16(padapter, REG_APS_FSMCO, value16);
151
152 /* Enable CMD53 R/W Operation */
153 /* bMacPwrCtrlOn = true; */
154 /* rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */
155
156 rtw_write8(padapter, REG_CR, 0x00);
157 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
158 value16 = rtw_read16(padapter, REG_CR);
159 value16 |= (
160 HCI_TXDMA_EN |
161 HCI_RXDMA_EN |
162 TXDMA_EN |
163 RXDMA_EN |
164 PROTOCOL_EN |
165 SCHEDULE_EN |
166 ENSEC |
167 CALTMR_EN
168 );
169 rtw_write16(padapter, REG_CR, value16);
170
171 hal_btcoex_PowerOnSetting(padapter);
172
173 /* external switch to S1 */
174 /* 0x38[11] = 0x1 */
175 /* 0x4c[23] = 0x1 */
176 /* 0x64[0] = 0 */
177 value16 = rtw_read16(padapter, REG_PWR_DATA);
178 /* Switch the control of EESK, EECS to RFC for DPDT or Antenna switch */
179 value16 |= BIT(11); /* BIT_EEPRPAD_RFE_CTRL_EN */
180 rtw_write16(padapter, REG_PWR_DATA, value16);
181 /* DBG_8192C("%s: REG_PWR_DATA(0x%x) = 0x%04X\n", __func__, REG_PWR_DATA, rtw_read16(padapter, REG_PWR_DATA)); */
182
183 value32 = rtw_read32(padapter, REG_LEDCFG0);
184 value32 |= BIT(23); /* DPDT_SEL_EN, 1 for SW control */
185 rtw_write32(padapter, REG_LEDCFG0, value32);
186 /* DBG_8192C("%s: REG_LEDCFG0(0x%x) = 0x%08X\n", __func__, REG_LEDCFG0, rtw_read32(padapter, REG_LEDCFG0)); */
187
188 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B);
189 value8 &= ~BIT(0); /* BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration */
190 rtw_write8(padapter, REG_PAD_CTRL1_8723B, value8);
191 /* DBG_8192C("%s: REG_PAD_CTRL1(0x%x) = 0x%02X\n", __func__, REG_PAD_CTRL1_8723B, rtw_read8(padapter, REG_PAD_CTRL1_8723B)); */
192
193 #ifdef CONFIG_GPIO_WAKEUP
194 HostWakeUpGpioClear(padapter);
195 #endif
196
197 return _SUCCESS;
198 }
199
200 /* Tx Page FIFO threshold */
_init_available_page_threshold(struct adapter * padapter,u8 numHQ,u8 numNQ,u8 numLQ,u8 numPubQ)201 static void _init_available_page_threshold(struct adapter *padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ)
202 {
203 u16 HQ_threshold, NQ_threshold, LQ_threshold;
204
205 HQ_threshold = (numPubQ + numHQ + 1) >> 1;
206 HQ_threshold |= (HQ_threshold << 8);
207
208 NQ_threshold = (numPubQ + numNQ + 1) >> 1;
209 NQ_threshold |= (NQ_threshold << 8);
210
211 LQ_threshold = (numPubQ + numLQ + 1) >> 1;
212 LQ_threshold |= (LQ_threshold << 8);
213
214 rtw_write16(padapter, 0x218, HQ_threshold);
215 rtw_write16(padapter, 0x21A, NQ_threshold);
216 rtw_write16(padapter, 0x21C, LQ_threshold);
217 DBG_8192C("%s(): Enable Tx FIFO Page Threshold H:0x%x, N:0x%x, L:0x%x\n", __func__, HQ_threshold, NQ_threshold, LQ_threshold);
218 }
219
_InitQueueReservedPage(struct adapter * padapter)220 static void _InitQueueReservedPage(struct adapter *padapter)
221 {
222 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
223 struct registry_priv *pregistrypriv = &padapter->registrypriv;
224 u32 numHQ = 0;
225 u32 numLQ = 0;
226 u32 numNQ = 0;
227 u32 numPubQ;
228 u32 value32;
229 u8 value8;
230 bool bWiFiConfig = pregistrypriv->wifi_spec;
231
232 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
233 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723B : NORMAL_PAGE_NUM_HPQ_8723B;
234
235 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
236 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723B : NORMAL_PAGE_NUM_LPQ_8723B;
237
238 /* NOTE: This step shall be proceed before writting REG_RQPN. */
239 if (pHalData->OutEpQueueSel & TX_SELE_NQ)
240 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723B : NORMAL_PAGE_NUM_NPQ_8723B;
241
242 numPubQ = TX_TOTAL_PAGE_NUMBER_8723B - numHQ - numLQ - numNQ;
243
244 value8 = (u8)_NPQ(numNQ);
245 rtw_write8(padapter, REG_RQPN_NPQ, value8);
246
247 /* TX DMA */
248 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
249 rtw_write32(padapter, REG_RQPN, value32);
250
251 rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ);
252
253 _init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ);
254 }
255
_InitTxBufferBoundary(struct adapter * padapter)256 static void _InitTxBufferBoundary(struct adapter *padapter)
257 {
258 struct registry_priv *pregistrypriv = &padapter->registrypriv;
259
260 /* u16 txdmactrl; */
261 u8 txpktbuf_bndy;
262
263 if (!pregistrypriv->wifi_spec) {
264 txpktbuf_bndy = TX_PAGE_BOUNDARY_8723B;
265 } else {
266 /* for WMM */
267 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
268 }
269
270 rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723B, txpktbuf_bndy);
271 rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy);
272 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy);
273 rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
274 rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
275 }
276
_InitNormalChipRegPriority(struct adapter * Adapter,u16 beQ,u16 bkQ,u16 viQ,u16 voQ,u16 mgtQ,u16 hiQ)277 static void _InitNormalChipRegPriority(
278 struct adapter *Adapter,
279 u16 beQ,
280 u16 bkQ,
281 u16 viQ,
282 u16 voQ,
283 u16 mgtQ,
284 u16 hiQ
285 )
286 {
287 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
288
289 value16 |=
290 _TXDMA_BEQ_MAP(beQ) |
291 _TXDMA_BKQ_MAP(bkQ) |
292 _TXDMA_VIQ_MAP(viQ) |
293 _TXDMA_VOQ_MAP(voQ) |
294 _TXDMA_MGQ_MAP(mgtQ) |
295 _TXDMA_HIQ_MAP(hiQ);
296
297 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
298 }
299
_InitNormalChipOneOutEpPriority(struct adapter * Adapter)300 static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
301 {
302 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
303
304 u16 value = 0;
305 switch (pHalData->OutEpQueueSel) {
306 case TX_SELE_HQ:
307 value = QUEUE_HIGH;
308 break;
309 case TX_SELE_LQ:
310 value = QUEUE_LOW;
311 break;
312 case TX_SELE_NQ:
313 value = QUEUE_NORMAL;
314 break;
315 default:
316 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
317 break;
318 }
319
320 _InitNormalChipRegPriority(
321 Adapter, value, value, value, value, value, value
322 );
323
324 }
325
_InitNormalChipTwoOutEpPriority(struct adapter * Adapter)326 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
327 {
328 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
329 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
330 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
331
332
333 u16 valueHi = 0;
334 u16 valueLow = 0;
335
336 switch (pHalData->OutEpQueueSel) {
337 case (TX_SELE_HQ | TX_SELE_LQ):
338 valueHi = QUEUE_HIGH;
339 valueLow = QUEUE_LOW;
340 break;
341 case (TX_SELE_NQ | TX_SELE_LQ):
342 valueHi = QUEUE_NORMAL;
343 valueLow = QUEUE_LOW;
344 break;
345 case (TX_SELE_HQ | TX_SELE_NQ):
346 valueHi = QUEUE_HIGH;
347 valueLow = QUEUE_NORMAL;
348 break;
349 default:
350 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
351 break;
352 }
353
354 if (!pregistrypriv->wifi_spec) {
355 beQ = valueLow;
356 bkQ = valueLow;
357 viQ = valueHi;
358 voQ = valueHi;
359 mgtQ = valueHi;
360 hiQ = valueHi;
361 } else {
362 /* for WMM , CONFIG_OUT_EP_WIFI_MODE */
363 beQ = valueLow;
364 bkQ = valueHi;
365 viQ = valueHi;
366 voQ = valueLow;
367 mgtQ = valueHi;
368 hiQ = valueHi;
369 }
370
371 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
372
373 }
374
_InitNormalChipThreeOutEpPriority(struct adapter * padapter)375 static void _InitNormalChipThreeOutEpPriority(struct adapter *padapter)
376 {
377 struct registry_priv *pregistrypriv = &padapter->registrypriv;
378 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
379
380 if (!pregistrypriv->wifi_spec) {
381 /* typical setting */
382 beQ = QUEUE_LOW;
383 bkQ = QUEUE_LOW;
384 viQ = QUEUE_NORMAL;
385 voQ = QUEUE_HIGH;
386 mgtQ = QUEUE_HIGH;
387 hiQ = QUEUE_HIGH;
388 } else {
389 /* for WMM */
390 beQ = QUEUE_LOW;
391 bkQ = QUEUE_NORMAL;
392 viQ = QUEUE_NORMAL;
393 voQ = QUEUE_HIGH;
394 mgtQ = QUEUE_HIGH;
395 hiQ = QUEUE_HIGH;
396 }
397 _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
398 }
399
_InitQueuePriority(struct adapter * Adapter)400 static void _InitQueuePriority(struct adapter *Adapter)
401 {
402 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
403
404 switch (pHalData->OutEpNumber) {
405 case 1:
406 _InitNormalChipOneOutEpPriority(Adapter);
407 break;
408 case 2:
409 _InitNormalChipTwoOutEpPriority(Adapter);
410 break;
411 case 3:
412 _InitNormalChipThreeOutEpPriority(Adapter);
413 break;
414 default:
415 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
416 break;
417 }
418
419
420 }
421
_InitPageBoundary(struct adapter * padapter)422 static void _InitPageBoundary(struct adapter *padapter)
423 {
424 /* RX Page Boundary */
425 u16 rxff_bndy = RX_DMA_BOUNDARY_8723B;
426
427 rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
428 }
429
_InitTransferPageSize(struct adapter * padapter)430 static void _InitTransferPageSize(struct adapter *padapter)
431 {
432 /* Tx page size is always 128. */
433
434 u8 value8;
435 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
436 rtw_write8(padapter, REG_PBP, value8);
437 }
438
_InitDriverInfoSize(struct adapter * padapter,u8 drvInfoSize)439 static void _InitDriverInfoSize(struct adapter *padapter, u8 drvInfoSize)
440 {
441 rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
442 }
443
_InitNetworkType(struct adapter * padapter)444 static void _InitNetworkType(struct adapter *padapter)
445 {
446 u32 value32;
447
448 value32 = rtw_read32(padapter, REG_CR);
449
450 /* TODO: use the other function to set network type */
451 /* value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
452 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
453
454 rtw_write32(padapter, REG_CR, value32);
455 }
456
_InitWMACSetting(struct adapter * padapter)457 static void _InitWMACSetting(struct adapter *padapter)
458 {
459 struct hal_com_data *pHalData;
460 u16 value16;
461
462
463 pHalData = GET_HAL_DATA(padapter);
464
465 pHalData->ReceiveConfig = 0;
466 pHalData->ReceiveConfig |= RCR_APM | RCR_AM | RCR_AB;
467 pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF;
468 pHalData->ReceiveConfig |= RCR_HTC_LOC_CTRL;
469 pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
470 rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig);
471
472 /* Accept all multicast address */
473 rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
474 rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
475
476 /* Accept all data frames */
477 value16 = 0xFFFF;
478 rtw_write16(padapter, REG_RXFLTMAP2, value16);
479
480 /* 2010.09.08 hpfan */
481 /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
482 /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
483 value16 = 0x400;
484 rtw_write16(padapter, REG_RXFLTMAP1, value16);
485
486 /* Accept all management frames */
487 value16 = 0xFFFF;
488 rtw_write16(padapter, REG_RXFLTMAP0, value16);
489 }
490
_InitAdaptiveCtrl(struct adapter * padapter)491 static void _InitAdaptiveCtrl(struct adapter *padapter)
492 {
493 u16 value16;
494 u32 value32;
495
496 /* Response Rate Set */
497 value32 = rtw_read32(padapter, REG_RRSR);
498 value32 &= ~RATE_BITMAP_ALL;
499 value32 |= RATE_RRSR_CCK_ONLY_1M;
500 rtw_write32(padapter, REG_RRSR, value32);
501
502 /* CF-END Threshold */
503 /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
504
505 /* SIFS (used in NAV) */
506 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
507 rtw_write16(padapter, REG_SPEC_SIFS, value16);
508
509 /* Retry Limit */
510 value16 = _LRL(0x30) | _SRL(0x30);
511 rtw_write16(padapter, REG_RL, value16);
512 }
513
_InitEDCA(struct adapter * padapter)514 static void _InitEDCA(struct adapter *padapter)
515 {
516 /* Set Spec SIFS (used in NAV) */
517 rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
518 rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
519
520 /* Set SIFS for CCK */
521 rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
522
523 /* Set SIFS for OFDM */
524 rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
525
526 /* TXOP */
527 rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
528 rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
529 rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
530 rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
531 }
532
_InitRetryFunction(struct adapter * padapter)533 static void _InitRetryFunction(struct adapter *padapter)
534 {
535 u8 value8;
536
537 value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
538 value8 |= EN_AMPDU_RTY_NEW;
539 rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
540
541 /* Set ACK timeout */
542 rtw_write8(padapter, REG_ACKTO, 0x40);
543 }
544
HalRxAggr8723BSdio(struct adapter * padapter)545 static void HalRxAggr8723BSdio(struct adapter *padapter)
546 {
547 struct registry_priv *pregistrypriv;
548 u8 valueDMATimeout;
549 u8 valueDMAPageCount;
550
551
552 pregistrypriv = &padapter->registrypriv;
553
554 if (pregistrypriv->wifi_spec) {
555 /* 2010.04.27 hpfan */
556 /* Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer */
557 /* Timeout value is calculated by 34 / (2^n) */
558 valueDMATimeout = 0x06;
559 valueDMAPageCount = 0x06;
560 } else {
561 /* 20130530, Isaac@SD1 suggest 3 kinds of parameter */
562 /* TX/RX Balance */
563 valueDMATimeout = 0x06;
564 valueDMAPageCount = 0x06;
565 }
566
567 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 1, valueDMATimeout);
568 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
569 }
570
sdio_AggSettingRxUpdate(struct adapter * padapter)571 static void sdio_AggSettingRxUpdate(struct adapter *padapter)
572 {
573 struct hal_com_data *pHalData;
574 u8 valueDMA;
575 u8 valueRxAggCtrl = 0;
576 u8 aggBurstNum = 3; /* 0:1, 1:2, 2:3, 3:4 */
577 u8 aggBurstSize = 0; /* 0:1K, 1:512Byte, 2:256Byte... */
578
579 pHalData = GET_HAL_DATA(padapter);
580
581 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
582 valueDMA |= RXDMA_AGG_EN;
583 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
584
585 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
586 valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C);
587 valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30);
588 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
589 }
590
_initSdioAggregationSetting(struct adapter * padapter)591 static void _initSdioAggregationSetting(struct adapter *padapter)
592 {
593 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
594
595 /* Tx aggregation setting */
596 /* sdio_AggSettingTxUpdate(padapter); */
597
598 /* Rx aggregation setting */
599 HalRxAggr8723BSdio(padapter);
600
601 sdio_AggSettingRxUpdate(padapter);
602
603 /* 201/12/10 MH Add for USB agg mode dynamic switch. */
604 pHalData->UsbRxHighSpeedMode = false;
605 }
606
_InitOperationMode(struct adapter * padapter)607 static void _InitOperationMode(struct adapter *padapter)
608 {
609 struct mlme_ext_priv *pmlmeext;
610 u8 regBwOpMode = 0;
611
612 pmlmeext = &padapter->mlmeextpriv;
613
614 /* 1 This part need to modified according to the rate set we filtered!! */
615 /* */
616 /* Set RRSR, RATR, and REG_BWOPMODE registers */
617 /* */
618 switch (pmlmeext->cur_wireless_mode) {
619 case WIRELESS_MODE_B:
620 regBwOpMode = BW_OPMODE_20MHZ;
621 break;
622 case WIRELESS_MODE_A:
623 /* RT_ASSERT(false, ("Error wireless a mode\n")); */
624 break;
625 case WIRELESS_MODE_G:
626 regBwOpMode = BW_OPMODE_20MHZ;
627 break;
628 case WIRELESS_MODE_AUTO:
629 regBwOpMode = BW_OPMODE_20MHZ;
630 break;
631 case WIRELESS_MODE_N_24G:
632 /* It support CCK rate by default. */
633 /* CCK rate will be filtered out only when associated AP does not support it. */
634 regBwOpMode = BW_OPMODE_20MHZ;
635 break;
636 case WIRELESS_MODE_N_5G:
637 /* RT_ASSERT(false, ("Error wireless mode")); */
638 regBwOpMode = BW_OPMODE_5G;
639 break;
640
641 default: /* for MacOSX compiler warning. */
642 break;
643 }
644
645 rtw_write8(padapter, REG_BWOPMODE, regBwOpMode);
646
647 }
648
_InitInterrupt(struct adapter * padapter)649 static void _InitInterrupt(struct adapter *padapter)
650 {
651 /* HISR - turn all off */
652 rtw_write32(padapter, REG_HISR, 0);
653
654 /* HIMR - turn all off */
655 rtw_write32(padapter, REG_HIMR, 0);
656
657 /* */
658 /* Initialize and enable SDIO Host Interrupt. */
659 /* */
660 InitInterrupt8723BSdio(padapter);
661
662 /* */
663 /* Initialize system Host Interrupt. */
664 /* */
665 InitSysInterrupt8723BSdio(padapter);
666 }
667
_InitRFType(struct adapter * padapter)668 static void _InitRFType(struct adapter *padapter)
669 {
670 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
671
672 #if DISABLE_BB_RF
673 pHalData->rf_chip = RF_PSEUDO_11N;
674 return;
675 #endif
676
677 pHalData->rf_chip = RF_6052;
678
679 pHalData->rf_type = RF_1T1R;
680 DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
681 }
682
_RfPowerSave(struct adapter * padapter)683 static void _RfPowerSave(struct adapter *padapter)
684 {
685 /* YJ, TODO */
686 }
687
688 /* */
689 /* 2010/08/09 MH Add for power down check. */
690 /* */
HalDetectPwrDownMode(struct adapter * Adapter)691 static bool HalDetectPwrDownMode(struct adapter *Adapter)
692 {
693 u8 tmpvalue;
694 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
695 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
696
697
698 EFUSE_ShadowRead(Adapter, 1, 0x7B/*EEPROM_RF_OPT3_92C*/, (u32 *)&tmpvalue);
699
700 /* 2010/08/25 MH INF priority > PDN Efuse value. */
701 if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
702 pHalData->pwrdown = true;
703 else
704 pHalData->pwrdown = false;
705
706 DBG_8192C("HalDetectPwrDownMode(): PDN =%d\n", pHalData->pwrdown);
707
708 return pHalData->pwrdown;
709 } /* HalDetectPwrDownMode */
710
rtl8723bs_hal_init(struct adapter * padapter)711 static u32 rtl8723bs_hal_init(struct adapter *padapter)
712 {
713 s32 ret;
714 struct hal_com_data *pHalData;
715 struct pwrctrl_priv *pwrctrlpriv;
716 struct registry_priv *pregistrypriv;
717 u32 NavUpper = WiFiNavUpperUs;
718 u8 u1bTmp;
719
720 pHalData = GET_HAL_DATA(padapter);
721 pwrctrlpriv = adapter_to_pwrctl(padapter);
722 pregistrypriv = &padapter->registrypriv;
723
724 if (
725 adapter_to_pwrctl(padapter)->bips_processing == true &&
726 adapter_to_pwrctl(padapter)->pre_ips_type == 0
727 ) {
728 unsigned long start_time;
729 u8 cpwm_orig, cpwm_now;
730 u8 val8, bMacPwrCtrlOn = true;
731
732 DBG_871X("%s: Leaving IPS in FWLPS state\n", __func__);
733
734 /* for polling cpwm */
735 cpwm_orig = 0;
736 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
737
738 /* ser rpwm */
739 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
740 val8 &= 0x80;
741 val8 += 0x80;
742 val8 |= BIT(6);
743 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
744 DBG_871X("%s: write rpwm =%02x\n", __func__, val8);
745 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
746
747 /* do polling cpwm */
748 start_time = jiffies;
749 do {
750
751 mdelay(1);
752
753 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
754 if ((cpwm_orig ^ cpwm_now) & 0x80)
755 break;
756
757 if (jiffies_to_msecs(jiffies - start_time) > 100) {
758 DBG_871X("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __func__);
759 break;
760 }
761 } while (1);
762
763 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0);
764
765 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
766
767 hal_btcoex_InitHwConfig(padapter, false);
768
769 return _SUCCESS;
770 }
771
772 #ifdef CONFIG_WOWLAN
773 if (rtw_read8(padapter, REG_MCUFWDL) & BIT7) {
774 u8 reg_val = 0;
775 DBG_871X("+Reset Entry+\n");
776 rtw_write8(padapter, REG_MCUFWDL, 0x00);
777 _8051Reset8723(padapter);
778 /* reset BB */
779 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN);
780 reg_val &= ~(BIT(0) | BIT(1));
781 rtw_write8(padapter, REG_SYS_FUNC_EN, reg_val);
782 /* reset RF */
783 rtw_write8(padapter, REG_RF_CTRL, 0);
784 /* reset TRX path */
785 rtw_write16(padapter, REG_CR, 0);
786 /* reset MAC, Digital Core */
787 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
788 reg_val &= ~(BIT(4) | BIT(7));
789 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, reg_val);
790 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
791 reg_val |= BIT(4) | BIT(7);
792 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, reg_val);
793 DBG_871X("-Reset Entry-\n");
794 }
795 #endif /* CONFIG_WOWLAN */
796 /* Disable Interrupt first. */
797 /* rtw_hal_disable_interrupt(padapter); */
798
799 ret = _InitPowerOn_8723BS(padapter);
800 if (_FAIL == ret) {
801 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init Power On!\n"));
802 return _FAIL;
803 }
804
805 rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
806
807 ret = rtl8723b_FirmwareDownload(padapter, false);
808 if (ret != _SUCCESS) {
809 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: Download Firmware failed!!\n", __func__));
810 padapter->bFWReady = false;
811 pHalData->fw_ractrl = false;
812 return ret;
813 } else {
814 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("rtl8723bs_hal_init(): Download Firmware Success!!\n"));
815 padapter->bFWReady = true;
816 pHalData->fw_ractrl = true;
817 }
818
819 rtl8723b_InitializeFirmwareVars(padapter);
820
821 /* SIC_Init(padapter); */
822
823 if (pwrctrlpriv->reg_rfoff)
824 pwrctrlpriv->rf_pwrstate = rf_off;
825
826 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
827 /* HW GPIO pin. Before PHY_RFConfig8192C. */
828 HalDetectPwrDownMode(padapter);
829
830 /* Set RF type for BB/RF configuration */
831 _InitRFType(padapter);
832
833 /* Save target channel */
834 /* <Roger_Notes> Current Channel will be updated again later. */
835 pHalData->CurrentChannel = 6;
836
837 #if (HAL_MAC_ENABLE == 1)
838 ret = PHY_MACConfig8723B(padapter);
839 if (ret != _SUCCESS) {
840 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure MAC!!\n"));
841 return ret;
842 }
843 #endif
844 /* */
845 /* d. Initialize BB related configurations. */
846 /* */
847 #if (HAL_BB_ENABLE == 1)
848 ret = PHY_BBConfig8723B(padapter);
849 if (ret != _SUCCESS) {
850 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure BB!!\n"));
851 return ret;
852 }
853 #endif
854
855 /* If RF is on, we need to init RF. Otherwise, skip the procedure. */
856 /* We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
857 /* if (pHalData->eRFPowerState == eRfOn) */
858 {
859 #if (HAL_RF_ENABLE == 1)
860 ret = PHY_RFConfig8723B(padapter);
861 if (ret != _SUCCESS) {
862 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure RF!!\n"));
863 return ret;
864 }
865 #endif
866 }
867
868 /* */
869 /* Joseph Note: Keep RfRegChnlVal for later use. */
870 /* */
871 pHalData->RfRegChnlVal[0] =
872 PHY_QueryRFReg(padapter, (enum RF_PATH)0, RF_CHNLBW, bRFRegOffsetMask);
873 pHalData->RfRegChnlVal[1] =
874 PHY_QueryRFReg(padapter, (enum RF_PATH)1, RF_CHNLBW, bRFRegOffsetMask);
875
876
877 /* if (!pHalData->bMACFuncEnable) { */
878 _InitQueueReservedPage(padapter);
879 _InitTxBufferBoundary(padapter);
880
881 /* init LLT after tx buffer boundary is defined */
882 ret = rtl8723b_InitLLTTable(padapter);
883 if (_SUCCESS != ret) {
884 DBG_8192C("%s: Failed to init LLT Table!\n", __func__);
885 return _FAIL;
886 }
887 /* */
888 _InitQueuePriority(padapter);
889 _InitPageBoundary(padapter);
890 _InitTransferPageSize(padapter);
891
892 /* Get Rx PHY status in order to report RSSI and others. */
893 _InitDriverInfoSize(padapter, DRVINFO_SZ);
894 hal_init_macaddr(padapter);
895 _InitNetworkType(padapter);
896 _InitWMACSetting(padapter);
897 _InitAdaptiveCtrl(padapter);
898 _InitEDCA(padapter);
899 _InitRetryFunction(padapter);
900 _initSdioAggregationSetting(padapter);
901 _InitOperationMode(padapter);
902 rtl8723b_InitBeaconParameters(padapter);
903 _InitInterrupt(padapter);
904 _InitBurstPktLen_8723BS(padapter);
905
906 /* YJ, TODO */
907 rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723B, 0x3); /* CCA */
908 rtw_write8(padapter, 0x976, 0); /* hpfan_todo: 2nd CCA related */
909
910 rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
911 rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
912
913 invalidate_cam_all(padapter);
914
915 rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
916 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
917
918 /* Record original value for template. This is arough data, we can only use the data */
919 /* for power adjust. The value can not be adjustde according to different power!!! */
920 /* pHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx; */
921 /* pHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx; */
922
923 rtl8723b_InitAntenna_Selection(padapter);
924
925 /* */
926 /* Disable BAR, suggested by Scott */
927 /* 2010.04.09 add by hpfan */
928 /* */
929 rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
930
931 /* HW SEQ CTRL */
932 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
933 rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
934
935
936 /* */
937 /* Configure SDIO TxRx Control to enable Rx DMA timer masking. */
938 /* 2010.02.24. */
939 /* */
940 rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0);
941
942 _RfPowerSave(padapter);
943
944
945 rtl8723b_InitHalDm(padapter);
946
947 /* DbgPrint("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */
948
949 /* */
950 /* Update current Tx FIFO page status. */
951 /* */
952 HalQueryTxBufferStatus8723BSdio(padapter);
953 HalQueryTxOQTBufferStatus8723BSdio(padapter);
954 pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
955
956 /* Enable MACTXEN/MACRXEN block */
957 u1bTmp = rtw_read8(padapter, REG_CR);
958 u1bTmp |= (MACTXEN | MACRXEN);
959 rtw_write8(padapter, REG_CR, u1bTmp);
960
961 rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
962
963 /* ack for xmit mgmt frames. */
964 rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
965
966 /* pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
967
968 {
969 pwrctrlpriv->rf_pwrstate = rf_on;
970
971 if (pwrctrlpriv->rf_pwrstate == rf_on) {
972 struct pwrctrl_priv *pwrpriv;
973 unsigned long start_time;
974 u8 restore_iqk_rst;
975 u8 b2Ant;
976 u8 h2cCmdBuf;
977
978 pwrpriv = adapter_to_pwrctl(padapter);
979
980 PHY_LCCalibrate_8723B(&pHalData->odmpriv);
981
982 /* Inform WiFi FW that it is the beginning of IQK */
983 h2cCmdBuf = 1;
984 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
985
986 start_time = jiffies;
987 do {
988 if (rtw_read8(padapter, 0x1e7) & 0x01)
989 break;
990
991 msleep(50);
992 } while (jiffies_to_msecs(jiffies - start_time) <= 400);
993
994 hal_btcoex_IQKNotify(padapter, true);
995
996 restore_iqk_rst = pwrpriv->bips_processing;
997 b2Ant = pHalData->EEPROMBluetoothAntNum == Ant_x2;
998 PHY_IQCalibrate_8723B(padapter, false, restore_iqk_rst, b2Ant, pHalData->ant_path);
999 pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
1000
1001 hal_btcoex_IQKNotify(padapter, false);
1002
1003 /* Inform WiFi FW that it is the finish of IQK */
1004 h2cCmdBuf = 0;
1005 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1006
1007 ODM_TXPowerTrackingCheck(&pHalData->odmpriv);
1008 }
1009 }
1010
1011 /* Init BT hw config. */
1012 hal_btcoex_InitHwConfig(padapter, false);
1013
1014 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("-%s\n", __func__));
1015
1016 return _SUCCESS;
1017 }
1018
1019 /* */
1020 /* Description: */
1021 /* RTL8723e card disable power sequence v003 which suggested by Scott. */
1022 /* */
1023 /* First created by tynli. 2011.01.28. */
1024 /* */
CardDisableRTL8723BSdio(struct adapter * padapter)1025 static void CardDisableRTL8723BSdio(struct adapter *padapter)
1026 {
1027 u8 u1bTmp;
1028 u8 bMacPwrCtrlOn;
1029 u8 ret = _FAIL;
1030
1031 /* Run LPS WL RFOFF flow */
1032 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_enter_lps_flow);
1033 if (ret == _FAIL) {
1034 DBG_8192C(KERN_ERR "%s: run RF OFF flow fail!\n", __func__);
1035 }
1036
1037 /* ==== Reset digital sequence ====== */
1038
1039 u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
1040 if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) /* 8051 RAM code */
1041 rtl8723b_FirmwareSelfReset(padapter);
1042
1043 /* Reset MCU 0x2[10]= 0. Suggested by Filen. 2011.01.26. by tynli. */
1044 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
1045 u1bTmp &= ~BIT(2); /* 0x2[10], FEN_CPUEN */
1046 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp);
1047
1048 /* MCUFWDL 0x80[1:0]= 0 */
1049 /* reset MCU ready status */
1050 rtw_write8(padapter, REG_MCUFWDL, 0);
1051
1052 /* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
1053 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
1054 u1bTmp &= ~BIT(0);
1055 rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
1056 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
1057 u1bTmp |= BIT(0);
1058 rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
1059
1060 /* ==== Reset digital sequence end ====== */
1061
1062 bMacPwrCtrlOn = false; /* Disable CMD53 R/W */
1063 ret = false;
1064 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1065 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_disable_flow);
1066 if (!ret) {
1067 DBG_8192C(KERN_ERR "%s: run CARD DISABLE flow fail!\n", __func__);
1068 }
1069 }
1070
rtl8723bs_hal_deinit(struct adapter * padapter)1071 static u32 rtl8723bs_hal_deinit(struct adapter *padapter)
1072 {
1073 struct dvobj_priv *psdpriv = padapter->dvobj;
1074 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1075
1076 if (padapter->hw_init_completed) {
1077 if (adapter_to_pwrctl(padapter)->bips_processing) {
1078 if (padapter->netif_up) {
1079 int cnt = 0;
1080 u8 val8 = 0;
1081
1082 DBG_871X("%s: issue H2C to FW when entering IPS\n", __func__);
1083
1084 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0x3);
1085 /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc = 0 means H2C done by FW. */
1086 do {
1087 val8 = rtw_read8(padapter, REG_HMETFR);
1088 cnt++;
1089 DBG_871X("%s polling REG_HMETFR = 0x%x, cnt =%d\n", __func__, val8, cnt);
1090 mdelay(10);
1091 } while (cnt < 100 && (val8 != 0));
1092 /* H2C done, enter 32k */
1093 if (val8 == 0) {
1094 /* ser rpwm to enter 32k */
1095 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
1096 val8 += 0x80;
1097 val8 |= BIT(0);
1098 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1099 DBG_871X("%s: write rpwm =%02x\n", __func__, val8);
1100 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
1101 cnt = val8 = 0;
1102 do {
1103 val8 = rtw_read8(padapter, REG_CR);
1104 cnt++;
1105 DBG_871X("%s polling 0x100 = 0x%x, cnt =%d\n", __func__, val8, cnt);
1106 mdelay(10);
1107 } while (cnt < 100 && (val8 != 0xEA));
1108 } else {
1109 DBG_871X(
1110 "MAC_1C0 =%08x, MAC_1C4 =%08x, MAC_1C8 =%08x, MAC_1CC =%08x\n",
1111 rtw_read32(padapter, 0x1c0),
1112 rtw_read32(padapter, 0x1c4),
1113 rtw_read32(padapter, 0x1c8),
1114 rtw_read32(padapter, 0x1cc)
1115 );
1116 }
1117
1118 DBG_871X(
1119 "polling done when entering IPS, check result : 0x100 = 0x%x, cnt =%d, MAC_1cc = 0x%02x\n",
1120 rtw_read8(padapter, REG_CR),
1121 cnt,
1122 rtw_read8(padapter, REG_HMETFR)
1123 );
1124
1125 adapter_to_pwrctl(padapter)->pre_ips_type = 0;
1126
1127 } else {
1128 pdbgpriv->dbg_carddisable_cnt++;
1129 CardDisableRTL8723BSdio(padapter);
1130
1131 adapter_to_pwrctl(padapter)->pre_ips_type = 1;
1132 }
1133
1134 } else {
1135 pdbgpriv->dbg_carddisable_cnt++;
1136 CardDisableRTL8723BSdio(padapter);
1137 }
1138 } else
1139 pdbgpriv->dbg_deinit_fail_cnt++;
1140
1141 return _SUCCESS;
1142 }
1143
rtl8723bs_inirp_init(struct adapter * padapter)1144 static u32 rtl8723bs_inirp_init(struct adapter *padapter)
1145 {
1146 return _SUCCESS;
1147 }
1148
rtl8723bs_inirp_deinit(struct adapter * padapter)1149 static u32 rtl8723bs_inirp_deinit(struct adapter *padapter)
1150 {
1151 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+rtl8723bs_inirp_deinit\n"));
1152
1153 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("-rtl8723bs_inirp_deinit\n"));
1154
1155 return _SUCCESS;
1156 }
1157
rtl8723bs_init_default_value(struct adapter * padapter)1158 static void rtl8723bs_init_default_value(struct adapter *padapter)
1159 {
1160 struct hal_com_data *pHalData;
1161
1162
1163 pHalData = GET_HAL_DATA(padapter);
1164
1165 rtl8723b_init_default_value(padapter);
1166
1167 /* interface related variable */
1168 pHalData->SdioRxFIFOCnt = 0;
1169 }
1170
rtl8723bs_interface_configure(struct adapter * padapter)1171 static void rtl8723bs_interface_configure(struct adapter *padapter)
1172 {
1173 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1174 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
1175 struct registry_priv *pregistrypriv = &padapter->registrypriv;
1176 bool bWiFiConfig = pregistrypriv->wifi_spec;
1177
1178
1179 pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
1180 pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
1181 pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
1182
1183 if (bWiFiConfig)
1184 pHalData->OutEpNumber = 2;
1185 else
1186 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
1187
1188 switch (pHalData->OutEpNumber) {
1189 case 3:
1190 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
1191 break;
1192 case 2:
1193 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
1194 break;
1195 case 1:
1196 pHalData->OutEpQueueSel = TX_SELE_HQ;
1197 break;
1198 default:
1199 break;
1200 }
1201
1202 Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
1203 }
1204
1205 /* */
1206 /* Description: */
1207 /* We should set Efuse cell selection to WiFi cell in default. */
1208 /* */
1209 /* Assumption: */
1210 /* PASSIVE_LEVEL */
1211 /* */
1212 /* Added by Roger, 2010.11.23. */
1213 /* */
_EfuseCellSel(struct adapter * padapter)1214 static void _EfuseCellSel(struct adapter *padapter)
1215 {
1216 u32 value32;
1217
1218 value32 = rtw_read32(padapter, EFUSE_TEST);
1219 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1220 rtw_write32(padapter, EFUSE_TEST, value32);
1221 }
1222
_ReadRFType(struct adapter * Adapter)1223 static void _ReadRFType(struct adapter *Adapter)
1224 {
1225 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1226
1227 #if DISABLE_BB_RF
1228 pHalData->rf_chip = RF_PSEUDO_11N;
1229 #else
1230 pHalData->rf_chip = RF_6052;
1231 #endif
1232 }
1233
1234
Hal_EfuseParseMACAddr_8723BS(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1235 static void Hal_EfuseParseMACAddr_8723BS(
1236 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1237 )
1238 {
1239 u16 i;
1240 u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0xb7, 0x23, 0x00};
1241 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1242
1243 if (AutoLoadFail) {
1244 /* sMacAddr[5] = (u8)GetRandomNumber(1, 254); */
1245 for (i = 0; i < 6; i++)
1246 pEEPROM->mac_addr[i] = sMacAddr[i];
1247 } else {
1248 /* Read Permanent MAC address */
1249 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723BS], ETH_ALEN);
1250 }
1251 /* NicIFSetMacAddress(padapter, padapter->PermanentAddress); */
1252
1253 RT_TRACE(
1254 _module_hci_hal_init_c_,
1255 _drv_notice_,
1256 (
1257 "Hal_EfuseParseMACAddr_8723BS: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
1258 pEEPROM->mac_addr[0],
1259 pEEPROM->mac_addr[1],
1260 pEEPROM->mac_addr[2],
1261 pEEPROM->mac_addr[3],
1262 pEEPROM->mac_addr[4],
1263 pEEPROM->mac_addr[5]
1264 )
1265 );
1266 }
1267
Hal_EfuseParseBoardType_8723BS(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1268 static void Hal_EfuseParseBoardType_8723BS(
1269 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1270 )
1271 {
1272 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1273
1274 if (!AutoLoadFail) {
1275 pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_8723B] & 0xE0) >> 5;
1276 if (pHalData->BoardType == 0xFF)
1277 pHalData->BoardType = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;
1278 } else
1279 pHalData->BoardType = 0;
1280 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Board Type: 0x%2x\n", pHalData->BoardType));
1281 }
1282
_ReadEfuseInfo8723BS(struct adapter * padapter)1283 static void _ReadEfuseInfo8723BS(struct adapter *padapter)
1284 {
1285 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1286 u8 *hwinfo = NULL;
1287
1288 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("====>_ReadEfuseInfo8723BS()\n"));
1289
1290 /* */
1291 /* This part read and parse the eeprom/efuse content */
1292 /* */
1293
1294 if (sizeof(pEEPROM->efuse_eeprom_data) < HWSET_MAX_SIZE_8723B)
1295 DBG_871X("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8723B!\n");
1296
1297 hwinfo = pEEPROM->efuse_eeprom_data;
1298
1299 Hal_InitPGData(padapter, hwinfo);
1300
1301 Hal_EfuseParseIDCode(padapter, hwinfo);
1302 Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1303
1304 Hal_EfuseParseMACAddr_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1305
1306 Hal_EfuseParseTxPowerInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1307 Hal_EfuseParseBoardType_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1308
1309 /* */
1310 /* Read Bluetooth co-exist and initialize */
1311 /* */
1312 Hal_EfuseParsePackageType_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1313 Hal_EfuseParseBTCoexistInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1314 Hal_EfuseParseChnlPlan_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1315 Hal_EfuseParseXtal_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1316 Hal_EfuseParseThermalMeter_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1317 Hal_EfuseParseAntennaDiversity_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1318 Hal_EfuseParseCustomerID_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1319
1320 Hal_EfuseParseVoltage_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1321
1322 #ifdef CONFIG_WOWLAN
1323 Hal_DetectWoWMode(padapter);
1324 #endif
1325
1326 Hal_ReadRFGainOffset(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1327
1328 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<==== _ReadEfuseInfo8723BS()\n"));
1329 }
1330
_ReadPROMContent(struct adapter * padapter)1331 static void _ReadPROMContent(struct adapter *padapter)
1332 {
1333 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1334 u8 eeValue;
1335
1336 eeValue = rtw_read8(padapter, REG_9346CR);
1337 /* To check system boot selection. */
1338 pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1339 pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1340
1341 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1342 ("%s: 9346CR = 0x%02X, Boot from %s, Autoload %s\n",
1343 __func__, eeValue,
1344 (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1345 (pEEPROM->bautoload_fail_flag ? "Fail" : "OK")));
1346
1347 /* pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
1348
1349 _ReadEfuseInfo8723BS(padapter);
1350 }
1351
_InitOtherVariable(struct adapter * Adapter)1352 static void _InitOtherVariable(struct adapter *Adapter)
1353 {
1354 }
1355
1356 /* */
1357 /* Description: */
1358 /* Read HW adapter information by E-Fuse or EEPROM according CR9346 reported. */
1359 /* */
1360 /* Assumption: */
1361 /* PASSIVE_LEVEL (SDIO interface) */
1362 /* */
1363 /* */
_ReadAdapterInfo8723BS(struct adapter * padapter)1364 static s32 _ReadAdapterInfo8723BS(struct adapter *padapter)
1365 {
1366 u8 val8;
1367 unsigned long start;
1368
1369 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+_ReadAdapterInfo8723BS\n"));
1370
1371 /* before access eFuse, make sure card enable has been called */
1372 if (!padapter->hw_init_completed)
1373 _InitPowerOn_8723BS(padapter);
1374
1375
1376 val8 = rtw_read8(padapter, 0x4e);
1377 MSG_8192C("%s, 0x4e = 0x%x\n", __func__, val8);
1378 val8 |= BIT(6);
1379 rtw_write8(padapter, 0x4e, val8);
1380
1381
1382 start = jiffies;
1383
1384 _EfuseCellSel(padapter);
1385 _ReadRFType(padapter);
1386 _ReadPROMContent(padapter);
1387 _InitOtherVariable(padapter);
1388
1389 if (!padapter->hw_init_completed) {
1390 rtw_write8(padapter, 0x67, 0x00); /* for BT, Switch Ant control to BT */
1391 CardDisableRTL8723BSdio(padapter);/* for the power consumption issue, wifi ko module is loaded during booting, but wifi GUI is off */
1392 }
1393
1394
1395 MSG_8192C("<==== _ReadAdapterInfo8723BS in %d ms\n", jiffies_to_msecs(jiffies - start));
1396
1397 return _SUCCESS;
1398 }
1399
ReadAdapterInfo8723BS(struct adapter * padapter)1400 static void ReadAdapterInfo8723BS(struct adapter *padapter)
1401 {
1402 /* Read EEPROM size before call any EEPROM function */
1403 padapter->EepromAddressSize = GetEEPROMSize8723B(padapter);
1404
1405 _ReadAdapterInfo8723BS(padapter);
1406 }
1407
1408 /*
1409 * If variable not handled here,
1410 * some variables will be processed in SetHwReg8723B()
1411 */
SetHwReg8723BS(struct adapter * padapter,u8 variable,u8 * val)1412 static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
1413 {
1414 u8 val8;
1415
1416 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1417 struct wowlan_ioctl_param *poidparam;
1418 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
1419 int res;
1420 u32 tmp;
1421 u16 len = 0;
1422 u8 trycnt = 100;
1423 u32 himr = 0;
1424 #if defined(CONFIG_WOWLAN)
1425 struct security_priv *psecuritypriv = &padapter->securitypriv;
1426 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
1427 struct sta_info *psta = NULL;
1428 u64 iv_low = 0, iv_high = 0;
1429 u8 mstatus = (*(u8 *)val);
1430 #endif
1431 #endif
1432
1433 switch (variable) {
1434 case HW_VAR_SET_RPWM:
1435 /* rpwm value only use BIT0(clock bit) , BIT6(Ack bit), and BIT7(Toggle bit) */
1436 /* BIT0 value - 1: 32k, 0:40MHz. */
1437 /* BIT6 value - 1: report cpwm value after success set, 0:do not report. */
1438 /* BIT7 value - Toggle bit change. */
1439 {
1440 val8 = *val;
1441 val8 &= 0xC1;
1442 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1443 }
1444 break;
1445 case HW_VAR_SET_REQ_FW_PS:
1446 {
1447 u8 req_fw_ps = 0;
1448 req_fw_ps = rtw_read8(padapter, 0x8f);
1449 req_fw_ps |= 0x10;
1450 rtw_write8(padapter, 0x8f, req_fw_ps);
1451 }
1452 break;
1453 case HW_VAR_RXDMA_AGG_PG_TH:
1454 val8 = *val;
1455 break;
1456
1457 #ifdef CONFIG_WOWLAN
1458 case HW_VAR_WOWLAN:
1459 {
1460 poidparam = (struct wowlan_ioctl_param *)val;
1461 switch (poidparam->subcode) {
1462 case WOWLAN_ENABLE:
1463 DBG_871X_LEVEL(_drv_always_, "WOWLAN_ENABLE\n");
1464
1465 /* backup data rate to register 0x8b for wowlan FW */
1466 rtw_write8(padapter, 0x8d, 1);
1467 rtw_write8(padapter, 0x8c, 0);
1468 rtw_write8(padapter, 0x8f, 0x40);
1469 rtw_write8(padapter, 0x8b,
1470 rtw_read8(padapter, 0x2f0));
1471
1472 /* 1. Download WOWLAN FW */
1473 DBG_871X_LEVEL(_drv_always_, "Re-download WoWlan FW!\n");
1474 SetFwRelatedForWoWLAN8723b(padapter, true);
1475
1476 /* 2. RX DMA stop */
1477 DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
1478 rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
1479 do {
1480 if ((rtw_read32(padapter, REG_RXPKT_NUM) & RXDMA_IDLE)) {
1481 DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
1482 break;
1483 } else {
1484 /* If RX_DMA is not idle, receive one pkt from DMA */
1485 res = sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp);
1486 len = le16_to_cpu(tmp);
1487 DBG_871X_LEVEL(_drv_always_, "RX len:%d\n", len);
1488 if (len > 0)
1489 res = RecvOnePkt(padapter, len);
1490 else
1491 DBG_871X_LEVEL(_drv_always_, "read length fail %d\n", len);
1492
1493 DBG_871X_LEVEL(_drv_always_, "RecvOnePkt Result: %d\n", res);
1494 }
1495 } while (trycnt--);
1496 if (trycnt == 0)
1497 DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed......\n");
1498
1499 /* 3. Clear IMR and ISR */
1500 DBG_871X_LEVEL(_drv_always_, "Clear IMR and ISR\n");
1501 tmp = 0;
1502 sdio_local_write(padapter, SDIO_REG_HIMR_ON, 4, (u8 *)&tmp);
1503 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1504 sdio_local_read(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1505 sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1506
1507 /* 4. Enable CPWM2 only */
1508 DBG_871X_LEVEL(_drv_always_, "Enable only CPWM2\n");
1509 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1510 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
1511
1512 himr = cpu_to_le32(SDIO_HIMR_DISABLED) | SDIO_HIMR_CPWM2_MSK;
1513 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
1514
1515 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1516 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp);
1517
1518 /* 5. Set Enable WOWLAN H2C command. */
1519 DBG_871X_LEVEL(_drv_always_, "Set Enable WOWLan cmd\n");
1520 rtl8723b_set_wowlan_cmd(padapter, 1);
1521
1522 /* 6. Check EnableWoWlan CMD is ready */
1523 if (!pwrctl->wowlan_pno_enable) {
1524 DBG_871X_LEVEL(_drv_always_, "Check EnableWoWlan CMD is ready\n");
1525 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1526 trycnt = 10;
1527 while (!(mstatus & BIT1) && trycnt > 1) {
1528 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1529 DBG_871X("Loop index: %d :0x%02x\n", trycnt, mstatus);
1530 trycnt--;
1531 msleep(2);
1532 }
1533 }
1534 break;
1535
1536 case WOWLAN_DISABLE:
1537 DBG_871X_LEVEL(_drv_always_, "WOWLAN_DISABLE\n");
1538
1539 psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(pmlmepriv));
1540 if (psta)
1541 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, RT_MEDIA_DISCONNECT, psta->mac_id);
1542 else
1543 DBG_871X("psta is null\n");
1544
1545 /* 1. Read wakeup reason */
1546 pwrctl->wowlan_wake_reason = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
1547 DBG_871X_LEVEL(
1548 _drv_always_,
1549 "wakeup_reason: 0x%02x, mac_630 = 0x%08x, mac_634 = 0x%08x, mac_1c0 = 0x%08x, mac_1c4 = 0x%08x"
1550 ", mac_494 = 0x%08x, , mac_498 = 0x%08x, mac_49c = 0x%08x, mac_608 = 0x%08x, mac_4a0 = 0x%08x, mac_4a4 = 0x%08x\n"
1551 ", mac_1cc = 0x%08x, mac_2f0 = 0x%08x, mac_2f4 = 0x%08x, mac_2f8 = 0x%08x, mac_2fc = 0x%08x, mac_8c = 0x%08x",
1552 pwrctl->wowlan_wake_reason,
1553 rtw_read32(padapter, REG_WOWLAN_GTK_DBG1),
1554 rtw_read32(padapter, REG_WOWLAN_GTK_DBG2),
1555 rtw_read32(padapter, 0x1c0),
1556 rtw_read32(padapter, 0x1c4),
1557 rtw_read32(padapter, 0x494),
1558 rtw_read32(padapter, 0x498),
1559 rtw_read32(padapter, 0x49c),
1560 rtw_read32(padapter, 0x608),
1561 rtw_read32(padapter, 0x4a0),
1562 rtw_read32(padapter, 0x4a4),
1563 rtw_read32(padapter, 0x1cc),
1564 rtw_read32(padapter, 0x2f0),
1565 rtw_read32(padapter, 0x2f4),
1566 rtw_read32(padapter, 0x2f8),
1567 rtw_read32(padapter, 0x2fc),
1568 rtw_read32(padapter, 0x8c)
1569 );
1570 #ifdef CONFIG_PNO_SET_DEBUG
1571 DBG_871X("0x1b9: 0x%02x, 0x632: 0x%02x\n", rtw_read8(padapter, 0x1b9), rtw_read8(padapter, 0x632));
1572 DBG_871X("0x4fc: 0x%02x, 0x4fd: 0x%02x\n", rtw_read8(padapter, 0x4fc), rtw_read8(padapter, 0x4fd));
1573 DBG_871X("TXDMA STATUS: 0x%08x\n", rtw_read32(padapter, REG_TXDMA_STATUS));
1574 #endif
1575
1576 {
1577 /* 2. Set Disable WOWLAN H2C command. */
1578 DBG_871X_LEVEL(_drv_always_, "Set Disable WOWLan cmd\n");
1579 rtl8723b_set_wowlan_cmd(padapter, 0);
1580
1581 /* 3. Check Disable WoWlan CMD ready. */
1582 DBG_871X_LEVEL(_drv_always_, "Check DisableWoWlan CMD is ready\n");
1583 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1584 trycnt = 50;
1585 while (mstatus & BIT1 && trycnt > 1) {
1586 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1587 DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
1588 trycnt--;
1589 msleep(10);
1590 }
1591
1592 if (mstatus & BIT1) {
1593 DBG_871X_LEVEL(_drv_always_, "Disable WOW mode fail!!\n");
1594 DBG_871X("Set 0x690 = 0x00\n");
1595 rtw_write8(padapter, REG_WOW_CTRL, (rtw_read8(padapter, REG_WOW_CTRL) & 0xf0));
1596 DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n");
1597 rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
1598 }
1599
1600 /* 3.1 read fw iv */
1601 iv_low = rtw_read32(padapter, REG_TXPKTBUF_IV_LOW);
1602 /* only low two bytes is PN, check AES_IV macro for detail */
1603 iv_low &= 0xffff;
1604 iv_high = rtw_read32(padapter, REG_TXPKTBUF_IV_HIGH);
1605 /* get the real packet number */
1606 pwrctl->wowlan_fw_iv = iv_high << 16 | iv_low;
1607 DBG_871X_LEVEL(_drv_always_, "fw_iv: 0x%016llx\n", pwrctl->wowlan_fw_iv);
1608 /* Update TX iv data. */
1609 rtw_set_sec_pn(padapter);
1610
1611 /* 3.2 read GTK index and key */
1612 if (
1613 psecuritypriv->binstallKCK_KEK == true &&
1614 psecuritypriv->dot11PrivacyAlgrthm == _AES_
1615 ) {
1616 u8 gtk_keyindex = 0;
1617 u8 get_key[16];
1618 /* read gtk key index */
1619 gtk_keyindex = rtw_read8(padapter, 0x48c);
1620
1621 if (gtk_keyindex < 4) {
1622 psecuritypriv->dot118021XGrpKeyid = gtk_keyindex;
1623 read_cam(padapter, gtk_keyindex, get_key);
1624 memcpy(psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, get_key, 16);
1625 DBG_871X_LEVEL(
1626 _drv_always_,
1627 "GTK (%d) = 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1628 gtk_keyindex,
1629 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[0],
1630 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[1],
1631 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[2],
1632 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[3]
1633 );
1634 } else
1635 DBG_871X_LEVEL(_drv_always_, "GTK index =%d\n", gtk_keyindex);
1636 }
1637
1638 /* 4. Re-download Normal FW. */
1639 DBG_871X_LEVEL(_drv_always_, "Re-download Normal FW!\n");
1640 SetFwRelatedForWoWLAN8723b(padapter, false);
1641 }
1642 #ifdef CONFIG_GPIO_WAKEUP
1643 DBG_871X_LEVEL(_drv_always_, "Set Wake GPIO to high for default.\n");
1644 HalSetOutPutGPIO(padapter, WAKEUP_GPIO_IDX, 1);
1645 #endif
1646
1647 /* 5. Download reserved pages and report media status if needed. */
1648 if (
1649 (pwrctl->wowlan_wake_reason != FWDecisionDisconnect) &&
1650 (pwrctl->wowlan_wake_reason != Rx_Pairwisekey) &&
1651 (pwrctl->wowlan_wake_reason != Rx_DisAssoc) &&
1652 (pwrctl->wowlan_wake_reason != Rx_DeAuth)
1653 ) {
1654 rtl8723b_set_FwJoinBssRpt_cmd(padapter, RT_MEDIA_CONNECT);
1655 if (psta)
1656 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, RT_MEDIA_CONNECT, psta->mac_id);
1657 }
1658 #ifdef CONFIG_PNO_SUPPORT
1659 rtw_write8(padapter, 0x1b8, 0);
1660 DBG_871X("reset 0x1b8: %d\n", rtw_read8(padapter, 0x1b8));
1661 rtw_write8(padapter, 0x1b9, 0);
1662 DBG_871X("reset 0x1b9: %d\n", rtw_read8(padapter, 0x1b9));
1663 rtw_write8(padapter, REG_PNO_STATUS, 0);
1664 DBG_871X("reset REG_PNO_STATUS: %d\n", rtw_read8(padapter, REG_PNO_STATUS));
1665 #endif
1666 break;
1667
1668 default:
1669 break;
1670 }
1671 }
1672 break;
1673 #endif /* CONFIG_WOWLAN */
1674 #ifdef CONFIG_AP_WOWLAN
1675 case HW_VAR_AP_WOWLAN:
1676 {
1677 poidparam = (struct wowlan_ioctl_param *)val;
1678 switch (poidparam->subcode) {
1679 case WOWLAN_AP_ENABLE:
1680 DBG_871X("%s, WOWLAN_AP_ENABLE\n", __func__);
1681 /* 1. Download WOWLAN FW */
1682 DBG_871X_LEVEL(_drv_always_, "Re-download WoWlan FW!\n");
1683 SetFwRelatedForWoWLAN8723b(padapter, true);
1684
1685 /* 2. RX DMA stop */
1686 DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
1687 rtw_write32(padapter, REG_RXPKT_NUM,
1688 (rtw_read32(padapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
1689 do {
1690 if ((rtw_read32(padapter, REG_RXPKT_NUM) & RXDMA_IDLE)) {
1691 DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
1692 break;
1693 } else {
1694 /* If RX_DMA is not idle, receive one pkt from DMA */
1695 res = sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp);
1696 len = le16_to_cpu(tmp);
1697
1698 DBG_871X_LEVEL(_drv_always_, "RX len:%d\n", len);
1699 if (len > 0)
1700 res = RecvOnePkt(padapter, len);
1701 else
1702 DBG_871X_LEVEL(_drv_always_, "read length fail %d\n", len);
1703
1704 DBG_871X_LEVEL(_drv_always_, "RecvOnePkt Result: %d\n", res);
1705 }
1706 } while (trycnt--);
1707
1708 if (trycnt == 0)
1709 DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed......\n");
1710
1711 /* 3. Clear IMR and ISR */
1712 DBG_871X_LEVEL(_drv_always_, "Clear IMR and ISR\n");
1713 tmp = 0;
1714 sdio_local_write(padapter, SDIO_REG_HIMR_ON, 4, (u8 *)&tmp);
1715 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1716 sdio_local_read(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1717 sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1718
1719 /* 4. Enable CPWM2 only */
1720 DBG_871X_LEVEL(_drv_always_, "Enable only CPWM2\n");
1721 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1722 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
1723
1724 himr = cpu_to_le32(SDIO_HIMR_DISABLED) | SDIO_HIMR_CPWM2_MSK;
1725 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
1726
1727 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1728 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp);
1729
1730 /* 5. Set Enable WOWLAN H2C command. */
1731 DBG_871X_LEVEL(_drv_always_, "Set Enable AP WOWLan cmd\n");
1732 rtl8723b_set_ap_wowlan_cmd(padapter, 1);
1733 /* 6. add some delay for H2C cmd ready */
1734 msleep(10);
1735
1736 rtw_write8(padapter, REG_WOWLAN_WAKE_REASON, 0);
1737 break;
1738 case WOWLAN_AP_DISABLE:
1739 DBG_871X("%s, WOWLAN_AP_DISABLE\n", __func__);
1740 /* 1. Read wakeup reason */
1741 pwrctl->wowlan_wake_reason =
1742 rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
1743
1744 DBG_871X_LEVEL(_drv_always_, "wakeup_reason: 0x%02x\n",
1745 pwrctl->wowlan_wake_reason);
1746
1747 /* 2. Set Disable WOWLAN H2C command. */
1748 DBG_871X_LEVEL(_drv_always_, "Set Disable WOWLan cmd\n");
1749 rtl8723b_set_ap_wowlan_cmd(padapter, 0);
1750 /* 6. add some delay for H2C cmd ready */
1751 msleep(2);
1752
1753 DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n");
1754
1755 rtw_write32(padapter, REG_RXPKT_NUM,
1756 (rtw_read32(padapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
1757
1758 SetFwRelatedForWoWLAN8723b(padapter, false);
1759
1760 #ifdef CONFIG_GPIO_WAKEUP
1761 DBG_871X_LEVEL(_drv_always_, "Set Wake GPIO to high for default.\n");
1762 HalSetOutPutGPIO(padapter, WAKEUP_GPIO_IDX, 1);
1763 #endif /* CONFIG_GPIO_WAKEUP */
1764 rtl8723b_set_FwJoinBssRpt_cmd(padapter, RT_MEDIA_CONNECT);
1765 issue_beacon(padapter, 0);
1766 break;
1767 default:
1768 break;
1769 }
1770 }
1771 break;
1772 #endif /* CONFIG_AP_WOWLAN */
1773 case HW_VAR_DM_IN_LPS:
1774 rtl8723b_hal_dm_in_lps(padapter);
1775 break;
1776 default:
1777 SetHwReg8723B(padapter, variable, val);
1778 break;
1779 }
1780 }
1781
1782 /*
1783 * If variable not handled here,
1784 * some variables will be processed in GetHwReg8723B()
1785 */
GetHwReg8723BS(struct adapter * padapter,u8 variable,u8 * val)1786 static void GetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
1787 {
1788 switch (variable) {
1789 case HW_VAR_CPWM:
1790 *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8723B);
1791 break;
1792
1793 case HW_VAR_FW_PS_STATE:
1794 {
1795 /* 3. read dword 0x88 driver read fw ps state */
1796 *((u16 *)val) = rtw_read16(padapter, 0x88);
1797 }
1798 break;
1799 default:
1800 GetHwReg8723B(padapter, variable, val);
1801 break;
1802 }
1803 }
1804
SetHwRegWithBuf8723B(struct adapter * padapter,u8 variable,u8 * pbuf,int len)1805 static void SetHwRegWithBuf8723B(struct adapter *padapter, u8 variable, u8 *pbuf, int len)
1806 {
1807 switch (variable) {
1808 case HW_VAR_C2H_HANDLE:
1809 /* DBG_8192C("%s len =%d\n", __func__, len); */
1810 C2HPacketHandler_8723B(padapter, pbuf, len);
1811 break;
1812 default:
1813 break;
1814 }
1815 }
1816
1817 /* */
1818 /* Description: */
1819 /* Query setting of specified variable. */
1820 /* */
GetHalDefVar8723BSDIO(struct adapter * Adapter,enum HAL_DEF_VARIABLE eVariable,void * pValue)1821 static u8 GetHalDefVar8723BSDIO(
1822 struct adapter *Adapter, enum HAL_DEF_VARIABLE eVariable, void *pValue
1823 )
1824 {
1825 u8 bResult = _SUCCESS;
1826
1827 switch (eVariable) {
1828 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1829 break;
1830 case HAL_DEF_CURRENT_ANTENNA:
1831 break;
1832 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1833 /* Stanley@BB.SD3 suggests 16K can get stable performance */
1834 /* coding by Lucas@20130730 */
1835 *(u32 *)pValue = MAX_AMPDU_FACTOR_16K;
1836 break;
1837 default:
1838 bResult = GetHalDefVar8723B(Adapter, eVariable, pValue);
1839 break;
1840 }
1841
1842 return bResult;
1843 }
1844
1845 /* */
1846 /* Description: */
1847 /* Change default setting of specified variable. */
1848 /* */
SetHalDefVar8723BSDIO(struct adapter * Adapter,enum HAL_DEF_VARIABLE eVariable,void * pValue)1849 static u8 SetHalDefVar8723BSDIO(struct adapter *Adapter,
1850 enum HAL_DEF_VARIABLE eVariable, void *pValue)
1851 {
1852 return SetHalDefVar8723B(Adapter, eVariable, pValue);
1853 }
1854
rtl8723bs_set_hal_ops(struct adapter * padapter)1855 void rtl8723bs_set_hal_ops(struct adapter *padapter)
1856 {
1857 struct hal_ops *pHalFunc = &padapter->HalFunc;
1858
1859 rtl8723b_set_hal_ops(pHalFunc);
1860
1861 pHalFunc->hal_init = &rtl8723bs_hal_init;
1862 pHalFunc->hal_deinit = &rtl8723bs_hal_deinit;
1863
1864 pHalFunc->inirp_init = &rtl8723bs_inirp_init;
1865 pHalFunc->inirp_deinit = &rtl8723bs_inirp_deinit;
1866
1867 pHalFunc->init_xmit_priv = &rtl8723bs_init_xmit_priv;
1868 pHalFunc->free_xmit_priv = &rtl8723bs_free_xmit_priv;
1869
1870 pHalFunc->init_recv_priv = &rtl8723bs_init_recv_priv;
1871 pHalFunc->free_recv_priv = &rtl8723bs_free_recv_priv;
1872
1873 pHalFunc->init_default_value = &rtl8723bs_init_default_value;
1874 pHalFunc->intf_chip_configure = &rtl8723bs_interface_configure;
1875 pHalFunc->read_adapter_info = &ReadAdapterInfo8723BS;
1876
1877 pHalFunc->enable_interrupt = &EnableInterrupt8723BSdio;
1878 pHalFunc->disable_interrupt = &DisableInterrupt8723BSdio;
1879 pHalFunc->check_ips_status = &CheckIPSStatus;
1880 #ifdef CONFIG_WOWLAN
1881 pHalFunc->clear_interrupt = &ClearInterrupt8723BSdio;
1882 #endif
1883 pHalFunc->SetHwRegHandler = &SetHwReg8723BS;
1884 pHalFunc->GetHwRegHandler = &GetHwReg8723BS;
1885 pHalFunc->SetHwRegHandlerWithBuf = &SetHwRegWithBuf8723B;
1886 pHalFunc->GetHalDefVarHandler = &GetHalDefVar8723BSDIO;
1887 pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723BSDIO;
1888
1889 pHalFunc->hal_xmit = &rtl8723bs_hal_xmit;
1890 pHalFunc->mgnt_xmit = &rtl8723bs_mgnt_xmit;
1891 pHalFunc->hal_xmitframe_enqueue = &rtl8723bs_hal_xmitframe_enqueue;
1892
1893 #if defined(CONFIG_CHECK_BT_HANG)
1894 pHalFunc->hal_init_checkbthang_workqueue = &rtl8723bs_init_checkbthang_workqueue;
1895 pHalFunc->hal_free_checkbthang_workqueue = &rtl8723bs_free_checkbthang_workqueue;
1896 pHalFunc->hal_cancle_checkbthang_workqueue = &rtl8723bs_cancle_checkbthang_workqueue;
1897 pHalFunc->hal_checke_bt_hang = &rtl8723bs_hal_check_bt_hang;
1898 #endif
1899 }
1900
