1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7 #define _SDIO_HALINIT_C_
8
9 #include <drv_types.h>
10 #include <rtw_debug.h>
11 #include <rtl8723b_hal.h>
12
13 #include "hal_com_h2c.h"
14 /*
15 * Description:
16 *Call power on sequence to enable card
17 *
18 * Return:
19 *_SUCCESS enable success
20 *_FAIL enable fail
21 */
CardEnable(struct adapter * padapter)22 static u8 CardEnable(struct adapter *padapter)
23 {
24 u8 bMacPwrCtrlOn;
25 u8 ret = _FAIL;
26
27
28 rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
29 if (!bMacPwrCtrlOn) {
30 /* RSV_CTRL 0x1C[7:0] = 0x00 */
31 /* unlock ISO/CLK/Power control register */
32 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
33
34 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_enable_flow);
35 if (ret == _SUCCESS) {
36 u8 bMacPwrCtrlOn = true;
37 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
38 }
39 } else
40 ret = _SUCCESS;
41
42 return ret;
43 }
44
45 #ifdef CONFIG_GPIO_WAKEUP
46 /* we set it high under init and fw will */
47 /* give us Low Pulse when host wake up */
HostWakeUpGpioClear(struct adapter * Adapter)48 void HostWakeUpGpioClear(struct adapter *Adapter)
49 {
50 u32 value32;
51
52 value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL_2);
53
54 /* set GPIO 12 1 */
55 value32 |= BIT(12);/* 4+8 */
56 /* GPIO 12 out put */
57 value32 |= BIT(20);/* 4+16 */
58
59 rtw_write32(Adapter, REG_GPIO_PIN_CTRL_2, value32);
60 } /* HostWakeUpGpioClear */
61
HalSetOutPutGPIO(struct adapter * padapter,u8 index,u8 OutPutValue)62 void HalSetOutPutGPIO(struct adapter *padapter, u8 index, u8 OutPutValue)
63 {
64 if (index <= 7) {
65 /* config GPIO mode */
66 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
67
68 /* config GPIO Sel */
69 /* 0: input */
70 /* 1: output */
71 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index));
72
73 /* set output value */
74 if (OutPutValue)
75 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index));
76 else
77 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index));
78 } else {
79 /* 88C Series: */
80 /* index: 11~8 transform to 3~0 */
81 /* 8723 Series: */
82 /* index: 12~8 transform to 4~0 */
83 index -= 8;
84
85 /* config GPIO mode */
86 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
87
88 /* config GPIO Sel */
89 /* 0: input */
90 /* 1: output */
91 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index));
92
93 /* set output value */
94 if (OutPutValue)
95 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index));
96 else
97 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index));
98 }
99 }
100 #endif
101
102 static
_InitPowerOn_8723BS(struct adapter * padapter)103 u8 _InitPowerOn_8723BS(struct adapter *padapter)
104 {
105 u8 value8;
106 u16 value16;
107 u32 value32;
108 u8 ret;
109 /* u8 bMacPwrCtrlOn; */
110
111
112 /* all of these MUST be configured before power on */
113 #ifdef CONFIG_EXT_CLK
114 /* Use external crystal(XTAL) */
115 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B + 2);
116 value8 |= BIT(7);
117 rtw_write8(padapter, REG_PAD_CTRL1_8723B + 2, value8);
118
119 /* CLK_REQ High active or Low Active */
120 /* Request GPIO polarity: */
121 /* 0: low active */
122 /* 1: high active */
123 value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL + 1);
124 value8 |= BIT(5);
125 rtw_write8(padapter, REG_MULTI_FUNC_CTRL + 1, value8);
126 #endif /* CONFIG_EXT_CLK */
127
128 /* only cmd52 can be used before power on(card enable) */
129 ret = CardEnable(padapter);
130 if (!ret) {
131 RT_TRACE(
132 _module_hci_hal_init_c_,
133 _drv_emerg_,
134 ("%s: run power on flow fail\n", __func__)
135 );
136 return _FAIL;
137 }
138
139 /* Radio-Off Pin Trigger */
140 value8 = rtw_read8(padapter, REG_GPIO_INTM + 1);
141 value8 |= BIT(1); /* Enable falling edge triggering interrupt */
142 rtw_write8(padapter, REG_GPIO_INTM + 1, value8);
143 value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1);
144 value8 |= BIT(1);
145 rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8);
146
147 /* Enable power down and GPIO interrupt */
148 value16 = rtw_read16(padapter, REG_APS_FSMCO);
149 value16 |= EnPDN; /* Enable HW power down and RF on */
150 rtw_write16(padapter, REG_APS_FSMCO, value16);
151
152 /* Enable CMD53 R/W Operation */
153 /* bMacPwrCtrlOn = true; */
154 /* rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */
155
156 rtw_write8(padapter, REG_CR, 0x00);
157 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
158 value16 = rtw_read16(padapter, REG_CR);
159 value16 |= (
160 HCI_TXDMA_EN |
161 HCI_RXDMA_EN |
162 TXDMA_EN |
163 RXDMA_EN |
164 PROTOCOL_EN |
165 SCHEDULE_EN |
166 ENSEC |
167 CALTMR_EN
168 );
169 rtw_write16(padapter, REG_CR, value16);
170
171 hal_btcoex_PowerOnSetting(padapter);
172
173 /* external switch to S1 */
174 /* 0x38[11] = 0x1 */
175 /* 0x4c[23] = 0x1 */
176 /* 0x64[0] = 0 */
177 value16 = rtw_read16(padapter, REG_PWR_DATA);
178 /* Switch the control of EESK, EECS to RFC for DPDT or Antenna switch */
179 value16 |= BIT(11); /* BIT_EEPRPAD_RFE_CTRL_EN */
180 rtw_write16(padapter, REG_PWR_DATA, value16);
181 /* DBG_8192C("%s: REG_PWR_DATA(0x%x) = 0x%04X\n", __func__, REG_PWR_DATA, rtw_read16(padapter, REG_PWR_DATA)); */
182
183 value32 = rtw_read32(padapter, REG_LEDCFG0);
184 value32 |= BIT(23); /* DPDT_SEL_EN, 1 for SW control */
185 rtw_write32(padapter, REG_LEDCFG0, value32);
186 /* DBG_8192C("%s: REG_LEDCFG0(0x%x) = 0x%08X\n", __func__, REG_LEDCFG0, rtw_read32(padapter, REG_LEDCFG0)); */
187
188 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B);
189 value8 &= ~BIT(0); /* BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration */
190 rtw_write8(padapter, REG_PAD_CTRL1_8723B, value8);
191 /* DBG_8192C("%s: REG_PAD_CTRL1(0x%x) = 0x%02X\n", __func__, REG_PAD_CTRL1_8723B, rtw_read8(padapter, REG_PAD_CTRL1_8723B)); */
192
193 #ifdef CONFIG_GPIO_WAKEUP
194 HostWakeUpGpioClear(padapter);
195 #endif
196
197 return _SUCCESS;
198 }
199
200 /* Tx Page FIFO threshold */
_init_available_page_threshold(struct adapter * padapter,u8 numHQ,u8 numNQ,u8 numLQ,u8 numPubQ)201 static void _init_available_page_threshold(struct adapter *padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ)
202 {
203 u16 HQ_threshold, NQ_threshold, LQ_threshold;
204
205 HQ_threshold = (numPubQ + numHQ + 1) >> 1;
206 HQ_threshold |= (HQ_threshold << 8);
207
208 NQ_threshold = (numPubQ + numNQ + 1) >> 1;
209 NQ_threshold |= (NQ_threshold << 8);
210
211 LQ_threshold = (numPubQ + numLQ + 1) >> 1;
212 LQ_threshold |= (LQ_threshold << 8);
213
214 rtw_write16(padapter, 0x218, HQ_threshold);
215 rtw_write16(padapter, 0x21A, NQ_threshold);
216 rtw_write16(padapter, 0x21C, LQ_threshold);
217 DBG_8192C("%s(): Enable Tx FIFO Page Threshold H:0x%x, N:0x%x, L:0x%x\n", __func__, HQ_threshold, NQ_threshold, LQ_threshold);
218 }
219
_InitQueueReservedPage(struct adapter * padapter)220 static void _InitQueueReservedPage(struct adapter *padapter)
221 {
222 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
223 struct registry_priv *pregistrypriv = &padapter->registrypriv;
224 u32 numHQ = 0;
225 u32 numLQ = 0;
226 u32 numNQ = 0;
227 u32 numPubQ;
228 u32 value32;
229 u8 value8;
230 bool bWiFiConfig = pregistrypriv->wifi_spec;
231
232 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
233 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723B : NORMAL_PAGE_NUM_HPQ_8723B;
234
235 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
236 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723B : NORMAL_PAGE_NUM_LPQ_8723B;
237
238 /* NOTE: This step shall be proceed before writing REG_RQPN. */
239 if (pHalData->OutEpQueueSel & TX_SELE_NQ)
240 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723B : NORMAL_PAGE_NUM_NPQ_8723B;
241
242 numPubQ = TX_TOTAL_PAGE_NUMBER_8723B - numHQ - numLQ - numNQ;
243
244 value8 = (u8)_NPQ(numNQ);
245 rtw_write8(padapter, REG_RQPN_NPQ, value8);
246
247 /* TX DMA */
248 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
249 rtw_write32(padapter, REG_RQPN, value32);
250
251 rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ);
252
253 _init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ);
254 }
255
_InitTxBufferBoundary(struct adapter * padapter)256 static void _InitTxBufferBoundary(struct adapter *padapter)
257 {
258 struct registry_priv *pregistrypriv = &padapter->registrypriv;
259
260 /* u16 txdmactrl; */
261 u8 txpktbuf_bndy;
262
263 if (!pregistrypriv->wifi_spec) {
264 txpktbuf_bndy = TX_PAGE_BOUNDARY_8723B;
265 } else {
266 /* for WMM */
267 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
268 }
269
270 rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723B, txpktbuf_bndy);
271 rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy);
272 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy);
273 rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
274 rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy);
275 }
276
_InitNormalChipRegPriority(struct adapter * Adapter,u16 beQ,u16 bkQ,u16 viQ,u16 voQ,u16 mgtQ,u16 hiQ)277 static void _InitNormalChipRegPriority(
278 struct adapter *Adapter,
279 u16 beQ,
280 u16 bkQ,
281 u16 viQ,
282 u16 voQ,
283 u16 mgtQ,
284 u16 hiQ
285 )
286 {
287 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
288
289 value16 |=
290 _TXDMA_BEQ_MAP(beQ) |
291 _TXDMA_BKQ_MAP(bkQ) |
292 _TXDMA_VIQ_MAP(viQ) |
293 _TXDMA_VOQ_MAP(voQ) |
294 _TXDMA_MGQ_MAP(mgtQ) |
295 _TXDMA_HIQ_MAP(hiQ);
296
297 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
298 }
299
_InitNormalChipOneOutEpPriority(struct adapter * Adapter)300 static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
301 {
302 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
303
304 u16 value = 0;
305 switch (pHalData->OutEpQueueSel) {
306 case TX_SELE_HQ:
307 value = QUEUE_HIGH;
308 break;
309 case TX_SELE_LQ:
310 value = QUEUE_LOW;
311 break;
312 case TX_SELE_NQ:
313 value = QUEUE_NORMAL;
314 break;
315 default:
316 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
317 break;
318 }
319
320 _InitNormalChipRegPriority(
321 Adapter, value, value, value, value, value, value
322 );
323
324 }
325
_InitNormalChipTwoOutEpPriority(struct adapter * Adapter)326 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
327 {
328 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
329 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
330 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
331
332
333 u16 valueHi = 0;
334 u16 valueLow = 0;
335
336 switch (pHalData->OutEpQueueSel) {
337 case (TX_SELE_HQ | TX_SELE_LQ):
338 valueHi = QUEUE_HIGH;
339 valueLow = QUEUE_LOW;
340 break;
341 case (TX_SELE_NQ | TX_SELE_LQ):
342 valueHi = QUEUE_NORMAL;
343 valueLow = QUEUE_LOW;
344 break;
345 case (TX_SELE_HQ | TX_SELE_NQ):
346 valueHi = QUEUE_HIGH;
347 valueLow = QUEUE_NORMAL;
348 break;
349 default:
350 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
351 break;
352 }
353
354 if (!pregistrypriv->wifi_spec) {
355 beQ = valueLow;
356 bkQ = valueLow;
357 viQ = valueHi;
358 voQ = valueHi;
359 mgtQ = valueHi;
360 hiQ = valueHi;
361 } else {
362 /* for WMM , CONFIG_OUT_EP_WIFI_MODE */
363 beQ = valueLow;
364 bkQ = valueHi;
365 viQ = valueHi;
366 voQ = valueLow;
367 mgtQ = valueHi;
368 hiQ = valueHi;
369 }
370
371 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
372
373 }
374
_InitNormalChipThreeOutEpPriority(struct adapter * padapter)375 static void _InitNormalChipThreeOutEpPriority(struct adapter *padapter)
376 {
377 struct registry_priv *pregistrypriv = &padapter->registrypriv;
378 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
379
380 if (!pregistrypriv->wifi_spec) {
381 /* typical setting */
382 beQ = QUEUE_LOW;
383 bkQ = QUEUE_LOW;
384 viQ = QUEUE_NORMAL;
385 voQ = QUEUE_HIGH;
386 mgtQ = QUEUE_HIGH;
387 hiQ = QUEUE_HIGH;
388 } else {
389 /* for WMM */
390 beQ = QUEUE_LOW;
391 bkQ = QUEUE_NORMAL;
392 viQ = QUEUE_NORMAL;
393 voQ = QUEUE_HIGH;
394 mgtQ = QUEUE_HIGH;
395 hiQ = QUEUE_HIGH;
396 }
397 _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
398 }
399
_InitQueuePriority(struct adapter * Adapter)400 static void _InitQueuePriority(struct adapter *Adapter)
401 {
402 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
403
404 switch (pHalData->OutEpNumber) {
405 case 1:
406 _InitNormalChipOneOutEpPriority(Adapter);
407 break;
408 case 2:
409 _InitNormalChipTwoOutEpPriority(Adapter);
410 break;
411 case 3:
412 _InitNormalChipThreeOutEpPriority(Adapter);
413 break;
414 default:
415 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
416 break;
417 }
418
419
420 }
421
_InitPageBoundary(struct adapter * padapter)422 static void _InitPageBoundary(struct adapter *padapter)
423 {
424 /* RX Page Boundary */
425 u16 rxff_bndy = RX_DMA_BOUNDARY_8723B;
426
427 rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
428 }
429
_InitTransferPageSize(struct adapter * padapter)430 static void _InitTransferPageSize(struct adapter *padapter)
431 {
432 /* Tx page size is always 128. */
433
434 u8 value8;
435 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
436 rtw_write8(padapter, REG_PBP, value8);
437 }
438
_InitDriverInfoSize(struct adapter * padapter,u8 drvInfoSize)439 static void _InitDriverInfoSize(struct adapter *padapter, u8 drvInfoSize)
440 {
441 rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
442 }
443
_InitNetworkType(struct adapter * padapter)444 static void _InitNetworkType(struct adapter *padapter)
445 {
446 u32 value32;
447
448 value32 = rtw_read32(padapter, REG_CR);
449
450 /* TODO: use the other function to set network type */
451 /* value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
452 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
453
454 rtw_write32(padapter, REG_CR, value32);
455 }
456
_InitWMACSetting(struct adapter * padapter)457 static void _InitWMACSetting(struct adapter *padapter)
458 {
459 struct hal_com_data *pHalData;
460 u16 value16;
461
462
463 pHalData = GET_HAL_DATA(padapter);
464
465 pHalData->ReceiveConfig = 0;
466 pHalData->ReceiveConfig |= RCR_APM | RCR_AM | RCR_AB;
467 pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF;
468 pHalData->ReceiveConfig |= RCR_HTC_LOC_CTRL;
469 pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
470 rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig);
471
472 /* Accept all multicast address */
473 rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
474 rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
475
476 /* Accept all data frames */
477 value16 = 0xFFFF;
478 rtw_write16(padapter, REG_RXFLTMAP2, value16);
479
480 /* 2010.09.08 hpfan */
481 /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
482 /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
483 value16 = 0x400;
484 rtw_write16(padapter, REG_RXFLTMAP1, value16);
485
486 /* Accept all management frames */
487 value16 = 0xFFFF;
488 rtw_write16(padapter, REG_RXFLTMAP0, value16);
489 }
490
_InitAdaptiveCtrl(struct adapter * padapter)491 static void _InitAdaptiveCtrl(struct adapter *padapter)
492 {
493 u16 value16;
494 u32 value32;
495
496 /* Response Rate Set */
497 value32 = rtw_read32(padapter, REG_RRSR);
498 value32 &= ~RATE_BITMAP_ALL;
499 value32 |= RATE_RRSR_CCK_ONLY_1M;
500 rtw_write32(padapter, REG_RRSR, value32);
501
502 /* CF-END Threshold */
503 /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
504
505 /* SIFS (used in NAV) */
506 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
507 rtw_write16(padapter, REG_SPEC_SIFS, value16);
508
509 /* Retry Limit */
510 value16 = _LRL(0x30) | _SRL(0x30);
511 rtw_write16(padapter, REG_RL, value16);
512 }
513
_InitEDCA(struct adapter * padapter)514 static void _InitEDCA(struct adapter *padapter)
515 {
516 /* Set Spec SIFS (used in NAV) */
517 rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
518 rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
519
520 /* Set SIFS for CCK */
521 rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
522
523 /* Set SIFS for OFDM */
524 rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
525
526 /* TXOP */
527 rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
528 rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
529 rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
530 rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
531 }
532
_InitRetryFunction(struct adapter * padapter)533 static void _InitRetryFunction(struct adapter *padapter)
534 {
535 u8 value8;
536
537 value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
538 value8 |= EN_AMPDU_RTY_NEW;
539 rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
540
541 /* Set ACK timeout */
542 rtw_write8(padapter, REG_ACKTO, 0x40);
543 }
544
HalRxAggr8723BSdio(struct adapter * padapter)545 static void HalRxAggr8723BSdio(struct adapter *padapter)
546 {
547 u8 valueDMATimeout;
548 u8 valueDMAPageCount;
549
550 valueDMATimeout = 0x06;
551 valueDMAPageCount = 0x06;
552
553 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 1, valueDMATimeout);
554 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
555 }
556
sdio_AggSettingRxUpdate(struct adapter * padapter)557 static void sdio_AggSettingRxUpdate(struct adapter *padapter)
558 {
559 u8 valueDMA;
560 u8 valueRxAggCtrl = 0;
561 u8 aggBurstNum = 3; /* 0:1, 1:2, 2:3, 3:4 */
562 u8 aggBurstSize = 0; /* 0:1K, 1:512Byte, 2:256Byte... */
563
564 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
565 valueDMA |= RXDMA_AGG_EN;
566 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
567
568 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
569 valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C);
570 valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30);
571 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
572 }
573
_initSdioAggregationSetting(struct adapter * padapter)574 static void _initSdioAggregationSetting(struct adapter *padapter)
575 {
576 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
577
578 /* Tx aggregation setting */
579 /* sdio_AggSettingTxUpdate(padapter); */
580
581 /* Rx aggregation setting */
582 HalRxAggr8723BSdio(padapter);
583
584 sdio_AggSettingRxUpdate(padapter);
585
586 /* 201/12/10 MH Add for USB agg mode dynamic switch. */
587 pHalData->UsbRxHighSpeedMode = false;
588 }
589
_InitOperationMode(struct adapter * padapter)590 static void _InitOperationMode(struct adapter *padapter)
591 {
592 struct mlme_ext_priv *pmlmeext;
593 u8 regBwOpMode = 0;
594
595 pmlmeext = &padapter->mlmeextpriv;
596
597 /* 1 This part need to modified according to the rate set we filtered!! */
598 /* */
599 /* Set RRSR, RATR, and REG_BWOPMODE registers */
600 /* */
601 switch (pmlmeext->cur_wireless_mode) {
602 case WIRELESS_MODE_B:
603 regBwOpMode = BW_OPMODE_20MHZ;
604 break;
605 case WIRELESS_MODE_A:
606 /* RT_ASSERT(false, ("Error wireless a mode\n")); */
607 break;
608 case WIRELESS_MODE_G:
609 regBwOpMode = BW_OPMODE_20MHZ;
610 break;
611 case WIRELESS_MODE_AUTO:
612 regBwOpMode = BW_OPMODE_20MHZ;
613 break;
614 case WIRELESS_MODE_N_24G:
615 /* It support CCK rate by default. */
616 /* CCK rate will be filtered out only when associated AP does not support it. */
617 regBwOpMode = BW_OPMODE_20MHZ;
618 break;
619 case WIRELESS_MODE_N_5G:
620 /* RT_ASSERT(false, ("Error wireless mode")); */
621 regBwOpMode = BW_OPMODE_5G;
622 break;
623
624 default: /* for MacOSX compiler warning. */
625 break;
626 }
627
628 rtw_write8(padapter, REG_BWOPMODE, regBwOpMode);
629
630 }
631
_InitInterrupt(struct adapter * padapter)632 static void _InitInterrupt(struct adapter *padapter)
633 {
634 /* HISR - turn all off */
635 rtw_write32(padapter, REG_HISR, 0);
636
637 /* HIMR - turn all off */
638 rtw_write32(padapter, REG_HIMR, 0);
639
640 /* */
641 /* Initialize and enable SDIO Host Interrupt. */
642 /* */
643 InitInterrupt8723BSdio(padapter);
644
645 /* */
646 /* Initialize system Host Interrupt. */
647 /* */
648 InitSysInterrupt8723BSdio(padapter);
649 }
650
_InitRFType(struct adapter * padapter)651 static void _InitRFType(struct adapter *padapter)
652 {
653 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
654
655 #if DISABLE_BB_RF
656 pHalData->rf_chip = RF_PSEUDO_11N;
657 return;
658 #endif
659
660 pHalData->rf_chip = RF_6052;
661
662 pHalData->rf_type = RF_1T1R;
663 DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
664 }
665
_RfPowerSave(struct adapter * padapter)666 static void _RfPowerSave(struct adapter *padapter)
667 {
668 /* YJ, TODO */
669 }
670
671 /* */
672 /* 2010/08/09 MH Add for power down check. */
673 /* */
HalDetectPwrDownMode(struct adapter * Adapter)674 static bool HalDetectPwrDownMode(struct adapter *Adapter)
675 {
676 u8 tmpvalue;
677 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
678 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
679
680
681 EFUSE_ShadowRead(Adapter, 1, 0x7B/*EEPROM_RF_OPT3_92C*/, (u32 *)&tmpvalue);
682
683 /* 2010/08/25 MH INF priority > PDN Efuse value. */
684 if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
685 pHalData->pwrdown = true;
686 else
687 pHalData->pwrdown = false;
688
689 DBG_8192C("HalDetectPwrDownMode(): PDN =%d\n", pHalData->pwrdown);
690
691 return pHalData->pwrdown;
692 } /* HalDetectPwrDownMode */
693
rtl8723bs_hal_init(struct adapter * padapter)694 static u32 rtl8723bs_hal_init(struct adapter *padapter)
695 {
696 s32 ret;
697 struct hal_com_data *pHalData;
698 struct pwrctrl_priv *pwrctrlpriv;
699 u32 NavUpper = WiFiNavUpperUs;
700 u8 u1bTmp;
701
702 pHalData = GET_HAL_DATA(padapter);
703 pwrctrlpriv = adapter_to_pwrctl(padapter);
704
705 if (
706 adapter_to_pwrctl(padapter)->bips_processing == true &&
707 adapter_to_pwrctl(padapter)->pre_ips_type == 0
708 ) {
709 unsigned long start_time;
710 u8 cpwm_orig, cpwm_now;
711 u8 val8, bMacPwrCtrlOn = true;
712
713 DBG_871X("%s: Leaving IPS in FWLPS state\n", __func__);
714
715 /* for polling cpwm */
716 cpwm_orig = 0;
717 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
718
719 /* ser rpwm */
720 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
721 val8 &= 0x80;
722 val8 += 0x80;
723 val8 |= BIT(6);
724 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
725 DBG_871X("%s: write rpwm =%02x\n", __func__, val8);
726 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
727
728 /* do polling cpwm */
729 start_time = jiffies;
730 do {
731
732 mdelay(1);
733
734 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
735 if ((cpwm_orig ^ cpwm_now) & 0x80)
736 break;
737
738 if (jiffies_to_msecs(jiffies - start_time) > 100) {
739 DBG_871X("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __func__);
740 break;
741 }
742 } while (1);
743
744 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0);
745
746 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
747
748 hal_btcoex_InitHwConfig(padapter, false);
749
750 return _SUCCESS;
751 }
752
753 #ifdef CONFIG_WOWLAN
754 if (rtw_read8(padapter, REG_MCUFWDL) & BIT7) {
755 u8 reg_val = 0;
756 DBG_871X("+Reset Entry+\n");
757 rtw_write8(padapter, REG_MCUFWDL, 0x00);
758 _8051Reset8723(padapter);
759 /* reset BB */
760 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN);
761 reg_val &= ~(BIT(0) | BIT(1));
762 rtw_write8(padapter, REG_SYS_FUNC_EN, reg_val);
763 /* reset RF */
764 rtw_write8(padapter, REG_RF_CTRL, 0);
765 /* reset TRX path */
766 rtw_write16(padapter, REG_CR, 0);
767 /* reset MAC, Digital Core */
768 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
769 reg_val &= ~(BIT(4) | BIT(7));
770 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, reg_val);
771 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
772 reg_val |= BIT(4) | BIT(7);
773 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, reg_val);
774 DBG_871X("-Reset Entry-\n");
775 }
776 #endif /* CONFIG_WOWLAN */
777 /* Disable Interrupt first. */
778 /* rtw_hal_disable_interrupt(padapter); */
779
780 ret = _InitPowerOn_8723BS(padapter);
781 if (_FAIL == ret) {
782 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init Power On!\n"));
783 return _FAIL;
784 }
785
786 rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
787
788 ret = rtl8723b_FirmwareDownload(padapter, false);
789 if (ret != _SUCCESS) {
790 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: Download Firmware failed!!\n", __func__));
791 padapter->bFWReady = false;
792 pHalData->fw_ractrl = false;
793 return ret;
794 } else {
795 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("rtl8723bs_hal_init(): Download Firmware Success!!\n"));
796 padapter->bFWReady = true;
797 pHalData->fw_ractrl = true;
798 }
799
800 rtl8723b_InitializeFirmwareVars(padapter);
801
802 /* SIC_Init(padapter); */
803
804 if (pwrctrlpriv->reg_rfoff)
805 pwrctrlpriv->rf_pwrstate = rf_off;
806
807 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
808 /* HW GPIO pin. Before PHY_RFConfig8192C. */
809 HalDetectPwrDownMode(padapter);
810
811 /* Set RF type for BB/RF configuration */
812 _InitRFType(padapter);
813
814 /* Save target channel */
815 /* <Roger_Notes> Current Channel will be updated again later. */
816 pHalData->CurrentChannel = 6;
817
818 #if (HAL_MAC_ENABLE == 1)
819 ret = PHY_MACConfig8723B(padapter);
820 if (ret != _SUCCESS) {
821 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure MAC!!\n"));
822 return ret;
823 }
824 #endif
825 /* */
826 /* d. Initialize BB related configurations. */
827 /* */
828 #if (HAL_BB_ENABLE == 1)
829 ret = PHY_BBConfig8723B(padapter);
830 if (ret != _SUCCESS) {
831 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure BB!!\n"));
832 return ret;
833 }
834 #endif
835
836 /* If RF is on, we need to init RF. Otherwise, skip the procedure. */
837 /* We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
838 /* if (pHalData->eRFPowerState == eRfOn) */
839 {
840 #if (HAL_RF_ENABLE == 1)
841 ret = PHY_RFConfig8723B(padapter);
842 if (ret != _SUCCESS) {
843 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure RF!!\n"));
844 return ret;
845 }
846 #endif
847 }
848
849 /* */
850 /* Joseph Note: Keep RfRegChnlVal for later use. */
851 /* */
852 pHalData->RfRegChnlVal[0] =
853 PHY_QueryRFReg(padapter, (enum RF_PATH)0, RF_CHNLBW, bRFRegOffsetMask);
854 pHalData->RfRegChnlVal[1] =
855 PHY_QueryRFReg(padapter, (enum RF_PATH)1, RF_CHNLBW, bRFRegOffsetMask);
856
857
858 /* if (!pHalData->bMACFuncEnable) { */
859 _InitQueueReservedPage(padapter);
860 _InitTxBufferBoundary(padapter);
861
862 /* init LLT after tx buffer boundary is defined */
863 ret = rtl8723b_InitLLTTable(padapter);
864 if (_SUCCESS != ret) {
865 DBG_8192C("%s: Failed to init LLT Table!\n", __func__);
866 return _FAIL;
867 }
868 /* */
869 _InitQueuePriority(padapter);
870 _InitPageBoundary(padapter);
871 _InitTransferPageSize(padapter);
872
873 /* Get Rx PHY status in order to report RSSI and others. */
874 _InitDriverInfoSize(padapter, DRVINFO_SZ);
875 hal_init_macaddr(padapter);
876 _InitNetworkType(padapter);
877 _InitWMACSetting(padapter);
878 _InitAdaptiveCtrl(padapter);
879 _InitEDCA(padapter);
880 _InitRetryFunction(padapter);
881 _initSdioAggregationSetting(padapter);
882 _InitOperationMode(padapter);
883 rtl8723b_InitBeaconParameters(padapter);
884 _InitInterrupt(padapter);
885 _InitBurstPktLen_8723BS(padapter);
886
887 /* YJ, TODO */
888 rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723B, 0x3); /* CCA */
889 rtw_write8(padapter, 0x976, 0); /* hpfan_todo: 2nd CCA related */
890
891 rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
892 rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
893
894 invalidate_cam_all(padapter);
895
896 rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
897 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
898
899 /* Record original value for template. This is arough data, we can only use the data */
900 /* for power adjust. The value can not be adjustde according to different power!!! */
901 /* pHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx; */
902 /* pHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx; */
903
904 rtl8723b_InitAntenna_Selection(padapter);
905
906 /* */
907 /* Disable BAR, suggested by Scott */
908 /* 2010.04.09 add by hpfan */
909 /* */
910 rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
911
912 /* HW SEQ CTRL */
913 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
914 rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
915
916
917 /* */
918 /* Configure SDIO TxRx Control to enable Rx DMA timer masking. */
919 /* 2010.02.24. */
920 /* */
921 rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0);
922
923 _RfPowerSave(padapter);
924
925
926 rtl8723b_InitHalDm(padapter);
927
928 /* DbgPrint("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */
929
930 /* */
931 /* Update current Tx FIFO page status. */
932 /* */
933 HalQueryTxBufferStatus8723BSdio(padapter);
934 HalQueryTxOQTBufferStatus8723BSdio(padapter);
935 pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
936
937 /* Enable MACTXEN/MACRXEN block */
938 u1bTmp = rtw_read8(padapter, REG_CR);
939 u1bTmp |= (MACTXEN | MACRXEN);
940 rtw_write8(padapter, REG_CR, u1bTmp);
941
942 rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
943
944 /* ack for xmit mgmt frames. */
945 rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12));
946
947 /* pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
948
949 {
950 pwrctrlpriv->rf_pwrstate = rf_on;
951
952 if (pwrctrlpriv->rf_pwrstate == rf_on) {
953 struct pwrctrl_priv *pwrpriv;
954 unsigned long start_time;
955 u8 restore_iqk_rst;
956 u8 b2Ant;
957 u8 h2cCmdBuf;
958
959 pwrpriv = adapter_to_pwrctl(padapter);
960
961 PHY_LCCalibrate_8723B(&pHalData->odmpriv);
962
963 /* Inform WiFi FW that it is the beginning of IQK */
964 h2cCmdBuf = 1;
965 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
966
967 start_time = jiffies;
968 do {
969 if (rtw_read8(padapter, 0x1e7) & 0x01)
970 break;
971
972 msleep(50);
973 } while (jiffies_to_msecs(jiffies - start_time) <= 400);
974
975 hal_btcoex_IQKNotify(padapter, true);
976
977 restore_iqk_rst = pwrpriv->bips_processing;
978 b2Ant = pHalData->EEPROMBluetoothAntNum == Ant_x2;
979 PHY_IQCalibrate_8723B(padapter, false, restore_iqk_rst, b2Ant, pHalData->ant_path);
980 pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
981
982 hal_btcoex_IQKNotify(padapter, false);
983
984 /* Inform WiFi FW that it is the finish of IQK */
985 h2cCmdBuf = 0;
986 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
987
988 ODM_TXPowerTrackingCheck(&pHalData->odmpriv);
989 }
990 }
991
992 /* Init BT hw config. */
993 hal_btcoex_InitHwConfig(padapter, false);
994
995 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("-%s\n", __func__));
996
997 return _SUCCESS;
998 }
999
1000 /* */
1001 /* Description: */
1002 /* RTL8723e card disable power sequence v003 which suggested by Scott. */
1003 /* */
1004 /* First created by tynli. 2011.01.28. */
1005 /* */
CardDisableRTL8723BSdio(struct adapter * padapter)1006 static void CardDisableRTL8723BSdio(struct adapter *padapter)
1007 {
1008 u8 u1bTmp;
1009 u8 bMacPwrCtrlOn;
1010 u8 ret = _FAIL;
1011
1012 /* Run LPS WL RFOFF flow */
1013 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_enter_lps_flow);
1014 if (ret == _FAIL) {
1015 DBG_8192C(KERN_ERR "%s: run RF OFF flow fail!\n", __func__);
1016 }
1017
1018 /* ==== Reset digital sequence ====== */
1019
1020 u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
1021 if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) /* 8051 RAM code */
1022 rtl8723b_FirmwareSelfReset(padapter);
1023
1024 /* Reset MCU 0x2[10]= 0. Suggested by Filen. 2011.01.26. by tynli. */
1025 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1);
1026 u1bTmp &= ~BIT(2); /* 0x2[10], FEN_CPUEN */
1027 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp);
1028
1029 /* MCUFWDL 0x80[1:0]= 0 */
1030 /* reset MCU ready status */
1031 rtw_write8(padapter, REG_MCUFWDL, 0);
1032
1033 /* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
1034 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
1035 u1bTmp &= ~BIT(0);
1036 rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp);
1037 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1);
1038 u1bTmp |= BIT(0);
1039 rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
1040
1041 /* ==== Reset digital sequence end ====== */
1042
1043 bMacPwrCtrlOn = false; /* Disable CMD53 R/W */
1044 ret = false;
1045 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1046 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_disable_flow);
1047 if (!ret) {
1048 DBG_8192C(KERN_ERR "%s: run CARD DISABLE flow fail!\n", __func__);
1049 }
1050 }
1051
rtl8723bs_hal_deinit(struct adapter * padapter)1052 static u32 rtl8723bs_hal_deinit(struct adapter *padapter)
1053 {
1054 struct dvobj_priv *psdpriv = padapter->dvobj;
1055 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1056
1057 if (padapter->hw_init_completed) {
1058 if (adapter_to_pwrctl(padapter)->bips_processing) {
1059 if (padapter->netif_up) {
1060 int cnt = 0;
1061 u8 val8 = 0;
1062
1063 DBG_871X("%s: issue H2C to FW when entering IPS\n", __func__);
1064
1065 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0x3);
1066 /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc = 0 means H2C done by FW. */
1067 do {
1068 val8 = rtw_read8(padapter, REG_HMETFR);
1069 cnt++;
1070 DBG_871X("%s polling REG_HMETFR = 0x%x, cnt =%d\n", __func__, val8, cnt);
1071 mdelay(10);
1072 } while (cnt < 100 && (val8 != 0));
1073 /* H2C done, enter 32k */
1074 if (val8 == 0) {
1075 /* ser rpwm to enter 32k */
1076 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1);
1077 val8 += 0x80;
1078 val8 |= BIT(0);
1079 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1080 DBG_871X("%s: write rpwm =%02x\n", __func__, val8);
1081 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
1082 cnt = val8 = 0;
1083 do {
1084 val8 = rtw_read8(padapter, REG_CR);
1085 cnt++;
1086 DBG_871X("%s polling 0x100 = 0x%x, cnt =%d\n", __func__, val8, cnt);
1087 mdelay(10);
1088 } while (cnt < 100 && (val8 != 0xEA));
1089 } else {
1090 DBG_871X(
1091 "MAC_1C0 =%08x, MAC_1C4 =%08x, MAC_1C8 =%08x, MAC_1CC =%08x\n",
1092 rtw_read32(padapter, 0x1c0),
1093 rtw_read32(padapter, 0x1c4),
1094 rtw_read32(padapter, 0x1c8),
1095 rtw_read32(padapter, 0x1cc)
1096 );
1097 }
1098
1099 DBG_871X(
1100 "polling done when entering IPS, check result : 0x100 = 0x%x, cnt =%d, MAC_1cc = 0x%02x\n",
1101 rtw_read8(padapter, REG_CR),
1102 cnt,
1103 rtw_read8(padapter, REG_HMETFR)
1104 );
1105
1106 adapter_to_pwrctl(padapter)->pre_ips_type = 0;
1107
1108 } else {
1109 pdbgpriv->dbg_carddisable_cnt++;
1110 CardDisableRTL8723BSdio(padapter);
1111
1112 adapter_to_pwrctl(padapter)->pre_ips_type = 1;
1113 }
1114
1115 } else {
1116 pdbgpriv->dbg_carddisable_cnt++;
1117 CardDisableRTL8723BSdio(padapter);
1118 }
1119 } else
1120 pdbgpriv->dbg_deinit_fail_cnt++;
1121
1122 return _SUCCESS;
1123 }
1124
rtl8723bs_inirp_init(struct adapter * padapter)1125 static u32 rtl8723bs_inirp_init(struct adapter *padapter)
1126 {
1127 return _SUCCESS;
1128 }
1129
rtl8723bs_inirp_deinit(struct adapter * padapter)1130 static u32 rtl8723bs_inirp_deinit(struct adapter *padapter)
1131 {
1132 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+rtl8723bs_inirp_deinit\n"));
1133
1134 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("-rtl8723bs_inirp_deinit\n"));
1135
1136 return _SUCCESS;
1137 }
1138
rtl8723bs_init_default_value(struct adapter * padapter)1139 static void rtl8723bs_init_default_value(struct adapter *padapter)
1140 {
1141 struct hal_com_data *pHalData;
1142
1143
1144 pHalData = GET_HAL_DATA(padapter);
1145
1146 rtl8723b_init_default_value(padapter);
1147
1148 /* interface related variable */
1149 pHalData->SdioRxFIFOCnt = 0;
1150 }
1151
rtl8723bs_interface_configure(struct adapter * padapter)1152 static void rtl8723bs_interface_configure(struct adapter *padapter)
1153 {
1154 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1155 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
1156 struct registry_priv *pregistrypriv = &padapter->registrypriv;
1157 bool bWiFiConfig = pregistrypriv->wifi_spec;
1158
1159
1160 pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
1161 pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
1162 pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
1163
1164 if (bWiFiConfig)
1165 pHalData->OutEpNumber = 2;
1166 else
1167 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
1168
1169 switch (pHalData->OutEpNumber) {
1170 case 3:
1171 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ;
1172 break;
1173 case 2:
1174 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
1175 break;
1176 case 1:
1177 pHalData->OutEpQueueSel = TX_SELE_HQ;
1178 break;
1179 default:
1180 break;
1181 }
1182
1183 Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
1184 }
1185
1186 /* */
1187 /* Description: */
1188 /* We should set Efuse cell selection to WiFi cell in default. */
1189 /* */
1190 /* Assumption: */
1191 /* PASSIVE_LEVEL */
1192 /* */
1193 /* Added by Roger, 2010.11.23. */
1194 /* */
_EfuseCellSel(struct adapter * padapter)1195 static void _EfuseCellSel(struct adapter *padapter)
1196 {
1197 u32 value32;
1198
1199 value32 = rtw_read32(padapter, EFUSE_TEST);
1200 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1201 rtw_write32(padapter, EFUSE_TEST, value32);
1202 }
1203
_ReadRFType(struct adapter * Adapter)1204 static void _ReadRFType(struct adapter *Adapter)
1205 {
1206 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1207
1208 #if DISABLE_BB_RF
1209 pHalData->rf_chip = RF_PSEUDO_11N;
1210 #else
1211 pHalData->rf_chip = RF_6052;
1212 #endif
1213 }
1214
1215
Hal_EfuseParseMACAddr_8723BS(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1216 static void Hal_EfuseParseMACAddr_8723BS(
1217 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1218 )
1219 {
1220 u16 i;
1221 u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0xb7, 0x23, 0x00};
1222 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1223
1224 if (AutoLoadFail) {
1225 /* sMacAddr[5] = (u8)GetRandomNumber(1, 254); */
1226 for (i = 0; i < 6; i++)
1227 pEEPROM->mac_addr[i] = sMacAddr[i];
1228 } else {
1229 /* Read Permanent MAC address */
1230 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723BS], ETH_ALEN);
1231 }
1232 /* NicIFSetMacAddress(padapter, padapter->PermanentAddress); */
1233
1234 RT_TRACE(
1235 _module_hci_hal_init_c_,
1236 _drv_notice_,
1237 (
1238 "Hal_EfuseParseMACAddr_8723BS: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
1239 pEEPROM->mac_addr[0],
1240 pEEPROM->mac_addr[1],
1241 pEEPROM->mac_addr[2],
1242 pEEPROM->mac_addr[3],
1243 pEEPROM->mac_addr[4],
1244 pEEPROM->mac_addr[5]
1245 )
1246 );
1247 }
1248
Hal_EfuseParseBoardType_8723BS(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1249 static void Hal_EfuseParseBoardType_8723BS(
1250 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1251 )
1252 {
1253 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1254
1255 if (!AutoLoadFail) {
1256 pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_8723B] & 0xE0) >> 5;
1257 if (pHalData->BoardType == 0xFF)
1258 pHalData->BoardType = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;
1259 } else
1260 pHalData->BoardType = 0;
1261 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Board Type: 0x%2x\n", pHalData->BoardType));
1262 }
1263
_ReadEfuseInfo8723BS(struct adapter * padapter)1264 static void _ReadEfuseInfo8723BS(struct adapter *padapter)
1265 {
1266 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1267 u8 *hwinfo = NULL;
1268
1269 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("====>_ReadEfuseInfo8723BS()\n"));
1270
1271 /* */
1272 /* This part read and parse the eeprom/efuse content */
1273 /* */
1274
1275 if (sizeof(pEEPROM->efuse_eeprom_data) < HWSET_MAX_SIZE_8723B)
1276 DBG_871X("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8723B!\n");
1277
1278 hwinfo = pEEPROM->efuse_eeprom_data;
1279
1280 Hal_InitPGData(padapter, hwinfo);
1281
1282 Hal_EfuseParseIDCode(padapter, hwinfo);
1283 Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1284
1285 Hal_EfuseParseMACAddr_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1286
1287 Hal_EfuseParseTxPowerInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1288 Hal_EfuseParseBoardType_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1289
1290 /* */
1291 /* Read Bluetooth co-exist and initialize */
1292 /* */
1293 Hal_EfuseParsePackageType_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1294 Hal_EfuseParseBTCoexistInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1295 Hal_EfuseParseChnlPlan_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1296 Hal_EfuseParseXtal_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1297 Hal_EfuseParseThermalMeter_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1298 Hal_EfuseParseAntennaDiversity_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1299 Hal_EfuseParseCustomerID_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1300
1301 Hal_EfuseParseVoltage_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1302
1303 #ifdef CONFIG_WOWLAN
1304 Hal_DetectWoWMode(padapter);
1305 #endif
1306
1307 Hal_ReadRFGainOffset(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1308
1309 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<==== _ReadEfuseInfo8723BS()\n"));
1310 }
1311
_ReadPROMContent(struct adapter * padapter)1312 static void _ReadPROMContent(struct adapter *padapter)
1313 {
1314 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1315 u8 eeValue;
1316
1317 eeValue = rtw_read8(padapter, REG_9346CR);
1318 /* To check system boot selection. */
1319 pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1320 pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1321
1322 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1323 ("%s: 9346CR = 0x%02X, Boot from %s, Autoload %s\n",
1324 __func__, eeValue,
1325 (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1326 (pEEPROM->bautoload_fail_flag ? "Fail" : "OK")));
1327
1328 /* pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
1329
1330 _ReadEfuseInfo8723BS(padapter);
1331 }
1332
_InitOtherVariable(struct adapter * Adapter)1333 static void _InitOtherVariable(struct adapter *Adapter)
1334 {
1335 }
1336
1337 /* */
1338 /* Description: */
1339 /* Read HW adapter information by E-Fuse or EEPROM according CR9346 reported. */
1340 /* */
1341 /* Assumption: */
1342 /* PASSIVE_LEVEL (SDIO interface) */
1343 /* */
1344 /* */
_ReadAdapterInfo8723BS(struct adapter * padapter)1345 static s32 _ReadAdapterInfo8723BS(struct adapter *padapter)
1346 {
1347 u8 val8;
1348 unsigned long start;
1349
1350 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+_ReadAdapterInfo8723BS\n"));
1351
1352 /* before access eFuse, make sure card enable has been called */
1353 if (!padapter->hw_init_completed)
1354 _InitPowerOn_8723BS(padapter);
1355
1356
1357 val8 = rtw_read8(padapter, 0x4e);
1358 MSG_8192C("%s, 0x4e = 0x%x\n", __func__, val8);
1359 val8 |= BIT(6);
1360 rtw_write8(padapter, 0x4e, val8);
1361
1362
1363 start = jiffies;
1364
1365 _EfuseCellSel(padapter);
1366 _ReadRFType(padapter);
1367 _ReadPROMContent(padapter);
1368 _InitOtherVariable(padapter);
1369
1370 if (!padapter->hw_init_completed) {
1371 rtw_write8(padapter, 0x67, 0x00); /* for BT, Switch Ant control to BT */
1372 CardDisableRTL8723BSdio(padapter);/* for the power consumption issue, wifi ko module is loaded during booting, but wifi GUI is off */
1373 }
1374
1375
1376 MSG_8192C("<==== _ReadAdapterInfo8723BS in %d ms\n", jiffies_to_msecs(jiffies - start));
1377
1378 return _SUCCESS;
1379 }
1380
ReadAdapterInfo8723BS(struct adapter * padapter)1381 static void ReadAdapterInfo8723BS(struct adapter *padapter)
1382 {
1383 /* Read EEPROM size before call any EEPROM function */
1384 padapter->EepromAddressSize = GetEEPROMSize8723B(padapter);
1385
1386 _ReadAdapterInfo8723BS(padapter);
1387 }
1388
1389 /*
1390 * If variable not handled here,
1391 * some variables will be processed in SetHwReg8723B()
1392 */
SetHwReg8723BS(struct adapter * padapter,u8 variable,u8 * val)1393 static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
1394 {
1395 u8 val8;
1396
1397 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1398 struct wowlan_ioctl_param *poidparam;
1399 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
1400 int res;
1401 u32 tmp;
1402 u16 len = 0;
1403 u8 trycnt = 100;
1404 u32 himr = 0;
1405 #if defined(CONFIG_WOWLAN)
1406 struct security_priv *psecuritypriv = &padapter->securitypriv;
1407 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
1408 struct sta_info *psta = NULL;
1409 u64 iv_low = 0, iv_high = 0;
1410 u8 mstatus = (*(u8 *)val);
1411 #endif
1412 #endif
1413
1414 switch (variable) {
1415 case HW_VAR_SET_RPWM:
1416 /* rpwm value only use BIT0(clock bit) , BIT6(Ack bit), and BIT7(Toggle bit) */
1417 /* BIT0 value - 1: 32k, 0:40MHz. */
1418 /* BIT6 value - 1: report cpwm value after success set, 0:do not report. */
1419 /* BIT7 value - Toggle bit change. */
1420 {
1421 val8 = *val;
1422 val8 &= 0xC1;
1423 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8);
1424 }
1425 break;
1426 case HW_VAR_SET_REQ_FW_PS:
1427 {
1428 u8 req_fw_ps = 0;
1429 req_fw_ps = rtw_read8(padapter, 0x8f);
1430 req_fw_ps |= 0x10;
1431 rtw_write8(padapter, 0x8f, req_fw_ps);
1432 }
1433 break;
1434 case HW_VAR_RXDMA_AGG_PG_TH:
1435 val8 = *val;
1436 break;
1437
1438 #ifdef CONFIG_WOWLAN
1439 case HW_VAR_WOWLAN:
1440 {
1441 poidparam = (struct wowlan_ioctl_param *)val;
1442 switch (poidparam->subcode) {
1443 case WOWLAN_ENABLE:
1444 DBG_871X_LEVEL(_drv_always_, "WOWLAN_ENABLE\n");
1445
1446 /* backup data rate to register 0x8b for wowlan FW */
1447 rtw_write8(padapter, 0x8d, 1);
1448 rtw_write8(padapter, 0x8c, 0);
1449 rtw_write8(padapter, 0x8f, 0x40);
1450 rtw_write8(padapter, 0x8b,
1451 rtw_read8(padapter, 0x2f0));
1452
1453 /* 1. Download WOWLAN FW */
1454 DBG_871X_LEVEL(_drv_always_, "Re-download WoWlan FW!\n");
1455 SetFwRelatedForWoWLAN8723b(padapter, true);
1456
1457 /* 2. RX DMA stop */
1458 DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
1459 rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
1460 do {
1461 if ((rtw_read32(padapter, REG_RXPKT_NUM) & RXDMA_IDLE)) {
1462 DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
1463 break;
1464 } else {
1465 /* If RX_DMA is not idle, receive one pkt from DMA */
1466 res = sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp);
1467 len = le16_to_cpu(tmp);
1468 DBG_871X_LEVEL(_drv_always_, "RX len:%d\n", len);
1469 if (len > 0)
1470 res = RecvOnePkt(padapter, len);
1471 else
1472 DBG_871X_LEVEL(_drv_always_, "read length fail %d\n", len);
1473
1474 DBG_871X_LEVEL(_drv_always_, "RecvOnePkt Result: %d\n", res);
1475 }
1476 } while (trycnt--);
1477 if (trycnt == 0)
1478 DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed......\n");
1479
1480 /* 3. Clear IMR and ISR */
1481 DBG_871X_LEVEL(_drv_always_, "Clear IMR and ISR\n");
1482 tmp = 0;
1483 sdio_local_write(padapter, SDIO_REG_HIMR_ON, 4, (u8 *)&tmp);
1484 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1485 sdio_local_read(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1486 sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1487
1488 /* 4. Enable CPWM2 only */
1489 DBG_871X_LEVEL(_drv_always_, "Enable only CPWM2\n");
1490 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1491 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
1492
1493 himr = cpu_to_le32(SDIO_HIMR_DISABLED) | SDIO_HIMR_CPWM2_MSK;
1494 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
1495
1496 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1497 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp);
1498
1499 /* 5. Set Enable WOWLAN H2C command. */
1500 DBG_871X_LEVEL(_drv_always_, "Set Enable WOWLan cmd\n");
1501 rtl8723b_set_wowlan_cmd(padapter, 1);
1502
1503 /* 6. Check EnableWoWlan CMD is ready */
1504 if (!pwrctl->wowlan_pno_enable) {
1505 DBG_871X_LEVEL(_drv_always_, "Check EnableWoWlan CMD is ready\n");
1506 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1507 trycnt = 10;
1508 while (!(mstatus & BIT1) && trycnt > 1) {
1509 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1510 DBG_871X("Loop index: %d :0x%02x\n", trycnt, mstatus);
1511 trycnt--;
1512 msleep(2);
1513 }
1514 }
1515 break;
1516
1517 case WOWLAN_DISABLE:
1518 DBG_871X_LEVEL(_drv_always_, "WOWLAN_DISABLE\n");
1519
1520 psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(pmlmepriv));
1521 if (psta)
1522 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, RT_MEDIA_DISCONNECT, psta->mac_id);
1523 else
1524 DBG_871X("psta is null\n");
1525
1526 /* 1. Read wakeup reason */
1527 pwrctl->wowlan_wake_reason = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
1528 DBG_871X_LEVEL(
1529 _drv_always_,
1530 "wakeup_reason: 0x%02x, mac_630 = 0x%08x, mac_634 = 0x%08x, mac_1c0 = 0x%08x, mac_1c4 = 0x%08x"
1531 ", mac_494 = 0x%08x, , mac_498 = 0x%08x, mac_49c = 0x%08x, mac_608 = 0x%08x, mac_4a0 = 0x%08x, mac_4a4 = 0x%08x\n"
1532 ", mac_1cc = 0x%08x, mac_2f0 = 0x%08x, mac_2f4 = 0x%08x, mac_2f8 = 0x%08x, mac_2fc = 0x%08x, mac_8c = 0x%08x",
1533 pwrctl->wowlan_wake_reason,
1534 rtw_read32(padapter, REG_WOWLAN_GTK_DBG1),
1535 rtw_read32(padapter, REG_WOWLAN_GTK_DBG2),
1536 rtw_read32(padapter, 0x1c0),
1537 rtw_read32(padapter, 0x1c4),
1538 rtw_read32(padapter, 0x494),
1539 rtw_read32(padapter, 0x498),
1540 rtw_read32(padapter, 0x49c),
1541 rtw_read32(padapter, 0x608),
1542 rtw_read32(padapter, 0x4a0),
1543 rtw_read32(padapter, 0x4a4),
1544 rtw_read32(padapter, 0x1cc),
1545 rtw_read32(padapter, 0x2f0),
1546 rtw_read32(padapter, 0x2f4),
1547 rtw_read32(padapter, 0x2f8),
1548 rtw_read32(padapter, 0x2fc),
1549 rtw_read32(padapter, 0x8c)
1550 );
1551 #ifdef CONFIG_PNO_SET_DEBUG
1552 DBG_871X("0x1b9: 0x%02x, 0x632: 0x%02x\n", rtw_read8(padapter, 0x1b9), rtw_read8(padapter, 0x632));
1553 DBG_871X("0x4fc: 0x%02x, 0x4fd: 0x%02x\n", rtw_read8(padapter, 0x4fc), rtw_read8(padapter, 0x4fd));
1554 DBG_871X("TXDMA STATUS: 0x%08x\n", rtw_read32(padapter, REG_TXDMA_STATUS));
1555 #endif
1556
1557 {
1558 /* 2. Set Disable WOWLAN H2C command. */
1559 DBG_871X_LEVEL(_drv_always_, "Set Disable WOWLan cmd\n");
1560 rtl8723b_set_wowlan_cmd(padapter, 0);
1561
1562 /* 3. Check Disable WoWlan CMD ready. */
1563 DBG_871X_LEVEL(_drv_always_, "Check DisableWoWlan CMD is ready\n");
1564 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1565 trycnt = 50;
1566 while (mstatus & BIT1 && trycnt > 1) {
1567 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1568 DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
1569 trycnt--;
1570 msleep(10);
1571 }
1572
1573 if (mstatus & BIT1) {
1574 DBG_871X_LEVEL(_drv_always_, "Disable WOW mode fail!!\n");
1575 DBG_871X("Set 0x690 = 0x00\n");
1576 rtw_write8(padapter, REG_WOW_CTRL, (rtw_read8(padapter, REG_WOW_CTRL) & 0xf0));
1577 DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n");
1578 rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
1579 }
1580
1581 /* 3.1 read fw iv */
1582 iv_low = rtw_read32(padapter, REG_TXPKTBUF_IV_LOW);
1583 /* only low two bytes is PN, check AES_IV macro for detail */
1584 iv_low &= 0xffff;
1585 iv_high = rtw_read32(padapter, REG_TXPKTBUF_IV_HIGH);
1586 /* get the real packet number */
1587 pwrctl->wowlan_fw_iv = iv_high << 16 | iv_low;
1588 DBG_871X_LEVEL(_drv_always_, "fw_iv: 0x%016llx\n", pwrctl->wowlan_fw_iv);
1589 /* Update TX iv data. */
1590 rtw_set_sec_pn(padapter);
1591
1592 /* 3.2 read GTK index and key */
1593 if (
1594 psecuritypriv->binstallKCK_KEK == true &&
1595 psecuritypriv->dot11PrivacyAlgrthm == _AES_
1596 ) {
1597 u8 gtk_keyindex = 0;
1598 u8 get_key[16];
1599 /* read gtk key index */
1600 gtk_keyindex = rtw_read8(padapter, 0x48c);
1601
1602 if (gtk_keyindex < 4) {
1603 psecuritypriv->dot118021XGrpKeyid = gtk_keyindex;
1604 read_cam(padapter, gtk_keyindex, get_key);
1605 memcpy(psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, get_key, 16);
1606 DBG_871X_LEVEL(
1607 _drv_always_,
1608 "GTK (%d) = 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1609 gtk_keyindex,
1610 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[0],
1611 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[1],
1612 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[2],
1613 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[3]
1614 );
1615 } else
1616 DBG_871X_LEVEL(_drv_always_, "GTK index =%d\n", gtk_keyindex);
1617 }
1618
1619 /* 4. Re-download Normal FW. */
1620 DBG_871X_LEVEL(_drv_always_, "Re-download Normal FW!\n");
1621 SetFwRelatedForWoWLAN8723b(padapter, false);
1622 }
1623 #ifdef CONFIG_GPIO_WAKEUP
1624 DBG_871X_LEVEL(_drv_always_, "Set Wake GPIO to high for default.\n");
1625 HalSetOutPutGPIO(padapter, WAKEUP_GPIO_IDX, 1);
1626 #endif
1627
1628 /* 5. Download reserved pages and report media status if needed. */
1629 if (
1630 (pwrctl->wowlan_wake_reason != FWDecisionDisconnect) &&
1631 (pwrctl->wowlan_wake_reason != Rx_Pairwisekey) &&
1632 (pwrctl->wowlan_wake_reason != Rx_DisAssoc) &&
1633 (pwrctl->wowlan_wake_reason != Rx_DeAuth)
1634 ) {
1635 rtl8723b_set_FwJoinBssRpt_cmd(padapter, RT_MEDIA_CONNECT);
1636 if (psta)
1637 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, RT_MEDIA_CONNECT, psta->mac_id);
1638 }
1639 #ifdef CONFIG_PNO_SUPPORT
1640 rtw_write8(padapter, 0x1b8, 0);
1641 DBG_871X("reset 0x1b8: %d\n", rtw_read8(padapter, 0x1b8));
1642 rtw_write8(padapter, 0x1b9, 0);
1643 DBG_871X("reset 0x1b9: %d\n", rtw_read8(padapter, 0x1b9));
1644 rtw_write8(padapter, REG_PNO_STATUS, 0);
1645 DBG_871X("reset REG_PNO_STATUS: %d\n", rtw_read8(padapter, REG_PNO_STATUS));
1646 #endif
1647 break;
1648
1649 default:
1650 break;
1651 }
1652 }
1653 break;
1654 #endif /* CONFIG_WOWLAN */
1655 #ifdef CONFIG_AP_WOWLAN
1656 case HW_VAR_AP_WOWLAN:
1657 {
1658 poidparam = (struct wowlan_ioctl_param *)val;
1659 switch (poidparam->subcode) {
1660 case WOWLAN_AP_ENABLE:
1661 DBG_871X("%s, WOWLAN_AP_ENABLE\n", __func__);
1662 /* 1. Download WOWLAN FW */
1663 DBG_871X_LEVEL(_drv_always_, "Re-download WoWlan FW!\n");
1664 SetFwRelatedForWoWLAN8723b(padapter, true);
1665
1666 /* 2. RX DMA stop */
1667 DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
1668 rtw_write32(padapter, REG_RXPKT_NUM,
1669 (rtw_read32(padapter, REG_RXPKT_NUM) | RW_RELEASE_EN));
1670 do {
1671 if ((rtw_read32(padapter, REG_RXPKT_NUM) & RXDMA_IDLE)) {
1672 DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
1673 break;
1674 } else {
1675 /* If RX_DMA is not idle, receive one pkt from DMA */
1676 res = sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp);
1677 len = le16_to_cpu(tmp);
1678
1679 DBG_871X_LEVEL(_drv_always_, "RX len:%d\n", len);
1680 if (len > 0)
1681 res = RecvOnePkt(padapter, len);
1682 else
1683 DBG_871X_LEVEL(_drv_always_, "read length fail %d\n", len);
1684
1685 DBG_871X_LEVEL(_drv_always_, "RecvOnePkt Result: %d\n", res);
1686 }
1687 } while (trycnt--);
1688
1689 if (trycnt == 0)
1690 DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed......\n");
1691
1692 /* 3. Clear IMR and ISR */
1693 DBG_871X_LEVEL(_drv_always_, "Clear IMR and ISR\n");
1694 tmp = 0;
1695 sdio_local_write(padapter, SDIO_REG_HIMR_ON, 4, (u8 *)&tmp);
1696 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1697 sdio_local_read(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1698 sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1699
1700 /* 4. Enable CPWM2 only */
1701 DBG_871X_LEVEL(_drv_always_, "Enable only CPWM2\n");
1702 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1703 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
1704
1705 himr = cpu_to_le32(SDIO_HIMR_DISABLED) | SDIO_HIMR_CPWM2_MSK;
1706 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
1707
1708 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1709 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp);
1710
1711 /* 5. Set Enable WOWLAN H2C command. */
1712 DBG_871X_LEVEL(_drv_always_, "Set Enable AP WOWLan cmd\n");
1713 rtl8723b_set_ap_wowlan_cmd(padapter, 1);
1714 /* 6. add some delay for H2C cmd ready */
1715 msleep(10);
1716
1717 rtw_write8(padapter, REG_WOWLAN_WAKE_REASON, 0);
1718 break;
1719 case WOWLAN_AP_DISABLE:
1720 DBG_871X("%s, WOWLAN_AP_DISABLE\n", __func__);
1721 /* 1. Read wakeup reason */
1722 pwrctl->wowlan_wake_reason =
1723 rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
1724
1725 DBG_871X_LEVEL(_drv_always_, "wakeup_reason: 0x%02x\n",
1726 pwrctl->wowlan_wake_reason);
1727
1728 /* 2. Set Disable WOWLAN H2C command. */
1729 DBG_871X_LEVEL(_drv_always_, "Set Disable WOWLan cmd\n");
1730 rtl8723b_set_ap_wowlan_cmd(padapter, 0);
1731 /* 6. add some delay for H2C cmd ready */
1732 msleep(2);
1733
1734 DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n");
1735
1736 rtw_write32(padapter, REG_RXPKT_NUM,
1737 (rtw_read32(padapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
1738
1739 SetFwRelatedForWoWLAN8723b(padapter, false);
1740
1741 #ifdef CONFIG_GPIO_WAKEUP
1742 DBG_871X_LEVEL(_drv_always_, "Set Wake GPIO to high for default.\n");
1743 HalSetOutPutGPIO(padapter, WAKEUP_GPIO_IDX, 1);
1744 #endif /* CONFIG_GPIO_WAKEUP */
1745 rtl8723b_set_FwJoinBssRpt_cmd(padapter, RT_MEDIA_CONNECT);
1746 issue_beacon(padapter, 0);
1747 break;
1748 default:
1749 break;
1750 }
1751 }
1752 break;
1753 #endif /* CONFIG_AP_WOWLAN */
1754 case HW_VAR_DM_IN_LPS:
1755 rtl8723b_hal_dm_in_lps(padapter);
1756 break;
1757 default:
1758 SetHwReg8723B(padapter, variable, val);
1759 break;
1760 }
1761 }
1762
1763 /*
1764 * If variable not handled here,
1765 * some variables will be processed in GetHwReg8723B()
1766 */
GetHwReg8723BS(struct adapter * padapter,u8 variable,u8 * val)1767 static void GetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
1768 {
1769 switch (variable) {
1770 case HW_VAR_CPWM:
1771 *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8723B);
1772 break;
1773
1774 case HW_VAR_FW_PS_STATE:
1775 {
1776 /* 3. read dword 0x88 driver read fw ps state */
1777 *((u16 *)val) = rtw_read16(padapter, 0x88);
1778 }
1779 break;
1780 default:
1781 GetHwReg8723B(padapter, variable, val);
1782 break;
1783 }
1784 }
1785
SetHwRegWithBuf8723B(struct adapter * padapter,u8 variable,u8 * pbuf,int len)1786 static void SetHwRegWithBuf8723B(struct adapter *padapter, u8 variable, u8 *pbuf, int len)
1787 {
1788 switch (variable) {
1789 case HW_VAR_C2H_HANDLE:
1790 /* DBG_8192C("%s len =%d\n", __func__, len); */
1791 C2HPacketHandler_8723B(padapter, pbuf, len);
1792 break;
1793 default:
1794 break;
1795 }
1796 }
1797
1798 /* */
1799 /* Description: */
1800 /* Query setting of specified variable. */
1801 /* */
GetHalDefVar8723BSDIO(struct adapter * Adapter,enum HAL_DEF_VARIABLE eVariable,void * pValue)1802 static u8 GetHalDefVar8723BSDIO(
1803 struct adapter *Adapter, enum HAL_DEF_VARIABLE eVariable, void *pValue
1804 )
1805 {
1806 u8 bResult = _SUCCESS;
1807
1808 switch (eVariable) {
1809 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1810 break;
1811 case HAL_DEF_CURRENT_ANTENNA:
1812 break;
1813 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1814 /* Stanley@BB.SD3 suggests 16K can get stable performance */
1815 /* coding by Lucas@20130730 */
1816 *(u32 *)pValue = MAX_AMPDU_FACTOR_16K;
1817 break;
1818 default:
1819 bResult = GetHalDefVar8723B(Adapter, eVariable, pValue);
1820 break;
1821 }
1822
1823 return bResult;
1824 }
1825
1826 /* */
1827 /* Description: */
1828 /* Change default setting of specified variable. */
1829 /* */
SetHalDefVar8723BSDIO(struct adapter * Adapter,enum HAL_DEF_VARIABLE eVariable,void * pValue)1830 static u8 SetHalDefVar8723BSDIO(struct adapter *Adapter,
1831 enum HAL_DEF_VARIABLE eVariable, void *pValue)
1832 {
1833 return SetHalDefVar8723B(Adapter, eVariable, pValue);
1834 }
1835
rtl8723bs_set_hal_ops(struct adapter * padapter)1836 void rtl8723bs_set_hal_ops(struct adapter *padapter)
1837 {
1838 struct hal_ops *pHalFunc = &padapter->HalFunc;
1839
1840 rtl8723b_set_hal_ops(pHalFunc);
1841
1842 pHalFunc->hal_init = &rtl8723bs_hal_init;
1843 pHalFunc->hal_deinit = &rtl8723bs_hal_deinit;
1844
1845 pHalFunc->inirp_init = &rtl8723bs_inirp_init;
1846 pHalFunc->inirp_deinit = &rtl8723bs_inirp_deinit;
1847
1848 pHalFunc->init_xmit_priv = &rtl8723bs_init_xmit_priv;
1849 pHalFunc->free_xmit_priv = &rtl8723bs_free_xmit_priv;
1850
1851 pHalFunc->init_recv_priv = &rtl8723bs_init_recv_priv;
1852 pHalFunc->free_recv_priv = &rtl8723bs_free_recv_priv;
1853
1854 pHalFunc->init_default_value = &rtl8723bs_init_default_value;
1855 pHalFunc->intf_chip_configure = &rtl8723bs_interface_configure;
1856 pHalFunc->read_adapter_info = &ReadAdapterInfo8723BS;
1857
1858 pHalFunc->enable_interrupt = &EnableInterrupt8723BSdio;
1859 pHalFunc->disable_interrupt = &DisableInterrupt8723BSdio;
1860 pHalFunc->check_ips_status = &CheckIPSStatus;
1861 #ifdef CONFIG_WOWLAN
1862 pHalFunc->clear_interrupt = &ClearInterrupt8723BSdio;
1863 #endif
1864 pHalFunc->SetHwRegHandler = &SetHwReg8723BS;
1865 pHalFunc->GetHwRegHandler = &GetHwReg8723BS;
1866 pHalFunc->SetHwRegHandlerWithBuf = &SetHwRegWithBuf8723B;
1867 pHalFunc->GetHalDefVarHandler = &GetHalDefVar8723BSDIO;
1868 pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723BSDIO;
1869
1870 pHalFunc->hal_xmit = &rtl8723bs_hal_xmit;
1871 pHalFunc->mgnt_xmit = &rtl8723bs_mgnt_xmit;
1872 pHalFunc->hal_xmitframe_enqueue = &rtl8723bs_hal_xmitframe_enqueue;
1873
1874 #if defined(CONFIG_CHECK_BT_HANG)
1875 pHalFunc->hal_init_checkbthang_workqueue = &rtl8723bs_init_checkbthang_workqueue;
1876 pHalFunc->hal_free_checkbthang_workqueue = &rtl8723bs_free_checkbthang_workqueue;
1877 pHalFunc->hal_cancle_checkbthang_workqueue = &rtl8723bs_cancle_checkbthang_workqueue;
1878 pHalFunc->hal_checke_bt_hang = &rtl8723bs_hal_check_bt_hang;
1879 #endif
1880 }
1881
