1 /* SPDX-License-Identifier: GPL-2.0+ 2 * 3 * register description for HopeRf rf69 radio module 4 * 5 * Copyright (C) 2016 Wolf-Entwicklungen 6 * Marcus Wolf <linux@wolf-entwicklungen.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 /*******************************************/ 20 /* RF69 register addresses */ 21 /*******************************************/ 22 #define REG_FIFO 0x00 23 #define REG_OPMODE 0x01 24 #define REG_DATAMODUL 0x02 25 #define REG_BITRATE_MSB 0x03 26 #define REG_BITRATE_LSB 0x04 27 #define REG_FDEV_MSB 0x05 28 #define REG_FDEV_LSB 0x06 29 #define REG_FRF_MSB 0x07 30 #define REG_FRF_MID 0x08 31 #define REG_FRF_LSB 0x09 32 #define REG_OSC1 0x0A 33 #define REG_AFCCTRL 0x0B 34 #define REG_LOWBAT 0x0C 35 #define REG_LISTEN1 0x0D 36 #define REG_LISTEN2 0x0E 37 #define REG_LISTEN3 0x0F 38 #define REG_VERSION 0x10 39 #define REG_PALEVEL 0x11 40 #define REG_PARAMP 0x12 41 #define REG_OCP 0x13 42 #define REG_AGCREF 0x14 /* not available on RF69 */ 43 #define REG_AGCTHRESH1 0x15 /* not available on RF69 */ 44 #define REG_AGCTHRESH2 0x16 /* not available on RF69 */ 45 #define REG_AGCTHRESH3 0x17 /* not available on RF69 */ 46 #define REG_LNA 0x18 47 #define REG_RXBW 0x19 48 #define REG_AFCBW 0x1A 49 #define REG_OOKPEAK 0x1B 50 #define REG_OOKAVG 0x1C 51 #define REG_OOKFIX 0x1D 52 #define REG_AFCFEI 0x1E 53 #define REG_AFCMSB 0x1F 54 #define REG_AFCLSB 0x20 55 #define REG_FEIMSB 0x21 56 #define REG_FEILSB 0x22 57 #define REG_RSSICONFIG 0x23 58 #define REG_RSSIVALUE 0x24 59 #define REG_DIOMAPPING1 0x25 60 #define REG_DIOMAPPING2 0x26 61 #define REG_IRQFLAGS1 0x27 62 #define REG_IRQFLAGS2 0x28 63 #define REG_RSSITHRESH 0x29 64 #define REG_RXTIMEOUT1 0x2A 65 #define REG_RXTIMEOUT2 0x2B 66 #define REG_PREAMBLE_MSB 0x2C 67 #define REG_PREAMBLE_LSB 0x2D 68 #define REG_SYNC_CONFIG 0x2E 69 #define REG_SYNCVALUE1 0x2F 70 #define REG_SYNCVALUE2 0x30 71 #define REG_SYNCVALUE3 0x31 72 #define REG_SYNCVALUE4 0x32 73 #define REG_SYNCVALUE5 0x33 74 #define REG_SYNCVALUE6 0x34 75 #define REG_SYNCVALUE7 0x35 76 #define REG_SYNCVALUE8 0x36 77 #define REG_PACKETCONFIG1 0x37 78 #define REG_PAYLOAD_LENGTH 0x38 79 #define REG_NODEADRS 0x39 80 #define REG_BROADCASTADRS 0x3A 81 #define REG_AUTOMODES 0x3B 82 #define REG_FIFO_THRESH 0x3C 83 #define REG_PACKETCONFIG2 0x3D 84 #define REG_AESKEY1 0x3E 85 #define REG_AESKEY2 0x3F 86 #define REG_AESKEY3 0x40 87 #define REG_AESKEY4 0x41 88 #define REG_AESKEY5 0x42 89 #define REG_AESKEY6 0x43 90 #define REG_AESKEY7 0x44 91 #define REG_AESKEY8 0x45 92 #define REG_AESKEY9 0x46 93 #define REG_AESKEY10 0x47 94 #define REG_AESKEY11 0x48 95 #define REG_AESKEY12 0x49 96 #define REG_AESKEY13 0x4A 97 #define REG_AESKEY14 0x4B 98 #define REG_AESKEY15 0x4C 99 #define REG_AESKEY16 0x4D 100 #define REG_TEMP1 0x4E 101 #define REG_TEMP2 0x4F 102 #define REG_TESTPA1 0x5A /* only present on RFM69HW */ 103 #define REG_TESTPA2 0x5C /* only present on RFM69HW */ 104 #define REG_TESTDAGC 0x6F 105 106 /******************************************************/ 107 /* RF69/SX1231 bit definition */ 108 /******************************************************/ 109 /* write bit */ 110 #define WRITE_BIT 0x80 111 112 /* RegOpMode */ 113 #define MASK_OPMODE_SEQUENCER_OFF 0x80 114 #define MASK_OPMODE_LISTEN_ON 0x40 115 #define MASK_OPMODE_LISTEN_ABORT 0x20 116 #define MASK_OPMODE_MODE 0x1C 117 118 #define OPMODE_MODE_SLEEP 0x00 119 #define OPMODE_MODE_STANDBY 0x04 /* default */ 120 #define OPMODE_MODE_SYNTHESIZER 0x08 121 #define OPMODE_MODE_TRANSMIT 0x0C 122 #define OPMODE_MODE_RECEIVE 0x10 123 124 /* RegDataModul */ 125 #define MASK_DATAMODUL_MODE 0x06 126 #define MASK_DATAMODUL_MODULATION_TYPE 0x18 127 #define MASK_DATAMODUL_MODULATION_SHAPE 0x03 128 129 #define DATAMODUL_MODE_PACKET 0x00 /* default */ 130 #define DATAMODUL_MODE_CONTINUOUS 0x40 131 #define DATAMODUL_MODE_CONTINUOUS_NOSYNC 0x60 132 133 #define DATAMODUL_MODULATION_TYPE_FSK 0x00 /* default */ 134 #define DATAMODUL_MODULATION_TYPE_OOK 0x08 135 136 #define DATAMODUL_MODULATION_SHAPE_NONE 0x00 /* default */ 137 #define DATAMODUL_MODULATION_SHAPE_1_0 0x01 138 #define DATAMODUL_MODULATION_SHAPE_0_5 0x02 139 #define DATAMODUL_MODULATION_SHAPE_0_3 0x03 140 #define DATAMODUL_MODULATION_SHAPE_BR 0x01 141 #define DATAMODUL_MODULATION_SHAPE_2BR 0x02 142 143 /* RegFDevMsb (0x05)*/ 144 #define FDEVMASB_MASK 0x3f 145 146 /* 147 * // RegOsc1 148 * #define OSC1_RCCAL_START 0x80 149 * #define OSC1_RCCAL_DONE 0x40 150 * 151 * // RegLowBat 152 * #define LOWBAT_MONITOR 0x10 153 * #define LOWBAT_ON 0x08 154 * #define LOWBAT_OFF 0x00 // Default 155 * 156 * #define LOWBAT_TRIM_1695 0x00 157 * #define LOWBAT_TRIM_1764 0x01 158 * #define LOWBAT_TRIM_1835 0x02 // Default 159 * #define LOWBAT_TRIM_1905 0x03 160 * #define LOWBAT_TRIM_1976 0x04 161 * #define LOWBAT_TRIM_2045 0x05 162 * #define LOWBAT_TRIM_2116 0x06 163 * #define LOWBAT_TRIM_2185 0x07 164 * 165 * 166 * // RegListen1 167 * #define LISTEN1_RESOL_64 0x50 168 * #define LISTEN1_RESOL_4100 0xA0 // Default 169 * #define LISTEN1_RESOL_262000 0xF0 170 * 171 * #define LISTEN1_CRITERIA_RSSI 0x00 // Default 172 * #define LISTEN1_CRITERIA_RSSIANDSYNC 0x08 173 * 174 * #define LISTEN1_END_00 0x00 175 * #define LISTEN1_END_01 0x02 // Default 176 * #define LISTEN1_END_10 0x04 177 * 178 * 179 * // RegListen2 180 * #define LISTEN2_COEFIDLE_VALUE 0xF5 // Default 181 * 182 * // RegListen3 183 * #define LISTEN3_COEFRX_VALUE 0x20 // Default 184 */ 185 186 // RegPaLevel 187 #define MASK_PALEVEL_PA0 0x80 188 #define MASK_PALEVEL_PA1 0x40 189 #define MASK_PALEVEL_PA2 0x20 190 #define MASK_PALEVEL_OUTPUT_POWER 0x1F 191 192 // RegPaRamp 193 #define PARAMP_3400 0x00 194 #define PARAMP_2000 0x01 195 #define PARAMP_1000 0x02 196 #define PARAMP_500 0x03 197 #define PARAMP_250 0x04 198 #define PARAMP_125 0x05 199 #define PARAMP_100 0x06 200 #define PARAMP_62 0x07 201 #define PARAMP_50 0x08 202 #define PARAMP_40 0x09 /* default */ 203 #define PARAMP_31 0x0A 204 #define PARAMP_25 0x0B 205 #define PARAMP_20 0x0C 206 #define PARAMP_15 0x0D 207 #define PARAMP_12 0x0E 208 #define PARAMP_10 0x0F 209 210 #define MASK_PARAMP 0x0F 211 212 /* 213 * // RegOcp 214 * #define OCP_OFF 0x0F 215 * #define OCP_ON 0x1A // Default 216 * 217 * #define OCP_TRIM_45 0x00 218 * #define OCP_TRIM_50 0x01 219 * #define OCP_TRIM_55 0x02 220 * #define OCP_TRIM_60 0x03 221 * #define OCP_TRIM_65 0x04 222 * #define OCP_TRIM_70 0x05 223 * #define OCP_TRIM_75 0x06 224 * #define OCP_TRIM_80 0x07 225 * #define OCP_TRIM_85 0x08 226 * #define OCP_TRIM_90 0x09 227 * #define OCP_TRIM_95 0x0A 228 * #define OCP_TRIM_100 0x0B // Default 229 * #define OCP_TRIM_105 0x0C 230 * #define OCP_TRIM_110 0x0D 231 * #define OCP_TRIM_115 0x0E 232 * #define OCP_TRIM_120 0x0F 233 */ 234 235 /* RegLna (0x18) */ 236 #define MASK_LNA_ZIN 0x80 237 #define MASK_LNA_CURRENT_GAIN 0x38 238 #define MASK_LNA_GAIN 0x07 239 240 #define LNA_GAIN_AUTO 0x00 /* default */ 241 #define LNA_GAIN_MAX 0x01 242 #define LNA_GAIN_MAX_MINUS_6 0x02 243 #define LNA_GAIN_MAX_MINUS_12 0x03 244 #define LNA_GAIN_MAX_MINUS_24 0x04 245 #define LNA_GAIN_MAX_MINUS_36 0x05 246 #define LNA_GAIN_MAX_MINUS_48 0x06 247 248 /* RegRxBw (0x19) and RegAfcBw (0x1A) */ 249 #define MASK_BW_DCC_FREQ 0xE0 250 #define MASK_BW_MANTISSE 0x18 251 #define MASK_BW_EXPONENT 0x07 252 253 #define BW_DCC_16_PERCENT 0x00 254 #define BW_DCC_8_PERCENT 0x20 255 #define BW_DCC_4_PERCENT 0x40 /* default */ 256 #define BW_DCC_2_PERCENT 0x60 257 #define BW_DCC_1_PERCENT 0x80 258 #define BW_DCC_0_5_PERCENT 0xA0 259 #define BW_DCC_0_25_PERCENT 0xC0 260 #define BW_DCC_0_125_PERCENT 0xE0 261 262 #define BW_MANT_16 0x00 263 #define BW_MANT_20 0x08 264 #define BW_MANT_24 0x10 /* default */ 265 266 /* RegOokPeak (0x1B) */ 267 #define MASK_OOKPEAK_THRESTYPE 0xc0 268 #define MASK_OOKPEAK_THRESSTEP 0x38 269 #define MASK_OOKPEAK_THRESDEC 0x07 270 271 #define OOKPEAK_THRESHTYPE_FIXED 0x00 272 #define OOKPEAK_THRESHTYPE_PEAK 0x40 /* default */ 273 #define OOKPEAK_THRESHTYPE_AVERAGE 0x80 274 275 #define OOKPEAK_THRESHSTEP_0_5_DB 0x00 /* default */ 276 #define OOKPEAK_THRESHSTEP_1_0_DB 0x08 277 #define OOKPEAK_THRESHSTEP_1_5_DB 0x10 278 #define OOKPEAK_THRESHSTEP_2_0_DB 0x18 279 #define OOKPEAK_THRESHSTEP_3_0_DB 0x20 280 #define OOKPEAK_THRESHSTEP_4_0_DB 0x28 281 #define OOKPEAK_THRESHSTEP_5_0_DB 0x30 282 #define OOKPEAK_THRESHSTEP_6_0_DB 0x38 283 284 #define OOKPEAK_THRESHDEC_ONCE 0x00 /* default */ 285 #define OOKPEAK_THRESHDEC_EVERY_2ND 0x01 286 #define OOKPEAK_THRESHDEC_EVERY_4TH 0x02 287 #define OOKPEAK_THRESHDEC_EVERY_8TH 0x03 288 #define OOKPEAK_THRESHDEC_TWICE 0x04 289 #define OOKPEAK_THRESHDEC_4_TIMES 0x05 290 #define OOKPEAK_THRESHDEC_8_TIMES 0x06 291 #define OOKPEAK_THRESHDEC_16_TIMES 0x07 292 293 /* 294 * // RegOokAvg 295 * #define OOKAVG_AVERAGETHRESHFILT_00 0x00 296 * #define OOKAVG_AVERAGETHRESHFILT_01 0x40 297 * #define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default 298 * #define OOKAVG_AVERAGETHRESHFILT_11 0xC0 299 * 300 * 301 * // RegAfcFei 302 * #define AFCFEI_FEI_DONE 0x40 303 * #define AFCFEI_FEI_START 0x20 304 * #define AFCFEI_AFC_DONE 0x10 305 * #define AFCFEI_AFCAUTOCLEAR_ON 0x08 306 * #define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default 307 * 308 * #define AFCFEI_AFCAUTO_ON 0x04 309 * #define AFCFEI_AFCAUTO_OFF 0x00 // Default 310 * 311 * #define AFCFEI_AFC_CLEAR 0x02 312 * #define AFCFEI_AFC_START 0x01 313 * 314 * // RegRssiConfig 315 * #define RSSI_FASTRX_ON 0x08 316 * #define RSSI_FASTRX_OFF 0x00 // Default 317 * #define RSSI_DONE 0x02 318 * #define RSSI_START 0x01 319 */ 320 321 /* RegDioMapping1 */ 322 #define MASK_DIO0 0xC0 323 #define MASK_DIO1 0x30 324 #define MASK_DIO2 0x0C 325 #define MASK_DIO3 0x03 326 #define SHIFT_DIO0 6 327 #define SHIFT_DIO1 4 328 #define SHIFT_DIO2 2 329 #define SHIFT_DIO3 0 330 331 /* RegDioMapping2 */ 332 #define MASK_DIO4 0xC0 333 #define MASK_DIO5 0x30 334 #define SHIFT_DIO4 6 335 #define SHIFT_DIO5 4 336 337 /* DIO numbers */ 338 #define DIO0 0 339 #define DIO1 1 340 #define DIO2 2 341 #define DIO3 3 342 #define DIO4 4 343 #define DIO5 5 344 345 /* DIO Mapping values (packet mode) */ 346 #define DIO_MODE_READY_DIO4 0x00 347 #define DIO_MODE_READY_DIO5 0x03 348 #define DIO_CLK_OUT 0x00 349 #define DIO_DATA 0x01 350 #define DIO_TIMEOUT_DIO1 0x03 351 #define DIO_TIMEOUT_DIO4 0x00 352 #define DIO_RSSI_DIO0 0x03 353 #define DIO_RSSI_DIO3_4 0x01 354 #define DIO_RX_READY 0x02 355 #define DIO_PLL_LOCK 0x03 356 #define DIO_TX_READY 0x01 357 #define DIO_FIFO_FULL_DIO1 0x01 358 #define DIO_FIFO_FULL_DIO3 0x00 359 #define DIO_SYNC_ADDRESS 0x02 360 #define DIO_FIFO_NOT_EMPTY_DIO1 0x02 361 #define DIO_FIFO_NOT_EMPTY_FIO2 0x00 362 #define DIO_AUTOMODE 0x04 363 #define DIO_FIFO_LEVEL 0x00 364 #define DIO_CRC_OK 0x00 365 #define DIO_PAYLOAD_READY 0x01 366 #define DIO_PACKET_SENT 0x00 367 #define DIO_DCLK 0x00 368 369 /* RegDioMapping2 CLK_OUT part */ 370 #define MASK_DIOMAPPING2_CLK_OUT 0x07 371 372 #define DIOMAPPING2_CLK_OUT_NO_DIV 0x00 373 #define DIOMAPPING2_CLK_OUT_DIV_2 0x01 374 #define DIOMAPPING2_CLK_OUT_DIV_4 0x02 375 #define DIOMAPPING2_CLK_OUT_DIV_8 0x03 376 #define DIOMAPPING2_CLK_OUT_DIV_16 0x04 377 #define DIOMAPPING2_CLK_OUT_DIV_32 0x05 378 #define DIOMAPPING2_CLK_OUT_RC 0x06 379 #define DIOMAPPING2_CLK_OUT_OFF 0x07 /* default */ 380 381 /* RegIrqFlags1 */ 382 #define MASK_IRQFLAGS1_MODE_READY 0x80 383 #define MASK_IRQFLAGS1_RX_READY 0x40 384 #define MASK_IRQFLAGS1_TX_READY 0x20 385 #define MASK_IRQFLAGS1_PLL_LOCK 0x10 386 #define MASK_IRQFLAGS1_RSSI 0x08 387 #define MASK_IRQFLAGS1_TIMEOUT 0x04 388 #define MASK_IRQFLAGS1_AUTOMODE 0x02 389 #define MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH 0x01 390 391 /* RegIrqFlags2 */ 392 #define MASK_IRQFLAGS2_FIFO_FULL 0x80 393 #define MASK_IRQFLAGS2_FIFO_NOT_EMPTY 0x40 394 #define MASK_IRQFLAGS2_FIFO_LEVEL 0x20 395 #define MASK_IRQFLAGS2_FIFO_OVERRUN 0x10 396 #define MASK_IRQFLAGS2_PACKET_SENT 0x08 397 #define MASK_IRQFLAGS2_PAYLOAD_READY 0x04 398 #define MASK_IRQFLAGS2_CRC_OK 0x02 399 #define MASK_IRQFLAGS2_LOW_BAT 0x01 400 401 /* RegSyncConfig */ 402 #define MASK_SYNC_CONFIG_SYNC_ON 0x80 /* default */ 403 #define MASK_SYNC_CONFIG_FIFO_FILL_CONDITION 0x40 404 #define MASK_SYNC_CONFIG_SYNC_SIZE 0x38 405 #define MASK_SYNC_CONFIG_SYNC_TOLERANCE 0x07 406 407 /* RegPacketConfig1 */ 408 #define MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE 0x80 409 #define MASK_PACKETCONFIG1_DCFREE 0x60 410 #define MASK_PACKETCONFIG1_CRC_ON 0x10 /* default */ 411 #define MASK_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 412 #define MASK_PACKETCONFIG1_ADDRESSFILTERING 0x06 413 414 #define PACKETCONFIG1_DCFREE_OFF 0x00 /* default */ 415 #define PACKETCONFIG1_DCFREE_MANCHESTER 0x20 416 #define PACKETCONFIG1_DCFREE_WHITENING 0x40 417 #define PACKETCONFIG1_ADDRESSFILTERING_OFF 0x00 /* default */ 418 #define PACKETCONFIG1_ADDRESSFILTERING_NODE 0x02 419 #define PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST 0x04 420 421 /* 422 * // RegAutoModes 423 * #define AUTOMODES_ENTER_OFF 0x00 // Default 424 * #define AUTOMODES_ENTER_FIFONOTEMPTY 0x20 425 * #define AUTOMODES_ENTER_FIFOLEVEL 0x40 426 * #define AUTOMODES_ENTER_CRCOK 0x60 427 * #define AUTOMODES_ENTER_PAYLOADREADY 0x80 428 * #define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0 429 * #define AUTOMODES_ENTER_PACKETSENT 0xC0 430 * #define AUTOMODES_ENTER_FIFOEMPTY 0xE0 431 * 432 * #define AUTOMODES_EXIT_OFF 0x00 // Default 433 * #define AUTOMODES_EXIT_FIFOEMPTY 0x04 434 * #define AUTOMODES_EXIT_FIFOLEVEL 0x08 435 * #define AUTOMODES_EXIT_CRCOK 0x0C 436 * #define AUTOMODES_EXIT_PAYLOADREADY 0x10 437 * #define AUTOMODES_EXIT_SYNCADRSMATCH 0x14 438 * #define AUTOMODES_EXIT_PACKETSENT 0x18 439 * #define AUTOMODES_EXIT_RXTIMEOUT 0x1C 440 * 441 * #define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default 442 * #define AUTOMODES_INTERMEDIATE_STANDBY 0x01 443 * #define AUTOMODES_INTERMEDIATE_RECEIVER 0x02 444 * #define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03 445 * 446 */ 447 /* RegFifoThresh (0x3c) */ 448 #define MASK_FIFO_THRESH_TXSTART 0x80 449 #define MASK_FIFO_THRESH_VALUE 0x7F 450 451 /* 452 * 453 * // RegPacketConfig2 454 * #define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default 455 * #define PACKET2_RXRESTARTDELAY_2BITS 0x10 456 * #define PACKET2_RXRESTARTDELAY_4BITS 0x20 457 * #define PACKET2_RXRESTARTDELAY_8BITS 0x30 458 * #define PACKET2_RXRESTARTDELAY_16BITS 0x40 459 * #define PACKET2_RXRESTARTDELAY_32BITS 0x50 460 * #define PACKET2_RXRESTARTDELAY_64BITS 0x60 461 * #define PACKET2_RXRESTARTDELAY_128BITS 0x70 462 * #define PACKET2_RXRESTARTDELAY_256BITS 0x80 463 * #define PACKET2_RXRESTARTDELAY_512BITS 0x90 464 * #define PACKET2_RXRESTARTDELAY_1024BITS 0xA0 465 * #define PACKET2_RXRESTARTDELAY_2048BITS 0xB0 466 * #define PACKET2_RXRESTARTDELAY_NONE 0xC0 467 * #define PACKET2_RXRESTART 0x04 468 * 469 * #define PACKET2_AUTORXRESTART_ON 0x02 // Default 470 * #define PACKET2_AUTORXRESTART_OFF 0x00 471 * 472 * #define PACKET2_AES_ON 0x01 473 * #define PACKET2_AES_OFF 0x00 // Default 474 * 475 * 476 * // RegTemp1 477 * #define TEMP1_MEAS_START 0x08 478 * #define TEMP1_MEAS_RUNNING 0x04 479 * #define TEMP1_ADCLOWPOWER_ON 0x01 // Default 480 * #define TEMP1_ADCLOWPOWER_OFF 0x00 481 */ 482 483 // RegTestDagc (0x6F) 484 #define DAGC_NORMAL 0x00 /* Reset value */ 485 #define DAGC_IMPROVED_LOWBETA1 0x20 486 #define DAGC_IMPROVED_LOWBETA0 0x30 /* Recommended val */ 487
