1 #ifndef _HFI1_KERNEL_H
2 #define _HFI1_KERNEL_H
3 /*
4 * Copyright(c) 2015-2018 Intel Corporation.
5 *
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
8 *
9 * GPL LICENSE SUMMARY
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * BSD LICENSE
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 *
26 * - Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * - Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
31 * distribution.
32 * - Neither the name of Intel Corporation nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific prior written permission.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 *
48 */
49
50 #include <linux/interrupt.h>
51 #include <linux/pci.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/mutex.h>
54 #include <linux/list.h>
55 #include <linux/scatterlist.h>
56 #include <linux/slab.h>
57 #include <linux/io.h>
58 #include <linux/fs.h>
59 #include <linux/completion.h>
60 #include <linux/kref.h>
61 #include <linux/sched.h>
62 #include <linux/cdev.h>
63 #include <linux/delay.h>
64 #include <linux/kthread.h>
65 #include <linux/i2c.h>
66 #include <linux/i2c-algo-bit.h>
67 #include <linux/xarray.h>
68 #include <rdma/ib_hdrs.h>
69 #include <rdma/opa_addr.h>
70 #include <linux/rhashtable.h>
71 #include <linux/netdevice.h>
72 #include <rdma/rdma_vt.h>
73
74 #include "chip_registers.h"
75 #include "common.h"
76 #include "opfn.h"
77 #include "verbs.h"
78 #include "pio.h"
79 #include "chip.h"
80 #include "mad.h"
81 #include "qsfp.h"
82 #include "platform.h"
83 #include "affinity.h"
84 #include "msix.h"
85
86 /* bumped 1 from s/w major version of TrueScale */
87 #define HFI1_CHIP_VERS_MAJ 3U
88
89 /* don't care about this except printing */
90 #define HFI1_CHIP_VERS_MIN 0U
91
92 /* The Organization Unique Identifier (Mfg code), and its position in GUID */
93 #define HFI1_OUI 0x001175
94 #define HFI1_OUI_LSB 40
95
96 #define DROP_PACKET_OFF 0
97 #define DROP_PACKET_ON 1
98
99 #define NEIGHBOR_TYPE_HFI 0
100 #define NEIGHBOR_TYPE_SWITCH 1
101
102 #define HFI1_MAX_ACTIVE_WORKQUEUE_ENTRIES 5
103
104 extern unsigned long hfi1_cap_mask;
105 #define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
106 #define HFI1_CAP_UGET_MASK(mask, cap) \
107 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
108 #define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
109 #define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
110 #define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
111 #define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
112 #define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
113 HFI1_CAP_MISC_MASK)
114 /* Offline Disabled Reason is 4-bits */
115 #define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
116
117 /*
118 * Control context is always 0 and handles the error packets.
119 * It also handles the VL15 and multicast packets.
120 */
121 #define HFI1_CTRL_CTXT 0
122
123 /*
124 * Driver context will store software counters for each of the events
125 * associated with these status registers
126 */
127 #define NUM_CCE_ERR_STATUS_COUNTERS 41
128 #define NUM_RCV_ERR_STATUS_COUNTERS 64
129 #define NUM_MISC_ERR_STATUS_COUNTERS 13
130 #define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
131 #define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
132 #define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
133 #define NUM_SEND_ERR_STATUS_COUNTERS 3
134 #define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
135 #define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
136
137 /*
138 * per driver stats, either not device nor port-specific, or
139 * summed over all of the devices and ports.
140 * They are described by name via ipathfs filesystem, so layout
141 * and number of elements can change without breaking compatibility.
142 * If members are added or deleted hfi1_statnames[] in debugfs.c must
143 * change to match.
144 */
145 struct hfi1_ib_stats {
146 __u64 sps_ints; /* number of interrupts handled */
147 __u64 sps_errints; /* number of error interrupts */
148 __u64 sps_txerrs; /* tx-related packet errors */
149 __u64 sps_rcverrs; /* non-crc rcv packet errors */
150 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
151 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
152 __u64 sps_ctxts; /* number of contexts currently open */
153 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
154 __u64 sps_buffull;
155 __u64 sps_hdrfull;
156 };
157
158 extern struct hfi1_ib_stats hfi1_stats;
159 extern const struct pci_error_handlers hfi1_pci_err_handler;
160
161 extern int num_driver_cntrs;
162
163 /*
164 * First-cut criterion for "device is active" is
165 * two thousand dwords combined Tx, Rx traffic per
166 * 5-second interval. SMA packets are 64 dwords,
167 * and occur "a few per second", presumably each way.
168 */
169 #define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
170
171 /*
172 * Below contains all data related to a single context (formerly called port).
173 */
174
175 struct hfi1_opcode_stats_perctx;
176
177 struct ctxt_eager_bufs {
178 struct eager_buffer {
179 void *addr;
180 dma_addr_t dma;
181 ssize_t len;
182 } *buffers;
183 struct {
184 void *addr;
185 dma_addr_t dma;
186 } *rcvtids;
187 u32 size; /* total size of eager buffers */
188 u32 rcvtid_size; /* size of each eager rcv tid */
189 u16 count; /* size of buffers array */
190 u16 numbufs; /* number of buffers allocated */
191 u16 alloced; /* number of rcvarray entries used */
192 u16 threshold; /* head update threshold */
193 };
194
195 struct exp_tid_set {
196 struct list_head list;
197 u32 count;
198 };
199
200 typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
201
202 struct tid_queue {
203 struct list_head queue_head;
204 /* queue head for QP TID resource waiters */
205 u32 enqueue; /* count of tid enqueues */
206 u32 dequeue; /* count of tid dequeues */
207 };
208
209 struct hfi1_ctxtdata {
210 /* rcvhdrq base, needs mmap before useful */
211 void *rcvhdrq;
212 /* kernel virtual address where hdrqtail is updated */
213 volatile __le64 *rcvhdrtail_kvaddr;
214 /* so functions that need physical port can get it easily */
215 struct hfi1_pportdata *ppd;
216 /* so file ops can get at unit */
217 struct hfi1_devdata *dd;
218 /* this receive context's assigned PIO ACK send context */
219 struct send_context *sc;
220 /* per context recv functions */
221 const rhf_rcv_function_ptr *rhf_rcv_function_map;
222 /*
223 * The interrupt handler for a particular receive context can vary
224 * throughout it's lifetime. This is not a lock protected data member so
225 * it must be updated atomically and the prev and new value must always
226 * be valid. Worst case is we process an extra interrupt and up to 64
227 * packets with the wrong interrupt handler.
228 */
229 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
230 /* verbs rx_stats per rcd */
231 struct hfi1_opcode_stats_perctx *opstats;
232 /* clear interrupt mask */
233 u64 imask;
234 /* ctxt rcvhdrq head offset */
235 u32 head;
236 /* number of rcvhdrq entries */
237 u16 rcvhdrq_cnt;
238 u8 ireg; /* clear interrupt register */
239 /* receive packet sequence counter */
240 u8 seq_cnt;
241 /* size of each of the rcvhdrq entries */
242 u8 rcvhdrqentsize;
243 /* offset of RHF within receive header entry */
244 u8 rhf_offset;
245 /* dynamic receive available interrupt timeout */
246 u8 rcvavail_timeout;
247 /* Indicates that this is vnic context */
248 bool is_vnic;
249 /* vnic queue index this context is mapped to */
250 u8 vnic_q_idx;
251 /* Is ASPM interrupt supported for this context */
252 bool aspm_intr_supported;
253 /* ASPM state (enabled/disabled) for this context */
254 bool aspm_enabled;
255 /* Is ASPM processing enabled for this context (in intr context) */
256 bool aspm_intr_enable;
257 struct ctxt_eager_bufs egrbufs;
258 /* QPs waiting for context processing */
259 struct list_head qp_wait_list;
260 /* tid allocation lists */
261 struct exp_tid_set tid_group_list;
262 struct exp_tid_set tid_used_list;
263 struct exp_tid_set tid_full_list;
264
265 /* Timer for re-enabling ASPM if interrupt activity quiets down */
266 struct timer_list aspm_timer;
267 /* per-context configuration flags */
268 unsigned long flags;
269 /* array of tid_groups */
270 struct tid_group *groups;
271 /* mmap of hdrq, must fit in 44 bits */
272 dma_addr_t rcvhdrq_dma;
273 dma_addr_t rcvhdrqtailaddr_dma;
274 /* Last interrupt timestamp */
275 ktime_t aspm_ts_last_intr;
276 /* Last timestamp at which we scheduled a timer for this context */
277 ktime_t aspm_ts_timer_sched;
278 /* Lock to serialize between intr, timer intr and user threads */
279 spinlock_t aspm_lock;
280 /* Reference count the base context usage */
281 struct kref kref;
282 /* numa node of this context */
283 int numa_id;
284 /* associated msix interrupt. */
285 s16 msix_intr;
286 /* job key */
287 u16 jkey;
288 /* number of RcvArray groups for this context. */
289 u16 rcv_array_groups;
290 /* index of first eager TID entry. */
291 u16 eager_base;
292 /* number of expected TID entries */
293 u16 expected_count;
294 /* index of first expected TID entry. */
295 u16 expected_base;
296 /* Device context index */
297 u8 ctxt;
298
299 /* PSM Specific fields */
300 /* lock protecting all Expected TID data */
301 struct mutex exp_mutex;
302 /* lock protecting all Expected TID data of kernel contexts */
303 spinlock_t exp_lock;
304 /* Queue for QP's waiting for HW TID flows */
305 struct tid_queue flow_queue;
306 /* Queue for QP's waiting for HW receive array entries */
307 struct tid_queue rarr_queue;
308 /* when waiting for rcv or pioavail */
309 wait_queue_head_t wait;
310 /* uuid from PSM */
311 u8 uuid[16];
312 /* same size as task_struct .comm[], command that opened context */
313 char comm[TASK_COMM_LEN];
314 /* Bitmask of in use context(s) */
315 DECLARE_BITMAP(in_use_ctxts, HFI1_MAX_SHARED_CTXTS);
316 /* per-context event flags for fileops/intr communication */
317 unsigned long event_flags;
318 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
319 void *subctxt_uregbase;
320 /* An array of pages for the eager receive buffers * N */
321 void *subctxt_rcvegrbuf;
322 /* An array of pages for the eager header queue entries * N */
323 void *subctxt_rcvhdr_base;
324 /* total number of polled urgent packets */
325 u32 urgent;
326 /* saved total number of polled urgent packets for poll edge trigger */
327 u32 urgent_poll;
328 /* Type of packets or conditions we want to poll for */
329 u16 poll_type;
330 /* non-zero if ctxt is being shared. */
331 u16 subctxt_id;
332 /* The version of the library which opened this ctxt */
333 u32 userversion;
334 /*
335 * non-zero if ctxt can be shared, and defines the maximum number of
336 * sub-contexts for this device context.
337 */
338 u8 subctxt_cnt;
339
340 /* Bit mask to track free TID RDMA HW flows */
341 unsigned long flow_mask;
342 struct tid_flow_state flows[RXE_NUM_TID_FLOWS];
343 };
344
345 /**
346 * rcvhdrq_size - return total size in bytes for header queue
347 * @rcd: the receive context
348 *
349 * rcvhdrqentsize is in DWs, so we have to convert to bytes
350 *
351 */
rcvhdrq_size(struct hfi1_ctxtdata * rcd)352 static inline u32 rcvhdrq_size(struct hfi1_ctxtdata *rcd)
353 {
354 return PAGE_ALIGN(rcd->rcvhdrq_cnt *
355 rcd->rcvhdrqentsize * sizeof(u32));
356 }
357
358 /*
359 * Represents a single packet at a high level. Put commonly computed things in
360 * here so we do not have to keep doing them over and over. The rule of thumb is
361 * if something is used one time to derive some value, store that something in
362 * here. If it is used multiple times, then store the result of that derivation
363 * in here.
364 */
365 struct hfi1_packet {
366 void *ebuf;
367 void *hdr;
368 void *payload;
369 struct hfi1_ctxtdata *rcd;
370 __le32 *rhf_addr;
371 struct rvt_qp *qp;
372 struct ib_other_headers *ohdr;
373 struct ib_grh *grh;
374 struct opa_16b_mgmt *mgmt;
375 u64 rhf;
376 u32 maxcnt;
377 u32 rhqoff;
378 u32 dlid;
379 u32 slid;
380 u16 tlen;
381 s16 etail;
382 u16 pkey;
383 u8 hlen;
384 u8 numpkt;
385 u8 rsize;
386 u8 updegr;
387 u8 etype;
388 u8 extra_byte;
389 u8 pad;
390 u8 sc;
391 u8 sl;
392 u8 opcode;
393 bool migrated;
394 };
395
396 /* Packet types */
397 #define HFI1_PKT_TYPE_9B 0
398 #define HFI1_PKT_TYPE_16B 1
399
400 /*
401 * OPA 16B Header
402 */
403 #define OPA_16B_L4_MASK 0xFFull
404 #define OPA_16B_SC_MASK 0x1F00000ull
405 #define OPA_16B_SC_SHIFT 20
406 #define OPA_16B_LID_MASK 0xFFFFFull
407 #define OPA_16B_DLID_MASK 0xF000ull
408 #define OPA_16B_DLID_SHIFT 20
409 #define OPA_16B_DLID_HIGH_SHIFT 12
410 #define OPA_16B_SLID_MASK 0xF00ull
411 #define OPA_16B_SLID_SHIFT 20
412 #define OPA_16B_SLID_HIGH_SHIFT 8
413 #define OPA_16B_BECN_MASK 0x80000000ull
414 #define OPA_16B_BECN_SHIFT 31
415 #define OPA_16B_FECN_MASK 0x10000000ull
416 #define OPA_16B_FECN_SHIFT 28
417 #define OPA_16B_L2_MASK 0x60000000ull
418 #define OPA_16B_L2_SHIFT 29
419 #define OPA_16B_PKEY_MASK 0xFFFF0000ull
420 #define OPA_16B_PKEY_SHIFT 16
421 #define OPA_16B_LEN_MASK 0x7FF00000ull
422 #define OPA_16B_LEN_SHIFT 20
423 #define OPA_16B_RC_MASK 0xE000000ull
424 #define OPA_16B_RC_SHIFT 25
425 #define OPA_16B_AGE_MASK 0xFF0000ull
426 #define OPA_16B_AGE_SHIFT 16
427 #define OPA_16B_ENTROPY_MASK 0xFFFFull
428
429 /*
430 * OPA 16B L2/L4 Encodings
431 */
432 #define OPA_16B_L4_9B 0x00
433 #define OPA_16B_L2_TYPE 0x02
434 #define OPA_16B_L4_FM 0x08
435 #define OPA_16B_L4_IB_LOCAL 0x09
436 #define OPA_16B_L4_IB_GLOBAL 0x0A
437 #define OPA_16B_L4_ETHR OPA_VNIC_L4_ETHR
438
439 /*
440 * OPA 16B Management
441 */
442 #define OPA_16B_L4_FM_PAD 3 /* fixed 3B pad */
443 #define OPA_16B_L4_FM_HLEN 24 /* 16B(16) + L4_FM(8) */
444
hfi1_16B_get_l4(struct hfi1_16b_header * hdr)445 static inline u8 hfi1_16B_get_l4(struct hfi1_16b_header *hdr)
446 {
447 return (u8)(hdr->lrh[2] & OPA_16B_L4_MASK);
448 }
449
hfi1_16B_get_sc(struct hfi1_16b_header * hdr)450 static inline u8 hfi1_16B_get_sc(struct hfi1_16b_header *hdr)
451 {
452 return (u8)((hdr->lrh[1] & OPA_16B_SC_MASK) >> OPA_16B_SC_SHIFT);
453 }
454
hfi1_16B_get_dlid(struct hfi1_16b_header * hdr)455 static inline u32 hfi1_16B_get_dlid(struct hfi1_16b_header *hdr)
456 {
457 return (u32)((hdr->lrh[1] & OPA_16B_LID_MASK) |
458 (((hdr->lrh[2] & OPA_16B_DLID_MASK) >>
459 OPA_16B_DLID_HIGH_SHIFT) << OPA_16B_DLID_SHIFT));
460 }
461
hfi1_16B_get_slid(struct hfi1_16b_header * hdr)462 static inline u32 hfi1_16B_get_slid(struct hfi1_16b_header *hdr)
463 {
464 return (u32)((hdr->lrh[0] & OPA_16B_LID_MASK) |
465 (((hdr->lrh[2] & OPA_16B_SLID_MASK) >>
466 OPA_16B_SLID_HIGH_SHIFT) << OPA_16B_SLID_SHIFT));
467 }
468
hfi1_16B_get_becn(struct hfi1_16b_header * hdr)469 static inline u8 hfi1_16B_get_becn(struct hfi1_16b_header *hdr)
470 {
471 return (u8)((hdr->lrh[0] & OPA_16B_BECN_MASK) >> OPA_16B_BECN_SHIFT);
472 }
473
hfi1_16B_get_fecn(struct hfi1_16b_header * hdr)474 static inline u8 hfi1_16B_get_fecn(struct hfi1_16b_header *hdr)
475 {
476 return (u8)((hdr->lrh[1] & OPA_16B_FECN_MASK) >> OPA_16B_FECN_SHIFT);
477 }
478
hfi1_16B_get_l2(struct hfi1_16b_header * hdr)479 static inline u8 hfi1_16B_get_l2(struct hfi1_16b_header *hdr)
480 {
481 return (u8)((hdr->lrh[1] & OPA_16B_L2_MASK) >> OPA_16B_L2_SHIFT);
482 }
483
hfi1_16B_get_pkey(struct hfi1_16b_header * hdr)484 static inline u16 hfi1_16B_get_pkey(struct hfi1_16b_header *hdr)
485 {
486 return (u16)((hdr->lrh[2] & OPA_16B_PKEY_MASK) >> OPA_16B_PKEY_SHIFT);
487 }
488
hfi1_16B_get_rc(struct hfi1_16b_header * hdr)489 static inline u8 hfi1_16B_get_rc(struct hfi1_16b_header *hdr)
490 {
491 return (u8)((hdr->lrh[1] & OPA_16B_RC_MASK) >> OPA_16B_RC_SHIFT);
492 }
493
hfi1_16B_get_age(struct hfi1_16b_header * hdr)494 static inline u8 hfi1_16B_get_age(struct hfi1_16b_header *hdr)
495 {
496 return (u8)((hdr->lrh[3] & OPA_16B_AGE_MASK) >> OPA_16B_AGE_SHIFT);
497 }
498
hfi1_16B_get_len(struct hfi1_16b_header * hdr)499 static inline u16 hfi1_16B_get_len(struct hfi1_16b_header *hdr)
500 {
501 return (u16)((hdr->lrh[0] & OPA_16B_LEN_MASK) >> OPA_16B_LEN_SHIFT);
502 }
503
hfi1_16B_get_entropy(struct hfi1_16b_header * hdr)504 static inline u16 hfi1_16B_get_entropy(struct hfi1_16b_header *hdr)
505 {
506 return (u16)(hdr->lrh[3] & OPA_16B_ENTROPY_MASK);
507 }
508
509 #define OPA_16B_MAKE_QW(low_dw, high_dw) (((u64)(high_dw) << 32) | (low_dw))
510
511 /*
512 * BTH
513 */
514 #define OPA_16B_BTH_PAD_MASK 7
hfi1_16B_bth_get_pad(struct ib_other_headers * ohdr)515 static inline u8 hfi1_16B_bth_get_pad(struct ib_other_headers *ohdr)
516 {
517 return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_PAD_SHIFT) &
518 OPA_16B_BTH_PAD_MASK);
519 }
520
521 /*
522 * 16B Management
523 */
524 #define OPA_16B_MGMT_QPN_MASK 0xFFFFFF
hfi1_16B_get_dest_qpn(struct opa_16b_mgmt * mgmt)525 static inline u32 hfi1_16B_get_dest_qpn(struct opa_16b_mgmt *mgmt)
526 {
527 return be32_to_cpu(mgmt->dest_qpn) & OPA_16B_MGMT_QPN_MASK;
528 }
529
hfi1_16B_get_src_qpn(struct opa_16b_mgmt * mgmt)530 static inline u32 hfi1_16B_get_src_qpn(struct opa_16b_mgmt *mgmt)
531 {
532 return be32_to_cpu(mgmt->src_qpn) & OPA_16B_MGMT_QPN_MASK;
533 }
534
hfi1_16B_set_qpn(struct opa_16b_mgmt * mgmt,u32 dest_qp,u32 src_qp)535 static inline void hfi1_16B_set_qpn(struct opa_16b_mgmt *mgmt,
536 u32 dest_qp, u32 src_qp)
537 {
538 mgmt->dest_qpn = cpu_to_be32(dest_qp & OPA_16B_MGMT_QPN_MASK);
539 mgmt->src_qpn = cpu_to_be32(src_qp & OPA_16B_MGMT_QPN_MASK);
540 }
541
542 /**
543 * hfi1_get_rc_ohdr - get extended header
544 * @opah - the opaheader
545 */
546 static inline struct ib_other_headers *
hfi1_get_rc_ohdr(struct hfi1_opa_header * opah)547 hfi1_get_rc_ohdr(struct hfi1_opa_header *opah)
548 {
549 struct ib_other_headers *ohdr;
550 struct ib_header *hdr = NULL;
551 struct hfi1_16b_header *hdr_16b = NULL;
552
553 /* Find out where the BTH is */
554 if (opah->hdr_type == HFI1_PKT_TYPE_9B) {
555 hdr = &opah->ibh;
556 if (ib_get_lnh(hdr) == HFI1_LRH_BTH)
557 ohdr = &hdr->u.oth;
558 else
559 ohdr = &hdr->u.l.oth;
560 } else {
561 u8 l4;
562
563 hdr_16b = &opah->opah;
564 l4 = hfi1_16B_get_l4(hdr_16b);
565 if (l4 == OPA_16B_L4_IB_LOCAL)
566 ohdr = &hdr_16b->u.oth;
567 else
568 ohdr = &hdr_16b->u.l.oth;
569 }
570 return ohdr;
571 }
572
573 struct rvt_sge_state;
574
575 /*
576 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
577 * Mostly for MADs that set or query link parameters, also ipath
578 * config interfaces
579 */
580 #define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
581 #define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
582 #define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
583 #define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
584 #define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
585 #define HFI1_IB_CFG_SPD 5 /* current Link spd */
586 #define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
587 #define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
588 #define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
589 #define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
590 #define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
591 #define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
592 #define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
593 #define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
594 #define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
595 #define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
596 #define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
597 #define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
598 #define HFI1_IB_CFG_VL_HIGH_LIMIT 19
599 #define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
600 #define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
601
602 /*
603 * HFI or Host Link States
604 *
605 * These describe the states the driver thinks the logical and physical
606 * states are in. Used as an argument to set_link_state(). Implemented
607 * as bits for easy multi-state checking. The actual state can only be
608 * one.
609 */
610 #define __HLS_UP_INIT_BP 0
611 #define __HLS_UP_ARMED_BP 1
612 #define __HLS_UP_ACTIVE_BP 2
613 #define __HLS_DN_DOWNDEF_BP 3 /* link down default */
614 #define __HLS_DN_POLL_BP 4
615 #define __HLS_DN_DISABLE_BP 5
616 #define __HLS_DN_OFFLINE_BP 6
617 #define __HLS_VERIFY_CAP_BP 7
618 #define __HLS_GOING_UP_BP 8
619 #define __HLS_GOING_OFFLINE_BP 9
620 #define __HLS_LINK_COOLDOWN_BP 10
621
622 #define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
623 #define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
624 #define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
625 #define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
626 #define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
627 #define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
628 #define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
629 #define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
630 #define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
631 #define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
632 #define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
633
634 #define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
635 #define HLS_DOWN ~(HLS_UP)
636
637 #define HLS_DEFAULT HLS_DN_POLL
638
639 /* use this MTU size if none other is given */
640 #define HFI1_DEFAULT_ACTIVE_MTU 10240
641 /* use this MTU size as the default maximum */
642 #define HFI1_DEFAULT_MAX_MTU 10240
643 /* default partition key */
644 #define DEFAULT_PKEY 0xffff
645
646 /*
647 * Possible fabric manager config parameters for fm_{get,set}_table()
648 */
649 #define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */
650 #define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */
651 #define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */
652 #define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */
653 #define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */
654 #define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */
655
656 /*
657 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
658 * these are bits so they can be combined, e.g.
659 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
660 */
661 #define HFI1_RCVCTRL_TAILUPD_ENB 0x01
662 #define HFI1_RCVCTRL_TAILUPD_DIS 0x02
663 #define HFI1_RCVCTRL_CTXT_ENB 0x04
664 #define HFI1_RCVCTRL_CTXT_DIS 0x08
665 #define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
666 #define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
667 #define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
668 #define HFI1_RCVCTRL_PKEY_DIS 0x80
669 #define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
670 #define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
671 #define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
672 #define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
673 #define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
674 #define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
675 #define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
676 #define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
677 #define HFI1_RCVCTRL_URGENT_ENB 0x40000
678 #define HFI1_RCVCTRL_URGENT_DIS 0x80000
679
680 /* partition enforcement flags */
681 #define HFI1_PART_ENFORCE_IN 0x1
682 #define HFI1_PART_ENFORCE_OUT 0x2
683
684 /* how often we check for synthetic counter wrap around */
685 #define SYNTH_CNT_TIME 3
686
687 /* Counter flags */
688 #define CNTR_NORMAL 0x0 /* Normal counters, just read register */
689 #define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */
690 #define CNTR_DISABLED 0x2 /* Disable this counter */
691 #define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */
692 #define CNTR_VL 0x8 /* Per VL counter */
693 #define CNTR_SDMA 0x10
694 #define CNTR_INVALID_VL -1 /* Specifies invalid VL */
695 #define CNTR_MODE_W 0x0
696 #define CNTR_MODE_R 0x1
697
698 /* VLs Supported/Operational */
699 #define HFI1_MIN_VLS_SUPPORTED 1
700 #define HFI1_MAX_VLS_SUPPORTED 8
701
702 #define HFI1_GUIDS_PER_PORT 5
703 #define HFI1_PORT_GUID_INDEX 0
704
incr_cntr64(u64 * cntr)705 static inline void incr_cntr64(u64 *cntr)
706 {
707 if (*cntr < (u64)-1LL)
708 (*cntr)++;
709 }
710
incr_cntr32(u32 * cntr)711 static inline void incr_cntr32(u32 *cntr)
712 {
713 if (*cntr < (u32)-1LL)
714 (*cntr)++;
715 }
716
717 #define MAX_NAME_SIZE 64
718 struct hfi1_msix_entry {
719 enum irq_type type;
720 int irq;
721 void *arg;
722 cpumask_t mask;
723 struct irq_affinity_notify notify;
724 };
725
726 struct hfi1_msix_info {
727 /* lock to synchronize in_use_msix access */
728 spinlock_t msix_lock;
729 DECLARE_BITMAP(in_use_msix, CCE_NUM_MSIX_VECTORS);
730 struct hfi1_msix_entry *msix_entries;
731 u16 max_requested;
732 };
733
734 /* per-SL CCA information */
735 struct cca_timer {
736 struct hrtimer hrtimer;
737 struct hfi1_pportdata *ppd; /* read-only */
738 int sl; /* read-only */
739 u16 ccti; /* read/write - current value of CCTI */
740 };
741
742 struct link_down_reason {
743 /*
744 * SMA-facing value. Should be set from .latest when
745 * HLS_UP_* -> HLS_DN_* transition actually occurs.
746 */
747 u8 sma;
748 u8 latest;
749 };
750
751 enum {
752 LO_PRIO_TABLE,
753 HI_PRIO_TABLE,
754 MAX_PRIO_TABLE
755 };
756
757 struct vl_arb_cache {
758 /* protect vl arb cache */
759 spinlock_t lock;
760 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
761 };
762
763 /*
764 * The structure below encapsulates data relevant to a physical IB Port.
765 * Current chips support only one such port, but the separation
766 * clarifies things a bit. Note that to conform to IB conventions,
767 * port-numbers are one-based. The first or only port is port1.
768 */
769 struct hfi1_pportdata {
770 struct hfi1_ibport ibport_data;
771
772 struct hfi1_devdata *dd;
773 struct kobject pport_cc_kobj;
774 struct kobject sc2vl_kobj;
775 struct kobject sl2sc_kobj;
776 struct kobject vl2mtu_kobj;
777
778 /* PHY support */
779 struct qsfp_data qsfp_info;
780 /* Values for SI tuning of SerDes */
781 u32 port_type;
782 u32 tx_preset_eq;
783 u32 tx_preset_noeq;
784 u32 rx_preset;
785 u8 local_atten;
786 u8 remote_atten;
787 u8 default_atten;
788 u8 max_power_class;
789
790 /* did we read platform config from scratch registers? */
791 bool config_from_scratch;
792
793 /* GUIDs for this interface, in host order, guids[0] is a port guid */
794 u64 guids[HFI1_GUIDS_PER_PORT];
795
796 /* GUID for peer interface, in host order */
797 u64 neighbor_guid;
798
799 /* up or down physical link state */
800 u32 linkup;
801
802 /*
803 * this address is mapped read-only into user processes so they can
804 * get status cheaply, whenever they want. One qword of status per port
805 */
806 u64 *statusp;
807
808 /* SendDMA related entries */
809
810 struct workqueue_struct *hfi1_wq;
811 struct workqueue_struct *link_wq;
812
813 /* move out of interrupt context */
814 struct work_struct link_vc_work;
815 struct work_struct link_up_work;
816 struct work_struct link_down_work;
817 struct work_struct sma_message_work;
818 struct work_struct freeze_work;
819 struct work_struct link_downgrade_work;
820 struct work_struct link_bounce_work;
821 struct delayed_work start_link_work;
822 /* host link state variables */
823 struct mutex hls_lock;
824 u32 host_link_state;
825
826 /* these are the "32 bit" regs */
827
828 u32 ibmtu; /* The MTU programmed for this unit */
829 /*
830 * Current max size IB packet (in bytes) including IB headers, that
831 * we can send. Changes when ibmtu changes.
832 */
833 u32 ibmaxlen;
834 u32 current_egress_rate; /* units [10^6 bits/sec] */
835 /* LID programmed for this instance */
836 u32 lid;
837 /* list of pkeys programmed; 0 if not set */
838 u16 pkeys[MAX_PKEY_VALUES];
839 u16 link_width_supported;
840 u16 link_width_downgrade_supported;
841 u16 link_speed_supported;
842 u16 link_width_enabled;
843 u16 link_width_downgrade_enabled;
844 u16 link_speed_enabled;
845 u16 link_width_active;
846 u16 link_width_downgrade_tx_active;
847 u16 link_width_downgrade_rx_active;
848 u16 link_speed_active;
849 u8 vls_supported;
850 u8 vls_operational;
851 u8 actual_vls_operational;
852 /* LID mask control */
853 u8 lmc;
854 /* Rx Polarity inversion (compensate for ~tx on partner) */
855 u8 rx_pol_inv;
856
857 u8 hw_pidx; /* physical port index */
858 u8 port; /* IB port number and index into dd->pports - 1 */
859 /* type of neighbor node */
860 u8 neighbor_type;
861 u8 neighbor_normal;
862 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */
863 u8 neighbor_port_number;
864 u8 is_sm_config_started;
865 u8 offline_disabled_reason;
866 u8 is_active_optimize_enabled;
867 u8 driver_link_ready; /* driver ready for active link */
868 u8 link_enabled; /* link enabled? */
869 u8 linkinit_reason;
870 u8 local_tx_rate; /* rate given to 8051 firmware */
871 u8 qsfp_retry_count;
872
873 /* placeholders for IB MAD packet settings */
874 u8 overrun_threshold;
875 u8 phy_error_threshold;
876 unsigned int is_link_down_queued;
877
878 /* Used to override LED behavior for things like maintenance beaconing*/
879 /*
880 * Alternates per phase of blink
881 * [0] holds LED off duration, [1] holds LED on duration
882 */
883 unsigned long led_override_vals[2];
884 u8 led_override_phase; /* LSB picks from vals[] */
885 atomic_t led_override_timer_active;
886 /* Used to flash LEDs in override mode */
887 struct timer_list led_override_timer;
888
889 u32 sm_trap_qp;
890 u32 sa_qp;
891
892 /*
893 * cca_timer_lock protects access to the per-SL cca_timer
894 * structures (specifically the ccti member).
895 */
896 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
897 struct cca_timer cca_timer[OPA_MAX_SLS];
898
899 /* List of congestion control table entries */
900 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
901
902 /* congestion entries, each entry corresponding to a SL */
903 struct opa_congestion_setting_entry_shadow
904 congestion_entries[OPA_MAX_SLS];
905
906 /*
907 * cc_state_lock protects (write) access to the per-port
908 * struct cc_state.
909 */
910 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
911
912 struct cc_state __rcu *cc_state;
913
914 /* Total number of congestion control table entries */
915 u16 total_cct_entry;
916
917 /* Bit map identifying service level */
918 u32 cc_sl_control_map;
919
920 /* CA's max number of 64 entry units in the congestion control table */
921 u8 cc_max_table_entries;
922
923 /*
924 * begin congestion log related entries
925 * cc_log_lock protects all congestion log related data
926 */
927 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
928 u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
929 u16 threshold_event_counter;
930 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
931 int cc_log_idx; /* index for logging events */
932 int cc_mad_idx; /* index for reporting events */
933 /* end congestion log related entries */
934
935 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
936
937 /* port relative counter buffer */
938 u64 *cntrs;
939 /* port relative synthetic counter buffer */
940 u64 *scntrs;
941 /* port_xmit_discards are synthesized from different egress errors */
942 u64 port_xmit_discards;
943 u64 port_xmit_discards_vl[C_VL_COUNT];
944 u64 port_xmit_constraint_errors;
945 u64 port_rcv_constraint_errors;
946 /* count of 'link_err' interrupts from DC */
947 u64 link_downed;
948 /* number of times link retrained successfully */
949 u64 link_up;
950 /* number of times a link unknown frame was reported */
951 u64 unknown_frame_count;
952 /* port_ltp_crc_mode is returned in 'portinfo' MADs */
953 u16 port_ltp_crc_mode;
954 /* port_crc_mode_enabled is the crc we support */
955 u8 port_crc_mode_enabled;
956 /* mgmt_allowed is also returned in 'portinfo' MADs */
957 u8 mgmt_allowed;
958 u8 part_enforce; /* partition enforcement flags */
959 struct link_down_reason local_link_down_reason;
960 struct link_down_reason neigh_link_down_reason;
961 /* Value to be sent to link peer on LinkDown .*/
962 u8 remote_link_down_reason;
963 /* Error events that will cause a port bounce. */
964 u32 port_error_action;
965 struct work_struct linkstate_active_work;
966 /* Does this port need to prescan for FECNs */
967 bool cc_prescan;
968 /*
969 * Sample sendWaitCnt & sendWaitVlCnt during link transition
970 * and counter request.
971 */
972 u64 port_vl_xmit_wait_last[C_VL_COUNT + 1];
973 u16 prev_link_width;
974 u64 vl_xmit_flit_cnt[C_VL_COUNT + 1];
975 };
976
977 typedef void (*opcode_handler)(struct hfi1_packet *packet);
978 typedef void (*hfi1_make_req)(struct rvt_qp *qp,
979 struct hfi1_pkt_state *ps,
980 struct rvt_swqe *wqe);
981 extern const rhf_rcv_function_ptr normal_rhf_rcv_functions[];
982
983
984 /* return values for the RHF receive functions */
985 #define RHF_RCV_CONTINUE 0 /* keep going */
986 #define RHF_RCV_DONE 1 /* stop, this packet processed */
987 #define RHF_RCV_REPROCESS 2 /* stop. retain this packet */
988
989 struct rcv_array_data {
990 u16 ngroups;
991 u16 nctxt_extra;
992 u8 group_size;
993 };
994
995 struct per_vl_data {
996 u16 mtu;
997 struct send_context *sc;
998 };
999
1000 /* 16 to directly index */
1001 #define PER_VL_SEND_CONTEXTS 16
1002
1003 struct err_info_rcvport {
1004 u8 status_and_code;
1005 u64 packet_flit1;
1006 u64 packet_flit2;
1007 };
1008
1009 struct err_info_constraint {
1010 u8 status;
1011 u16 pkey;
1012 u32 slid;
1013 };
1014
1015 struct hfi1_temp {
1016 unsigned int curr; /* current temperature */
1017 unsigned int lo_lim; /* low temperature limit */
1018 unsigned int hi_lim; /* high temperature limit */
1019 unsigned int crit_lim; /* critical temperature limit */
1020 u8 triggers; /* temperature triggers */
1021 };
1022
1023 struct hfi1_i2c_bus {
1024 struct hfi1_devdata *controlling_dd; /* current controlling device */
1025 struct i2c_adapter adapter; /* bus details */
1026 struct i2c_algo_bit_data algo; /* bus algorithm details */
1027 int num; /* bus number, 0 or 1 */
1028 };
1029
1030 /* common data between shared ASIC HFIs */
1031 struct hfi1_asic_data {
1032 struct hfi1_devdata *dds[2]; /* back pointers */
1033 struct mutex asic_resource_mutex;
1034 struct hfi1_i2c_bus *i2c_bus0;
1035 struct hfi1_i2c_bus *i2c_bus1;
1036 };
1037
1038 /* sizes for both the QP and RSM map tables */
1039 #define NUM_MAP_ENTRIES 256
1040 #define NUM_MAP_REGS 32
1041
1042 /*
1043 * Number of VNIC contexts used. Ensure it is less than or equal to
1044 * max queues supported by VNIC (HFI1_VNIC_MAX_QUEUE).
1045 */
1046 #define HFI1_NUM_VNIC_CTXT 8
1047
1048 /* Number of VNIC RSM entries */
1049 #define NUM_VNIC_MAP_ENTRIES 8
1050
1051 /* Virtual NIC information */
1052 struct hfi1_vnic_data {
1053 struct hfi1_ctxtdata *ctxt[HFI1_NUM_VNIC_CTXT];
1054 struct kmem_cache *txreq_cache;
1055 struct xarray vesws;
1056 u8 num_vports;
1057 u8 rmt_start;
1058 u8 num_ctxt;
1059 };
1060
1061 struct hfi1_vnic_vport_info;
1062
1063 /* device data struct now contains only "general per-device" info.
1064 * fields related to a physical IB port are in a hfi1_pportdata struct.
1065 */
1066 struct sdma_engine;
1067 struct sdma_vl_map;
1068
1069 #define BOARD_VERS_MAX 96 /* how long the version string can be */
1070 #define SERIAL_MAX 16 /* length of the serial number */
1071
1072 typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
1073 struct hfi1_devdata {
1074 struct hfi1_ibdev verbs_dev; /* must be first */
1075 /* pointers to related structs for this device */
1076 /* pci access data structure */
1077 struct pci_dev *pcidev;
1078 struct cdev user_cdev;
1079 struct cdev diag_cdev;
1080 struct cdev ui_cdev;
1081 struct device *user_device;
1082 struct device *diag_device;
1083 struct device *ui_device;
1084
1085 /* first mapping up to RcvArray */
1086 u8 __iomem *kregbase1;
1087 resource_size_t physaddr;
1088
1089 /* second uncached mapping from RcvArray to pio send buffers */
1090 u8 __iomem *kregbase2;
1091 /* for detecting offset above kregbase2 address */
1092 u32 base2_start;
1093
1094 /* Per VL data. Enough for all VLs but not all elements are set/used. */
1095 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
1096 /* send context data */
1097 struct send_context_info *send_contexts;
1098 /* map hardware send contexts to software index */
1099 u8 *hw_to_sw;
1100 /* spinlock for allocating and releasing send context resources */
1101 spinlock_t sc_lock;
1102 /* lock for pio_map */
1103 spinlock_t pio_map_lock;
1104 /* Send Context initialization lock. */
1105 spinlock_t sc_init_lock;
1106 /* lock for sdma_map */
1107 spinlock_t sde_map_lock;
1108 /* array of kernel send contexts */
1109 struct send_context **kernel_send_context;
1110 /* array of vl maps */
1111 struct pio_vl_map __rcu *pio_map;
1112 /* default flags to last descriptor */
1113 u64 default_desc1;
1114
1115 /* fields common to all SDMA engines */
1116
1117 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */
1118 dma_addr_t sdma_heads_phys;
1119 void *sdma_pad_dma; /* DMA'ed by chip */
1120 dma_addr_t sdma_pad_phys;
1121 /* for deallocation */
1122 size_t sdma_heads_size;
1123 /* num used */
1124 u32 num_sdma;
1125 /* array of engines sized by num_sdma */
1126 struct sdma_engine *per_sdma;
1127 /* array of vl maps */
1128 struct sdma_vl_map __rcu *sdma_map;
1129 /* SPC freeze waitqueue and variable */
1130 wait_queue_head_t sdma_unfreeze_wq;
1131 atomic_t sdma_unfreeze_count;
1132
1133 u32 lcb_access_count; /* count of LCB users */
1134
1135 /* common data between shared ASIC HFIs in this OS */
1136 struct hfi1_asic_data *asic_data;
1137
1138 /* mem-mapped pointer to base of PIO buffers */
1139 void __iomem *piobase;
1140 /*
1141 * write-combining mem-mapped pointer to base of RcvArray
1142 * memory.
1143 */
1144 void __iomem *rcvarray_wc;
1145 /*
1146 * credit return base - a per-NUMA range of DMA address that
1147 * the chip will use to update the per-context free counter
1148 */
1149 struct credit_return_base *cr_base;
1150
1151 /* send context numbers and sizes for each type */
1152 struct sc_config_sizes sc_sizes[SC_MAX];
1153
1154 char *boardname; /* human readable board info */
1155
1156 /* reset value */
1157 u64 z_int_counter;
1158 u64 z_rcv_limit;
1159 u64 z_send_schedule;
1160
1161 u64 __percpu *send_schedule;
1162 /* number of reserved contexts for VNIC usage */
1163 u16 num_vnic_contexts;
1164 /* number of receive contexts in use by the driver */
1165 u32 num_rcv_contexts;
1166 /* number of pio send contexts in use by the driver */
1167 u32 num_send_contexts;
1168 /*
1169 * number of ctxts available for PSM open
1170 */
1171 u32 freectxts;
1172 /* total number of available user/PSM contexts */
1173 u32 num_user_contexts;
1174 /* base receive interrupt timeout, in CSR units */
1175 u32 rcv_intr_timeout_csr;
1176
1177 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
1178 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
1179 spinlock_t uctxt_lock; /* protect rcd changes */
1180 struct mutex dc8051_lock; /* exclusive access to 8051 */
1181 struct workqueue_struct *update_cntr_wq;
1182 struct work_struct update_cntr_work;
1183 /* exclusive access to 8051 memory */
1184 spinlock_t dc8051_memlock;
1185 int dc8051_timed_out; /* remember if the 8051 timed out */
1186 /*
1187 * A page that will hold event notification bitmaps for all
1188 * contexts. This page will be mapped into all processes.
1189 */
1190 unsigned long *events;
1191 /*
1192 * per unit status, see also portdata statusp
1193 * mapped read-only into user processes so they can get unit and
1194 * IB link status cheaply
1195 */
1196 struct hfi1_status *status;
1197
1198 /* revision register shadow */
1199 u64 revision;
1200 /* Base GUID for device (network order) */
1201 u64 base_guid;
1202
1203 /* both sides of the PCIe link are gen3 capable */
1204 u8 link_gen3_capable;
1205 u8 dc_shutdown;
1206 /* localbus width (1, 2,4,8,16,32) from config space */
1207 u32 lbus_width;
1208 /* localbus speed in MHz */
1209 u32 lbus_speed;
1210 int unit; /* unit # of this chip */
1211 int node; /* home node of this chip */
1212
1213 /* save these PCI fields to restore after a reset */
1214 u32 pcibar0;
1215 u32 pcibar1;
1216 u32 pci_rom;
1217 u16 pci_command;
1218 u16 pcie_devctl;
1219 u16 pcie_lnkctl;
1220 u16 pcie_devctl2;
1221 u32 pci_msix0;
1222 u32 pci_tph2;
1223
1224 /*
1225 * ASCII serial number, from flash, large enough for original
1226 * all digit strings, and longer serial number format
1227 */
1228 u8 serial[SERIAL_MAX];
1229 /* human readable board version */
1230 u8 boardversion[BOARD_VERS_MAX];
1231 u8 lbus_info[32]; /* human readable localbus info */
1232 /* chip major rev, from CceRevision */
1233 u8 majrev;
1234 /* chip minor rev, from CceRevision */
1235 u8 minrev;
1236 /* hardware ID */
1237 u8 hfi1_id;
1238 /* implementation code */
1239 u8 icode;
1240 /* vAU of this device */
1241 u8 vau;
1242 /* vCU of this device */
1243 u8 vcu;
1244 /* link credits of this device */
1245 u16 link_credits;
1246 /* initial vl15 credits to use */
1247 u16 vl15_init;
1248
1249 /*
1250 * Cached value for vl15buf, read during verify cap interrupt. VL15
1251 * credits are to be kept at 0 and set when handling the link-up
1252 * interrupt. This removes the possibility of receiving VL15 MAD
1253 * packets before this HFI is ready.
1254 */
1255 u16 vl15buf_cached;
1256
1257 /* Misc small ints */
1258 u8 n_krcv_queues;
1259 u8 qos_shift;
1260
1261 u16 irev; /* implementation revision */
1262 u32 dc8051_ver; /* 8051 firmware version */
1263
1264 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1265 struct platform_config platform_config;
1266 struct platform_config_cache pcfg_cache;
1267
1268 struct diag_client *diag_client;
1269
1270 /* general interrupt: mask of handled interrupts */
1271 u64 gi_mask[CCE_NUM_INT_CSRS];
1272
1273 struct rcv_array_data rcv_entries;
1274
1275 /* cycle length of PS* counters in HW (in picoseconds) */
1276 u16 psxmitwait_check_rate;
1277
1278 /*
1279 * 64 bit synthetic counters
1280 */
1281 struct timer_list synth_stats_timer;
1282
1283 /* MSI-X information */
1284 struct hfi1_msix_info msix_info;
1285
1286 /*
1287 * device counters
1288 */
1289 char *cntrnames;
1290 size_t cntrnameslen;
1291 size_t ndevcntrs;
1292 u64 *cntrs;
1293 u64 *scntrs;
1294
1295 /*
1296 * remembered values for synthetic counters
1297 */
1298 u64 last_tx;
1299 u64 last_rx;
1300
1301 /*
1302 * per-port counters
1303 */
1304 size_t nportcntrs;
1305 char *portcntrnames;
1306 size_t portcntrnameslen;
1307
1308 struct err_info_rcvport err_info_rcvport;
1309 struct err_info_constraint err_info_rcv_constraint;
1310 struct err_info_constraint err_info_xmit_constraint;
1311
1312 atomic_t drop_packet;
1313 u8 do_drop;
1314 u8 err_info_uncorrectable;
1315 u8 err_info_fmconfig;
1316
1317 /*
1318 * Software counters for the status bits defined by the
1319 * associated error status registers
1320 */
1321 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1322 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1323 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1324 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1325 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1326 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1327 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1328
1329 /* Software counter that spans all contexts */
1330 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1331 /* Software counter that spans all DMA engines */
1332 u64 sw_send_dma_eng_err_status_cnt[
1333 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1334 /* Software counter that aggregates all cce_err_status errors */
1335 u64 sw_cce_err_status_aggregate;
1336 /* Software counter that aggregates all bypass packet rcv errors */
1337 u64 sw_rcv_bypass_packet_errors;
1338
1339 /* Save the enabled LCB error bits */
1340 u64 lcb_err_en;
1341 struct cpu_mask_set *comp_vect;
1342 int *comp_vect_mappings;
1343 u32 comp_vect_possible_cpus;
1344
1345 /*
1346 * Capability to have different send engines simply by changing a
1347 * pointer value.
1348 */
1349 send_routine process_pio_send ____cacheline_aligned_in_smp;
1350 send_routine process_dma_send;
1351 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1352 u64 pbc, const void *from, size_t count);
1353 int (*process_vnic_dma_send)(struct hfi1_devdata *dd, u8 q_idx,
1354 struct hfi1_vnic_vport_info *vinfo,
1355 struct sk_buff *skb, u64 pbc, u8 plen);
1356 /* hfi1_pportdata, points to array of (physical) port-specific
1357 * data structs, indexed by pidx (0..n-1)
1358 */
1359 struct hfi1_pportdata *pport;
1360 /* receive context data */
1361 struct hfi1_ctxtdata **rcd;
1362 u64 __percpu *int_counter;
1363 /* verbs tx opcode stats */
1364 struct hfi1_opcode_stats_perctx __percpu *tx_opstats;
1365 /* device (not port) flags, basically device capabilities */
1366 u16 flags;
1367 /* Number of physical ports available */
1368 u8 num_pports;
1369 /* Lowest context number which can be used by user processes or VNIC */
1370 u8 first_dyn_alloc_ctxt;
1371 /* adding a new field here would make it part of this cacheline */
1372
1373 /* seqlock for sc2vl */
1374 seqlock_t sc2vl_lock ____cacheline_aligned_in_smp;
1375 u64 sc2vl[4];
1376 u64 __percpu *rcv_limit;
1377 /* adding a new field here would make it part of this cacheline */
1378
1379 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1380 u8 oui1;
1381 u8 oui2;
1382 u8 oui3;
1383
1384 /* Timer and counter used to detect RcvBufOvflCnt changes */
1385 struct timer_list rcverr_timer;
1386
1387 wait_queue_head_t event_queue;
1388
1389 /* receive context tail dummy address */
1390 __le64 *rcvhdrtail_dummy_kvaddr;
1391 dma_addr_t rcvhdrtail_dummy_dma;
1392
1393 u32 rcv_ovfl_cnt;
1394 /* Serialize ASPM enable/disable between multiple verbs contexts */
1395 spinlock_t aspm_lock;
1396 /* Number of verbs contexts which have disabled ASPM */
1397 atomic_t aspm_disabled_cnt;
1398 /* Keeps track of user space clients */
1399 atomic_t user_refcount;
1400 /* Used to wait for outstanding user space clients before dev removal */
1401 struct completion user_comp;
1402
1403 bool eprom_available; /* true if EPROM is available for this device */
1404 bool aspm_supported; /* Does HW support ASPM */
1405 bool aspm_enabled; /* ASPM state: enabled/disabled */
1406 struct rhashtable *sdma_rht;
1407
1408 struct kobject kobj;
1409
1410 /* vnic data */
1411 struct hfi1_vnic_data vnic;
1412 /* Lock to protect IRQ SRC register access */
1413 spinlock_t irq_src_lock;
1414 };
1415
hfi1_vnic_is_rsm_full(struct hfi1_devdata * dd,int spare)1416 static inline bool hfi1_vnic_is_rsm_full(struct hfi1_devdata *dd, int spare)
1417 {
1418 return (dd->vnic.rmt_start + spare) > NUM_MAP_ENTRIES;
1419 }
1420
1421 /* 8051 firmware version helper */
1422 #define dc8051_ver(a, b, c) ((a) << 16 | (b) << 8 | (c))
1423 #define dc8051_ver_maj(a) (((a) & 0xff0000) >> 16)
1424 #define dc8051_ver_min(a) (((a) & 0x00ff00) >> 8)
1425 #define dc8051_ver_patch(a) ((a) & 0x0000ff)
1426
1427 /* f_put_tid types */
1428 #define PT_EXPECTED 0
1429 #define PT_EAGER 1
1430 #define PT_INVALID_FLUSH 2
1431 #define PT_INVALID 3
1432
1433 struct tid_rb_node;
1434 struct mmu_rb_node;
1435 struct mmu_rb_handler;
1436
1437 /* Private data for file operations */
1438 struct hfi1_filedata {
1439 struct hfi1_devdata *dd;
1440 struct hfi1_ctxtdata *uctxt;
1441 struct hfi1_user_sdma_comp_q *cq;
1442 struct hfi1_user_sdma_pkt_q *pq;
1443 u16 subctxt;
1444 /* for cpu affinity; -1 if none */
1445 int rec_cpu_num;
1446 u32 tid_n_pinned;
1447 struct mmu_rb_handler *handler;
1448 struct tid_rb_node **entry_to_rb;
1449 spinlock_t tid_lock; /* protect tid_[limit,used] counters */
1450 u32 tid_limit;
1451 u32 tid_used;
1452 u32 *invalid_tids;
1453 u32 invalid_tid_idx;
1454 /* protect invalid_tids array and invalid_tid_idx */
1455 spinlock_t invalid_lock;
1456 struct mm_struct *mm;
1457 };
1458
1459 extern struct xarray hfi1_dev_table;
1460 struct hfi1_devdata *hfi1_lookup(int unit);
1461
uctxt_offset(struct hfi1_ctxtdata * uctxt)1462 static inline unsigned long uctxt_offset(struct hfi1_ctxtdata *uctxt)
1463 {
1464 return (uctxt->ctxt - uctxt->dd->first_dyn_alloc_ctxt) *
1465 HFI1_MAX_SHARED_CTXTS;
1466 }
1467
1468 int hfi1_init(struct hfi1_devdata *dd, int reinit);
1469 int hfi1_count_active_units(void);
1470
1471 int hfi1_diag_add(struct hfi1_devdata *dd);
1472 void hfi1_diag_remove(struct hfi1_devdata *dd);
1473 void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1474
1475 void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1476
1477 int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1478 int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *rcd);
1479 int hfi1_create_kctxts(struct hfi1_devdata *dd);
1480 int hfi1_create_ctxtdata(struct hfi1_pportdata *ppd, int numa,
1481 struct hfi1_ctxtdata **rcd);
1482 void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd);
1483 void hfi1_init_pportdata(struct pci_dev *pdev, struct hfi1_pportdata *ppd,
1484 struct hfi1_devdata *dd, u8 hw_pidx, u8 port);
1485 void hfi1_free_ctxtdata(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd);
1486 int hfi1_rcd_put(struct hfi1_ctxtdata *rcd);
1487 int hfi1_rcd_get(struct hfi1_ctxtdata *rcd);
1488 struct hfi1_ctxtdata *hfi1_rcd_get_by_index_safe(struct hfi1_devdata *dd,
1489 u16 ctxt);
1490 struct hfi1_ctxtdata *hfi1_rcd_get_by_index(struct hfi1_devdata *dd, u16 ctxt);
1491 int handle_receive_interrupt(struct hfi1_ctxtdata *rcd, int thread);
1492 int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1493 int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *rcd, int thread);
1494 void set_all_slowpath(struct hfi1_devdata *dd);
1495
1496 extern const struct pci_device_id hfi1_pci_tbl[];
1497 void hfi1_make_ud_req_9B(struct rvt_qp *qp,
1498 struct hfi1_pkt_state *ps,
1499 struct rvt_swqe *wqe);
1500
1501 void hfi1_make_ud_req_16B(struct rvt_qp *qp,
1502 struct hfi1_pkt_state *ps,
1503 struct rvt_swqe *wqe);
1504
1505 /* receive packet handler dispositions */
1506 #define RCV_PKT_OK 0x0 /* keep going */
1507 #define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */
1508 #define RCV_PKT_DONE 0x2 /* stop, no more packets detected */
1509
1510 /* calculate the current RHF address */
get_rhf_addr(struct hfi1_ctxtdata * rcd)1511 static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1512 {
1513 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->rhf_offset;
1514 }
1515
1516 int hfi1_reset_device(int);
1517
1518 void receive_interrupt_work(struct work_struct *work);
1519
1520 /* extract service channel from header and rhf */
hfi1_9B_get_sc5(struct ib_header * hdr,u64 rhf)1521 static inline int hfi1_9B_get_sc5(struct ib_header *hdr, u64 rhf)
1522 {
1523 return ib_get_sc(hdr) | ((!!(rhf_dc_info(rhf))) << 4);
1524 }
1525
1526 #define HFI1_JKEY_WIDTH 16
1527 #define HFI1_JKEY_MASK (BIT(16) - 1)
1528 #define HFI1_ADMIN_JKEY_RANGE 32
1529
1530 /*
1531 * J_KEYs are split and allocated in the following groups:
1532 * 0 - 31 - users with administrator privileges
1533 * 32 - 63 - kernel protocols using KDETH packets
1534 * 64 - 65535 - all other users using KDETH packets
1535 */
generate_jkey(kuid_t uid)1536 static inline u16 generate_jkey(kuid_t uid)
1537 {
1538 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK;
1539
1540 if (capable(CAP_SYS_ADMIN))
1541 jkey &= HFI1_ADMIN_JKEY_RANGE - 1;
1542 else if (jkey < 64)
1543 jkey |= BIT(HFI1_JKEY_WIDTH - 1);
1544
1545 return jkey;
1546 }
1547
1548 /*
1549 * active_egress_rate
1550 *
1551 * returns the active egress rate in units of [10^6 bits/sec]
1552 */
active_egress_rate(struct hfi1_pportdata * ppd)1553 static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1554 {
1555 u16 link_speed = ppd->link_speed_active;
1556 u16 link_width = ppd->link_width_active;
1557 u32 egress_rate;
1558
1559 if (link_speed == OPA_LINK_SPEED_25G)
1560 egress_rate = 25000;
1561 else /* assume OPA_LINK_SPEED_12_5G */
1562 egress_rate = 12500;
1563
1564 switch (link_width) {
1565 case OPA_LINK_WIDTH_4X:
1566 egress_rate *= 4;
1567 break;
1568 case OPA_LINK_WIDTH_3X:
1569 egress_rate *= 3;
1570 break;
1571 case OPA_LINK_WIDTH_2X:
1572 egress_rate *= 2;
1573 break;
1574 default:
1575 /* assume IB_WIDTH_1X */
1576 break;
1577 }
1578
1579 return egress_rate;
1580 }
1581
1582 /*
1583 * egress_cycles
1584 *
1585 * Returns the number of 'fabric clock cycles' to egress a packet
1586 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1587 * rate is (approximately) 805 MHz, the units of the returned value
1588 * are (1/805 MHz).
1589 */
egress_cycles(u32 len,u32 rate)1590 static inline u32 egress_cycles(u32 len, u32 rate)
1591 {
1592 u32 cycles;
1593
1594 /*
1595 * cycles is:
1596 *
1597 * (length) [bits] / (rate) [bits/sec]
1598 * ---------------------------------------------------
1599 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1600 */
1601
1602 cycles = len * 8; /* bits */
1603 cycles *= 805;
1604 cycles /= rate;
1605
1606 return cycles;
1607 }
1608
1609 void set_link_ipg(struct hfi1_pportdata *ppd);
1610 void process_becn(struct hfi1_pportdata *ppd, u8 sl, u32 rlid, u32 lqpn,
1611 u32 rqpn, u8 svc_type);
1612 void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
1613 u16 pkey, u32 slid, u32 dlid, u8 sc5,
1614 const struct ib_grh *old_grh);
1615 void return_cnp_16B(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1616 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1617 u8 sc5, const struct ib_grh *old_grh);
1618 typedef void (*hfi1_handle_cnp)(struct hfi1_ibport *ibp, struct rvt_qp *qp,
1619 u32 remote_qpn, u16 pkey, u32 slid, u32 dlid,
1620 u8 sc5, const struct ib_grh *old_grh);
1621
1622 #define PKEY_CHECK_INVALID -1
1623 int egress_pkey_check(struct hfi1_pportdata *ppd, u32 slid, u16 pkey,
1624 u8 sc5, int8_t s_pkey_index);
1625
1626 #define PACKET_EGRESS_TIMEOUT 350
pause_for_credit_return(struct hfi1_devdata * dd)1627 static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1628 {
1629 /* Pause at least 1us, to ensure chip returns all credits */
1630 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1631
1632 udelay(usec ? usec : 1);
1633 }
1634
1635 /**
1636 * sc_to_vlt() reverse lookup sc to vl
1637 * @dd - devdata
1638 * @sc5 - 5 bit sc
1639 */
sc_to_vlt(struct hfi1_devdata * dd,u8 sc5)1640 static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1641 {
1642 unsigned seq;
1643 u8 rval;
1644
1645 if (sc5 >= OPA_MAX_SCS)
1646 return (u8)(0xff);
1647
1648 do {
1649 seq = read_seqbegin(&dd->sc2vl_lock);
1650 rval = *(((u8 *)dd->sc2vl) + sc5);
1651 } while (read_seqretry(&dd->sc2vl_lock, seq));
1652
1653 return rval;
1654 }
1655
1656 #define PKEY_MEMBER_MASK 0x8000
1657 #define PKEY_LOW_15_MASK 0x7fff
1658
1659 /*
1660 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1661 * being an entry from the ingress partition key table), return 0
1662 * otherwise. Use the matching criteria for ingress partition keys
1663 * specified in the OPAv1 spec., section 9.10.14.
1664 */
ingress_pkey_matches_entry(u16 pkey,u16 ent)1665 static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1666 {
1667 u16 mkey = pkey & PKEY_LOW_15_MASK;
1668 u16 ment = ent & PKEY_LOW_15_MASK;
1669
1670 if (mkey == ment) {
1671 /*
1672 * If pkey[15] is clear (limited partition member),
1673 * is bit 15 in the corresponding table element
1674 * clear (limited member)?
1675 */
1676 if (!(pkey & PKEY_MEMBER_MASK))
1677 return !!(ent & PKEY_MEMBER_MASK);
1678 return 1;
1679 }
1680 return 0;
1681 }
1682
1683 /*
1684 * ingress_pkey_table_search - search the entire pkey table for
1685 * an entry which matches 'pkey'. return 0 if a match is found,
1686 * and 1 otherwise.
1687 */
ingress_pkey_table_search(struct hfi1_pportdata * ppd,u16 pkey)1688 static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1689 {
1690 int i;
1691
1692 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1693 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1694 return 0;
1695 }
1696 return 1;
1697 }
1698
1699 /*
1700 * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1701 * i.e., increment port_rcv_constraint_errors for the port, and record
1702 * the 'error info' for this failure.
1703 */
ingress_pkey_table_fail(struct hfi1_pportdata * ppd,u16 pkey,u32 slid)1704 static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1705 u32 slid)
1706 {
1707 struct hfi1_devdata *dd = ppd->dd;
1708
1709 incr_cntr64(&ppd->port_rcv_constraint_errors);
1710 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1711 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1712 dd->err_info_rcv_constraint.slid = slid;
1713 dd->err_info_rcv_constraint.pkey = pkey;
1714 }
1715 }
1716
1717 /*
1718 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1719 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1720 * is a hint as to the best place in the partition key table to begin
1721 * searching. This function should not be called on the data path because
1722 * of performance reasons. On datapath pkey check is expected to be done
1723 * by HW and rcv_pkey_check function should be called instead.
1724 */
ingress_pkey_check(struct hfi1_pportdata * ppd,u16 pkey,u8 sc5,u8 idx,u32 slid,bool force)1725 static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1726 u8 sc5, u8 idx, u32 slid, bool force)
1727 {
1728 if (!(force) && !(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1729 return 0;
1730
1731 /* If SC15, pkey[0:14] must be 0x7fff */
1732 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1733 goto bad;
1734
1735 /* Is the pkey = 0x0, or 0x8000? */
1736 if ((pkey & PKEY_LOW_15_MASK) == 0)
1737 goto bad;
1738
1739 /* The most likely matching pkey has index 'idx' */
1740 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1741 return 0;
1742
1743 /* no match - try the whole table */
1744 if (!ingress_pkey_table_search(ppd, pkey))
1745 return 0;
1746
1747 bad:
1748 ingress_pkey_table_fail(ppd, pkey, slid);
1749 return 1;
1750 }
1751
1752 /*
1753 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1754 * otherwise. It only ensures pkey is vlid for QP0. This function
1755 * should be called on the data path instead of ingress_pkey_check
1756 * as on data path, pkey check is done by HW (except for QP0).
1757 */
rcv_pkey_check(struct hfi1_pportdata * ppd,u16 pkey,u8 sc5,u16 slid)1758 static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1759 u8 sc5, u16 slid)
1760 {
1761 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1762 return 0;
1763
1764 /* If SC15, pkey[0:14] must be 0x7fff */
1765 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1766 goto bad;
1767
1768 return 0;
1769 bad:
1770 ingress_pkey_table_fail(ppd, pkey, slid);
1771 return 1;
1772 }
1773
1774 /* MTU handling */
1775
1776 /* MTU enumeration, 256-4k match IB */
1777 #define OPA_MTU_0 0
1778 #define OPA_MTU_256 1
1779 #define OPA_MTU_512 2
1780 #define OPA_MTU_1024 3
1781 #define OPA_MTU_2048 4
1782 #define OPA_MTU_4096 5
1783
1784 u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1785 int mtu_to_enum(u32 mtu, int default_if_bad);
1786 u16 enum_to_mtu(int mtu);
valid_ib_mtu(unsigned int mtu)1787 static inline int valid_ib_mtu(unsigned int mtu)
1788 {
1789 return mtu == 256 || mtu == 512 ||
1790 mtu == 1024 || mtu == 2048 ||
1791 mtu == 4096;
1792 }
1793
valid_opa_max_mtu(unsigned int mtu)1794 static inline int valid_opa_max_mtu(unsigned int mtu)
1795 {
1796 return mtu >= 2048 &&
1797 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1798 }
1799
1800 int set_mtu(struct hfi1_pportdata *ppd);
1801
1802 int hfi1_set_lid(struct hfi1_pportdata *ppd, u32 lid, u8 lmc);
1803 void hfi1_disable_after_error(struct hfi1_devdata *dd);
1804 int hfi1_set_uevent_bits(struct hfi1_pportdata *ppd, const int evtbit);
1805 int hfi1_rcvbuf_validate(u32 size, u8 type, u16 *encode);
1806
1807 int fm_get_table(struct hfi1_pportdata *ppd, int which, void *t);
1808 int fm_set_table(struct hfi1_pportdata *ppd, int which, void *t);
1809
1810 void set_up_vau(struct hfi1_devdata *dd, u8 vau);
1811 void set_up_vl15(struct hfi1_devdata *dd, u16 vl15buf);
1812 void reset_link_credits(struct hfi1_devdata *dd);
1813 void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1814
1815 int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
1816
dd_from_ppd(struct hfi1_pportdata * ppd)1817 static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1818 {
1819 return ppd->dd;
1820 }
1821
dd_from_dev(struct hfi1_ibdev * dev)1822 static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1823 {
1824 return container_of(dev, struct hfi1_devdata, verbs_dev);
1825 }
1826
dd_from_ibdev(struct ib_device * ibdev)1827 static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1828 {
1829 return dd_from_dev(to_idev(ibdev));
1830 }
1831
ppd_from_ibp(struct hfi1_ibport * ibp)1832 static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1833 {
1834 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1835 }
1836
dev_from_rdi(struct rvt_dev_info * rdi)1837 static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1838 {
1839 return container_of(rdi, struct hfi1_ibdev, rdi);
1840 }
1841
to_iport(struct ib_device * ibdev,u8 port)1842 static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1843 {
1844 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1845 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1846
1847 WARN_ON(pidx >= dd->num_pports);
1848 return &dd->pport[pidx].ibport_data;
1849 }
1850
rcd_to_iport(struct hfi1_ctxtdata * rcd)1851 static inline struct hfi1_ibport *rcd_to_iport(struct hfi1_ctxtdata *rcd)
1852 {
1853 return &rcd->ppd->ibport_data;
1854 }
1855
1856 /**
1857 * hfi1_may_ecn - Check whether FECN or BECN processing should be done
1858 * @pkt: the packet to be evaluated
1859 *
1860 * Check whether the FECN or BECN bits in the packet's header are
1861 * enabled, depending on packet type.
1862 *
1863 * This function only checks for FECN and BECN bits. Additional checks
1864 * are done in the slowpath (hfi1_process_ecn_slowpath()) in order to
1865 * ensure correct handling.
1866 */
hfi1_may_ecn(struct hfi1_packet * pkt)1867 static inline bool hfi1_may_ecn(struct hfi1_packet *pkt)
1868 {
1869 bool fecn, becn;
1870
1871 if (pkt->etype == RHF_RCV_TYPE_BYPASS) {
1872 fecn = hfi1_16B_get_fecn(pkt->hdr);
1873 becn = hfi1_16B_get_becn(pkt->hdr);
1874 } else {
1875 fecn = ib_bth_get_fecn(pkt->ohdr);
1876 becn = ib_bth_get_becn(pkt->ohdr);
1877 }
1878 return fecn || becn;
1879 }
1880
1881 bool hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
1882 bool prescan);
process_ecn(struct rvt_qp * qp,struct hfi1_packet * pkt)1883 static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt)
1884 {
1885 bool do_work;
1886
1887 do_work = hfi1_may_ecn(pkt);
1888 if (unlikely(do_work))
1889 return hfi1_process_ecn_slowpath(qp, pkt, false);
1890 return false;
1891 }
1892
1893 /*
1894 * Return the indexed PKEY from the port PKEY table.
1895 */
hfi1_get_pkey(struct hfi1_ibport * ibp,unsigned index)1896 static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1897 {
1898 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1899 u16 ret;
1900
1901 if (index >= ARRAY_SIZE(ppd->pkeys))
1902 ret = 0;
1903 else
1904 ret = ppd->pkeys[index];
1905
1906 return ret;
1907 }
1908
1909 /*
1910 * Return the indexed GUID from the port GUIDs table.
1911 */
get_sguid(struct hfi1_ibport * ibp,unsigned int index)1912 static inline __be64 get_sguid(struct hfi1_ibport *ibp, unsigned int index)
1913 {
1914 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1915
1916 WARN_ON(index >= HFI1_GUIDS_PER_PORT);
1917 return cpu_to_be64(ppd->guids[index]);
1918 }
1919
1920 /*
1921 * Called by readers of cc_state only, must call under rcu_read_lock().
1922 */
get_cc_state(struct hfi1_pportdata * ppd)1923 static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1924 {
1925 return rcu_dereference(ppd->cc_state);
1926 }
1927
1928 /*
1929 * Called by writers of cc_state only, must call under cc_state_lock.
1930 */
1931 static inline
get_cc_state_protected(struct hfi1_pportdata * ppd)1932 struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd)
1933 {
1934 return rcu_dereference_protected(ppd->cc_state,
1935 lockdep_is_held(&ppd->cc_state_lock));
1936 }
1937
1938 /*
1939 * values for dd->flags (_device_ related flags)
1940 */
1941 #define HFI1_INITTED 0x1 /* chip and driver up and initted */
1942 #define HFI1_PRESENT 0x2 /* chip accesses can be done */
1943 #define HFI1_FROZEN 0x4 /* chip in SPC freeze */
1944 #define HFI1_HAS_SDMA_TIMEOUT 0x8
1945 #define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
1946 #define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
1947 #define HFI1_SHUTDOWN 0x100 /* device is shutting down */
1948
1949 /* IB dword length mask in PBC (lower 11 bits); same for all chips */
1950 #define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1951
1952 /* ctxt_flag bit offsets */
1953 /* base context has not finished initializing */
1954 #define HFI1_CTXT_BASE_UNINIT 1
1955 /* base context initaliation failed */
1956 #define HFI1_CTXT_BASE_FAILED 2
1957 /* waiting for a packet to arrive */
1958 #define HFI1_CTXT_WAITING_RCV 3
1959 /* waiting for an urgent packet to arrive */
1960 #define HFI1_CTXT_WAITING_URG 4
1961
1962 /* free up any allocated data at closes */
1963 int hfi1_init_dd(struct hfi1_devdata *dd);
1964 void hfi1_free_devdata(struct hfi1_devdata *dd);
1965
1966 /* LED beaconing functions */
1967 void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1968 unsigned int timeoff);
1969 void shutdown_led_override(struct hfi1_pportdata *ppd);
1970
1971 #define HFI1_CREDIT_RETURN_RATE (100)
1972
1973 /*
1974 * The number of words for the KDETH protocol field. If this is
1975 * larger then the actual field used, then part of the payload
1976 * will be in the header.
1977 *
1978 * Optimally, we want this sized so that a typical case will
1979 * use full cache lines. The typical local KDETH header would
1980 * be:
1981 *
1982 * Bytes Field
1983 * 8 LRH
1984 * 12 BHT
1985 * ?? KDETH
1986 * 8 RHF
1987 * ---
1988 * 28 + KDETH
1989 *
1990 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
1991 */
1992 #define DEFAULT_RCVHDRSIZE 9
1993
1994 /*
1995 * Maximal header byte count:
1996 *
1997 * Bytes Field
1998 * 8 LRH
1999 * 40 GRH (optional)
2000 * 12 BTH
2001 * ?? KDETH
2002 * 8 RHF
2003 * ---
2004 * 68 + KDETH
2005 *
2006 * We also want to maintain a cache line alignment to assist DMA'ing
2007 * of the header bytes. Round up to a good size.
2008 */
2009 #define DEFAULT_RCVHDR_ENTSIZE 32
2010
2011 bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm,
2012 u32 nlocked, u32 npages);
2013 int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr,
2014 size_t npages, bool writable, struct page **pages);
2015 void hfi1_release_user_pages(struct mm_struct *mm, struct page **p,
2016 size_t npages, bool dirty);
2017
clear_rcvhdrtail(const struct hfi1_ctxtdata * rcd)2018 static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
2019 {
2020 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL;
2021 }
2022
get_rcvhdrtail(const struct hfi1_ctxtdata * rcd)2023 static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
2024 {
2025 /*
2026 * volatile because it's a DMA target from the chip, routine is
2027 * inlined, and don't want register caching or reordering.
2028 */
2029 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
2030 }
2031
2032 /*
2033 * sysfs interface.
2034 */
2035
2036 extern const char ib_hfi1_version[];
2037 extern const struct attribute_group ib_hfi1_attr_group;
2038
2039 int hfi1_device_create(struct hfi1_devdata *dd);
2040 void hfi1_device_remove(struct hfi1_devdata *dd);
2041
2042 int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
2043 struct kobject *kobj);
2044 int hfi1_verbs_register_sysfs(struct hfi1_devdata *dd);
2045 void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *dd);
2046 /* Hook for sysfs read of QSFP */
2047 int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
2048
2049 int hfi1_pcie_init(struct hfi1_devdata *dd);
2050 void hfi1_pcie_cleanup(struct pci_dev *pdev);
2051 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev);
2052 void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
2053 int pcie_speeds(struct hfi1_devdata *dd);
2054 int restore_pci_variables(struct hfi1_devdata *dd);
2055 int save_pci_variables(struct hfi1_devdata *dd);
2056 int do_pcie_gen3_transition(struct hfi1_devdata *dd);
2057 void tune_pcie_caps(struct hfi1_devdata *dd);
2058 int parse_platform_config(struct hfi1_devdata *dd);
2059 int get_platform_config_field(struct hfi1_devdata *dd,
2060 enum platform_config_table_type_encoding
2061 table_type, int table_index, int field_index,
2062 u32 *data, u32 len);
2063
2064 struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
2065
2066 /*
2067 * Flush write combining store buffers (if present) and perform a write
2068 * barrier.
2069 */
flush_wc(void)2070 static inline void flush_wc(void)
2071 {
2072 asm volatile("sfence" : : : "memory");
2073 }
2074
2075 void handle_eflags(struct hfi1_packet *packet);
2076 void seqfile_dump_rcd(struct seq_file *s, struct hfi1_ctxtdata *rcd);
2077
2078 /* global module parameter variables */
2079 extern unsigned int hfi1_max_mtu;
2080 extern unsigned int hfi1_cu;
2081 extern unsigned int user_credit_return_threshold;
2082 extern int num_user_contexts;
2083 extern unsigned long n_krcvqs;
2084 extern uint krcvqs[];
2085 extern int krcvqsset;
2086 extern uint kdeth_qp;
2087 extern uint loopback;
2088 extern uint quick_linkup;
2089 extern uint rcv_intr_timeout;
2090 extern uint rcv_intr_count;
2091 extern uint rcv_intr_dynamic;
2092 extern ushort link_crc_mask;
2093
2094 extern struct mutex hfi1_mutex;
2095
2096 /* Number of seconds before our card status check... */
2097 #define STATUS_TIMEOUT 60
2098
2099 #define DRIVER_NAME "hfi1"
2100 #define HFI1_USER_MINOR_BASE 0
2101 #define HFI1_TRACE_MINOR 127
2102 #define HFI1_NMINORS 255
2103
2104 #define PCI_VENDOR_ID_INTEL 0x8086
2105 #define PCI_DEVICE_ID_INTEL0 0x24f0
2106 #define PCI_DEVICE_ID_INTEL1 0x24f1
2107
2108 #define HFI1_PKT_USER_SC_INTEGRITY \
2109 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
2110 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
2111 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
2112 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
2113
2114 #define HFI1_PKT_KERNEL_SC_INTEGRITY \
2115 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
2116
hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata * dd,u16 ctxt_type)2117 static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
2118 u16 ctxt_type)
2119 {
2120 u64 base_sc_integrity;
2121
2122 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2123 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2124 return 0;
2125
2126 base_sc_integrity =
2127 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2128 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
2129 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2130 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2131 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2132 #ifndef CONFIG_FAULT_INJECTION
2133 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
2134 #endif
2135 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2136 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2137 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2138 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
2139 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2140 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2141 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
2142 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
2143 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
2144 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2145
2146 if (ctxt_type == SC_USER)
2147 base_sc_integrity |=
2148 #ifndef CONFIG_FAULT_INJECTION
2149 SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK |
2150 #endif
2151 HFI1_PKT_USER_SC_INTEGRITY;
2152 else if (ctxt_type != SC_KERNEL)
2153 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
2154
2155 /* turn on send-side job key checks if !A0 */
2156 if (!is_ax(dd))
2157 base_sc_integrity |= SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2158
2159 return base_sc_integrity;
2160 }
2161
hfi1_pkt_base_sdma_integrity(struct hfi1_devdata * dd)2162 static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
2163 {
2164 u64 base_sdma_integrity;
2165
2166 /* No integrity checks if HFI1_CAP_NO_INTEGRITY is set */
2167 if (HFI1_CAP_IS_KSET(NO_INTEGRITY))
2168 return 0;
2169
2170 base_sdma_integrity =
2171 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
2172 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
2173 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
2174 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
2175 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
2176 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
2177 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
2178 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
2179 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
2180 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
2181 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
2182 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
2183 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
2184 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
2185
2186 if (!HFI1_CAP_IS_KSET(STATIC_RATE_CTRL))
2187 base_sdma_integrity |=
2188 SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK;
2189
2190 /* turn on send-side job key checks if !A0 */
2191 if (!is_ax(dd))
2192 base_sdma_integrity |=
2193 SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
2194
2195 return base_sdma_integrity;
2196 }
2197
2198 #define dd_dev_emerg(dd, fmt, ...) \
2199 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
2200 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2201
2202 #define dd_dev_err(dd, fmt, ...) \
2203 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
2204 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2205
2206 #define dd_dev_err_ratelimited(dd, fmt, ...) \
2207 dev_err_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2208 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2209 ##__VA_ARGS__)
2210
2211 #define dd_dev_warn(dd, fmt, ...) \
2212 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
2213 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2214
2215 #define dd_dev_warn_ratelimited(dd, fmt, ...) \
2216 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2217 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2218 ##__VA_ARGS__)
2219
2220 #define dd_dev_info(dd, fmt, ...) \
2221 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
2222 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2223
2224 #define dd_dev_info_ratelimited(dd, fmt, ...) \
2225 dev_info_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
2226 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), \
2227 ##__VA_ARGS__)
2228
2229 #define dd_dev_dbg(dd, fmt, ...) \
2230 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
2231 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
2232
2233 #define hfi1_dev_porterr(dd, port, fmt, ...) \
2234 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
2235 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (port), ##__VA_ARGS__)
2236
2237 /*
2238 * this is used for formatting hw error messages...
2239 */
2240 struct hfi1_hwerror_msgs {
2241 u64 mask;
2242 const char *msg;
2243 size_t sz;
2244 };
2245
2246 /* in intr.c... */
2247 void hfi1_format_hwerrors(u64 hwerrs,
2248 const struct hfi1_hwerror_msgs *hwerrmsgs,
2249 size_t nhwerrmsgs, char *msg, size_t lmsg);
2250
2251 #define USER_OPCODE_CHECK_VAL 0xC0
2252 #define USER_OPCODE_CHECK_MASK 0xC0
2253 #define OPCODE_CHECK_VAL_DISABLED 0x0
2254 #define OPCODE_CHECK_MASK_DISABLED 0x0
2255
hfi1_reset_cpu_counters(struct hfi1_devdata * dd)2256 static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
2257 {
2258 struct hfi1_pportdata *ppd;
2259 int i;
2260
2261 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
2262 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
2263 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
2264
2265 ppd = (struct hfi1_pportdata *)(dd + 1);
2266 for (i = 0; i < dd->num_pports; i++, ppd++) {
2267 ppd->ibport_data.rvp.z_rc_acks =
2268 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
2269 ppd->ibport_data.rvp.z_rc_qacks =
2270 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
2271 }
2272 }
2273
2274 /* Control LED state */
setextled(struct hfi1_devdata * dd,u32 on)2275 static inline void setextled(struct hfi1_devdata *dd, u32 on)
2276 {
2277 if (on)
2278 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
2279 else
2280 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
2281 }
2282
2283 /* return the i2c resource given the target */
i2c_target(u32 target)2284 static inline u32 i2c_target(u32 target)
2285 {
2286 return target ? CR_I2C2 : CR_I2C1;
2287 }
2288
2289 /* return the i2c chain chip resource that this HFI uses for QSFP */
qsfp_resource(struct hfi1_devdata * dd)2290 static inline u32 qsfp_resource(struct hfi1_devdata *dd)
2291 {
2292 return i2c_target(dd->hfi1_id);
2293 }
2294
2295 /* Is this device integrated or discrete? */
is_integrated(struct hfi1_devdata * dd)2296 static inline bool is_integrated(struct hfi1_devdata *dd)
2297 {
2298 return dd->pcidev->device == PCI_DEVICE_ID_INTEL1;
2299 }
2300
2301 int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
2302
2303 #define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
2304 #define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
2305
hfi1_update_ah_attr(struct ib_device * ibdev,struct rdma_ah_attr * attr)2306 static inline void hfi1_update_ah_attr(struct ib_device *ibdev,
2307 struct rdma_ah_attr *attr)
2308 {
2309 struct hfi1_pportdata *ppd;
2310 struct hfi1_ibport *ibp;
2311 u32 dlid = rdma_ah_get_dlid(attr);
2312
2313 /*
2314 * Kernel clients may not have setup GRH information
2315 * Set that here.
2316 */
2317 ibp = to_iport(ibdev, rdma_ah_get_port_num(attr));
2318 ppd = ppd_from_ibp(ibp);
2319 if ((((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) ||
2320 (ppd->lid >= be16_to_cpu(IB_MULTICAST_LID_BASE))) &&
2321 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)) &&
2322 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2323 (!(rdma_ah_get_ah_flags(attr) & IB_AH_GRH))) ||
2324 (rdma_ah_get_make_grd(attr))) {
2325 rdma_ah_set_ah_flags(attr, IB_AH_GRH);
2326 rdma_ah_set_interface_id(attr, OPA_MAKE_ID(dlid));
2327 rdma_ah_set_subnet_prefix(attr, ibp->rvp.gid_prefix);
2328 }
2329 }
2330
2331 /*
2332 * hfi1_check_mcast- Check if the given lid is
2333 * in the OPA multicast range.
2334 *
2335 * The LID might either reside in ah.dlid or might be
2336 * in the GRH of the address handle as DGID if extended
2337 * addresses are in use.
2338 */
hfi1_check_mcast(u32 lid)2339 static inline bool hfi1_check_mcast(u32 lid)
2340 {
2341 return ((lid >= opa_get_mcast_base(OPA_MCAST_NR)) &&
2342 (lid != be32_to_cpu(OPA_LID_PERMISSIVE)));
2343 }
2344
2345 #define opa_get_lid(lid, format) \
2346 __opa_get_lid(lid, OPA_PORT_PACKET_FORMAT_##format)
2347
2348 /* Convert a lid to a specific lid space */
__opa_get_lid(u32 lid,u8 format)2349 static inline u32 __opa_get_lid(u32 lid, u8 format)
2350 {
2351 bool is_mcast = hfi1_check_mcast(lid);
2352
2353 switch (format) {
2354 case OPA_PORT_PACKET_FORMAT_8B:
2355 case OPA_PORT_PACKET_FORMAT_10B:
2356 if (is_mcast)
2357 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2358 0xF0000);
2359 return lid & 0xFFFFF;
2360 case OPA_PORT_PACKET_FORMAT_16B:
2361 if (is_mcast)
2362 return (lid - opa_get_mcast_base(OPA_MCAST_NR) +
2363 0xF00000);
2364 return lid & 0xFFFFFF;
2365 case OPA_PORT_PACKET_FORMAT_9B:
2366 if (is_mcast)
2367 return (lid -
2368 opa_get_mcast_base(OPA_MCAST_NR) +
2369 be16_to_cpu(IB_MULTICAST_LID_BASE));
2370 else
2371 return lid & 0xFFFF;
2372 default:
2373 return lid;
2374 }
2375 }
2376
2377 /* Return true if the given lid is the OPA 16B multicast range */
hfi1_is_16B_mcast(u32 lid)2378 static inline bool hfi1_is_16B_mcast(u32 lid)
2379 {
2380 return ((lid >=
2381 opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 16B)) &&
2382 (lid != opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B)));
2383 }
2384
hfi1_make_opa_lid(struct rdma_ah_attr * attr)2385 static inline void hfi1_make_opa_lid(struct rdma_ah_attr *attr)
2386 {
2387 const struct ib_global_route *grh = rdma_ah_read_grh(attr);
2388 u32 dlid = rdma_ah_get_dlid(attr);
2389
2390 /* Modify ah_attr.dlid to be in the 32 bit LID space.
2391 * This is how the address will be laid out:
2392 * Assuming MCAST_NR to be 4,
2393 * 32 bit permissive LID = 0xFFFFFFFF
2394 * Multicast LID range = 0xFFFFFFFE to 0xF0000000
2395 * Unicast LID range = 0xEFFFFFFF to 1
2396 * Invalid LID = 0
2397 */
2398 if (ib_is_opa_gid(&grh->dgid))
2399 dlid = opa_get_lid_from_gid(&grh->dgid);
2400 else if ((dlid >= be16_to_cpu(IB_MULTICAST_LID_BASE)) &&
2401 (dlid != be16_to_cpu(IB_LID_PERMISSIVE)) &&
2402 (dlid != be32_to_cpu(OPA_LID_PERMISSIVE)))
2403 dlid = dlid - be16_to_cpu(IB_MULTICAST_LID_BASE) +
2404 opa_get_mcast_base(OPA_MCAST_NR);
2405 else if (dlid == be16_to_cpu(IB_LID_PERMISSIVE))
2406 dlid = be32_to_cpu(OPA_LID_PERMISSIVE);
2407
2408 rdma_ah_set_dlid(attr, dlid);
2409 }
2410
hfi1_get_packet_type(u32 lid)2411 static inline u8 hfi1_get_packet_type(u32 lid)
2412 {
2413 /* 9B if lid > 0xF0000000 */
2414 if (lid >= opa_get_mcast_base(OPA_MCAST_NR))
2415 return HFI1_PKT_TYPE_9B;
2416
2417 /* 16B if lid > 0xC000 */
2418 if (lid >= opa_get_lid(opa_get_mcast_base(OPA_MCAST_NR), 9B))
2419 return HFI1_PKT_TYPE_16B;
2420
2421 return HFI1_PKT_TYPE_9B;
2422 }
2423
hfi1_get_hdr_type(u32 lid,struct rdma_ah_attr * attr)2424 static inline bool hfi1_get_hdr_type(u32 lid, struct rdma_ah_attr *attr)
2425 {
2426 /*
2427 * If there was an incoming 16B packet with permissive
2428 * LIDs, OPA GIDs would have been programmed when those
2429 * packets were received. A 16B packet will have to
2430 * be sent in response to that packet. Return a 16B
2431 * header type if that's the case.
2432 */
2433 if (rdma_ah_get_dlid(attr) == be32_to_cpu(OPA_LID_PERMISSIVE))
2434 return (ib_is_opa_gid(&rdma_ah_read_grh(attr)->dgid)) ?
2435 HFI1_PKT_TYPE_16B : HFI1_PKT_TYPE_9B;
2436
2437 /*
2438 * Return a 16B header type if either the the destination
2439 * or source lid is extended.
2440 */
2441 if (hfi1_get_packet_type(rdma_ah_get_dlid(attr)) == HFI1_PKT_TYPE_16B)
2442 return HFI1_PKT_TYPE_16B;
2443
2444 return hfi1_get_packet_type(lid);
2445 }
2446
hfi1_make_ext_grh(struct hfi1_packet * packet,struct ib_grh * grh,u32 slid,u32 dlid)2447 static inline void hfi1_make_ext_grh(struct hfi1_packet *packet,
2448 struct ib_grh *grh, u32 slid,
2449 u32 dlid)
2450 {
2451 struct hfi1_ibport *ibp = &packet->rcd->ppd->ibport_data;
2452 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
2453
2454 if (!ibp)
2455 return;
2456
2457 grh->hop_limit = 1;
2458 grh->sgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2459 if (slid == opa_get_lid(be32_to_cpu(OPA_LID_PERMISSIVE), 16B))
2460 grh->sgid.global.interface_id =
2461 OPA_MAKE_ID(be32_to_cpu(OPA_LID_PERMISSIVE));
2462 else
2463 grh->sgid.global.interface_id = OPA_MAKE_ID(slid);
2464
2465 /*
2466 * Upper layers (like mad) may compare the dgid in the
2467 * wc that is obtained here with the sgid_index in
2468 * the wr. Since sgid_index in wr is always 0 for
2469 * extended lids, set the dgid here to the default
2470 * IB gid.
2471 */
2472 grh->dgid.global.subnet_prefix = ibp->rvp.gid_prefix;
2473 grh->dgid.global.interface_id =
2474 cpu_to_be64(ppd->guids[HFI1_PORT_GUID_INDEX]);
2475 }
2476
hfi1_get_16b_padding(u32 hdr_size,u32 payload)2477 static inline int hfi1_get_16b_padding(u32 hdr_size, u32 payload)
2478 {
2479 return -(hdr_size + payload + (SIZE_OF_CRC << 2) +
2480 SIZE_OF_LT) & 0x7;
2481 }
2482
hfi1_make_ib_hdr(struct ib_header * hdr,u16 lrh0,u16 len,u16 dlid,u16 slid)2483 static inline void hfi1_make_ib_hdr(struct ib_header *hdr,
2484 u16 lrh0, u16 len,
2485 u16 dlid, u16 slid)
2486 {
2487 hdr->lrh[0] = cpu_to_be16(lrh0);
2488 hdr->lrh[1] = cpu_to_be16(dlid);
2489 hdr->lrh[2] = cpu_to_be16(len);
2490 hdr->lrh[3] = cpu_to_be16(slid);
2491 }
2492
hfi1_make_16b_hdr(struct hfi1_16b_header * hdr,u32 slid,u32 dlid,u16 len,u16 pkey,bool becn,bool fecn,u8 l4,u8 sc)2493 static inline void hfi1_make_16b_hdr(struct hfi1_16b_header *hdr,
2494 u32 slid, u32 dlid,
2495 u16 len, u16 pkey,
2496 bool becn, bool fecn, u8 l4,
2497 u8 sc)
2498 {
2499 u32 lrh0 = 0;
2500 u32 lrh1 = 0x40000000;
2501 u32 lrh2 = 0;
2502 u32 lrh3 = 0;
2503
2504 lrh0 = (lrh0 & ~OPA_16B_BECN_MASK) | (becn << OPA_16B_BECN_SHIFT);
2505 lrh0 = (lrh0 & ~OPA_16B_LEN_MASK) | (len << OPA_16B_LEN_SHIFT);
2506 lrh0 = (lrh0 & ~OPA_16B_LID_MASK) | (slid & OPA_16B_LID_MASK);
2507 lrh1 = (lrh1 & ~OPA_16B_FECN_MASK) | (fecn << OPA_16B_FECN_SHIFT);
2508 lrh1 = (lrh1 & ~OPA_16B_SC_MASK) | (sc << OPA_16B_SC_SHIFT);
2509 lrh1 = (lrh1 & ~OPA_16B_LID_MASK) | (dlid & OPA_16B_LID_MASK);
2510 lrh2 = (lrh2 & ~OPA_16B_SLID_MASK) |
2511 ((slid >> OPA_16B_SLID_SHIFT) << OPA_16B_SLID_HIGH_SHIFT);
2512 lrh2 = (lrh2 & ~OPA_16B_DLID_MASK) |
2513 ((dlid >> OPA_16B_DLID_SHIFT) << OPA_16B_DLID_HIGH_SHIFT);
2514 lrh2 = (lrh2 & ~OPA_16B_PKEY_MASK) | ((u32)pkey << OPA_16B_PKEY_SHIFT);
2515 lrh2 = (lrh2 & ~OPA_16B_L4_MASK) | l4;
2516
2517 hdr->lrh[0] = lrh0;
2518 hdr->lrh[1] = lrh1;
2519 hdr->lrh[2] = lrh2;
2520 hdr->lrh[3] = lrh3;
2521 }
2522 #endif /* _HFI1_KERNEL_H */
2523
