1 /*
2  * OMAP GPIO handling defines and functions
3  *
4  * Copyright (C) 2003-2005 Nokia Corporation
5  *
6  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21  *
22  */
23 
24 #ifndef __ASM_ARCH_OMAP_GPIO_H
25 #define __ASM_ARCH_OMAP_GPIO_H
26 
27 #include <linux/io.h>
28 #include <linux/platform_device.h>
29 
30 #define OMAP1_MPUIO_BASE			0xfffb5000
31 
32 /*
33  * These are the omap15xx/16xx offsets. The omap7xx offset are
34  * OMAP_MPUIO_ / 2 offsets below.
35  */
36 #define OMAP_MPUIO_INPUT_LATCH		0x00
37 #define OMAP_MPUIO_OUTPUT		0x04
38 #define OMAP_MPUIO_IO_CNTL		0x08
39 #define OMAP_MPUIO_KBR_LATCH		0x10
40 #define OMAP_MPUIO_KBC			0x14
41 #define OMAP_MPUIO_GPIO_EVENT_MODE	0x18
42 #define OMAP_MPUIO_GPIO_INT_EDGE	0x1c
43 #define OMAP_MPUIO_KBD_INT		0x20
44 #define OMAP_MPUIO_GPIO_INT		0x24
45 #define OMAP_MPUIO_KBD_MASKIT		0x28
46 #define OMAP_MPUIO_GPIO_MASKIT		0x2c
47 #define OMAP_MPUIO_GPIO_DEBOUNCING	0x30
48 #define OMAP_MPUIO_LATCH		0x34
49 
50 #define OMAP34XX_NR_GPIOS		6
51 
52 /*
53  * OMAP1510 GPIO registers
54  */
55 #define OMAP1510_GPIO_DATA_INPUT	0x00
56 #define OMAP1510_GPIO_DATA_OUTPUT	0x04
57 #define OMAP1510_GPIO_DIR_CONTROL	0x08
58 #define OMAP1510_GPIO_INT_CONTROL	0x0c
59 #define OMAP1510_GPIO_INT_MASK		0x10
60 #define OMAP1510_GPIO_INT_STATUS	0x14
61 #define OMAP1510_GPIO_PIN_CONTROL	0x18
62 
63 #define OMAP1510_IH_GPIO_BASE		64
64 
65 /*
66  * OMAP1610 specific GPIO registers
67  */
68 #define OMAP1610_GPIO_REVISION		0x0000
69 #define OMAP1610_GPIO_SYSCONFIG		0x0010
70 #define OMAP1610_GPIO_SYSSTATUS		0x0014
71 #define OMAP1610_GPIO_IRQSTATUS1	0x0018
72 #define OMAP1610_GPIO_IRQENABLE1	0x001c
73 #define OMAP1610_GPIO_WAKEUPENABLE	0x0028
74 #define OMAP1610_GPIO_DATAIN		0x002c
75 #define OMAP1610_GPIO_DATAOUT		0x0030
76 #define OMAP1610_GPIO_DIRECTION		0x0034
77 #define OMAP1610_GPIO_EDGE_CTRL1	0x0038
78 #define OMAP1610_GPIO_EDGE_CTRL2	0x003c
79 #define OMAP1610_GPIO_CLEAR_IRQENABLE1	0x009c
80 #define OMAP1610_GPIO_CLEAR_WAKEUPENA	0x00a8
81 #define OMAP1610_GPIO_CLEAR_DATAOUT	0x00b0
82 #define OMAP1610_GPIO_SET_IRQENABLE1	0x00dc
83 #define OMAP1610_GPIO_SET_WAKEUPENA	0x00e8
84 #define OMAP1610_GPIO_SET_DATAOUT	0x00f0
85 
86 /*
87  * OMAP7XX specific GPIO registers
88  */
89 #define OMAP7XX_GPIO_DATA_INPUT		0x00
90 #define OMAP7XX_GPIO_DATA_OUTPUT	0x04
91 #define OMAP7XX_GPIO_DIR_CONTROL	0x08
92 #define OMAP7XX_GPIO_INT_CONTROL	0x0c
93 #define OMAP7XX_GPIO_INT_MASK		0x10
94 #define OMAP7XX_GPIO_INT_STATUS		0x14
95 
96 /*
97  * omap2+ specific GPIO registers
98  */
99 #define OMAP24XX_GPIO_REVISION		0x0000
100 #define OMAP24XX_GPIO_IRQSTATUS1	0x0018
101 #define OMAP24XX_GPIO_IRQSTATUS2	0x0028
102 #define OMAP24XX_GPIO_IRQENABLE2	0x002c
103 #define OMAP24XX_GPIO_IRQENABLE1	0x001c
104 #define OMAP24XX_GPIO_WAKE_EN		0x0020
105 #define OMAP24XX_GPIO_CTRL		0x0030
106 #define OMAP24XX_GPIO_OE		0x0034
107 #define OMAP24XX_GPIO_DATAIN		0x0038
108 #define OMAP24XX_GPIO_DATAOUT		0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0	0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1	0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT	0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT	0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN	0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL	0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1	0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1	0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA	0x0080
118 #define OMAP24XX_GPIO_SETWKUENA		0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT	0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT	0x0094
121 
122 #define OMAP4_GPIO_REVISION		0x0000
123 #define OMAP4_GPIO_EOI			0x0020
124 #define OMAP4_GPIO_IRQSTATUSRAW0	0x0024
125 #define OMAP4_GPIO_IRQSTATUSRAW1	0x0028
126 #define OMAP4_GPIO_IRQSTATUS0		0x002c
127 #define OMAP4_GPIO_IRQSTATUS1		0x0030
128 #define OMAP4_GPIO_IRQSTATUSSET0	0x0034
129 #define OMAP4_GPIO_IRQSTATUSSET1	0x0038
130 #define OMAP4_GPIO_IRQSTATUSCLR0	0x003c
131 #define OMAP4_GPIO_IRQSTATUSCLR1	0x0040
132 #define OMAP4_GPIO_IRQWAKEN0		0x0044
133 #define OMAP4_GPIO_IRQWAKEN1		0x0048
134 #define OMAP4_GPIO_IRQENABLE1		0x011c
135 #define OMAP4_GPIO_WAKE_EN		0x0120
136 #define OMAP4_GPIO_IRQSTATUS2		0x0128
137 #define OMAP4_GPIO_IRQENABLE2		0x012c
138 #define OMAP4_GPIO_CTRL			0x0130
139 #define OMAP4_GPIO_OE			0x0134
140 #define OMAP4_GPIO_DATAIN		0x0138
141 #define OMAP4_GPIO_DATAOUT		0x013c
142 #define OMAP4_GPIO_LEVELDETECT0		0x0140
143 #define OMAP4_GPIO_LEVELDETECT1		0x0144
144 #define OMAP4_GPIO_RISINGDETECT		0x0148
145 #define OMAP4_GPIO_FALLINGDETECT	0x014c
146 #define OMAP4_GPIO_DEBOUNCENABLE	0x0150
147 #define OMAP4_GPIO_DEBOUNCINGTIME	0x0154
148 #define OMAP4_GPIO_CLEARIRQENABLE1	0x0160
149 #define OMAP4_GPIO_SETIRQENABLE1	0x0164
150 #define OMAP4_GPIO_CLEARWKUENA		0x0180
151 #define OMAP4_GPIO_SETWKUENA		0x0184
152 #define OMAP4_GPIO_CLEARDATAOUT		0x0190
153 #define OMAP4_GPIO_SETDATAOUT		0x0194
154 
155 #define OMAP_MAX_GPIO_LINES		192
156 
157 #define OMAP_MPUIO(nr)		(OMAP_MAX_GPIO_LINES + (nr))
158 #define OMAP_GPIO_IS_MPUIO(nr)	((nr) >= OMAP_MAX_GPIO_LINES)
159 
160 struct omap_gpio_reg_offs {
161 	u16 revision;
162 	u16 direction;
163 	u16 datain;
164 	u16 dataout;
165 	u16 set_dataout;
166 	u16 clr_dataout;
167 	u16 irqstatus;
168 	u16 irqstatus2;
169 	u16 irqstatus_raw0;
170 	u16 irqstatus_raw1;
171 	u16 irqenable;
172 	u16 irqenable2;
173 	u16 set_irqenable;
174 	u16 clr_irqenable;
175 	u16 debounce;
176 	u16 debounce_en;
177 	u16 ctrl;
178 	u16 wkup_en;
179 	u16 leveldetect0;
180 	u16 leveldetect1;
181 	u16 risingdetect;
182 	u16 fallingdetect;
183 	u16 irqctrl;
184 	u16 edgectrl1;
185 	u16 edgectrl2;
186 	u16 pinctrl;
187 
188 	bool irqenable_inv;
189 };
190 
191 struct omap_gpio_platform_data {
192 	int bank_type;
193 	int bank_width;		/* GPIO bank width */
194 	int bank_stride;	/* Only needed for omap1 MPUIO */
195 	bool dbck_flag;		/* dbck required or not - True for OMAP3&4 */
196 	bool loses_context;	/* whether the bank would ever lose context */
197 	bool is_mpuio;		/* whether the bank is of type MPUIO */
198 	u32 non_wakeup_gpios;
199 
200 	struct omap_gpio_reg_offs *regs;
201 
202 	/* Return context loss count due to PM states changing */
203 	int (*get_context_loss_count)(struct device *dev);
204 };
205 
206 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
207 extern void omap2_gpio_prepare_for_idle(int off_mode);
208 extern void omap2_gpio_resume_after_idle(void);
209 #else
omap2_gpio_prepare_for_idle(int off_mode)210 static inline void omap2_gpio_prepare_for_idle(int off_mode)
211 {
212 }
213 
omap2_gpio_resume_after_idle(void)214 static inline void omap2_gpio_resume_after_idle(void)
215 {
216 }
217 #endif
218 
219 #endif
220