1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * OMAP44xx CM2 instance offset macros 4 * 5 * Copyright (C) 2009-2011 Texas Instruments, Inc. 6 * Copyright (C) 2009-2010 Nokia Corporation 7 * 8 * Paul Walmsley (paul@pwsan.com) 9 * Rajendra Nayak (rnayak@ti.com) 10 * Benoit Cousson (b-cousson@ti.com) 11 * 12 * This file is automatically generated from the OMAP hardware databases. 13 * We respectfully ask that any modifications to this file be coordinated 14 * with the public linux-omap@vger.kernel.org mailing list and the 15 * authors above to ensure that the autogeneration scripts are kept 16 * up-to-date with the file contents. 17 * 18 * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", 19 * or "OMAP4430". 20 */ 21 22 #ifndef __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 23 #define __ARCH_ARM_MACH_OMAP2_CM2_44XX_H 24 25 /* CM2 base address */ 26 #define OMAP4430_CM2_BASE 0x4a008000 27 28 #define OMAP44XX_CM2_REGADDR(inst, reg) \ 29 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg)) 30 31 /* CM2 instances */ 32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000 33 #define OMAP4430_CM2_CKGEN_INST 0x0100 34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600 35 #define OMAP4430_CM2_CORE_INST 0x0700 36 #define OMAP4430_CM2_IVAHD_INST 0x0f00 37 #define OMAP4430_CM2_CAM_INST 0x1000 38 #define OMAP4430_CM2_DSS_INST 0x1100 39 #define OMAP4430_CM2_GFX_INST 0x1200 40 #define OMAP4430_CM2_L3INIT_INST 0x1300 41 #define OMAP4430_CM2_L4PER_INST 0x1400 42 #define OMAP4430_CM2_CEFUSE_INST 0x1600 43 #define OMAP4430_CM2_RESTORE_INST 0x1e00 44 #define OMAP4430_CM2_INSTR_INST 0x1f00 45 46 /* CM2 clockdomain register offsets (from instance start) */ 47 #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000 48 #define OMAP4430_CM2_CORE_L3_1_CDOFFS 0x0000 49 #define OMAP4430_CM2_CORE_L3_2_CDOFFS 0x0100 50 #define OMAP4430_CM2_CORE_DUCATI_CDOFFS 0x0200 51 #define OMAP4430_CM2_CORE_SDMA_CDOFFS 0x0300 52 #define OMAP4430_CM2_CORE_MEMIF_CDOFFS 0x0400 53 #define OMAP4430_CM2_CORE_D2D_CDOFFS 0x0500 54 #define OMAP4430_CM2_CORE_L4CFG_CDOFFS 0x0600 55 #define OMAP4430_CM2_CORE_L3INSTR_CDOFFS 0x0700 56 #define OMAP4430_CM2_IVAHD_IVAHD_CDOFFS 0x0000 57 #define OMAP4430_CM2_CAM_CAM_CDOFFS 0x0000 58 #define OMAP4430_CM2_DSS_DSS_CDOFFS 0x0000 59 #define OMAP4430_CM2_GFX_GFX_CDOFFS 0x0000 60 #define OMAP4430_CM2_L3INIT_L3INIT_CDOFFS 0x0000 61 #define OMAP4430_CM2_L4PER_L4PER_CDOFFS 0x0000 62 #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 63 #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 64 65 /* CM2 */ 66 67 /* CM2.OCP_SOCKET_CM2 register offsets */ 68 #define OMAP4_REVISION_CM2_OFFSET 0x0000 69 #define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000) 70 #define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 71 #define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040) 72 73 /* CM2.CKGEN_CM2 register offsets */ 74 #define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 75 #define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000) 76 #define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 77 #define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004) 78 #define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 79 #define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008) 80 #define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 81 #define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010) 82 #define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 83 #define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014) 84 #define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 85 #define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018) 86 #define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c 87 #define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c) 88 #define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 89 #define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024) 90 #define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 91 #define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028) 92 #define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c 93 #define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c) 94 #define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 95 #define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030) 96 #define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 97 #define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038) 98 #define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 99 #define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040) 100 #define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 101 #define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044) 102 #define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 103 #define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048) 104 #define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c 105 #define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c) 106 #define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 107 #define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050) 108 #define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 109 #define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054) 110 #define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 111 #define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058) 112 #define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c 113 #define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c) 114 #define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 115 #define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060) 116 #define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 117 #define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) 118 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 119 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) 120 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c 121 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) 122 #define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 123 #define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) 124 #define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 125 #define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084) 126 #define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 127 #define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088) 128 #define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c 129 #define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c) 130 #define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 131 #define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) 132 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 133 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) 134 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac 135 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) 136 #define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 137 #define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) 138 #define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 139 #define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0) 140 #define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 141 #define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4) 142 #define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 143 #define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8) 144 #define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc 145 #define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc) 146 #define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 147 #define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) 148 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 149 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) 150 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec 151 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) 152 153 /* CM2.ALWAYS_ON_CM2 register offsets */ 154 #define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 155 #define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000) 156 #define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 157 #define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020) 158 #define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 159 #define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028) 160 #define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 161 #define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030) 162 #define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 163 #define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038) 164 #define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 165 #define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040) 166 167 /* CM2.CORE_CM2 register offsets */ 168 #define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 169 #define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000) 170 #define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 171 #define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008) 172 #define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 173 #define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020) 174 #define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 175 #define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100) 176 #define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 177 #define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108) 178 #define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 179 #define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120) 180 #define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 181 #define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128) 182 #define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 183 #define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130) 184 #define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 185 #define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200) 186 #define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 187 #define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204) 188 #define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 189 #define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208) 190 #define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 191 #define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220) 192 #define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 193 #define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300) 194 #define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 195 #define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304) 196 #define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 197 #define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308) 198 #define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 199 #define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320) 200 #define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 201 #define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400) 202 #define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 203 #define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420) 204 #define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 205 #define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428) 206 #define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 207 #define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430) 208 #define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 209 #define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438) 210 #define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 211 #define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440) 212 #define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 213 #define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450) 214 #define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 215 #define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458) 216 #define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 217 #define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460) 218 #define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 219 #define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500) 220 #define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 221 #define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504) 222 #define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 223 #define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) 224 #define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 225 #define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) 226 #define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528 227 #define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) 228 #define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 229 #define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) 230 #define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 231 #define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600) 232 #define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 233 #define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608) 234 #define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 235 #define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620) 236 #define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 237 #define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628) 238 #define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 239 #define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630) 240 #define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 241 #define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638) 242 #define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 243 #define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700) 244 #define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 245 #define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720) 246 #define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 247 #define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728) 248 #define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 249 #define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740) 250 251 /* CM2.IVAHD_CM2 register offsets */ 252 #define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 253 #define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000) 254 #define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 255 #define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004) 256 #define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 257 #define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008) 258 #define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 259 #define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020) 260 #define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 261 #define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028) 262 263 /* CM2.CAM_CM2 register offsets */ 264 #define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 265 #define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000) 266 #define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 267 #define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004) 268 #define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 269 #define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008) 270 #define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 271 #define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020) 272 #define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 273 #define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028) 274 275 /* CM2.DSS_CM2 register offsets */ 276 #define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 277 #define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000) 278 #define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 279 #define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004) 280 #define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 281 #define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008) 282 #define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 283 #define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020) 284 #define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 285 #define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028) 286 287 /* CM2.GFX_CM2 register offsets */ 288 #define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 289 #define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000) 290 #define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 291 #define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004) 292 #define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 293 #define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008) 294 #define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 295 #define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020) 296 297 /* CM2.L3INIT_CM2 register offsets */ 298 #define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 299 #define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000) 300 #define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 301 #define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004) 302 #define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 303 #define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008) 304 #define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 305 #define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028) 306 #define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 307 #define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030) 308 #define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 309 #define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038) 310 #define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 311 #define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040) 312 #define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 313 #define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058) 314 #define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 315 #define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060) 316 #define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 317 #define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068) 318 #define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 319 #define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078) 320 #define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 321 #define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080) 322 #define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 323 #define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088) 324 #define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 325 #define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090) 326 #define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 327 #define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098) 328 #define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 329 #define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8) 330 #define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 331 #define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0) 332 #define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 333 #define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8) 334 #define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 335 #define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0) 336 #define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 337 #define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0) 338 339 /* CM2.L4PER_CM2 register offsets */ 340 #define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 341 #define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000) 342 #define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 343 #define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008) 344 #define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 345 #define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020) 346 #define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 347 #define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028) 348 #define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 349 #define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030) 350 #define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 351 #define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038) 352 #define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 353 #define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040) 354 #define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 355 #define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048) 356 #define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 357 #define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050) 358 #define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 359 #define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058) 360 #define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 361 #define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060) 362 #define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 363 #define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068) 364 #define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 365 #define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070) 366 #define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 367 #define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078) 368 #define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 369 #define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080) 370 #define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 371 #define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088) 372 #define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 373 #define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090) 374 #define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 375 #define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098) 376 #define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 377 #define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0) 378 #define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 379 #define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8) 380 #define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 381 #define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0) 382 #define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 383 #define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8) 384 #define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 385 #define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0) 386 #define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 387 #define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0) 388 #define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 389 #define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8) 390 #define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 391 #define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0) 392 #define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 393 #define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8) 394 #define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 395 #define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0) 396 #define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 397 #define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8) 398 #define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 399 #define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100) 400 #define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 401 #define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108) 402 #define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 403 #define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120) 404 #define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 405 #define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128) 406 #define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 407 #define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130) 408 #define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 409 #define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138) 410 #define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 411 #define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140) 412 #define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 413 #define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148) 414 #define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 415 #define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150) 416 #define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 417 #define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158) 418 #define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 419 #define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160) 420 #define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 421 #define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168) 422 #define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 423 #define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180) 424 #define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 425 #define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184) 426 #define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 427 #define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188) 428 #define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 429 #define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0) 430 #define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 431 #define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8) 432 #define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 433 #define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0) 434 #define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 435 #define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8) 436 #define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 437 #define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0) 438 #define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 439 #define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8) 440 #define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 441 #define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8) 442 443 /* CM2.CEFUSE_CM2 register offsets */ 444 #define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 445 #define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000) 446 #define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 447 #define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) 448 449 #endif 450
