1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Marvell RVU Admin Function driver 3 * 4 * Copyright (C) 2018 Marvell. 5 * 6 */ 7 8 #ifndef NPC_H 9 #define NPC_H 10 11 enum NPC_LID_E { 12 NPC_LID_LA = 0, 13 NPC_LID_LB, 14 NPC_LID_LC, 15 NPC_LID_LD, 16 NPC_LID_LE, 17 NPC_LID_LF, 18 NPC_LID_LG, 19 NPC_LID_LH, 20 }; 21 22 #define NPC_LT_NA 0 23 24 enum npc_kpu_la_ltype { 25 NPC_LT_LA_8023 = 1, 26 NPC_LT_LA_ETHER, 27 NPC_LT_LA_IH_NIX_ETHER, 28 NPC_LT_LA_IH_8_ETHER, 29 NPC_LT_LA_IH_4_ETHER, 30 NPC_LT_LA_IH_2_ETHER, 31 NPC_LT_LA_HIGIG2_ETHER, 32 NPC_LT_LA_IH_NIX_HIGIG2_ETHER, 33 NPC_LT_LA_CUSTOM_L2_90B_ETHER, 34 NPC_LT_LA_CH_LEN_90B_ETHER, 35 NPC_LT_LA_CPT_HDR, 36 NPC_LT_LA_CUSTOM_L2_24B_ETHER, 37 NPC_LT_LA_CUSTOM0 = 0xE, 38 NPC_LT_LA_CUSTOM1 = 0xF, 39 }; 40 41 enum npc_kpu_lb_ltype { 42 NPC_LT_LB_ETAG = 1, 43 NPC_LT_LB_CTAG, 44 NPC_LT_LB_STAG_QINQ, 45 NPC_LT_LB_BTAG, 46 NPC_LT_LB_PPPOE, 47 NPC_LT_LB_DSA, 48 NPC_LT_LB_DSA_VLAN, 49 NPC_LT_LB_EDSA, 50 NPC_LT_LB_EDSA_VLAN, 51 NPC_LT_LB_EXDSA, 52 NPC_LT_LB_EXDSA_VLAN, 53 NPC_LT_LB_FDSA, 54 NPC_LT_LB_VLAN_EXDSA, 55 NPC_LT_LB_CUSTOM0 = 0xE, 56 NPC_LT_LB_CUSTOM1 = 0xF, 57 }; 58 59 enum npc_kpu_lc_ltype { 60 NPC_LT_LC_IP = 1, 61 NPC_LT_LC_IP_OPT, 62 NPC_LT_LC_IP6, 63 NPC_LT_LC_IP6_EXT, 64 NPC_LT_LC_ARP, 65 NPC_LT_LC_RARP, 66 NPC_LT_LC_MPLS, 67 NPC_LT_LC_NSH, 68 NPC_LT_LC_PTP, 69 NPC_LT_LC_FCOE, 70 NPC_LT_LC_NGIO, 71 NPC_LT_LC_CUSTOM0 = 0xE, 72 NPC_LT_LC_CUSTOM1 = 0xF, 73 }; 74 75 /* Don't modify Ltypes upto SCTP, otherwise it will 76 * effect flow tag calculation and thus RSS. 77 */ 78 enum npc_kpu_ld_ltype { 79 NPC_LT_LD_TCP = 1, 80 NPC_LT_LD_UDP, 81 NPC_LT_LD_ICMP, 82 NPC_LT_LD_SCTP, 83 NPC_LT_LD_ICMP6, 84 NPC_LT_LD_CUSTOM0, 85 NPC_LT_LD_CUSTOM1, 86 NPC_LT_LD_IGMP = 8, 87 NPC_LT_LD_AH, 88 NPC_LT_LD_GRE, 89 NPC_LT_LD_NVGRE, 90 NPC_LT_LD_NSH, 91 NPC_LT_LD_TU_MPLS_IN_NSH, 92 NPC_LT_LD_TU_MPLS_IN_IP, 93 }; 94 95 enum npc_kpu_le_ltype { 96 NPC_LT_LE_VXLAN = 1, 97 NPC_LT_LE_GENEVE, 98 NPC_LT_LE_ESP, 99 NPC_LT_LE_GTPU = 4, 100 NPC_LT_LE_VXLANGPE, 101 NPC_LT_LE_GTPC, 102 NPC_LT_LE_NSH, 103 NPC_LT_LE_TU_MPLS_IN_GRE, 104 NPC_LT_LE_TU_NSH_IN_GRE, 105 NPC_LT_LE_TU_MPLS_IN_UDP, 106 NPC_LT_LE_CUSTOM0 = 0xE, 107 NPC_LT_LE_CUSTOM1 = 0xF, 108 }; 109 110 enum npc_kpu_lf_ltype { 111 NPC_LT_LF_TU_ETHER = 1, 112 NPC_LT_LF_TU_PPP, 113 NPC_LT_LF_TU_MPLS_IN_VXLANGPE, 114 NPC_LT_LF_TU_NSH_IN_VXLANGPE, 115 NPC_LT_LF_TU_MPLS_IN_NSH, 116 NPC_LT_LF_TU_3RD_NSH, 117 NPC_LT_LF_CUSTOM0 = 0xE, 118 NPC_LT_LF_CUSTOM1 = 0xF, 119 }; 120 121 enum npc_kpu_lg_ltype { 122 NPC_LT_LG_TU_IP = 1, 123 NPC_LT_LG_TU_IP6, 124 NPC_LT_LG_TU_ARP, 125 NPC_LT_LG_TU_ETHER_IN_NSH, 126 NPC_LT_LG_CUSTOM0 = 0xE, 127 NPC_LT_LG_CUSTOM1 = 0xF, 128 }; 129 130 /* Don't modify Ltypes upto SCTP, otherwise it will 131 * effect flow tag calculation and thus RSS. 132 */ 133 enum npc_kpu_lh_ltype { 134 NPC_LT_LH_TU_TCP = 1, 135 NPC_LT_LH_TU_UDP, 136 NPC_LT_LH_TU_ICMP, 137 NPC_LT_LH_TU_SCTP, 138 NPC_LT_LH_TU_ICMP6, 139 NPC_LT_LH_TU_IGMP = 8, 140 NPC_LT_LH_TU_ESP, 141 NPC_LT_LH_TU_AH, 142 NPC_LT_LH_CUSTOM0 = 0xE, 143 NPC_LT_LH_CUSTOM1 = 0xF, 144 }; 145 146 /* NPC port kind defines how the incoming or outgoing packets 147 * are processed. NPC accepts packets from up to 64 pkinds. 148 * Software assigns pkind for each incoming port such as CGX 149 * Ethernet interfaces, LBK interfaces, etc. 150 */ 151 #define NPC_UNRESERVED_PKIND_COUNT NPC_RX_VLAN_EXDSA_PKIND 152 153 enum npc_pkind_type { 154 NPC_RX_LBK_PKIND = 0ULL, 155 NPC_RX_VLAN_EXDSA_PKIND = 56ULL, 156 NPC_RX_CHLEN24B_PKIND = 57ULL, 157 NPC_RX_CPT_HDR_PKIND, 158 NPC_RX_CHLEN90B_PKIND, 159 NPC_TX_HIGIG_PKIND, 160 NPC_RX_HIGIG_PKIND, 161 NPC_RX_EDSA_PKIND, 162 NPC_TX_DEF_PKIND, /* NIX-TX PKIND */ 163 }; 164 165 /* list of known and supported fields in packet header and 166 * fields present in key structure. 167 */ 168 enum key_fields { 169 NPC_DMAC, 170 NPC_SMAC, 171 NPC_ETYPE, 172 NPC_VLAN_ETYPE_CTAG, /* 0x8100 */ 173 NPC_VLAN_ETYPE_STAG, /* 0x88A8 */ 174 NPC_OUTER_VID, 175 NPC_TOS, 176 NPC_SIP_IPV4, 177 NPC_DIP_IPV4, 178 NPC_SIP_IPV6, 179 NPC_DIP_IPV6, 180 NPC_IPPROTO_TCP, 181 NPC_IPPROTO_UDP, 182 NPC_IPPROTO_SCTP, 183 NPC_IPPROTO_AH, 184 NPC_IPPROTO_ESP, 185 NPC_IPPROTO_ICMP, 186 NPC_IPPROTO_ICMP6, 187 NPC_SPORT_TCP, 188 NPC_DPORT_TCP, 189 NPC_SPORT_UDP, 190 NPC_DPORT_UDP, 191 NPC_SPORT_SCTP, 192 NPC_DPORT_SCTP, 193 NPC_HEADER_FIELDS_MAX, 194 NPC_CHAN = NPC_HEADER_FIELDS_MAX, /* Valid when Rx */ 195 NPC_PF_FUNC, /* Valid when Tx */ 196 NPC_ERRLEV, 197 NPC_ERRCODE, 198 NPC_LXMB, 199 NPC_LA, 200 NPC_LB, 201 NPC_LC, 202 NPC_LD, 203 NPC_LE, 204 NPC_LF, 205 NPC_LG, 206 NPC_LH, 207 /* Ethertype for untagged frame */ 208 NPC_ETYPE_ETHER, 209 /* Ethertype for single tagged frame */ 210 NPC_ETYPE_TAG1, 211 /* Ethertype for double tagged frame */ 212 NPC_ETYPE_TAG2, 213 /* outer vlan tci for single tagged frame */ 214 NPC_VLAN_TAG1, 215 /* outer vlan tci for double tagged frame */ 216 NPC_VLAN_TAG2, 217 /* other header fields programmed to extract but not of our interest */ 218 NPC_UNKNOWN, 219 NPC_KEY_FIELDS_MAX, 220 }; 221 222 struct npc_kpu_profile_cam { 223 u8 state; 224 u8 state_mask; 225 u16 dp0; 226 u16 dp0_mask; 227 u16 dp1; 228 u16 dp1_mask; 229 u16 dp2; 230 u16 dp2_mask; 231 } __packed; 232 233 struct npc_kpu_profile_action { 234 u8 errlev; 235 u8 errcode; 236 u8 dp0_offset; 237 u8 dp1_offset; 238 u8 dp2_offset; 239 u8 bypass_count; 240 u8 parse_done; 241 u8 next_state; 242 u8 ptr_advance; 243 u8 cap_ena; 244 u8 lid; 245 u8 ltype; 246 u8 flags; 247 u8 offset; 248 u8 mask; 249 u8 right; 250 u8 shift; 251 } __packed; 252 253 struct npc_kpu_profile { 254 int cam_entries; 255 int action_entries; 256 struct npc_kpu_profile_cam *cam; 257 struct npc_kpu_profile_action *action; 258 }; 259 260 /* NPC KPU register formats */ 261 struct npc_kpu_cam { 262 #if defined(__BIG_ENDIAN_BITFIELD) 263 u64 rsvd_63_56 : 8; 264 u64 state : 8; 265 u64 dp2_data : 16; 266 u64 dp1_data : 16; 267 u64 dp0_data : 16; 268 #else 269 u64 dp0_data : 16; 270 u64 dp1_data : 16; 271 u64 dp2_data : 16; 272 u64 state : 8; 273 u64 rsvd_63_56 : 8; 274 #endif 275 }; 276 277 struct npc_kpu_action0 { 278 #if defined(__BIG_ENDIAN_BITFIELD) 279 u64 rsvd_63_57 : 7; 280 u64 byp_count : 3; 281 u64 capture_ena : 1; 282 u64 parse_done : 1; 283 u64 next_state : 8; 284 u64 rsvd_43 : 1; 285 u64 capture_lid : 3; 286 u64 capture_ltype : 4; 287 u64 capture_flags : 8; 288 u64 ptr_advance : 8; 289 u64 var_len_offset : 8; 290 u64 var_len_mask : 8; 291 u64 var_len_right : 1; 292 u64 var_len_shift : 3; 293 #else 294 u64 var_len_shift : 3; 295 u64 var_len_right : 1; 296 u64 var_len_mask : 8; 297 u64 var_len_offset : 8; 298 u64 ptr_advance : 8; 299 u64 capture_flags : 8; 300 u64 capture_ltype : 4; 301 u64 capture_lid : 3; 302 u64 rsvd_43 : 1; 303 u64 next_state : 8; 304 u64 parse_done : 1; 305 u64 capture_ena : 1; 306 u64 byp_count : 3; 307 u64 rsvd_63_57 : 7; 308 #endif 309 }; 310 311 struct npc_kpu_action1 { 312 #if defined(__BIG_ENDIAN_BITFIELD) 313 u64 rsvd_63_36 : 28; 314 u64 errlev : 4; 315 u64 errcode : 8; 316 u64 dp2_offset : 8; 317 u64 dp1_offset : 8; 318 u64 dp0_offset : 8; 319 #else 320 u64 dp0_offset : 8; 321 u64 dp1_offset : 8; 322 u64 dp2_offset : 8; 323 u64 errcode : 8; 324 u64 errlev : 4; 325 u64 rsvd_63_36 : 28; 326 #endif 327 }; 328 329 struct npc_kpu_pkind_cpi_def { 330 #if defined(__BIG_ENDIAN_BITFIELD) 331 u64 ena : 1; 332 u64 rsvd_62_59 : 4; 333 u64 lid : 3; 334 u64 ltype_match : 4; 335 u64 ltype_mask : 4; 336 u64 flags_match : 8; 337 u64 flags_mask : 8; 338 u64 add_offset : 8; 339 u64 add_mask : 8; 340 u64 rsvd_15 : 1; 341 u64 add_shift : 3; 342 u64 rsvd_11_10 : 2; 343 u64 cpi_base : 10; 344 #else 345 u64 cpi_base : 10; 346 u64 rsvd_11_10 : 2; 347 u64 add_shift : 3; 348 u64 rsvd_15 : 1; 349 u64 add_mask : 8; 350 u64 add_offset : 8; 351 u64 flags_mask : 8; 352 u64 flags_match : 8; 353 u64 ltype_mask : 4; 354 u64 ltype_match : 4; 355 u64 lid : 3; 356 u64 rsvd_62_59 : 4; 357 u64 ena : 1; 358 #endif 359 }; 360 361 struct nix_rx_action { 362 #if defined(__BIG_ENDIAN_BITFIELD) 363 u64 rsvd_63_61 :3; 364 u64 flow_key_alg :5; 365 u64 match_id :16; 366 u64 index :20; 367 u64 pf_func :16; 368 u64 op :4; 369 #else 370 u64 op :4; 371 u64 pf_func :16; 372 u64 index :20; 373 u64 match_id :16; 374 u64 flow_key_alg :5; 375 u64 rsvd_63_61 :3; 376 #endif 377 }; 378 379 /* NPC_AF_INTFX_KEX_CFG field masks */ 380 #define NPC_PARSE_NIBBLE GENMASK_ULL(30, 0) 381 382 /* NPC_PARSE_KEX_S nibble definitions for each field */ 383 #define NPC_PARSE_NIBBLE_CHAN GENMASK_ULL(2, 0) 384 #define NPC_PARSE_NIBBLE_ERRLEV BIT_ULL(3) 385 #define NPC_PARSE_NIBBLE_ERRCODE GENMASK_ULL(5, 4) 386 #define NPC_PARSE_NIBBLE_L2L3_BCAST BIT_ULL(6) 387 #define NPC_PARSE_NIBBLE_LA_FLAGS GENMASK_ULL(8, 7) 388 #define NPC_PARSE_NIBBLE_LA_LTYPE BIT_ULL(9) 389 #define NPC_PARSE_NIBBLE_LB_FLAGS GENMASK_ULL(11, 10) 390 #define NPC_PARSE_NIBBLE_LB_LTYPE BIT_ULL(12) 391 #define NPC_PARSE_NIBBLE_LC_FLAGS GENMASK_ULL(14, 13) 392 #define NPC_PARSE_NIBBLE_LC_LTYPE BIT_ULL(15) 393 #define NPC_PARSE_NIBBLE_LD_FLAGS GENMASK_ULL(17, 16) 394 #define NPC_PARSE_NIBBLE_LD_LTYPE BIT_ULL(18) 395 #define NPC_PARSE_NIBBLE_LE_FLAGS GENMASK_ULL(20, 19) 396 #define NPC_PARSE_NIBBLE_LE_LTYPE BIT_ULL(21) 397 #define NPC_PARSE_NIBBLE_LF_FLAGS GENMASK_ULL(23, 22) 398 #define NPC_PARSE_NIBBLE_LF_LTYPE BIT_ULL(24) 399 #define NPC_PARSE_NIBBLE_LG_FLAGS GENMASK_ULL(26, 25) 400 #define NPC_PARSE_NIBBLE_LG_LTYPE BIT_ULL(27) 401 #define NPC_PARSE_NIBBLE_LH_FLAGS GENMASK_ULL(29, 28) 402 #define NPC_PARSE_NIBBLE_LH_LTYPE BIT_ULL(30) 403 404 struct nix_tx_action { 405 #if defined(__BIG_ENDIAN_BITFIELD) 406 u64 rsvd_63_48 :16; 407 u64 match_id :16; 408 u64 index :20; 409 u64 rsvd_11_8 :8; 410 u64 op :4; 411 #else 412 u64 op :4; 413 u64 rsvd_11_8 :8; 414 u64 index :20; 415 u64 match_id :16; 416 u64 rsvd_63_48 :16; 417 #endif 418 }; 419 420 /* NIX Receive Vtag Action Structure */ 421 #define RX_VTAG0_VALID_BIT BIT_ULL(15) 422 #define RX_VTAG0_TYPE_MASK GENMASK_ULL(14, 12) 423 #define RX_VTAG0_LID_MASK GENMASK_ULL(10, 8) 424 #define RX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0) 425 #define RX_VTAG1_VALID_BIT BIT_ULL(47) 426 #define RX_VTAG1_TYPE_MASK GENMASK_ULL(46, 44) 427 #define RX_VTAG1_LID_MASK GENMASK_ULL(42, 40) 428 #define RX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32) 429 430 /* NIX Transmit Vtag Action Structure */ 431 #define TX_VTAG0_DEF_MASK GENMASK_ULL(25, 16) 432 #define TX_VTAG0_OP_MASK GENMASK_ULL(13, 12) 433 #define TX_VTAG0_LID_MASK GENMASK_ULL(10, 8) 434 #define TX_VTAG0_RELPTR_MASK GENMASK_ULL(7, 0) 435 #define TX_VTAG1_DEF_MASK GENMASK_ULL(57, 48) 436 #define TX_VTAG1_OP_MASK GENMASK_ULL(45, 44) 437 #define TX_VTAG1_LID_MASK GENMASK_ULL(42, 40) 438 #define TX_VTAG1_RELPTR_MASK GENMASK_ULL(39, 32) 439 440 /* NPC MCAM reserved entry index per nixlf */ 441 #define NIXLF_UCAST_ENTRY 0 442 #define NIXLF_BCAST_ENTRY 1 443 #define NIXLF_ALLMULTI_ENTRY 2 444 #define NIXLF_PROMISC_ENTRY 3 445 446 struct npc_coalesced_kpu_prfl { 447 #define NPC_SIGN 0x00666f727063706e 448 #define NPC_PRFL_NAME "npc_prfls_array" 449 #define NPC_NAME_LEN 32 450 __le64 signature; /* "npcprof\0" (8 bytes/ASCII characters) */ 451 u8 name[NPC_NAME_LEN]; /* KPU Profile name */ 452 u64 version; /* KPU firmware/profile version */ 453 u8 num_prfl; /* No of NPC profiles. */ 454 u16 prfl_sz[0]; 455 }; 456 457 struct npc_mcam_kex { 458 /* MKEX Profle Header */ 459 u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */ 460 u8 name[MKEX_NAME_LEN]; /* MKEX Profile name */ 461 u64 cpu_model; /* Format as profiled by CPU hardware */ 462 u64 kpu_version; /* KPU firmware/profile version */ 463 u64 reserved; /* Reserved for extension */ 464 465 /* MKEX Profle Data */ 466 u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */ 467 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */ 468 u64 kex_ld_flags[NPC_MAX_LD]; 469 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */ 470 u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD]; 471 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */ 472 u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL]; 473 } __packed; 474 475 struct npc_kpu_fwdata { 476 int entries; 477 /* What follows is: 478 * struct npc_kpu_profile_cam[entries]; 479 * struct npc_kpu_profile_action[entries]; 480 */ 481 u8 data[0]; 482 } __packed; 483 484 struct npc_lt_def { 485 u8 ltype_mask; 486 u8 ltype_match; 487 u8 lid; 488 }; 489 490 struct npc_lt_def_ipsec { 491 u8 ltype_mask; 492 u8 ltype_match; 493 u8 lid; 494 u8 spi_offset; 495 u8 spi_nz; 496 }; 497 498 struct npc_lt_def_apad { 499 u8 ltype_mask; 500 u8 ltype_match; 501 u8 lid; 502 u8 valid; 503 } __packed; 504 505 struct npc_lt_def_color { 506 u8 ltype_mask; 507 u8 ltype_match; 508 u8 lid; 509 u8 noffset; 510 u8 offset; 511 } __packed; 512 513 struct npc_lt_def_et { 514 u8 ltype_mask; 515 u8 ltype_match; 516 u8 lid; 517 u8 valid; 518 u8 offset; 519 } __packed; 520 521 struct npc_lt_def_cfg { 522 struct npc_lt_def rx_ol2; 523 struct npc_lt_def rx_oip4; 524 struct npc_lt_def rx_iip4; 525 struct npc_lt_def rx_oip6; 526 struct npc_lt_def rx_iip6; 527 struct npc_lt_def rx_otcp; 528 struct npc_lt_def rx_itcp; 529 struct npc_lt_def rx_oudp; 530 struct npc_lt_def rx_iudp; 531 struct npc_lt_def rx_osctp; 532 struct npc_lt_def rx_isctp; 533 struct npc_lt_def_ipsec rx_ipsec[2]; 534 struct npc_lt_def pck_ol2; 535 struct npc_lt_def pck_oip4; 536 struct npc_lt_def pck_oip6; 537 struct npc_lt_def pck_iip4; 538 struct npc_lt_def_apad rx_apad0; 539 struct npc_lt_def_apad rx_apad1; 540 struct npc_lt_def_color ovlan; 541 struct npc_lt_def_color ivlan; 542 struct npc_lt_def_color rx_gen0_color; 543 struct npc_lt_def_color rx_gen1_color; 544 struct npc_lt_def_et rx_et[2]; 545 } __packed; 546 547 /* Loadable KPU profile firmware data */ 548 struct npc_kpu_profile_fwdata { 549 #define KPU_SIGN 0x00666f727075706b 550 #define KPU_NAME_LEN 32 551 /** Maximum number of custom KPU entries supported by the built-in profile. */ 552 #define KPU_MAX_CST_ENT 2 553 /* KPU Profle Header */ 554 __le64 signature; /* "kpuprof\0" (8 bytes/ASCII characters) */ 555 u8 name[KPU_NAME_LEN]; /* KPU Profile name */ 556 __le64 version; /* KPU profile version */ 557 u8 kpus; 558 u8 reserved[7]; 559 560 /* Default MKEX profile to be used with this KPU profile. May be 561 * overridden with mkex_profile module parameter. Format is same as for 562 * the MKEX profile to streamline processing. 563 */ 564 struct npc_mcam_kex mkex; 565 /* LTYPE values for specific HW offloaded protocols. */ 566 struct npc_lt_def_cfg lt_def; 567 /* Dynamically sized data: 568 * Custom KPU CAM and ACTION configuration entries. 569 * struct npc_kpu_fwdata kpu[kpus]; 570 */ 571 u8 data[0]; 572 } __packed; 573 574 struct rvu_npc_mcam_rule { 575 struct flow_msg packet; 576 struct flow_msg mask; 577 u8 intf; 578 union { 579 struct nix_tx_action tx_action; 580 struct nix_rx_action rx_action; 581 }; 582 u64 vtag_action; 583 struct list_head list; 584 u64 features; 585 u16 owner; 586 u16 entry; 587 u16 cntr; 588 bool has_cntr; 589 u8 default_rule; 590 bool enable; 591 bool vfvlan_cfg; 592 }; 593 594 #endif /* NPC_H */ 595
