1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
3 
4 /*
5  * nfp_net_ctrl.h
6  * Netronome network device driver: Control BAR layout
7  * Authors: Jakub Kicinski <jakub.kicinski@netronome.com>
8  *          Jason McMullan <jason.mcmullan@netronome.com>
9  *          Rolf Neugebauer <rolf.neugebauer@netronome.com>
10  *          Brad Petrus <brad.petrus@netronome.com>
11  */
12 
13 #ifndef _NFP_NET_CTRL_H_
14 #define _NFP_NET_CTRL_H_
15 
16 #include <linux/types.h>
17 
18 /**
19  * Configuration BAR size.
20  *
21  * The configuration BAR is 8K in size, but due to
22  * THB-350, 32k needs to be reserved.
23  */
24 #define NFP_NET_CFG_BAR_SZ		(32 * 1024)
25 
26 /**
27  * Offset in Freelist buffer where packet starts on RX
28  */
29 #define NFP_NET_RX_OFFSET		32
30 
31 /**
32  * LSO parameters
33  * %NFP_NET_LSO_MAX_HDR_SZ:	Maximum header size supported for LSO frames
34  * %NFP_NET_LSO_MAX_SEGS:	Maximum number of segments LSO frame can produce
35  */
36 #define NFP_NET_LSO_MAX_HDR_SZ		255
37 #define NFP_NET_LSO_MAX_SEGS		64
38 
39 /**
40  * Prepend field types
41  */
42 #define NFP_NET_META_FIELD_SIZE		4
43 #define NFP_NET_META_HASH		1 /* next field carries hash type */
44 #define NFP_NET_META_MARK		2
45 #define NFP_NET_META_PORTID		5
46 #define NFP_NET_META_CSUM		6 /* checksum complete type */
47 #define NFP_NET_META_CONN_HANDLE	7
48 
49 #define NFP_META_PORT_ID_CTRL		~0U
50 
51 /**
52  * Hash type pre-pended when a RSS hash was computed
53  */
54 #define NFP_NET_RSS_NONE		0
55 #define NFP_NET_RSS_IPV4		1
56 #define NFP_NET_RSS_IPV6		2
57 #define NFP_NET_RSS_IPV6_EX		3
58 #define NFP_NET_RSS_IPV4_TCP		4
59 #define NFP_NET_RSS_IPV6_TCP		5
60 #define NFP_NET_RSS_IPV6_EX_TCP		6
61 #define NFP_NET_RSS_IPV4_UDP		7
62 #define NFP_NET_RSS_IPV6_UDP		8
63 #define NFP_NET_RSS_IPV6_EX_UDP		9
64 
65 /**
66  * Ring counts
67  * %NFP_NET_TXR_MAX:	     Maximum number of TX rings
68  * %NFP_NET_RXR_MAX:	     Maximum number of RX rings
69  */
70 #define NFP_NET_TXR_MAX			64
71 #define NFP_NET_RXR_MAX			64
72 
73 /**
74  * Read/Write config words (0x0000 - 0x002c)
75  * %NFP_NET_CFG_CTRL:	     Global control
76  * %NFP_NET_CFG_UPDATE:      Indicate which fields are updated
77  * %NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings
78  * %NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings
79  * %NFP_NET_CFG_MTU:	     Set MTU size
80  * %NFP_NET_CFG_FLBUFSZ:     Set freelist buffer size (must be larger than MTU)
81  * %NFP_NET_CFG_EXN:	     MSI-X table entry for exceptions
82  * %NFP_NET_CFG_LSC:	     MSI-X table entry for link state changes
83  * %NFP_NET_CFG_MACADDR:     MAC address
84  *
85  * TODO:
86  * - define Error details in UPDATE
87  */
88 #define NFP_NET_CFG_CTRL		0x0000
89 #define   NFP_NET_CFG_CTRL_ENABLE	  (0x1 <<  0) /* Global enable */
90 #define   NFP_NET_CFG_CTRL_PROMISC	  (0x1 <<  1) /* Enable Promisc mode */
91 #define   NFP_NET_CFG_CTRL_L2BC		  (0x1 <<  2) /* Allow L2 Broadcast */
92 #define   NFP_NET_CFG_CTRL_L2MC		  (0x1 <<  3) /* Allow L2 Multicast */
93 #define   NFP_NET_CFG_CTRL_RXCSUM	  (0x1 <<  4) /* Enable RX Checksum */
94 #define   NFP_NET_CFG_CTRL_TXCSUM	  (0x1 <<  5) /* Enable TX Checksum */
95 #define   NFP_NET_CFG_CTRL_RXVLAN	  (0x1 <<  6) /* Enable VLAN strip */
96 #define   NFP_NET_CFG_CTRL_TXVLAN	  (0x1 <<  7) /* Enable VLAN insert */
97 #define   NFP_NET_CFG_CTRL_SCATTER	  (0x1 <<  8) /* Scatter DMA */
98 #define   NFP_NET_CFG_CTRL_GATHER	  (0x1 <<  9) /* Gather DMA */
99 #define   NFP_NET_CFG_CTRL_LSO		  (0x1 << 10) /* LSO/TSO (version 1) */
100 #define   NFP_NET_CFG_CTRL_CTAG_FILTER	  (0x1 << 11) /* VLAN CTAG filtering */
101 #define   NFP_NET_CFG_CTRL_CMSG_DATA	  (0x1 << 12) /* RX cmsgs on data Qs */
102 #define   NFP_NET_CFG_CTRL_RINGCFG	  (0x1 << 16) /* Ring runtime changes */
103 #define   NFP_NET_CFG_CTRL_RSS		  (0x1 << 17) /* RSS (version 1) */
104 #define   NFP_NET_CFG_CTRL_IRQMOD	  (0x1 << 18) /* Interrupt moderation */
105 #define   NFP_NET_CFG_CTRL_RINGPRIO	  (0x1 << 19) /* Ring priorities */
106 #define   NFP_NET_CFG_CTRL_MSIXAUTO	  (0x1 << 20) /* MSI-X auto-masking */
107 #define   NFP_NET_CFG_CTRL_TXRWB	  (0x1 << 21) /* Write-back of TX ring*/
108 #define   NFP_NET_CFG_CTRL_VXLAN	  (0x1 << 24) /* VXLAN tunnel support */
109 #define   NFP_NET_CFG_CTRL_NVGRE	  (0x1 << 25) /* NVGRE tunnel support */
110 #define   NFP_NET_CFG_CTRL_BPF		  (0x1 << 27) /* BPF offload capable */
111 #define   NFP_NET_CFG_CTRL_LSO2		  (0x1 << 28) /* LSO/TSO (version 2) */
112 #define   NFP_NET_CFG_CTRL_RSS2		  (0x1 << 29) /* RSS (version 2) */
113 #define   NFP_NET_CFG_CTRL_CSUM_COMPLETE  (0x1 << 30) /* Checksum complete */
114 #define   NFP_NET_CFG_CTRL_LIVE_ADDR	  (0x1 << 31) /* live MAC addr change */
115 
116 #define NFP_NET_CFG_CTRL_LSO_ANY	(NFP_NET_CFG_CTRL_LSO | \
117 					 NFP_NET_CFG_CTRL_LSO2)
118 #define NFP_NET_CFG_CTRL_RSS_ANY	(NFP_NET_CFG_CTRL_RSS | \
119 					 NFP_NET_CFG_CTRL_RSS2)
120 #define NFP_NET_CFG_CTRL_RXCSUM_ANY	(NFP_NET_CFG_CTRL_RXCSUM | \
121 					 NFP_NET_CFG_CTRL_CSUM_COMPLETE)
122 #define NFP_NET_CFG_CTRL_CHAIN_META	(NFP_NET_CFG_CTRL_RSS2 | \
123 					 NFP_NET_CFG_CTRL_CSUM_COMPLETE)
124 
125 #define NFP_NET_CFG_UPDATE		0x0004
126 #define   NFP_NET_CFG_UPDATE_GEN	  (0x1 <<  0) /* General update */
127 #define   NFP_NET_CFG_UPDATE_RING	  (0x1 <<  1) /* Ring config change */
128 #define   NFP_NET_CFG_UPDATE_RSS	  (0x1 <<  2) /* RSS config change */
129 #define   NFP_NET_CFG_UPDATE_TXRPRIO	  (0x1 <<  3) /* TX Ring prio change */
130 #define   NFP_NET_CFG_UPDATE_RXRPRIO	  (0x1 <<  4) /* RX Ring prio change */
131 #define   NFP_NET_CFG_UPDATE_MSIX	  (0x1 <<  5) /* MSI-X change */
132 #define   NFP_NET_CFG_UPDATE_RESET	  (0x1 <<  7) /* Update due to FLR */
133 #define   NFP_NET_CFG_UPDATE_IRQMOD	  (0x1 <<  8) /* IRQ mod change */
134 #define   NFP_NET_CFG_UPDATE_VXLAN	  (0x1 <<  9) /* VXLAN port change */
135 #define   NFP_NET_CFG_UPDATE_BPF	  (0x1 << 10) /* BPF program load */
136 #define   NFP_NET_CFG_UPDATE_MACADDR	  (0x1 << 11) /* MAC address change */
137 #define   NFP_NET_CFG_UPDATE_MBOX	  (0x1 << 12) /* Mailbox update */
138 #define   NFP_NET_CFG_UPDATE_VF		  (0x1 << 13) /* VF settings change */
139 #define   NFP_NET_CFG_UPDATE_CRYPTO	  (0x1 << 14) /* Crypto on/off */
140 #define   NFP_NET_CFG_UPDATE_ERR	  (0x1 << 31) /* A error occurred */
141 #define NFP_NET_CFG_TXRS_ENABLE		0x0008
142 #define NFP_NET_CFG_RXRS_ENABLE		0x0010
143 #define NFP_NET_CFG_MTU			0x0018
144 #define NFP_NET_CFG_FLBUFSZ		0x001c
145 #define NFP_NET_CFG_EXN			0x001f
146 #define NFP_NET_CFG_LSC			0x0020
147 #define NFP_NET_CFG_MACADDR		0x0024
148 
149 /**
150  * Read-only words (0x0030 - 0x0050):
151  * %NFP_NET_CFG_VERSION:     Firmware version number
152  * %NFP_NET_CFG_STS:	     Status
153  * %NFP_NET_CFG_CAP:	     Capabilities (same bits as %NFP_NET_CFG_CTRL)
154  * %NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings
155  * %NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings
156  * %NFP_NET_CFG_MAX_MTU:     Maximum support MTU
157  * %NFP_NET_CFG_START_TXQ:   Start Queue Control Queue to use for TX (PF only)
158  * %NFP_NET_CFG_START_RXQ:   Start Queue Control Queue to use for RX (PF only)
159  *
160  * TODO:
161  * - define more STS bits
162  */
163 #define NFP_NET_CFG_VERSION		0x0030
164 #define   NFP_NET_CFG_VERSION_RESERVED_MASK	(0xff << 24)
165 #define   NFP_NET_CFG_VERSION_CLASS_MASK  (0xff << 16)
166 #define   NFP_NET_CFG_VERSION_CLASS(x)	  (((x) & 0xff) << 16)
167 #define   NFP_NET_CFG_VERSION_CLASS_GENERIC	0
168 #define   NFP_NET_CFG_VERSION_MAJOR_MASK  (0xff <<  8)
169 #define   NFP_NET_CFG_VERSION_MAJOR(x)	  (((x) & 0xff) <<  8)
170 #define   NFP_NET_CFG_VERSION_MINOR_MASK  (0xff <<  0)
171 #define   NFP_NET_CFG_VERSION_MINOR(x)	  (((x) & 0xff) <<  0)
172 #define NFP_NET_CFG_STS			0x0034
173 #define   NFP_NET_CFG_STS_LINK		  (0x1 << 0) /* Link up or down */
174 /* Link rate */
175 #define   NFP_NET_CFG_STS_LINK_RATE_SHIFT 1
176 #define   NFP_NET_CFG_STS_LINK_RATE_MASK  0xF
177 #define   NFP_NET_CFG_STS_LINK_RATE	  \
178 	(NFP_NET_CFG_STS_LINK_RATE_MASK << NFP_NET_CFG_STS_LINK_RATE_SHIFT)
179 #define   NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED   0
180 #define   NFP_NET_CFG_STS_LINK_RATE_UNKNOWN	  1
181 #define   NFP_NET_CFG_STS_LINK_RATE_1G		  2
182 #define   NFP_NET_CFG_STS_LINK_RATE_10G		  3
183 #define   NFP_NET_CFG_STS_LINK_RATE_25G		  4
184 #define   NFP_NET_CFG_STS_LINK_RATE_40G		  5
185 #define   NFP_NET_CFG_STS_LINK_RATE_50G		  6
186 #define   NFP_NET_CFG_STS_LINK_RATE_100G	  7
187 #define NFP_NET_CFG_CAP			0x0038
188 #define NFP_NET_CFG_MAX_TXRINGS		0x003c
189 #define NFP_NET_CFG_MAX_RXRINGS		0x0040
190 #define NFP_NET_CFG_MAX_MTU		0x0044
191 /* Next two words are being used by VFs for solving THB350 issue */
192 #define NFP_NET_CFG_START_TXQ		0x0048
193 #define NFP_NET_CFG_START_RXQ		0x004c
194 
195 /**
196  * Prepend configuration
197  */
198 #define NFP_NET_CFG_RX_OFFSET		0x0050
199 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC		0	/* Prepend mode */
200 
201 /**
202  * RSS capabilities
203  * %NFP_NET_CFG_RSS_CAP_HFUNC:	supported hash functions (same bits as
204  *				%NFP_NET_CFG_RSS_HFUNC)
205  */
206 #define NFP_NET_CFG_RSS_CAP		0x0054
207 #define   NFP_NET_CFG_RSS_CAP_HFUNC	  0xff000000
208 
209 /**
210  * TLV area start
211  * %NFP_NET_CFG_TLV_BASE:	start anchor of the TLV area
212  */
213 #define NFP_NET_CFG_TLV_BASE		0x0058
214 
215 /**
216  * VXLAN/UDP encap configuration
217  * %NFP_NET_CFG_VXLAN_PORT:	Base address of table of tunnels' UDP dst ports
218  * %NFP_NET_CFG_VXLAN_SZ:	Size of the UDP port table in bytes
219  */
220 #define NFP_NET_CFG_VXLAN_PORT		0x0060
221 #define NFP_NET_CFG_VXLAN_SZ		  0x0008
222 
223 /**
224  * BPF section
225  * %NFP_NET_CFG_BPF_ABI:	BPF ABI version
226  * %NFP_NET_CFG_BPF_CAP:	BPF capabilities
227  * %NFP_NET_CFG_BPF_MAX_LEN:	Maximum size of JITed BPF code in bytes
228  * %NFP_NET_CFG_BPF_START:	Offset at which BPF will be loaded
229  * %NFP_NET_CFG_BPF_DONE:	Offset to jump to on exit
230  * %NFP_NET_CFG_BPF_STACK_SZ:	Total size of stack area in 64B chunks
231  * %NFP_NET_CFG_BPF_INL_MTU:	Packet data split offset in 64B chunks
232  * %NFP_NET_CFG_BPF_SIZE:	Size of the JITed BPF code in instructions
233  * %NFP_NET_CFG_BPF_ADDR:	DMA address of the buffer with JITed BPF code
234  */
235 #define NFP_NET_CFG_BPF_ABI		0x0080
236 #define NFP_NET_CFG_BPF_CAP		0x0081
237 #define   NFP_NET_BPF_CAP_RELO		(1 << 0) /* seamless reload */
238 #define NFP_NET_CFG_BPF_MAX_LEN		0x0082
239 #define NFP_NET_CFG_BPF_START		0x0084
240 #define NFP_NET_CFG_BPF_DONE		0x0086
241 #define NFP_NET_CFG_BPF_STACK_SZ	0x0088
242 #define NFP_NET_CFG_BPF_INL_MTU		0x0089
243 #define NFP_NET_CFG_BPF_SIZE		0x008e
244 #define NFP_NET_CFG_BPF_ADDR		0x0090
245 #define   NFP_NET_CFG_BPF_CFG_8CTX	(1 << 0) /* 8ctx mode */
246 #define   NFP_NET_CFG_BPF_CFG_MASK	7ULL
247 #define   NFP_NET_CFG_BPF_ADDR_MASK	(~NFP_NET_CFG_BPF_CFG_MASK)
248 
249 /**
250  * 40B reserved for future use (0x0098 - 0x00c0)
251  */
252 #define NFP_NET_CFG_RESERVED		0x0098
253 #define NFP_NET_CFG_RESERVED_SZ		0x0028
254 
255 /**
256  * RSS configuration (0x0100 - 0x01ac):
257  * Used only when NFP_NET_CFG_CTRL_RSS is enabled
258  * %NFP_NET_CFG_RSS_CFG:     RSS configuration word
259  * %NFP_NET_CFG_RSS_KEY:     RSS "secret" key
260  * %NFP_NET_CFG_RSS_ITBL:    RSS indirection table
261  */
262 #define NFP_NET_CFG_RSS_BASE		0x0100
263 #define NFP_NET_CFG_RSS_CTRL		NFP_NET_CFG_RSS_BASE
264 #define   NFP_NET_CFG_RSS_MASK		  (0x7f)
265 #define   NFP_NET_CFG_RSS_MASK_of(_x)	  ((_x) & 0x7f)
266 #define   NFP_NET_CFG_RSS_IPV4		  (1 <<  8) /* RSS for IPv4 */
267 #define   NFP_NET_CFG_RSS_IPV6		  (1 <<  9) /* RSS for IPv6 */
268 #define   NFP_NET_CFG_RSS_IPV4_TCP	  (1 << 10) /* RSS for IPv4/TCP */
269 #define   NFP_NET_CFG_RSS_IPV4_UDP	  (1 << 11) /* RSS for IPv4/UDP */
270 #define   NFP_NET_CFG_RSS_IPV6_TCP	  (1 << 12) /* RSS for IPv6/TCP */
271 #define   NFP_NET_CFG_RSS_IPV6_UDP	  (1 << 13) /* RSS for IPv6/UDP */
272 #define   NFP_NET_CFG_RSS_HFUNC		  0xff000000
273 #define   NFP_NET_CFG_RSS_TOEPLITZ	  (1 << 24) /* Use Toeplitz hash */
274 #define   NFP_NET_CFG_RSS_XOR		  (1 << 25) /* Use XOR as hash */
275 #define   NFP_NET_CFG_RSS_CRC32		  (1 << 26) /* Use CRC32 as hash */
276 #define   NFP_NET_CFG_RSS_HFUNCS	  3
277 #define NFP_NET_CFG_RSS_KEY		(NFP_NET_CFG_RSS_BASE + 0x4)
278 #define NFP_NET_CFG_RSS_KEY_SZ		0x28
279 #define NFP_NET_CFG_RSS_ITBL		(NFP_NET_CFG_RSS_BASE + 0x4 + \
280 					 NFP_NET_CFG_RSS_KEY_SZ)
281 #define NFP_NET_CFG_RSS_ITBL_SZ		0x80
282 
283 /**
284  * TX ring configuration (0x200 - 0x800)
285  * %NFP_NET_CFG_TXR_BASE:    Base offset for TX ring configuration
286  * %NFP_NET_CFG_TXR_ADDR:    Per TX ring DMA address (8B entries)
287  * %NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)
288  * %NFP_NET_CFG_TXR_SZ:      Per TX ring ring size (1B entries)
289  * %NFP_NET_CFG_TXR_VEC:     Per TX ring MSI-X table entry (1B entries)
290  * %NFP_NET_CFG_TXR_PRIO:    Per TX ring priority (1B entries)
291  * %NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet
292  */
293 #define NFP_NET_CFG_TXR_BASE		0x0200
294 #define NFP_NET_CFG_TXR_ADDR(_x)	(NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))
295 #define NFP_NET_CFG_TXR_WB_ADDR(_x)	(NFP_NET_CFG_TXR_BASE + 0x200 + \
296 					 ((_x) * 0x8))
297 #define NFP_NET_CFG_TXR_SZ(_x)		(NFP_NET_CFG_TXR_BASE + 0x400 + (_x))
298 #define NFP_NET_CFG_TXR_VEC(_x)		(NFP_NET_CFG_TXR_BASE + 0x440 + (_x))
299 #define NFP_NET_CFG_TXR_PRIO(_x)	(NFP_NET_CFG_TXR_BASE + 0x480 + (_x))
300 #define NFP_NET_CFG_TXR_IRQ_MOD(_x)	(NFP_NET_CFG_TXR_BASE + 0x500 + \
301 					 ((_x) * 0x4))
302 
303 /**
304  * RX ring configuration (0x0800 - 0x0c00)
305  * %NFP_NET_CFG_RXR_BASE:    Base offset for RX ring configuration
306  * %NFP_NET_CFG_RXR_ADDR:    Per RX ring DMA address (8B entries)
307  * %NFP_NET_CFG_RXR_SZ:      Per RX ring ring size (1B entries)
308  * %NFP_NET_CFG_RXR_VEC:     Per RX ring MSI-X table entry (1B entries)
309  * %NFP_NET_CFG_RXR_PRIO:    Per RX ring priority (1B entries)
310  * %NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries)
311  */
312 #define NFP_NET_CFG_RXR_BASE		0x0800
313 #define NFP_NET_CFG_RXR_ADDR(_x)	(NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))
314 #define NFP_NET_CFG_RXR_SZ(_x)		(NFP_NET_CFG_RXR_BASE + 0x200 + (_x))
315 #define NFP_NET_CFG_RXR_VEC(_x)		(NFP_NET_CFG_RXR_BASE + 0x240 + (_x))
316 #define NFP_NET_CFG_RXR_PRIO(_x)	(NFP_NET_CFG_RXR_BASE + 0x280 + (_x))
317 #define NFP_NET_CFG_RXR_IRQ_MOD(_x)	(NFP_NET_CFG_RXR_BASE + 0x300 + \
318 					 ((_x) * 0x4))
319 
320 /**
321  * Interrupt Control/Cause registers (0x0c00 - 0x0d00)
322  * These registers are only used when MSI-X auto-masking is not
323  * enabled (%NFP_NET_CFG_CTRL_MSIXAUTO not set).  The array is index
324  * by MSI-X entry and are 1B in size.  If an entry is zero, the
325  * corresponding entry is enabled.  If the FW generates an interrupt,
326  * it writes a cause into the corresponding field.  This also masks
327  * the MSI-X entry and the host driver must clear the register to
328  * re-enable the interrupt.
329  */
330 #define NFP_NET_CFG_ICR_BASE		0x0c00
331 #define NFP_NET_CFG_ICR(_x)		(NFP_NET_CFG_ICR_BASE + (_x))
332 #define   NFP_NET_CFG_ICR_UNMASKED	0x0
333 #define   NFP_NET_CFG_ICR_RXTX		0x1
334 #define   NFP_NET_CFG_ICR_LSC		0x2
335 
336 /**
337  * General device stats (0x0d00 - 0x0d90)
338  * all counters are 64bit.
339  */
340 #define NFP_NET_CFG_STATS_BASE		0x0d00
341 #define NFP_NET_CFG_STATS_RX_DISCARDS	(NFP_NET_CFG_STATS_BASE + 0x00)
342 #define NFP_NET_CFG_STATS_RX_ERRORS	(NFP_NET_CFG_STATS_BASE + 0x08)
343 #define NFP_NET_CFG_STATS_RX_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x10)
344 #define NFP_NET_CFG_STATS_RX_UC_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x18)
345 #define NFP_NET_CFG_STATS_RX_MC_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x20)
346 #define NFP_NET_CFG_STATS_RX_BC_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x28)
347 #define NFP_NET_CFG_STATS_RX_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x30)
348 #define NFP_NET_CFG_STATS_RX_MC_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x38)
349 #define NFP_NET_CFG_STATS_RX_BC_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x40)
350 
351 #define NFP_NET_CFG_STATS_TX_DISCARDS	(NFP_NET_CFG_STATS_BASE + 0x48)
352 #define NFP_NET_CFG_STATS_TX_ERRORS	(NFP_NET_CFG_STATS_BASE + 0x50)
353 #define NFP_NET_CFG_STATS_TX_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x58)
354 #define NFP_NET_CFG_STATS_TX_UC_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x60)
355 #define NFP_NET_CFG_STATS_TX_MC_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x68)
356 #define NFP_NET_CFG_STATS_TX_BC_OCTETS	(NFP_NET_CFG_STATS_BASE + 0x70)
357 #define NFP_NET_CFG_STATS_TX_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x78)
358 #define NFP_NET_CFG_STATS_TX_MC_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x80)
359 #define NFP_NET_CFG_STATS_TX_BC_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x88)
360 
361 #define NFP_NET_CFG_STATS_APP0_FRAMES	(NFP_NET_CFG_STATS_BASE + 0x90)
362 #define NFP_NET_CFG_STATS_APP0_BYTES	(NFP_NET_CFG_STATS_BASE + 0x98)
363 #define NFP_NET_CFG_STATS_APP1_FRAMES	(NFP_NET_CFG_STATS_BASE + 0xa0)
364 #define NFP_NET_CFG_STATS_APP1_BYTES	(NFP_NET_CFG_STATS_BASE + 0xa8)
365 #define NFP_NET_CFG_STATS_APP2_FRAMES	(NFP_NET_CFG_STATS_BASE + 0xb0)
366 #define NFP_NET_CFG_STATS_APP2_BYTES	(NFP_NET_CFG_STATS_BASE + 0xb8)
367 #define NFP_NET_CFG_STATS_APP3_FRAMES	(NFP_NET_CFG_STATS_BASE + 0xc0)
368 #define NFP_NET_CFG_STATS_APP3_BYTES	(NFP_NET_CFG_STATS_BASE + 0xc8)
369 
370 /**
371  * Per ring stats (0x1000 - 0x1800)
372  * options, 64bit per entry
373  * %NFP_NET_CFG_TXR_STATS:   TX ring statistics (Packet and Byte count)
374  * %NFP_NET_CFG_RXR_STATS:   RX ring statistics (Packet and Byte count)
375  */
376 #define NFP_NET_CFG_TXR_STATS_BASE	0x1000
377 #define NFP_NET_CFG_TXR_STATS(_x)	(NFP_NET_CFG_TXR_STATS_BASE + \
378 					 ((_x) * 0x10))
379 #define NFP_NET_CFG_RXR_STATS_BASE	0x1400
380 #define NFP_NET_CFG_RXR_STATS(_x)	(NFP_NET_CFG_RXR_STATS_BASE + \
381 					 ((_x) * 0x10))
382 
383 /**
384  * General use mailbox area (0x1800 - 0x19ff)
385  * 4B used for update command and 4B return code
386  * followed by a max of 504B of variable length value
387  */
388 #define NFP_NET_CFG_MBOX_BASE		0x1800
389 #define NFP_NET_CFG_MBOX_VAL_MAX_SZ	0x1F8
390 
391 #define NFP_NET_CFG_MBOX_SIMPLE_CMD	0x0
392 #define NFP_NET_CFG_MBOX_SIMPLE_RET	0x4
393 #define NFP_NET_CFG_MBOX_SIMPLE_VAL	0x8
394 
395 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_ADD 1
396 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_KILL 2
397 
398 #define NFP_NET_CFG_MBOX_CMD_PCI_DSCP_PRIOMAP_SET	5
399 #define NFP_NET_CFG_MBOX_CMD_TLV_CMSG			6
400 
401 /**
402  * VLAN filtering using general use mailbox
403  * %NFP_NET_CFG_VLAN_FILTER:		Base address of VLAN filter mailbox
404  * %NFP_NET_CFG_VLAN_FILTER_VID:	VLAN ID to filter
405  * %NFP_NET_CFG_VLAN_FILTER_PROTO:	VLAN proto to filter
406  * %NFP_NET_CFG_VXLAN_SZ:		Size of the VLAN filter mailbox in bytes
407  */
408 #define NFP_NET_CFG_VLAN_FILTER		NFP_NET_CFG_MBOX_SIMPLE_VAL
409 #define  NFP_NET_CFG_VLAN_FILTER_VID	NFP_NET_CFG_VLAN_FILTER
410 #define  NFP_NET_CFG_VLAN_FILTER_PROTO	 (NFP_NET_CFG_VLAN_FILTER + 2)
411 #define NFP_NET_CFG_VLAN_FILTER_SZ	 0x0004
412 
413 /**
414  * TLV capabilities
415  * %NFP_NET_CFG_TLV_TYPE:	Offset of type within the TLV
416  * %NFP_NET_CFG_TLV_TYPE_REQUIRED: Driver must be able to parse the TLV
417  * %NFP_NET_CFG_TLV_LENGTH:	Offset of length within the TLV
418  * %NFP_NET_CFG_TLV_LENGTH_INC: TLV length increments
419  * %NFP_NET_CFG_TLV_VALUE:	Offset of value with the TLV
420  *
421  * List of simple TLV structures, first one starts at %NFP_NET_CFG_TLV_BASE.
422  * Last structure must be of type %NFP_NET_CFG_TLV_TYPE_END.  Presence of TLVs
423  * is indicated by %NFP_NET_CFG_TLV_BASE being non-zero.  TLV structures may
424  * fill the entire remainder of the BAR or be shorter.  FW must make sure TLVs
425  * don't conflict with other features which allocate space beyond
426  * %NFP_NET_CFG_TLV_BASE.  %NFP_NET_CFG_TLV_TYPE_RESERVED should be used to wrap
427  * space used by such features.
428  * Note that the 4 byte TLV header is not counted in %NFP_NET_CFG_TLV_LENGTH.
429  */
430 #define NFP_NET_CFG_TLV_TYPE		0x00
431 #define   NFP_NET_CFG_TLV_TYPE_REQUIRED   0x8000
432 #define NFP_NET_CFG_TLV_LENGTH		0x02
433 #define   NFP_NET_CFG_TLV_LENGTH_INC	  4
434 #define NFP_NET_CFG_TLV_VALUE		0x04
435 
436 #define NFP_NET_CFG_TLV_HEADER_REQUIRED 0x80000000
437 #define NFP_NET_CFG_TLV_HEADER_TYPE	0x7fff0000
438 #define NFP_NET_CFG_TLV_HEADER_LENGTH	0x0000ffff
439 
440 /**
441  * Capability TLV types
442  *
443  * %NFP_NET_CFG_TLV_TYPE_UNKNOWN:
444  * Special TLV type to catch bugs, should never be encountered.  Drivers should
445  * treat encountering this type as error and refuse to probe.
446  *
447  * %NFP_NET_CFG_TLV_TYPE_RESERVED:
448  * Reserved space, may contain legacy fixed-offset fields, or be used for
449  * padding.  The use of this type should be otherwise avoided.
450  *
451  * %NFP_NET_CFG_TLV_TYPE_END:
452  * Empty, end of TLV list.  Must be the last TLV.  Drivers will stop processing
453  * further TLVs when encountered.
454  *
455  * %NFP_NET_CFG_TLV_TYPE_ME_FREQ:
456  * Single word, ME frequency in MHz as used in calculation for
457  * %NFP_NET_CFG_RXR_IRQ_MOD and %NFP_NET_CFG_TXR_IRQ_MOD.
458  *
459  * %NFP_NET_CFG_TLV_TYPE_MBOX:
460  * Variable, mailbox area.  Overwrites the default location which is
461  * %NFP_NET_CFG_MBOX_BASE and length %NFP_NET_CFG_MBOX_VAL_MAX_SZ.
462  *
463  * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0:
464  * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1:
465  * Variable, experimental IDs.  IDs designated for internal development and
466  * experiments before a stable TLV ID has been allocated to a feature.  Should
467  * never be present in production firmware.
468  *
469  * %NFP_NET_CFG_TLV_TYPE_REPR_CAP:
470  * Single word, equivalent of %NFP_NET_CFG_CAP for representors, features which
471  * can be used on representors.
472  *
473  * %NFP_NET_CFG_TLV_TYPE_MBOX_CMSG_TYPES:
474  * Variable, bitmap of control message types supported by the mailbox handler.
475  * Bit 0 corresponds to message type 0, bit 1 to 1, etc.  Control messages are
476  * encapsulated into simple TLVs, with an end TLV and written to the Mailbox.
477  *
478  * %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS:
479  * 8 words, bitmaps of supported and enabled crypto operations.
480  * First 16B (4 words) contains a bitmap of supported crypto operations,
481  * and next 16B contain the enabled operations.
482  */
483 #define NFP_NET_CFG_TLV_TYPE_UNKNOWN		0
484 #define NFP_NET_CFG_TLV_TYPE_RESERVED		1
485 #define NFP_NET_CFG_TLV_TYPE_END		2
486 #define NFP_NET_CFG_TLV_TYPE_ME_FREQ		3
487 #define NFP_NET_CFG_TLV_TYPE_MBOX		4
488 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0	5
489 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1	6
490 #define NFP_NET_CFG_TLV_TYPE_REPR_CAP		7
491 #define NFP_NET_CFG_TLV_TYPE_MBOX_CMSG_TYPES	10
492 #define NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS		11 /* see crypto/fw.h */
493 
494 struct device;
495 
496 /**
497  * struct nfp_net_tlv_caps - parsed control BAR TLV capabilities
498  * @me_freq_mhz:	ME clock_freq (MHz)
499  * @mbox_off:		vNIC mailbox area offset
500  * @mbox_len:		vNIC mailbox area length
501  * @repr_cap:		capabilities for representors
502  * @mbox_cmsg_types:	cmsgs which can be passed through the mailbox
503  * @crypto_ops:		supported crypto operations
504  * @crypto_enable_off:	offset of crypto ops enable region
505  */
506 struct nfp_net_tlv_caps {
507 	u32 me_freq_mhz;
508 	unsigned int mbox_off;
509 	unsigned int mbox_len;
510 	u32 repr_cap;
511 	u32 mbox_cmsg_types;
512 	u32 crypto_ops;
513 	unsigned int crypto_enable_off;
514 };
515 
516 int nfp_net_tlv_caps_parse(struct device *dev, u8 __iomem *ctrl_mem,
517 			   struct nfp_net_tlv_caps *caps);
518 #endif /* _NFP_NET_CTRL_H_ */
519