1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * 4 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450 5 * 6 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz> 7 * 8 */ 9 #ifndef __MATROXFB_H__ 10 #define __MATROXFB_H__ 11 12 /* general, but fairly heavy, debugging */ 13 #undef MATROXFB_DEBUG 14 15 /* heavy debugging: */ 16 /* -- logs putc[s], so every time a char is displayed, it's logged */ 17 #undef MATROXFB_DEBUG_HEAVY 18 19 /* This one _could_ cause infinite loops */ 20 /* It _does_ cause lots and lots of messages during idle loops */ 21 #undef MATROXFB_DEBUG_LOOP 22 23 /* Debug register calls, too? */ 24 #undef MATROXFB_DEBUG_REG 25 26 /* Guard accelerator accesses with spin_lock_irqsave... */ 27 #undef MATROXFB_USE_SPINLOCKS 28 29 #include <linux/module.h> 30 #include <linux/kernel.h> 31 #include <linux/errno.h> 32 #include <linux/string.h> 33 #include <linux/mm.h> 34 #include <linux/slab.h> 35 #include <linux/delay.h> 36 #include <linux/fb.h> 37 #include <linux/console.h> 38 #include <linux/selection.h> 39 #include <linux/ioport.h> 40 #include <linux/init.h> 41 #include <linux/timer.h> 42 #include <linux/pci.h> 43 #include <linux/spinlock.h> 44 #include <linux/kd.h> 45 46 #include <asm/io.h> 47 #include <asm/unaligned.h> 48 49 #if defined(CONFIG_PPC_PMAC) 50 #include <asm/prom.h> 51 #include "../macmodes.h" 52 #endif 53 54 #ifdef MATROXFB_DEBUG 55 56 #define DEBUG 57 #define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x)); 58 59 #ifdef MATROXFB_DEBUG_HEAVY 60 #define DBG_HEAVY(x) DBG(x) 61 #else /* MATROXFB_DEBUG_HEAVY */ 62 #define DBG_HEAVY(x) /* DBG_HEAVY */ 63 #endif /* MATROXFB_DEBUG_HEAVY */ 64 65 #ifdef MATROXFB_DEBUG_LOOP 66 #define DBG_LOOP(x) DBG(x) 67 #else /* MATROXFB_DEBUG_LOOP */ 68 #define DBG_LOOP(x) /* DBG_LOOP */ 69 #endif /* MATROXFB_DEBUG_LOOP */ 70 71 #ifdef MATROXFB_DEBUG_REG 72 #define DBG_REG(x) DBG(x) 73 #else /* MATROXFB_DEBUG_REG */ 74 #define DBG_REG(x) /* DBG_REG */ 75 #endif /* MATROXFB_DEBUG_REG */ 76 77 #else /* MATROXFB_DEBUG */ 78 79 #define DBG(x) /* DBG */ 80 #define DBG_HEAVY(x) /* DBG_HEAVY */ 81 #define DBG_REG(x) /* DBG_REG */ 82 #define DBG_LOOP(x) /* DBG_LOOP */ 83 84 #endif /* MATROXFB_DEBUG */ 85 86 #ifdef DEBUG 87 #define dprintk(X...) printk(X) 88 #else 89 #define dprintk(X...) no_printk(X) 90 #endif 91 92 #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 93 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A 94 #endif 95 #ifndef PCI_SS_VENDOR_ID_MATROX 96 #define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX 97 #endif 98 99 #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 100 #define PCI_SS_ID_MATROX_GENERIC 0xFF00 101 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01 102 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02 103 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03 104 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04 105 #define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05 106 #define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001 107 #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179 108 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */ 109 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */ 110 #endif 111 112 #define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR 113 #define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR 114 #define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR 115 116 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) 117 118 /* G-series and Mystique have (almost) same DAC */ 119 #undef NEED_DAC1064 120 #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G) 121 #define NEED_DAC1064 1 122 #endif 123 124 typedef struct { 125 void __iomem* vaddr; 126 } vaddr_t; 127 mga_readb(vaddr_t va,unsigned int offs)128 static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) { 129 return readb(va.vaddr + offs); 130 } 131 mga_writeb(vaddr_t va,unsigned int offs,u_int8_t value)132 static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) { 133 writeb(value, va.vaddr + offs); 134 } 135 mga_writew(vaddr_t va,unsigned int offs,u_int16_t value)136 static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) { 137 writew(value, va.vaddr + offs); 138 } 139 mga_readl(vaddr_t va,unsigned int offs)140 static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) { 141 return readl(va.vaddr + offs); 142 } 143 mga_writel(vaddr_t va,unsigned int offs,u_int32_t value)144 static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) { 145 writel(value, va.vaddr + offs); 146 } 147 mga_memcpy_toio(vaddr_t va,const void * src,int len)148 static inline void mga_memcpy_toio(vaddr_t va, const void* src, int len) { 149 #if defined(__alpha__) || defined(__i386__) || defined(__x86_64__) 150 /* 151 * iowrite32_rep works for us if: 152 * (1) Copies data as 32bit quantities, not byte after byte, 153 * (2) Performs LE ordered stores, and 154 * (3) It copes with unaligned source (destination is guaranteed to be page 155 * aligned and length is guaranteed to be multiple of 4). 156 */ 157 iowrite32_rep(va.vaddr, src, len >> 2); 158 #else 159 u_int32_t __iomem* addr = va.vaddr; 160 161 if ((unsigned long)src & 3) { 162 while (len >= 4) { 163 fb_writel(get_unaligned((u32 *)src), addr); 164 addr++; 165 len -= 4; 166 src += 4; 167 } 168 } else { 169 while (len >= 4) { 170 fb_writel(*(u32 *)src, addr); 171 addr++; 172 len -= 4; 173 src += 4; 174 } 175 } 176 #endif 177 } 178 vaddr_add(vaddr_t * va,unsigned long offs)179 static inline void vaddr_add(vaddr_t* va, unsigned long offs) { 180 va->vaddr += offs; 181 } 182 vaddr_va(vaddr_t va)183 static inline void __iomem* vaddr_va(vaddr_t va) { 184 return va.vaddr; 185 } 186 187 struct my_timming { 188 unsigned int pixclock; 189 int mnp; 190 unsigned int crtc; 191 unsigned int HDisplay; 192 unsigned int HSyncStart; 193 unsigned int HSyncEnd; 194 unsigned int HTotal; 195 unsigned int VDisplay; 196 unsigned int VSyncStart; 197 unsigned int VSyncEnd; 198 unsigned int VTotal; 199 unsigned int sync; 200 int dblscan; 201 int interlaced; 202 unsigned int delay; /* CRTC delay */ 203 }; 204 205 enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL }; 206 207 struct matrox_pll_cache { 208 unsigned int valid; 209 struct { 210 unsigned int mnp_key; 211 unsigned int mnp_value; 212 } data[4]; 213 }; 214 215 struct matrox_pll_limits { 216 unsigned int vcomin; 217 unsigned int vcomax; 218 }; 219 220 struct matrox_pll_features { 221 unsigned int vco_freq_min; 222 unsigned int ref_freq; 223 unsigned int feed_div_min; 224 unsigned int feed_div_max; 225 unsigned int in_div_min; 226 unsigned int in_div_max; 227 unsigned int post_shift_max; 228 }; 229 230 struct matroxfb_par 231 { 232 unsigned int final_bppShift; 233 unsigned int cmap_len; 234 struct { 235 unsigned int bytes; 236 unsigned int pixels; 237 unsigned int chunks; 238 } ydstorg; 239 }; 240 241 struct matrox_fb_info; 242 243 struct matrox_DAC1064_features { 244 u_int8_t xvrefctrl; 245 u_int8_t xmiscctrl; 246 }; 247 248 /* current hardware status */ 249 struct mavenregs { 250 u_int8_t regs[256]; 251 int mode; 252 int vlines; 253 int xtal; 254 int fv; 255 256 u_int16_t htotal; 257 u_int16_t hcorr; 258 }; 259 260 struct matrox_crtc2 { 261 u_int32_t ctl; 262 }; 263 264 struct matrox_hw_state { 265 u_int32_t MXoptionReg; 266 unsigned char DACclk[6]; 267 unsigned char DACreg[80]; 268 unsigned char MiscOutReg; 269 unsigned char DACpal[768]; 270 unsigned char CRTC[25]; 271 unsigned char CRTCEXT[9]; 272 unsigned char SEQ[5]; 273 /* unused for MGA mode, but who knows... */ 274 unsigned char GCTL[9]; 275 /* unused for MGA mode, but who knows... */ 276 unsigned char ATTR[21]; 277 278 /* TVOut only */ 279 struct mavenregs maven; 280 281 struct matrox_crtc2 crtc2; 282 }; 283 284 struct matrox_accel_data { 285 #ifdef CONFIG_FB_MATROX_MILLENIUM 286 unsigned char ramdac_rev; 287 #endif 288 u_int32_t m_dwg_rect; 289 u_int32_t m_opmode; 290 u_int32_t m_access; 291 u_int32_t m_pitch; 292 }; 293 294 struct v4l2_queryctrl; 295 struct v4l2_control; 296 297 struct matrox_altout { 298 const char *name; 299 int (*compute)(void* altout_dev, struct my_timming* input); 300 int (*program)(void* altout_dev); 301 int (*start)(void* altout_dev); 302 int (*verifymode)(void* altout_dev, u_int32_t mode); 303 int (*getqueryctrl)(void* altout_dev, 304 struct v4l2_queryctrl* ctrl); 305 int (*getctrl)(void* altout_dev, 306 struct v4l2_control* ctrl); 307 int (*setctrl)(void* altout_dev, 308 struct v4l2_control* ctrl); 309 }; 310 311 #define MATROXFB_SRC_NONE 0 312 #define MATROXFB_SRC_CRTC1 1 313 #define MATROXFB_SRC_CRTC2 2 314 315 enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 }; 316 317 struct matrox_bios { 318 unsigned int bios_valid : 1; 319 unsigned int pins_len; 320 unsigned char pins[128]; 321 struct { 322 unsigned char vMaj, vMin, vRev; 323 } version; 324 struct { 325 unsigned char state, tvout; 326 } output; 327 }; 328 329 struct matrox_switch; 330 struct matroxfb_driver; 331 struct matroxfb_dh_fb_info; 332 333 struct matrox_vsync { 334 wait_queue_head_t wait; 335 unsigned int cnt; 336 }; 337 338 struct matrox_fb_info { 339 struct fb_info fbcon; 340 341 struct list_head next_fb; 342 343 int dead; 344 int initialized; 345 unsigned int usecount; 346 347 unsigned int userusecount; 348 unsigned long irq_flags; 349 350 struct matroxfb_par curr; 351 struct matrox_hw_state hw; 352 353 struct matrox_accel_data accel; 354 355 struct pci_dev* pcidev; 356 357 struct { 358 struct matrox_vsync vsync; 359 unsigned int pixclock; 360 int mnp; 361 int panpos; 362 } crtc1; 363 struct { 364 struct matrox_vsync vsync; 365 unsigned int pixclock; 366 int mnp; 367 struct matroxfb_dh_fb_info* info; 368 struct rw_semaphore lock; 369 } crtc2; 370 struct { 371 struct rw_semaphore lock; 372 struct { 373 int brightness, contrast, saturation, hue, gamma; 374 int testout, deflicker; 375 } tvo_params; 376 } altout; 377 #define MATROXFB_MAX_OUTPUTS 3 378 struct { 379 unsigned int src; 380 struct matrox_altout* output; 381 void* data; 382 unsigned int mode; 383 unsigned int default_src; 384 } outputs[MATROXFB_MAX_OUTPUTS]; 385 386 #define MATROXFB_MAX_FB_DRIVERS 5 387 struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]); 388 void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]); 389 unsigned int drivers_count; 390 391 struct { 392 unsigned long base; /* physical */ 393 vaddr_t vbase; /* CPU view */ 394 unsigned int len; 395 unsigned int len_usable; 396 unsigned int len_maximum; 397 } video; 398 399 struct { 400 unsigned long base; /* physical */ 401 vaddr_t vbase; /* CPU view */ 402 unsigned int len; 403 } mmio; 404 405 unsigned int max_pixel_clock; 406 unsigned int max_pixel_clock_panellink; 407 408 struct matrox_switch* hw_switch; 409 410 struct { 411 struct matrox_pll_features pll; 412 struct matrox_DAC1064_features DAC1064; 413 } features; 414 struct { 415 spinlock_t DAC; 416 spinlock_t accel; 417 } lock; 418 419 enum mga_chip chip; 420 421 int interleave; 422 int millenium; 423 int milleniumII; 424 struct { 425 int cfb4; 426 const int* vxres; 427 int cross4MB; 428 int text; 429 int plnwt; 430 int srcorg; 431 } capable; 432 int wc_cookie; 433 struct { 434 int precise_width; 435 int mga_24bpp_fix; 436 int novga; 437 int nobios; 438 int nopciretry; 439 int noinit; 440 int sgram; 441 int support32MB; 442 443 int accelerator; 444 int text_type_aux; 445 int video64bits; 446 int crtc2; 447 int maven_capable; 448 unsigned int vgastep; 449 unsigned int textmode; 450 unsigned int textstep; 451 unsigned int textvram; /* character cells */ 452 unsigned int ydstorg; /* offset in bytes from video start to usable memory */ 453 /* 0 except for 6MB Millenium */ 454 int memtype; 455 int g450dac; 456 int dfp_type; 457 int panellink; /* G400 DFP possible (not G450/G550) */ 458 int dualhead; 459 unsigned int fbResource; 460 } devflags; 461 struct fb_ops fbops; 462 struct matrox_bios bios; 463 struct { 464 struct matrox_pll_limits pixel; 465 struct matrox_pll_limits system; 466 struct matrox_pll_limits video; 467 } limits; 468 struct { 469 struct matrox_pll_cache pixel; 470 struct matrox_pll_cache system; 471 struct matrox_pll_cache video; 472 } cache; 473 struct { 474 struct { 475 unsigned int video; 476 unsigned int system; 477 } pll; 478 struct { 479 u_int32_t opt; 480 u_int32_t opt2; 481 u_int32_t opt3; 482 u_int32_t mctlwtst; 483 u_int32_t mctlwtst_core; 484 u_int32_t memmisc; 485 u_int32_t memrdbk; 486 u_int32_t maccess; 487 } reg; 488 struct { 489 unsigned int ddr:1, 490 emrswen:1, 491 dll:1; 492 } memory; 493 } values; 494 u_int32_t cmap[16]; 495 }; 496 497 #define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon) 498 499 struct matrox_switch { 500 int (*preinit)(struct matrox_fb_info *minfo); 501 void (*reset)(struct matrox_fb_info *minfo); 502 int (*init)(struct matrox_fb_info *minfo, struct my_timming*); 503 void (*restore)(struct matrox_fb_info *minfo); 504 }; 505 506 struct matroxfb_driver { 507 struct list_head node; 508 char* name; 509 void* (*probe)(struct matrox_fb_info* info); 510 void (*remove)(struct matrox_fb_info* info, void* data); 511 }; 512 513 int matroxfb_register_driver(struct matroxfb_driver* drv); 514 void matroxfb_unregister_driver(struct matroxfb_driver* drv); 515 516 #define PCI_OPTION_REG 0x40 517 #define PCI_OPTION_ENABLE_ROM 0x40000000 518 519 #define PCI_MGA_INDEX 0x44 520 #define PCI_MGA_DATA 0x48 521 #define PCI_OPTION2_REG 0x50 522 #define PCI_OPTION3_REG 0x54 523 #define PCI_MEMMISC_REG 0x58 524 525 #define M_DWGCTL 0x1C00 526 #define M_MACCESS 0x1C04 527 #define M_CTLWTST 0x1C08 528 529 #define M_PLNWT 0x1C1C 530 531 #define M_BCOL 0x1C20 532 #define M_FCOL 0x1C24 533 534 #define M_SGN 0x1C58 535 #define M_LEN 0x1C5C 536 #define M_AR0 0x1C60 537 #define M_AR1 0x1C64 538 #define M_AR2 0x1C68 539 #define M_AR3 0x1C6C 540 #define M_AR4 0x1C70 541 #define M_AR5 0x1C74 542 #define M_AR6 0x1C78 543 544 #define M_CXBNDRY 0x1C80 545 #define M_FXBNDRY 0x1C84 546 #define M_YDSTLEN 0x1C88 547 #define M_PITCH 0x1C8C 548 #define M_YDST 0x1C90 549 #define M_YDSTORG 0x1C94 550 #define M_YTOP 0x1C98 551 #define M_YBOT 0x1C9C 552 553 /* mystique only */ 554 #define M_CACHEFLUSH 0x1FFF 555 556 #define M_EXEC 0x0100 557 558 #define M_DWG_TRAP 0x04 559 #define M_DWG_BITBLT 0x08 560 #define M_DWG_ILOAD 0x09 561 562 #define M_DWG_LINEAR 0x0080 563 #define M_DWG_SOLID 0x0800 564 #define M_DWG_ARZERO 0x1000 565 #define M_DWG_SGNZERO 0x2000 566 #define M_DWG_SHIFTZERO 0x4000 567 568 #define M_DWG_REPLACE 0x000C0000 569 #define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40) 570 #define M_DWG_XOR 0x00060010 571 572 #define M_DWG_BFCOL 0x04000000 573 #define M_DWG_BMONOWF 0x08000000 574 575 #define M_DWG_TRANSC 0x40000000 576 577 #define M_FIFOSTATUS 0x1E10 578 #define M_STATUS 0x1E14 579 #define M_ICLEAR 0x1E18 580 #define M_IEN 0x1E1C 581 582 #define M_VCOUNT 0x1E20 583 584 #define M_RESET 0x1E40 585 #define M_MEMRDBK 0x1E44 586 587 #define M_AGP2PLL 0x1E4C 588 589 #define M_OPMODE 0x1E54 590 #define M_OPMODE_DMA_GEN_WRITE 0x00 591 #define M_OPMODE_DMA_BLIT 0x04 592 #define M_OPMODE_DMA_VECTOR_WRITE 0x08 593 #define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */ 594 #define M_OPMODE_DMA_BE_8BPP 0x0000 595 #define M_OPMODE_DMA_BE_16BPP 0x0100 596 #define M_OPMODE_DMA_BE_32BPP 0x0200 597 #define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */ 598 #define M_OPMODE_DIR_BE_8BPP 0x000000 599 #define M_OPMODE_DIR_BE_16BPP 0x010000 600 #define M_OPMODE_DIR_BE_32BPP 0x020000 601 602 #define M_ATTR_INDEX 0x1FC0 603 #define M_ATTR_DATA 0x1FC1 604 605 #define M_MISC_REG 0x1FC2 606 #define M_3C2_RD 0x1FC2 607 608 #define M_SEQ_INDEX 0x1FC4 609 #define M_SEQ_DATA 0x1FC5 610 #define M_SEQ1 0x01 611 #define M_SEQ1_SCROFF 0x20 612 613 #define M_MISC_REG_READ 0x1FCC 614 615 #define M_GRAPHICS_INDEX 0x1FCE 616 #define M_GRAPHICS_DATA 0x1FCF 617 618 #define M_CRTC_INDEX 0x1FD4 619 620 #define M_ATTR_RESET 0x1FDA 621 #define M_3DA_WR 0x1FDA 622 #define M_INSTS1 0x1FDA 623 624 #define M_EXTVGA_INDEX 0x1FDE 625 #define M_EXTVGA_DATA 0x1FDF 626 627 /* G200 only */ 628 #define M_SRCORG 0x2CB4 629 #define M_DSTORG 0x2CB8 630 631 #define M_RAMDAC_BASE 0x3C00 632 633 /* fortunately, same on TVP3026 and MGA1064 */ 634 #define M_DAC_REG (M_RAMDAC_BASE+0) 635 #define M_DAC_VAL (M_RAMDAC_BASE+1) 636 #define M_PALETTE_MASK (M_RAMDAC_BASE+2) 637 638 #define M_X_INDEX 0x00 639 #define M_X_DATAREG 0x0A 640 641 #define DAC_XGENIOCTRL 0x2A 642 #define DAC_XGENIODATA 0x2B 643 644 #define M_C2CTL 0x3C10 645 646 #define MX_OPTION_BSWAP 0x00000000 647 648 #ifdef __LITTLE_ENDIAN 649 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) 650 #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) 651 #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) 652 #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) 653 #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) 654 #else 655 #ifdef __BIG_ENDIAN 656 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */ 657 #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) 658 #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT) 659 #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */ 660 #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT) 661 #else 662 #error "Byte ordering have to be defined. Cannot continue." 663 #endif 664 #endif 665 666 #define mga_inb(addr) mga_readb(minfo->mmio.vbase, (addr)) 667 #define mga_inl(addr) mga_readl(minfo->mmio.vbase, (addr)) 668 #define mga_outb(addr,val) mga_writeb(minfo->mmio.vbase, (addr), (val)) 669 #define mga_outw(addr,val) mga_writew(minfo->mmio.vbase, (addr), (val)) 670 #define mga_outl(addr,val) mga_writel(minfo->mmio.vbase, (addr), (val)) 671 #define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1)) 672 #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port)) 673 674 #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n)) 675 676 #define WaitTillIdle() do { mga_inl(M_STATUS); do {} while (mga_inl(M_STATUS) & 0x10000); } while (0) 677 678 /* code speedup */ 679 #ifdef CONFIG_FB_MATROX_MILLENIUM 680 #define isInterleave(x) (x->interleave) 681 #define isMillenium(x) (x->millenium) 682 #define isMilleniumII(x) (x->milleniumII) 683 #else 684 #define isInterleave(x) (0) 685 #define isMillenium(x) (0) 686 #define isMilleniumII(x) (0) 687 #endif 688 689 #define matroxfb_DAC_lock() spin_lock(&minfo->lock.DAC) 690 #define matroxfb_DAC_unlock() spin_unlock(&minfo->lock.DAC) 691 #define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&minfo->lock.DAC, flags) 692 #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&minfo->lock.DAC, flags) 693 extern void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, 694 int val); 695 extern int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg); 696 extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt); 697 extern int matroxfb_wait_for_sync(struct matrox_fb_info *minfo, u_int32_t crtc); 698 extern int matroxfb_enable_irq(struct matrox_fb_info *minfo, int reenable); 699 700 #ifdef MATROXFB_USE_SPINLOCKS 701 #define CRITBEGIN spin_lock_irqsave(&minfo->lock.accel, critflags); 702 #define CRITEND spin_unlock_irqrestore(&minfo->lock.accel, critflags); 703 #define CRITFLAGS unsigned long critflags; 704 #else 705 #define CRITBEGIN 706 #define CRITEND 707 #define CRITFLAGS 708 #endif 709 710 #endif /* __MATROXFB_H__ */ 711
