1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef _LINUX_QCOM_GENI_SE
7 #define _LINUX_QCOM_GENI_SE
8
9 #include <linux/interconnect.h>
10
11 /* Transfer mode supported by GENI Serial Engines */
12 enum geni_se_xfer_mode {
13 GENI_SE_INVALID,
14 GENI_SE_FIFO,
15 GENI_SE_DMA,
16 };
17
18 /* Protocols supported by GENI Serial Engines */
19 enum geni_se_protocol_type {
20 GENI_SE_NONE,
21 GENI_SE_SPI,
22 GENI_SE_UART,
23 GENI_SE_I2C,
24 GENI_SE_I3C,
25 };
26
27 struct geni_wrapper;
28 struct clk;
29
30 enum geni_icc_path_index {
31 GENI_TO_CORE,
32 CPU_TO_GENI,
33 GENI_TO_DDR
34 };
35
36 struct geni_icc_path {
37 struct icc_path *path;
38 unsigned int avg_bw;
39 };
40
41 /**
42 * struct geni_se - GENI Serial Engine
43 * @base: Base Address of the Serial Engine's register block
44 * @dev: Pointer to the Serial Engine device
45 * @wrapper: Pointer to the parent QUP Wrapper core
46 * @clk: Handle to the core serial engine clock
47 * @num_clk_levels: Number of valid clock levels in clk_perf_tbl
48 * @clk_perf_tbl: Table of clock frequency input to serial engine clock
49 * @icc_paths: Array of ICC paths for SE
50 * @opp_table: Pointer to the OPP table
51 * @has_opp_table: Specifies if the SE has an OPP table
52 */
53 struct geni_se {
54 void __iomem *base;
55 struct device *dev;
56 struct geni_wrapper *wrapper;
57 struct clk *clk;
58 unsigned int num_clk_levels;
59 unsigned long *clk_perf_tbl;
60 struct geni_icc_path icc_paths[3];
61 struct opp_table *opp_table;
62 bool has_opp_table;
63 };
64
65 /* Common SE registers */
66 #define GENI_FORCE_DEFAULT_REG 0x20
67 #define SE_GENI_STATUS 0x40
68 #define GENI_SER_M_CLK_CFG 0x48
69 #define GENI_SER_S_CLK_CFG 0x4c
70 #define GENI_FW_REVISION_RO 0x68
71 #define SE_GENI_CLK_SEL 0x7c
72 #define SE_GENI_DMA_MODE_EN 0x258
73 #define SE_GENI_M_CMD0 0x600
74 #define SE_GENI_M_CMD_CTRL_REG 0x604
75 #define SE_GENI_M_IRQ_STATUS 0x610
76 #define SE_GENI_M_IRQ_EN 0x614
77 #define SE_GENI_M_IRQ_CLEAR 0x618
78 #define SE_GENI_S_CMD0 0x630
79 #define SE_GENI_S_CMD_CTRL_REG 0x634
80 #define SE_GENI_S_IRQ_STATUS 0x640
81 #define SE_GENI_S_IRQ_EN 0x644
82 #define SE_GENI_S_IRQ_CLEAR 0x648
83 #define SE_GENI_TX_FIFOn 0x700
84 #define SE_GENI_RX_FIFOn 0x780
85 #define SE_GENI_TX_FIFO_STATUS 0x800
86 #define SE_GENI_RX_FIFO_STATUS 0x804
87 #define SE_GENI_TX_WATERMARK_REG 0x80c
88 #define SE_GENI_RX_WATERMARK_REG 0x810
89 #define SE_GENI_RX_RFR_WATERMARK_REG 0x814
90 #define SE_GENI_IOS 0x908
91 #define SE_DMA_TX_IRQ_STAT 0xc40
92 #define SE_DMA_TX_IRQ_CLR 0xc44
93 #define SE_DMA_TX_FSM_RST 0xc58
94 #define SE_DMA_RX_IRQ_STAT 0xd40
95 #define SE_DMA_RX_IRQ_CLR 0xd44
96 #define SE_DMA_RX_FSM_RST 0xd58
97 #define SE_HW_PARAM_0 0xe24
98 #define SE_HW_PARAM_1 0xe28
99
100 /* GENI_FORCE_DEFAULT_REG fields */
101 #define FORCE_DEFAULT BIT(0)
102
103 /* GENI_STATUS fields */
104 #define M_GENI_CMD_ACTIVE BIT(0)
105 #define S_GENI_CMD_ACTIVE BIT(12)
106
107 /* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
108 #define SER_CLK_EN BIT(0)
109 #define CLK_DIV_MSK GENMASK(15, 4)
110 #define CLK_DIV_SHFT 4
111
112 /* GENI_FW_REVISION_RO fields */
113 #define FW_REV_PROTOCOL_MSK GENMASK(15, 8)
114 #define FW_REV_PROTOCOL_SHFT 8
115
116 /* GENI_CLK_SEL fields */
117 #define CLK_SEL_MSK GENMASK(2, 0)
118
119 /* SE_GENI_DMA_MODE_EN */
120 #define GENI_DMA_MODE_EN BIT(0)
121
122 /* GENI_M_CMD0 fields */
123 #define M_OPCODE_MSK GENMASK(31, 27)
124 #define M_OPCODE_SHFT 27
125 #define M_PARAMS_MSK GENMASK(26, 0)
126
127 /* GENI_M_CMD_CTRL_REG */
128 #define M_GENI_CMD_CANCEL BIT(2)
129 #define M_GENI_CMD_ABORT BIT(1)
130 #define M_GENI_DISABLE BIT(0)
131
132 /* GENI_S_CMD0 fields */
133 #define S_OPCODE_MSK GENMASK(31, 27)
134 #define S_OPCODE_SHFT 27
135 #define S_PARAMS_MSK GENMASK(26, 0)
136
137 /* GENI_S_CMD_CTRL_REG */
138 #define S_GENI_CMD_CANCEL BIT(2)
139 #define S_GENI_CMD_ABORT BIT(1)
140 #define S_GENI_DISABLE BIT(0)
141
142 /* GENI_M_IRQ_EN fields */
143 #define M_CMD_DONE_EN BIT(0)
144 #define M_CMD_OVERRUN_EN BIT(1)
145 #define M_ILLEGAL_CMD_EN BIT(2)
146 #define M_CMD_FAILURE_EN BIT(3)
147 #define M_CMD_CANCEL_EN BIT(4)
148 #define M_CMD_ABORT_EN BIT(5)
149 #define M_TIMESTAMP_EN BIT(6)
150 #define M_RX_IRQ_EN BIT(7)
151 #define M_GP_SYNC_IRQ_0_EN BIT(8)
152 #define M_GP_IRQ_0_EN BIT(9)
153 #define M_GP_IRQ_1_EN BIT(10)
154 #define M_GP_IRQ_2_EN BIT(11)
155 #define M_GP_IRQ_3_EN BIT(12)
156 #define M_GP_IRQ_4_EN BIT(13)
157 #define M_GP_IRQ_5_EN BIT(14)
158 #define M_IO_DATA_DEASSERT_EN BIT(22)
159 #define M_IO_DATA_ASSERT_EN BIT(23)
160 #define M_RX_FIFO_RD_ERR_EN BIT(24)
161 #define M_RX_FIFO_WR_ERR_EN BIT(25)
162 #define M_RX_FIFO_WATERMARK_EN BIT(26)
163 #define M_RX_FIFO_LAST_EN BIT(27)
164 #define M_TX_FIFO_RD_ERR_EN BIT(28)
165 #define M_TX_FIFO_WR_ERR_EN BIT(29)
166 #define M_TX_FIFO_WATERMARK_EN BIT(30)
167 #define M_SEC_IRQ_EN BIT(31)
168 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
169 M_IO_DATA_DEASSERT_EN | \
170 M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
171 M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
172 M_TX_FIFO_WR_ERR_EN)
173
174 /* GENI_S_IRQ_EN fields */
175 #define S_CMD_DONE_EN BIT(0)
176 #define S_CMD_OVERRUN_EN BIT(1)
177 #define S_ILLEGAL_CMD_EN BIT(2)
178 #define S_CMD_FAILURE_EN BIT(3)
179 #define S_CMD_CANCEL_EN BIT(4)
180 #define S_CMD_ABORT_EN BIT(5)
181 #define S_GP_SYNC_IRQ_0_EN BIT(8)
182 #define S_GP_IRQ_0_EN BIT(9)
183 #define S_GP_IRQ_1_EN BIT(10)
184 #define S_GP_IRQ_2_EN BIT(11)
185 #define S_GP_IRQ_3_EN BIT(12)
186 #define S_GP_IRQ_4_EN BIT(13)
187 #define S_GP_IRQ_5_EN BIT(14)
188 #define S_IO_DATA_DEASSERT_EN BIT(22)
189 #define S_IO_DATA_ASSERT_EN BIT(23)
190 #define S_RX_FIFO_RD_ERR_EN BIT(24)
191 #define S_RX_FIFO_WR_ERR_EN BIT(25)
192 #define S_RX_FIFO_WATERMARK_EN BIT(26)
193 #define S_RX_FIFO_LAST_EN BIT(27)
194 #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \
195 S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
196
197 /* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
198 #define WATERMARK_MSK GENMASK(5, 0)
199
200 /* GENI_TX_FIFO_STATUS fields */
201 #define TX_FIFO_WC GENMASK(27, 0)
202
203 /* GENI_RX_FIFO_STATUS fields */
204 #define RX_LAST BIT(31)
205 #define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28)
206 #define RX_LAST_BYTE_VALID_SHFT 28
207 #define RX_FIFO_WC_MSK GENMASK(24, 0)
208
209 /* SE_GENI_IOS fields */
210 #define IO2_DATA_IN BIT(1)
211 #define RX_DATA_IN BIT(0)
212
213 /* SE_DMA_TX_IRQ_STAT Register fields */
214 #define TX_DMA_DONE BIT(0)
215 #define TX_EOT BIT(1)
216 #define TX_SBE BIT(2)
217 #define TX_RESET_DONE BIT(3)
218
219 /* SE_DMA_RX_IRQ_STAT Register fields */
220 #define RX_DMA_DONE BIT(0)
221 #define RX_EOT BIT(1)
222 #define RX_SBE BIT(2)
223 #define RX_RESET_DONE BIT(3)
224 #define RX_FLUSH_DONE BIT(4)
225 #define RX_GENI_GP_IRQ GENMASK(10, 5)
226 #define RX_GENI_CANCEL_IRQ BIT(11)
227 #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12)
228
229 /* SE_HW_PARAM_0 fields */
230 #define TX_FIFO_WIDTH_MSK GENMASK(29, 24)
231 #define TX_FIFO_WIDTH_SHFT 24
232 #define TX_FIFO_DEPTH_MSK GENMASK(21, 16)
233 #define TX_FIFO_DEPTH_SHFT 16
234
235 /* SE_HW_PARAM_1 fields */
236 #define RX_FIFO_WIDTH_MSK GENMASK(29, 24)
237 #define RX_FIFO_WIDTH_SHFT 24
238 #define RX_FIFO_DEPTH_MSK GENMASK(21, 16)
239 #define RX_FIFO_DEPTH_SHFT 16
240
241 #define HW_VER_MAJOR_MASK GENMASK(31, 28)
242 #define HW_VER_MAJOR_SHFT 28
243 #define HW_VER_MINOR_MASK GENMASK(27, 16)
244 #define HW_VER_MINOR_SHFT 16
245 #define HW_VER_STEP_MASK GENMASK(15, 0)
246
247 #define GENI_SE_VERSION_MAJOR(ver) ((ver & HW_VER_MAJOR_MASK) >> HW_VER_MAJOR_SHFT)
248 #define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
249 #define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
250
251 /* QUP SE VERSION value for major number 2 and minor number 5 */
252 #define QUP_SE_VERSION_2_5 0x20050000
253
254 /*
255 * Define bandwidth thresholds that cause the underlying Core 2X interconnect
256 * clock to run at the named frequency. These baseline values are recommended
257 * by the hardware team, and are not dynamically scaled with GENI bandwidth
258 * beyond basic on/off.
259 */
260 #define CORE_2X_19_2_MHZ 960
261 #define CORE_2X_50_MHZ 2500
262 #define CORE_2X_100_MHZ 5000
263 #define CORE_2X_150_MHZ 7500
264 #define CORE_2X_200_MHZ 10000
265 #define CORE_2X_236_MHZ 16383
266
267 #define GENI_DEFAULT_BW Bps_to_icc(1000)
268
269 #if IS_ENABLED(CONFIG_QCOM_GENI_SE)
270
271 u32 geni_se_get_qup_hw_version(struct geni_se *se);
272
273 /**
274 * geni_se_read_proto() - Read the protocol configured for a serial engine
275 * @se: Pointer to the concerned serial engine.
276 *
277 * Return: Protocol value as configured in the serial engine.
278 */
geni_se_read_proto(struct geni_se * se)279 static inline u32 geni_se_read_proto(struct geni_se *se)
280 {
281 u32 val;
282
283 val = readl_relaxed(se->base + GENI_FW_REVISION_RO);
284
285 return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT;
286 }
287
288 /**
289 * geni_se_setup_m_cmd() - Setup the primary sequencer
290 * @se: Pointer to the concerned serial engine.
291 * @cmd: Command/Operation to setup in the primary sequencer.
292 * @params: Parameter for the sequencer command.
293 *
294 * This function is used to configure the primary sequencer with the
295 * command and its associated parameters.
296 */
geni_se_setup_m_cmd(struct geni_se * se,u32 cmd,u32 params)297 static inline void geni_se_setup_m_cmd(struct geni_se *se, u32 cmd, u32 params)
298 {
299 u32 m_cmd;
300
301 m_cmd = (cmd << M_OPCODE_SHFT) | (params & M_PARAMS_MSK);
302 writel(m_cmd, se->base + SE_GENI_M_CMD0);
303 }
304
305 /**
306 * geni_se_setup_s_cmd() - Setup the secondary sequencer
307 * @se: Pointer to the concerned serial engine.
308 * @cmd: Command/Operation to setup in the secondary sequencer.
309 * @params: Parameter for the sequencer command.
310 *
311 * This function is used to configure the secondary sequencer with the
312 * command and its associated parameters.
313 */
geni_se_setup_s_cmd(struct geni_se * se,u32 cmd,u32 params)314 static inline void geni_se_setup_s_cmd(struct geni_se *se, u32 cmd, u32 params)
315 {
316 u32 s_cmd;
317
318 s_cmd = readl_relaxed(se->base + SE_GENI_S_CMD0);
319 s_cmd &= ~(S_OPCODE_MSK | S_PARAMS_MSK);
320 s_cmd |= (cmd << S_OPCODE_SHFT);
321 s_cmd |= (params & S_PARAMS_MSK);
322 writel(s_cmd, se->base + SE_GENI_S_CMD0);
323 }
324
325 /**
326 * geni_se_cancel_m_cmd() - Cancel the command configured in the primary
327 * sequencer
328 * @se: Pointer to the concerned serial engine.
329 *
330 * This function is used to cancel the currently configured command in the
331 * primary sequencer.
332 */
geni_se_cancel_m_cmd(struct geni_se * se)333 static inline void geni_se_cancel_m_cmd(struct geni_se *se)
334 {
335 writel_relaxed(M_GENI_CMD_CANCEL, se->base + SE_GENI_M_CMD_CTRL_REG);
336 }
337
338 /**
339 * geni_se_cancel_s_cmd() - Cancel the command configured in the secondary
340 * sequencer
341 * @se: Pointer to the concerned serial engine.
342 *
343 * This function is used to cancel the currently configured command in the
344 * secondary sequencer.
345 */
geni_se_cancel_s_cmd(struct geni_se * se)346 static inline void geni_se_cancel_s_cmd(struct geni_se *se)
347 {
348 writel_relaxed(S_GENI_CMD_CANCEL, se->base + SE_GENI_S_CMD_CTRL_REG);
349 }
350
351 /**
352 * geni_se_abort_m_cmd() - Abort the command configured in the primary sequencer
353 * @se: Pointer to the concerned serial engine.
354 *
355 * This function is used to force abort the currently configured command in the
356 * primary sequencer.
357 */
geni_se_abort_m_cmd(struct geni_se * se)358 static inline void geni_se_abort_m_cmd(struct geni_se *se)
359 {
360 writel_relaxed(M_GENI_CMD_ABORT, se->base + SE_GENI_M_CMD_CTRL_REG);
361 }
362
363 /**
364 * geni_se_abort_s_cmd() - Abort the command configured in the secondary
365 * sequencer
366 * @se: Pointer to the concerned serial engine.
367 *
368 * This function is used to force abort the currently configured command in the
369 * secondary sequencer.
370 */
geni_se_abort_s_cmd(struct geni_se * se)371 static inline void geni_se_abort_s_cmd(struct geni_se *se)
372 {
373 writel_relaxed(S_GENI_CMD_ABORT, se->base + SE_GENI_S_CMD_CTRL_REG);
374 }
375
376 /**
377 * geni_se_get_tx_fifo_depth() - Get the TX fifo depth of the serial engine
378 * @se: Pointer to the concerned serial engine.
379 *
380 * This function is used to get the depth i.e. number of elements in the
381 * TX fifo of the serial engine.
382 *
383 * Return: TX fifo depth in units of FIFO words.
384 */
geni_se_get_tx_fifo_depth(struct geni_se * se)385 static inline u32 geni_se_get_tx_fifo_depth(struct geni_se *se)
386 {
387 u32 val;
388
389 val = readl_relaxed(se->base + SE_HW_PARAM_0);
390
391 return (val & TX_FIFO_DEPTH_MSK) >> TX_FIFO_DEPTH_SHFT;
392 }
393
394 /**
395 * geni_se_get_tx_fifo_width() - Get the TX fifo width of the serial engine
396 * @se: Pointer to the concerned serial engine.
397 *
398 * This function is used to get the width i.e. word size per element in the
399 * TX fifo of the serial engine.
400 *
401 * Return: TX fifo width in bits
402 */
geni_se_get_tx_fifo_width(struct geni_se * se)403 static inline u32 geni_se_get_tx_fifo_width(struct geni_se *se)
404 {
405 u32 val;
406
407 val = readl_relaxed(se->base + SE_HW_PARAM_0);
408
409 return (val & TX_FIFO_WIDTH_MSK) >> TX_FIFO_WIDTH_SHFT;
410 }
411
412 /**
413 * geni_se_get_rx_fifo_depth() - Get the RX fifo depth of the serial engine
414 * @se: Pointer to the concerned serial engine.
415 *
416 * This function is used to get the depth i.e. number of elements in the
417 * RX fifo of the serial engine.
418 *
419 * Return: RX fifo depth in units of FIFO words
420 */
geni_se_get_rx_fifo_depth(struct geni_se * se)421 static inline u32 geni_se_get_rx_fifo_depth(struct geni_se *se)
422 {
423 u32 val;
424
425 val = readl_relaxed(se->base + SE_HW_PARAM_1);
426
427 return (val & RX_FIFO_DEPTH_MSK) >> RX_FIFO_DEPTH_SHFT;
428 }
429
430 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr);
431
432 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode);
433
434 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
435 bool msb_to_lsb, bool tx_cfg, bool rx_cfg);
436
437 int geni_se_resources_off(struct geni_se *se);
438
439 int geni_se_resources_on(struct geni_se *se);
440
441 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl);
442
443 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
444 unsigned int *index, unsigned long *res_freq,
445 bool exact);
446
447 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
448 dma_addr_t *iova);
449
450 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
451 dma_addr_t *iova);
452
453 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
454
455 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
456
457 int geni_icc_get(struct geni_se *se, const char *icc_ddr);
458
459 int geni_icc_set_bw(struct geni_se *se);
460 void geni_icc_set_tag(struct geni_se *se, u32 tag);
461
462 int geni_icc_enable(struct geni_se *se);
463
464 int geni_icc_disable(struct geni_se *se);
465
466 void geni_remove_earlycon_icc_vote(void);
467 #endif
468 #endif
469
