1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2019 MediaTek Inc. */
3
4 #ifndef __MT7615_MAC_H
5 #define __MT7615_MAC_H
6
7 #define MT_CT_PARSE_LEN 72
8 #define MT_CT_DMA_BUF_NUM 2
9
10 #define MT_RXD0_LENGTH GENMASK(15, 0)
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
13
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
21
22 enum rx_pkt_type {
23 PKT_TYPE_TXS,
24 PKT_TYPE_TXRXV,
25 PKT_TYPE_NORMAL,
26 PKT_TYPE_RX_DUP_RFB,
27 PKT_TYPE_RX_TMR,
28 PKT_TYPE_RETRIEVE,
29 PKT_TYPE_TXRX_NOTIFY,
30 PKT_TYPE_RX_EVENT,
31 PKT_TYPE_NORMAL_MCU,
32 };
33
34 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
35 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
36 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
37 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
38 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
39 #define MT_RXD1_NORMAL_CH_FREQ GENMASK(15, 8)
40 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
41 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
42 #define MT_RXD1_NORMAL_BEACON_MC BIT(4)
43 #define MT_RXD1_NORMAL_BF_REPORT BIT(3)
44 #define MT_RXD1_NORMAL_ADDR_TYPE GENMASK(2, 1)
45 #define MT_RXD1_NORMAL_BCAST GENMASK(2, 1)
46 #define MT_RXD1_NORMAL_MCAST BIT(2)
47 #define MT_RXD1_NORMAL_U2M BIT(1)
48 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
49
50 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
51 #define MT_RXD2_NORMAL_NON_AMPDU_SUB BIT(30)
52 #define MT_RXD2_NORMAL_NDATA BIT(29)
53 #define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
54 #define MT_RXD2_NORMAL_FRAG BIT(27)
55 #define MT_RXD2_NORMAL_INT_FRAME BIT(26)
56 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
57 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
58 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
59 #define MT_RXD2_NORMAL_LEN_MISMATCH BIT(22)
60 #define MT_RXD2_NORMAL_TKIP_MIC_ERR BIT(21)
61 #define MT_RXD2_NORMAL_ICV_ERR BIT(20)
62 #define MT_RXD2_NORMAL_CLM BIT(19)
63 #define MT_RXD2_NORMAL_CM BIT(18)
64 #define MT_RXD2_NORMAL_FCS_ERR BIT(17)
65 #define MT_RXD2_NORMAL_SW_BIT BIT(16)
66 #define MT_RXD2_NORMAL_SEC_MODE GENMASK(15, 12)
67 #define MT_RXD2_NORMAL_TID GENMASK(11, 8)
68 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
69
70 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
71 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
72 #define MT_RXD3_NORMAL_CLS_BITMAP GENMASK(28, 19)
73 #define MT_RXD3_NORMAL_WOL GENMASK(18, 14)
74 #define MT_RXD3_NORMAL_MAGIC_PKT BIT(13)
75 #define MT_RXD3_NORMAL_OFLD GENMASK(12, 11)
76 #define MT_RXD3_NORMAL_CLS BIT(10)
77 #define MT_RXD3_NORMAL_PATTERN_DROP BIT(9)
78 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(8)
79 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
80
81 #define MT_RXV1_ACID_DET_H BIT(31)
82 #define MT_RXV1_ACID_DET_L BIT(30)
83 #define MT_RXV1_VHTA2_B8_B3 GENMASK(29, 24)
84 #define MT_RXV1_NUM_RX GENMASK(23, 22)
85 #define MT_RXV1_HT_NO_SOUND BIT(21)
86 #define MT_RXV1_HT_SMOOTH BIT(20)
87 #define MT_RXV1_HT_SHORT_GI BIT(19)
88 #define MT_RXV1_HT_AGGR BIT(18)
89 #define MT_RXV1_VHTA1_B22 BIT(17)
90 #define MT_RXV1_FRAME_MODE GENMASK(16, 15)
91 #define MT_RXV1_TX_MODE GENMASK(14, 12)
92 #define MT_RXV1_HT_EXT_LTF GENMASK(11, 10)
93 #define MT_RXV1_HT_AD_CODE BIT(9)
94 #define MT_RXV1_HT_STBC GENMASK(8, 7)
95 #define MT_RXV1_TX_RATE GENMASK(6, 0)
96
97 #define MT_RXV2_SEL_ANT BIT(31)
98 #define MT_RXV2_VALID_BIT BIT(30)
99 #define MT_RXV2_NSTS GENMASK(29, 27)
100 #define MT_RXV2_GROUP_ID GENMASK(26, 21)
101 #define MT_RXV2_LENGTH GENMASK(20, 0)
102
103 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
104 #define MT_RXV3_IB_RSSI GENMASK(23, 16)
105
106 #define MT_RXV4_RCPI3 GENMASK(31, 24)
107 #define MT_RXV4_RCPI2 GENMASK(23, 16)
108 #define MT_RXV4_RCPI1 GENMASK(15, 8)
109 #define MT_RXV4_RCPI0 GENMASK(7, 0)
110
111 #define MT_RXV5_FOE GENMASK(11, 0)
112
113 #define MT_RXV6_NF3 GENMASK(31, 24)
114 #define MT_RXV6_NF2 GENMASK(23, 16)
115 #define MT_RXV6_NF1 GENMASK(15, 8)
116 #define MT_RXV6_NF0 GENMASK(7, 0)
117
118 enum tx_header_format {
119 MT_HDR_FORMAT_802_3,
120 MT_HDR_FORMAT_CMD,
121 MT_HDR_FORMAT_802_11,
122 MT_HDR_FORMAT_802_11_EXT,
123 };
124
125 enum tx_pkt_type {
126 MT_TX_TYPE_CT,
127 MT_TX_TYPE_SF,
128 MT_TX_TYPE_CMD,
129 MT_TX_TYPE_FW,
130 };
131
132 enum tx_port_idx {
133 MT_TX_PORT_IDX_LMAC,
134 MT_TX_PORT_IDX_MCU
135 };
136
137 enum tx_mcu_port_q_idx {
138 MT_TX_MCU_PORT_RX_Q0 = 0,
139 MT_TX_MCU_PORT_RX_Q1,
140 MT_TX_MCU_PORT_RX_Q2,
141 MT_TX_MCU_PORT_RX_Q3,
142 MT_TX_MCU_PORT_RX_FWDL = 0x1e
143 };
144
145 enum tx_phy_bandwidth {
146 MT_PHY_BW_20,
147 MT_PHY_BW_40,
148 MT_PHY_BW_80,
149 MT_PHY_BW_160,
150 };
151
152 #define MT_CT_INFO_APPLY_TXD BIT(0)
153 #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
154 #define MT_CT_INFO_MGMT_FRAME BIT(2)
155 #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
156 #define MT_CT_INFO_HSR2_TX BIT(4)
157
158 #define MT_TXD_SIZE (8 * 4)
159
160 #define MT_USB_TXD_SIZE (MT_TXD_SIZE + 8 * 4)
161 #define MT_USB_HDR_SIZE 4
162 #define MT_USB_TAIL_SIZE 4
163
164 #define MT_TXD0_P_IDX BIT(31)
165 #define MT_TXD0_Q_IDX GENMASK(30, 26)
166 #define MT_TXD0_UDP_TCP_SUM BIT(24)
167 #define MT_TXD0_IP_SUM BIT(23)
168 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
169 #define MT_TXD0_TX_BYTES GENMASK(15, 0)
170
171 #define MT_TXD1_OWN_MAC GENMASK(31, 26)
172 #define MT_TXD1_PKT_FMT GENMASK(25, 24)
173 #define MT_TXD1_TID GENMASK(23, 21)
174 #define MT_TXD1_AMSDU BIT(20)
175 #define MT_TXD1_UNXV BIT(19)
176 #define MT_TXD1_HDR_PAD GENMASK(18, 17)
177 #define MT_TXD1_TXD_LEN BIT(16)
178 #define MT_TXD1_LONG_FORMAT BIT(15)
179 #define MT_TXD1_HDR_FORMAT GENMASK(14, 13)
180 #define MT_TXD1_HDR_INFO GENMASK(12, 8)
181 #define MT_TXD1_WLAN_IDX GENMASK(7, 0)
182
183 #define MT_TXD2_FIX_RATE BIT(31)
184 #define MT_TXD2_TIMING_MEASURE BIT(30)
185 #define MT_TXD2_BA_DISABLE BIT(29)
186 #define MT_TXD2_POWER_OFFSET GENMASK(28, 24)
187 #define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)
188 #define MT_TXD2_FRAG GENMASK(15, 14)
189 #define MT_TXD2_HTC_VLD BIT(13)
190 #define MT_TXD2_DURATION BIT(12)
191 #define MT_TXD2_BIP BIT(11)
192 #define MT_TXD2_MULTICAST BIT(10)
193 #define MT_TXD2_RTS BIT(9)
194 #define MT_TXD2_SOUNDING BIT(8)
195 #define MT_TXD2_NDPA BIT(7)
196 #define MT_TXD2_NDP BIT(6)
197 #define MT_TXD2_FRAME_TYPE GENMASK(5, 4)
198 #define MT_TXD2_SUB_TYPE GENMASK(3, 0)
199
200 #define MT_TXD3_SN_VALID BIT(31)
201 #define MT_TXD3_PN_VALID BIT(30)
202 #define MT_TXD3_SEQ GENMASK(27, 16)
203 #define MT_TXD3_REM_TX_COUNT GENMASK(15, 11)
204 #define MT_TXD3_TX_COUNT GENMASK(10, 6)
205 #define MT_TXD3_PROTECT_FRAME BIT(1)
206 #define MT_TXD3_NO_ACK BIT(0)
207
208 #define MT_TXD4_PN_LOW GENMASK(31, 0)
209
210 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
211 #define MT_TXD5_SW_POWER_MGMT BIT(13)
212 #define MT_TXD5_DA_SELECT BIT(11)
213 #define MT_TXD5_TX_STATUS_HOST BIT(10)
214 #define MT_TXD5_TX_STATUS_MCU BIT(9)
215 #define MT_TXD5_TX_STATUS_FMT BIT(8)
216 #define MT_TXD5_PID GENMASK(7, 0)
217
218 #define MT_TXD6_FIXED_RATE BIT(31)
219 #define MT_TXD6_SGI BIT(30)
220 #define MT_TXD6_LDPC BIT(29)
221 #define MT_TXD6_TX_BF BIT(28)
222 #define MT_TXD6_TX_RATE GENMASK(27, 16)
223 #define MT_TXD6_ANT_ID GENMASK(15, 4)
224 #define MT_TXD6_DYN_BW BIT(3)
225 #define MT_TXD6_FIXED_BW BIT(2)
226 #define MT_TXD6_BW GENMASK(1, 0)
227
228 /* MT7663 DW7 HW-AMSDU */
229 #define MT_TXD7_HW_AMSDU_CAP BIT(30)
230 #define MT_TXD7_TYPE GENMASK(21, 20)
231 #define MT_TXD7_SUB_TYPE GENMASK(19, 16)
232 #define MT_TXD7_SPE_IDX GENMASK(15, 11)
233 #define MT_TXD7_SPE_IDX_SLE BIT(10)
234
235 #define MT_TXD8_L_TYPE GENMASK(5, 4)
236 #define MT_TXD8_L_SUB_TYPE GENMASK(3, 0)
237
238 #define MT_TX_RATE_STBC BIT(11)
239 #define MT_TX_RATE_NSS GENMASK(10, 9)
240 #define MT_TX_RATE_MODE GENMASK(8, 6)
241 #define MT_TX_RATE_IDX GENMASK(5, 0)
242
243 #define MT_TXP_MAX_BUF_NUM 6
244 #define MT_HW_TXP_MAX_MSDU_NUM 4
245 #define MT_HW_TXP_MAX_BUF_NUM 4
246
247 #define MT_MSDU_ID_VALID BIT(15)
248
249 #define MT_TXD_LEN_MASK GENMASK(11, 0)
250 #define MT_TXD_LEN_MSDU_LAST BIT(14)
251 #define MT_TXD_LEN_AMSDU_LAST BIT(15)
252 /* mt7663 */
253 #define MT_TXD_LEN_LAST BIT(15)
254
255 struct mt7615_txp_ptr {
256 __le32 buf0;
257 __le16 len0;
258 __le16 len1;
259 __le32 buf1;
260 } __packed __aligned(4);
261
262 struct mt7615_hw_txp {
263 __le16 msdu_id[MT_HW_TXP_MAX_MSDU_NUM];
264 struct mt7615_txp_ptr ptr[MT_HW_TXP_MAX_BUF_NUM / 2];
265 } __packed __aligned(4);
266
267 struct mt7615_fw_txp {
268 __le16 flags;
269 __le16 token;
270 u8 bss_idx;
271 u8 rept_wds_wcid;
272 u8 rsv;
273 u8 nbuf;
274 __le32 buf[MT_TXP_MAX_BUF_NUM];
275 __le16 len[MT_TXP_MAX_BUF_NUM];
276 } __packed __aligned(4);
277
278 struct mt7615_txp_common {
279 union {
280 struct mt7615_fw_txp fw;
281 struct mt7615_hw_txp hw;
282 };
283 };
284
285 struct mt7615_tx_free {
286 __le16 rx_byte_cnt;
287 __le16 ctrl;
288 u8 txd_cnt;
289 u8 rsv[3];
290 __le16 token[];
291 } __packed __aligned(4);
292
293 #define MT_TX_FREE_MSDU_ID_CNT GENMASK(6, 0)
294
295 #define MT_TXS0_PID GENMASK(31, 24)
296 #define MT_TXS0_BA_ERROR BIT(22)
297 #define MT_TXS0_PS_FLAG BIT(21)
298 #define MT_TXS0_TXOP_TIMEOUT BIT(20)
299 #define MT_TXS0_BIP_ERROR BIT(19)
300
301 #define MT_TXS0_QUEUE_TIMEOUT BIT(18)
302 #define MT_TXS0_RTS_TIMEOUT BIT(17)
303 #define MT_TXS0_ACK_TIMEOUT BIT(16)
304 #define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)
305
306 #define MT_TXS0_TX_STATUS_HOST BIT(15)
307 #define MT_TXS0_TX_STATUS_MCU BIT(14)
308 #define MT_TXS0_TXS_FORMAT BIT(13)
309 #define MT_TXS0_FIXED_RATE BIT(12)
310 #define MT_TXS0_TX_RATE GENMASK(11, 0)
311
312 #define MT_TXS1_ANT_ID GENMASK(31, 20)
313 #define MT_TXS1_RESP_RATE GENMASK(19, 16)
314 #define MT_TXS1_BW GENMASK(15, 14)
315 #define MT_TXS1_I_TXBF BIT(13)
316 #define MT_TXS1_E_TXBF BIT(12)
317 #define MT_TXS1_TID GENMASK(11, 9)
318 #define MT_TXS1_AMPDU BIT(8)
319 #define MT_TXS1_ACKED_MPDU BIT(7)
320 #define MT_TXS1_TX_POWER_DBM GENMASK(6, 0)
321
322 #define MT_TXS2_WCID GENMASK(31, 24)
323 #define MT_TXS2_RXV_SEQNO GENMASK(23, 16)
324 #define MT_TXS2_TX_DELAY GENMASK(15, 0)
325
326 #define MT_TXS3_LAST_TX_RATE GENMASK(31, 29)
327 #define MT_TXS3_TX_COUNT GENMASK(28, 24)
328 #define MT_TXS3_F1_TSSI1 GENMASK(23, 12)
329 #define MT_TXS3_F1_TSSI0 GENMASK(11, 0)
330 #define MT_TXS3_F0_SEQNO GENMASK(11, 0)
331
332 #define MT_TXS4_F0_TIMESTAMP GENMASK(31, 0)
333 #define MT_TXS4_F1_TSSI3 GENMASK(23, 12)
334 #define MT_TXS4_F1_TSSI2 GENMASK(11, 0)
335
336 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
337 #define MT_TXS5_F1_NOISE_2 GENMASK(23, 16)
338 #define MT_TXS5_F1_NOISE_1 GENMASK(15, 8)
339 #define MT_TXS5_F1_NOISE_0 GENMASK(7, 0)
340
341 #define MT_TXS6_F1_RCPI_3 GENMASK(31, 24)
342 #define MT_TXS6_F1_RCPI_2 GENMASK(23, 16)
343 #define MT_TXS6_F1_RCPI_1 GENMASK(15, 8)
344 #define MT_TXS6_F1_RCPI_0 GENMASK(7, 0)
345
346 struct mt7615_dfs_pulse {
347 u32 max_width; /* us */
348 int max_pwr; /* dbm */
349 int min_pwr; /* dbm */
350 u32 min_stgr_pri; /* us */
351 u32 max_stgr_pri; /* us */
352 u32 min_cr_pri; /* us */
353 u32 max_cr_pri; /* us */
354 };
355
356 struct mt7615_dfs_pattern {
357 u8 enb;
358 u8 stgr;
359 u8 min_crpn;
360 u8 max_crpn;
361 u8 min_crpr;
362 u8 min_pw;
363 u8 max_pw;
364 u32 min_pri;
365 u32 max_pri;
366 u8 min_crbn;
367 u8 max_crbn;
368 u8 min_stgpn;
369 u8 max_stgpn;
370 u8 min_stgpr;
371 };
372
373 struct mt7615_dfs_radar_spec {
374 struct mt7615_dfs_pulse pulse_th;
375 struct mt7615_dfs_pattern radar_pattern[16];
376 };
377
378 enum mt7615_cipher_type {
379 MT_CIPHER_NONE,
380 MT_CIPHER_WEP40,
381 MT_CIPHER_TKIP,
382 MT_CIPHER_TKIP_NO_MIC,
383 MT_CIPHER_AES_CCMP,
384 MT_CIPHER_WEP104,
385 MT_CIPHER_BIP_CMAC_128,
386 MT_CIPHER_WEP128,
387 MT_CIPHER_WAPI,
388 MT_CIPHER_CCMP_256 = 10,
389 MT_CIPHER_GCMP,
390 MT_CIPHER_GCMP_256,
391 };
392
393 static inline enum mt7615_cipher_type
mt7615_mac_get_cipher(int cipher)394 mt7615_mac_get_cipher(int cipher)
395 {
396 switch (cipher) {
397 case WLAN_CIPHER_SUITE_WEP40:
398 return MT_CIPHER_WEP40;
399 case WLAN_CIPHER_SUITE_WEP104:
400 return MT_CIPHER_WEP104;
401 case WLAN_CIPHER_SUITE_TKIP:
402 return MT_CIPHER_TKIP;
403 case WLAN_CIPHER_SUITE_AES_CMAC:
404 return MT_CIPHER_BIP_CMAC_128;
405 case WLAN_CIPHER_SUITE_CCMP:
406 return MT_CIPHER_AES_CCMP;
407 case WLAN_CIPHER_SUITE_CCMP_256:
408 return MT_CIPHER_CCMP_256;
409 case WLAN_CIPHER_SUITE_GCMP:
410 return MT_CIPHER_GCMP;
411 case WLAN_CIPHER_SUITE_GCMP_256:
412 return MT_CIPHER_GCMP_256;
413 case WLAN_CIPHER_SUITE_SMS4:
414 return MT_CIPHER_WAPI;
415 default:
416 return MT_CIPHER_NONE;
417 }
418 }
419
420 static inline struct mt7615_txp_common *
mt7615_txwi_to_txp(struct mt76_dev * dev,struct mt76_txwi_cache * t)421 mt7615_txwi_to_txp(struct mt76_dev *dev, struct mt76_txwi_cache *t)
422 {
423 u8 *txwi;
424
425 if (!t)
426 return NULL;
427
428 txwi = mt76_get_txwi_ptr(dev, t);
429
430 return (struct mt7615_txp_common *)(txwi + MT_TXD_SIZE);
431 }
432
mt7615_mac_wtbl_addr(struct mt7615_dev * dev,int wcid)433 static inline u32 mt7615_mac_wtbl_addr(struct mt7615_dev *dev, int wcid)
434 {
435 return MT_WTBL_BASE(dev) + wcid * MT_WTBL_ENTRY_SIZE;
436 }
437
438 #endif
439
