1 /*
2 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
4 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #ifndef __MT76X0U_EEPROM_H
17 #define __MT76X0U_EEPROM_H
18
19 struct mt76x0_dev;
20
21 #define MT76X0U_EE_MAX_VER 0x0c
22 #define MT76X0_EEPROM_SIZE 512
23
24 #define MT76X0U_DEFAULT_TX_POWER 6
25
26 enum mt76_eeprom_field {
27 MT_EE_CHIP_ID = 0x00,
28 MT_EE_VERSION_FAE = 0x02,
29 MT_EE_VERSION_EE = 0x03,
30 MT_EE_MAC_ADDR = 0x04,
31 MT_EE_NIC_CONF_0 = 0x34,
32 MT_EE_NIC_CONF_1 = 0x36,
33 MT_EE_COUNTRY_REGION_5GHZ = 0x38,
34 MT_EE_COUNTRY_REGION_2GHZ = 0x39,
35 MT_EE_FREQ_OFFSET = 0x3a,
36 MT_EE_NIC_CONF_2 = 0x42,
37
38 MT_EE_LNA_GAIN_2GHZ = 0x44,
39 MT_EE_LNA_GAIN_5GHZ_0 = 0x45,
40 MT_EE_RSSI_OFFSET = 0x46,
41 MT_EE_RSSI_OFFSET_5GHZ = 0x4a,
42 MT_EE_LNA_GAIN_5GHZ_1 = 0x49,
43 MT_EE_LNA_GAIN_5GHZ_2 = 0x4d,
44
45 MT_EE_TX_POWER_DELTA_BW40 = 0x50,
46
47 MT_EE_TX_POWER_OFFSET_2GHZ = 0x52,
48
49 MT_EE_TX_TSSI_SLOPE = 0x6e,
50 MT_EE_TX_TSSI_OFFSET_GROUP = 0x6f,
51 MT_EE_TX_TSSI_OFFSET = 0x76,
52
53 MT_EE_TX_POWER_OFFSET_5GHZ = 0x78,
54
55 MT_EE_TEMP_OFFSET = 0xd1,
56 MT_EE_FREQ_OFFSET_COMPENSATION = 0xdb,
57 MT_EE_TX_POWER_BYRATE_BASE = 0xde,
58
59 MT_EE_TX_POWER_BYRATE_BASE_5GHZ = 0x120,
60
61 MT_EE_USAGE_MAP_START = 0x1e0,
62 MT_EE_USAGE_MAP_END = 0x1fc,
63 };
64
65 #define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0)
66 #define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4)
67 #define MT_EE_NIC_CONF_0_PA_TYPE GENMASK(9, 8)
68 #define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12)
69
70 #define MT_EE_NIC_CONF_1_HW_RF_CTRL BIT(0)
71 #define MT_EE_NIC_CONF_1_TEMP_TX_ALC BIT(1)
72 #define MT_EE_NIC_CONF_1_LNA_EXT_2G BIT(2)
73 #define MT_EE_NIC_CONF_1_LNA_EXT_5G BIT(3)
74 #define MT_EE_NIC_CONF_1_TX_ALC_EN BIT(13)
75
76 #define MT_EE_NIC_CONF_2_RX_STREAM GENMASK(3, 0)
77 #define MT_EE_NIC_CONF_2_TX_STREAM GENMASK(7, 4)
78 #define MT_EE_NIC_CONF_2_HW_ANTDIV BIT(8)
79 #define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9)
80 #define MT_EE_NIC_CONF_2_TEMP_DISABLE BIT(11)
81 #define MT_EE_NIC_CONF_2_COEX_METHOD GENMASK(15, 13)
82
83 #define MT_EE_TX_POWER_BYRATE(i) (MT_EE_TX_POWER_BYRATE_BASE + \
84 (i) * 4)
85
86 #define MT_EFUSE_USAGE_MAP_SIZE (MT_EE_USAGE_MAP_END - \
87 MT_EE_USAGE_MAP_START + 1)
88
89 enum mt76x0_eeprom_access_modes {
90 MT_EE_READ = 0,
91 MT_EE_PHYSICAL_READ = 1,
92 };
93
94 struct reg_channel_bounds {
95 u8 start;
96 u8 num;
97 };
98
99 struct mt76x0_eeprom_params {
100 u8 rf_freq_off;
101 s16 temp_off;
102 s8 rssi_offset_2ghz[2];
103 s8 rssi_offset_5ghz[3];
104 s8 lna_gain_2ghz;
105 s8 lna_gain_5ghz[3];
106 u8 pa_type;
107
108 /* TX_PWR_CFG_* values from EEPROM for 20 and 40 Mhz bandwidths. */
109 u32 tx_pwr_cfg_2g[5][2];
110 u32 tx_pwr_cfg_5g[5][2];
111
112 u8 tx_pwr_per_chan[58];
113
114 struct reg_channel_bounds reg;
115
116 bool has_2ghz;
117 bool has_5ghz;
118 };
119
120 int mt76x0_eeprom_init(struct mt76x0_dev *dev);
121
s6_validate(u32 reg)122 static inline u32 s6_validate(u32 reg)
123 {
124 WARN_ON(reg & ~GENMASK(5, 0));
125 return reg & GENMASK(5, 0);
126 }
127
s6_to_int(u32 reg)128 static inline int s6_to_int(u32 reg)
129 {
130 int s6;
131
132 s6 = s6_validate(reg);
133 if (s6 & BIT(5))
134 s6 -= BIT(6);
135
136 return s6;
137 }
138
int_to_s6(int val)139 static inline u32 int_to_s6(int val)
140 {
141 if (val < -0x20)
142 return 0x20;
143 if (val > 0x1f)
144 return 0x1f;
145
146 return val & 0x3f;
147 }
148
149 #endif
150
