1 /*
2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef __MT76x2_H
18 #define __MT76x2_H
19
20 #include <linux/device.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/spinlock.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/irq.h>
26 #include <linux/interrupt.h>
27 #include <linux/mutex.h>
28 #include <linux/bitops.h>
29 #include <linux/kfifo.h>
30 #include <linux/average.h>
31
32 #define MT7662_FIRMWARE "mt7662.bin"
33 #define MT7662_ROM_PATCH "mt7662_rom_patch.bin"
34 #define MT7662_EEPROM_SIZE 512
35
36 #define MT7662U_FIRMWARE "mediatek/mt7662u.bin"
37 #define MT7662U_ROM_PATCH "mediatek/mt7662u_rom_patch.bin"
38
39 #define MT76x2_RX_RING_SIZE 256
40 #define MT_RX_HEADROOM 32
41
42 #define MT_MAX_CHAINS 2
43
44 #define MT_CALIBRATE_INTERVAL HZ
45
46 #define MT_MAX_VIFS 8
47 #define MT_VIF_WCID(_n) (254 - ((_n) & 7))
48
49 #include "mt76.h"
50 #include "mt76x2_regs.h"
51 #include "mt76x2_mac.h"
52 #include "mt76x2_dfs.h"
53
54 DECLARE_EWMA(signal, 10, 8)
55
56 struct mt76x2_mcu {
57 struct mutex mutex;
58
59 wait_queue_head_t wait;
60 struct sk_buff_head res_q;
61 struct mt76u_buf res_u;
62
63 u32 msg_seq;
64 };
65
66 struct mt76x2_rx_freq_cal {
67 s8 high_gain[MT_MAX_CHAINS];
68 s8 rssi_offset[MT_MAX_CHAINS];
69 s8 lna_gain;
70 u32 mcu_gain;
71 };
72
73 struct mt76x2_calibration {
74 struct mt76x2_rx_freq_cal rx;
75
76 u8 agc_gain_init[MT_MAX_CHAINS];
77 u8 agc_gain_cur[MT_MAX_CHAINS];
78
79 u16 false_cca;
80 s8 avg_rssi_all;
81 s8 agc_gain_adjust;
82 s8 low_gain;
83
84 u8 temp;
85
86 bool init_cal_done;
87 bool tssi_cal_done;
88 bool tssi_comp_pending;
89 bool dpd_cal_done;
90 bool channel_cal_done;
91 };
92
93 struct mt76x2_dev {
94 struct mt76_dev mt76; /* must be first */
95
96 struct mac_address macaddr_list[8];
97
98 struct mutex mutex;
99
100 const u16 *beacon_offsets;
101 unsigned long wcid_mask[128 / BITS_PER_LONG];
102
103 int txpower_conf;
104 int txpower_cur;
105
106 u8 txdone_seq;
107 DECLARE_KFIFO_PTR(txstatus_fifo, struct mt76x2_tx_status);
108
109 struct mt76x2_mcu mcu;
110 struct sk_buff *rx_head;
111
112 struct tasklet_struct tx_tasklet;
113 struct tasklet_struct pre_tbtt_tasklet;
114 struct delayed_work cal_work;
115 struct delayed_work mac_work;
116
117 u32 aggr_stats[32];
118
119 struct mt76_wcid global_wcid;
120 struct mt76_wcid __rcu *wcid[128];
121
122 spinlock_t irq_lock;
123 u32 irqmask;
124
125 struct sk_buff *beacons[8];
126 u8 beacon_mask;
127 u8 beacon_data_mask;
128
129 u8 tbtt_count;
130 u16 beacon_int;
131
132 u16 chainmask;
133
134 u32 rxfilter;
135
136 struct mt76x2_calibration cal;
137
138 s8 target_power;
139 s8 target_power_delta[2];
140 struct mt76_rate_power rate_power;
141 bool enable_tpc;
142
143 u8 coverage_class;
144 u8 slottime;
145
146 struct mt76x2_dfs_pattern_detector dfs_pd;
147 };
148
149 struct mt76x2_vif {
150 u8 idx;
151
152 struct mt76_wcid group_wcid;
153 };
154
155 struct mt76x2_sta {
156 struct mt76_wcid wcid; /* must be first */
157
158 struct mt76x2_vif *vif;
159 struct mt76x2_tx_status status;
160 int n_frames;
161
162 struct ewma_signal rssi;
163 int inactive_count;
164 };
165
mt76x2_wait_for_mac(struct mt76x2_dev * dev)166 static inline bool mt76x2_wait_for_mac(struct mt76x2_dev *dev)
167 {
168 int i;
169
170 for (i = 0; i < 500; i++) {
171 switch (mt76_rr(dev, MT_MAC_CSR0)) {
172 case 0:
173 case ~0:
174 break;
175 default:
176 return true;
177 }
178 usleep_range(5000, 10000);
179 }
180 return false;
181 }
182
is_mt7612(struct mt76x2_dev * dev)183 static inline bool is_mt7612(struct mt76x2_dev *dev)
184 {
185 return mt76_chip(&dev->mt76) == 0x7612;
186 }
187
188 void mt76x2_set_irq_mask(struct mt76x2_dev *dev, u32 clear, u32 set);
189
mt76x2_channel_silent(struct mt76x2_dev * dev)190 static inline bool mt76x2_channel_silent(struct mt76x2_dev *dev)
191 {
192 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
193
194 return ((chan->flags & IEEE80211_CHAN_RADAR) &&
195 chan->dfs_state != NL80211_DFS_AVAILABLE);
196 }
197
mt76x2_irq_enable(struct mt76x2_dev * dev,u32 mask)198 static inline void mt76x2_irq_enable(struct mt76x2_dev *dev, u32 mask)
199 {
200 mt76x2_set_irq_mask(dev, 0, mask);
201 }
202
mt76x2_irq_disable(struct mt76x2_dev * dev,u32 mask)203 static inline void mt76x2_irq_disable(struct mt76x2_dev *dev, u32 mask)
204 {
205 mt76x2_set_irq_mask(dev, mask, 0);
206 }
207
mt76x2_wait_for_bbp(struct mt76x2_dev * dev)208 static inline bool mt76x2_wait_for_bbp(struct mt76x2_dev *dev)
209 {
210 return mt76_poll_msec(dev, MT_MAC_STATUS,
211 MT_MAC_STATUS_TX | MT_MAC_STATUS_RX,
212 0, 100);
213 }
214
wait_for_wpdma(struct mt76x2_dev * dev)215 static inline bool wait_for_wpdma(struct mt76x2_dev *dev)
216 {
217 return mt76_poll(dev, MT_WPDMA_GLO_CFG,
218 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
219 MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
220 0, 1000);
221 }
222
223 extern const struct ieee80211_ops mt76x2_ops;
224
225 extern struct ieee80211_rate mt76x2_rates[12];
226
227 struct mt76x2_dev *mt76x2_alloc_device(struct device *pdev);
228 int mt76x2_register_device(struct mt76x2_dev *dev);
229 void mt76x2_init_debugfs(struct mt76x2_dev *dev);
230 void mt76x2_init_device(struct mt76x2_dev *dev);
231
232 irqreturn_t mt76x2_irq_handler(int irq, void *dev_instance);
233 void mt76x2_phy_power_on(struct mt76x2_dev *dev);
234 int mt76x2_init_hardware(struct mt76x2_dev *dev);
235 void mt76x2_stop_hardware(struct mt76x2_dev *dev);
236 int mt76x2_eeprom_init(struct mt76x2_dev *dev);
237 int mt76x2_apply_calibration_data(struct mt76x2_dev *dev, int channel);
238 void mt76x2_set_tx_ackto(struct mt76x2_dev *dev);
239
240 void mt76x2_phy_set_antenna(struct mt76x2_dev *dev);
241 int mt76x2_phy_start(struct mt76x2_dev *dev);
242 int mt76x2_phy_set_channel(struct mt76x2_dev *dev,
243 struct cfg80211_chan_def *chandef);
244 int mt76x2_mac_get_rssi(struct mt76x2_dev *dev, s8 rssi, int chain);
245 void mt76x2_phy_calibrate(struct work_struct *work);
246 void mt76x2_phy_set_txpower(struct mt76x2_dev *dev);
247
248 int mt76x2_mcu_init(struct mt76x2_dev *dev);
249 int mt76x2_mcu_set_channel(struct mt76x2_dev *dev, u8 channel, u8 bw,
250 u8 bw_index, bool scan);
251 int mt76x2_mcu_set_radio_state(struct mt76x2_dev *dev, bool on);
252 int mt76x2_mcu_load_cr(struct mt76x2_dev *dev, u8 type, u8 temp_level,
253 u8 channel);
254 int mt76x2_mcu_cleanup(struct mt76x2_dev *dev);
255
256 int mt76x2_dma_init(struct mt76x2_dev *dev);
257 void mt76x2_dma_cleanup(struct mt76x2_dev *dev);
258
259 void mt76x2_cleanup(struct mt76x2_dev *dev);
260
261 int mt76x2_tx_queue_mcu(struct mt76x2_dev *dev, enum mt76_txq_id qid,
262 struct sk_buff *skb, int cmd, int seq);
263 void mt76x2_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
264 struct sk_buff *skb);
265 void mt76x2_tx_complete(struct mt76x2_dev *dev, struct sk_buff *skb);
266 int mt76x2_tx_prepare_skb(struct mt76_dev *mdev, void *txwi,
267 struct sk_buff *skb, struct mt76_queue *q,
268 struct mt76_wcid *wcid, struct ieee80211_sta *sta,
269 u32 *tx_info);
270 void mt76x2_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue *q,
271 struct mt76_queue_entry *e, bool flush);
272 void mt76x2_mac_set_tx_protection(struct mt76x2_dev *dev, u32 val);
273
274 void mt76x2_pre_tbtt_tasklet(unsigned long arg);
275
276 void mt76x2_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q);
277 void mt76x2_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
278 struct sk_buff *skb);
279
280 void mt76x2_sta_ps(struct mt76_dev *dev, struct ieee80211_sta *sta, bool ps);
281
282 void mt76x2_update_channel(struct mt76_dev *mdev);
283
284 s8 mt76x2_tx_get_max_txpwr_adj(struct mt76x2_dev *dev,
285 const struct ieee80211_tx_rate *rate);
286 s8 mt76x2_tx_get_txpwr_adj(struct mt76x2_dev *dev, s8 txpwr, s8 max_txpwr_adj);
287 void mt76x2_tx_set_txpwr_auto(struct mt76x2_dev *dev, s8 txpwr);
288
289 int mt76x2_insert_hdr_pad(struct sk_buff *skb);
290
291 bool mt76x2_mac_load_tx_status(struct mt76x2_dev *dev,
292 struct mt76x2_tx_status *stat);
293 void mt76x2_send_tx_status(struct mt76x2_dev *dev,
294 struct mt76x2_tx_status *stat, u8 *update);
295 void mt76x2_reset_wlan(struct mt76x2_dev *dev, bool enable);
296 void mt76x2_init_txpower(struct mt76x2_dev *dev,
297 struct ieee80211_supported_band *sband);
298 void mt76_write_mac_initvals(struct mt76x2_dev *dev);
299
300 int mt76x2_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
301 struct ieee80211_ampdu_params *params);
302 int mt76x2_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
303 struct ieee80211_sta *sta);
304 int mt76x2_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
305 struct ieee80211_sta *sta);
306 void mt76x2_remove_interface(struct ieee80211_hw *hw,
307 struct ieee80211_vif *vif);
308 int mt76x2_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
309 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
310 struct ieee80211_key_conf *key);
311 int mt76x2_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
312 u16 queue, const struct ieee80211_tx_queue_params *params);
313 void mt76x2_configure_filter(struct ieee80211_hw *hw,
314 unsigned int changed_flags,
315 unsigned int *total_flags, u64 multicast);
316 void mt76x2_txq_init(struct mt76x2_dev *dev, struct ieee80211_txq *txq);
317 void mt76x2_sta_rate_tbl_update(struct ieee80211_hw *hw,
318 struct ieee80211_vif *vif,
319 struct ieee80211_sta *sta);
320
321 void mt76x2_phy_set_txpower_regs(struct mt76x2_dev *dev,
322 enum nl80211_band band);
323 void mt76x2_configure_tx_delay(struct mt76x2_dev *dev,
324 enum nl80211_band band, u8 bw);
325 void mt76x2_phy_set_bw(struct mt76x2_dev *dev, int width, u8 ctrl);
326 void mt76x2_phy_set_band(struct mt76x2_dev *dev, int band, bool primary_upper);
327 int mt76x2_phy_get_min_avg_rssi(struct mt76x2_dev *dev);
328 void mt76x2_apply_gain_adj(struct mt76x2_dev *dev);
329
330 #endif
331
