1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4 */
5
6 #ifndef __MT7530_H
7 #define __MT7530_H
8
9 #define MT7530_NUM_PORTS 7
10 #define MT7530_CPU_PORT 6
11 #define MT7530_NUM_FDB_RECORDS 2048
12 #define MT7530_ALL_MEMBERS 0xff
13
14 enum mt753x_id {
15 ID_MT7530 = 0,
16 ID_MT7621 = 1,
17 ID_MT7531 = 2,
18 };
19
20 #define NUM_TRGMII_CTRL 5
21
22 #define TRGMII_BASE(x) (0x10000 + (x))
23
24 /* Registers to ethsys access */
25 #define ETHSYS_CLKCFG0 0x2c
26 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
27
28 #define SYSC_REG_RSTCTRL 0x34
29 #define RESET_MCM BIT(2)
30
31 /* Registers to mac forward control for unknown frames */
32 #define MT7530_MFC 0x10
33 #define BC_FFP(x) (((x) & 0xff) << 24)
34 #define UNM_FFP(x) (((x) & 0xff) << 16)
35 #define UNM_FFP_MASK UNM_FFP(~0)
36 #define UNU_FFP(x) (((x) & 0xff) << 8)
37 #define UNU_FFP_MASK UNU_FFP(~0)
38 #define CPU_EN BIT(7)
39 #define CPU_PORT(x) ((x) << 4)
40 #define CPU_MASK (0xf << 4)
41 #define MIRROR_EN BIT(3)
42 #define MIRROR_PORT(x) ((x) & 0x7)
43 #define MIRROR_MASK 0x7
44
45 /* Registers for CPU forward control */
46 #define MT7531_CFC 0x4
47 #define MT7531_MIRROR_EN BIT(19)
48 #define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
49 #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
50 #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
51 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
52
53 #define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
54 MT7531_CFC : MT7530_MFC)
55 #define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \
56 MT7531_MIRROR_EN : MIRROR_EN)
57 #define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \
58 MT7531_MIRROR_MASK : MIRROR_MASK)
59
60 /* Registers for BPDU and PAE frame control*/
61 #define MT753X_BPC 0x24
62 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
63
64 enum mt753x_bpdu_port_fw {
65 MT753X_BPDU_FOLLOW_MFC,
66 MT753X_BPDU_CPU_EXCLUDE = 4,
67 MT753X_BPDU_CPU_INCLUDE = 5,
68 MT753X_BPDU_CPU_ONLY = 6,
69 MT753X_BPDU_DROP = 7,
70 };
71
72 /* Registers for address table access */
73 #define MT7530_ATA1 0x74
74 #define STATIC_EMP 0
75 #define STATIC_ENT 3
76 #define MT7530_ATA2 0x78
77
78 /* Register for address table write data */
79 #define MT7530_ATWD 0x7c
80
81 /* Register for address table control */
82 #define MT7530_ATC 0x80
83 #define ATC_HASH (((x) & 0xfff) << 16)
84 #define ATC_BUSY BIT(15)
85 #define ATC_SRCH_END BIT(14)
86 #define ATC_SRCH_HIT BIT(13)
87 #define ATC_INVALID BIT(12)
88 #define ATC_MAT(x) (((x) & 0xf) << 8)
89 #define ATC_MAT_MACTAB ATC_MAT(0)
90
91 enum mt7530_fdb_cmd {
92 MT7530_FDB_READ = 0,
93 MT7530_FDB_WRITE = 1,
94 MT7530_FDB_FLUSH = 2,
95 MT7530_FDB_START = 4,
96 MT7530_FDB_NEXT = 5,
97 };
98
99 /* Registers for table search read address */
100 #define MT7530_TSRA1 0x84
101 #define MAC_BYTE_0 24
102 #define MAC_BYTE_1 16
103 #define MAC_BYTE_2 8
104 #define MAC_BYTE_3 0
105 #define MAC_BYTE_MASK 0xff
106
107 #define MT7530_TSRA2 0x88
108 #define MAC_BYTE_4 24
109 #define MAC_BYTE_5 16
110 #define CVID 0
111 #define CVID_MASK 0xfff
112
113 #define MT7530_ATRD 0x8C
114 #define AGE_TIMER 24
115 #define AGE_TIMER_MASK 0xff
116 #define PORT_MAP 4
117 #define PORT_MAP_MASK 0xff
118 #define ENT_STATUS 2
119 #define ENT_STATUS_MASK 0x3
120
121 /* Register for vlan table control */
122 #define MT7530_VTCR 0x90
123 #define VTCR_BUSY BIT(31)
124 #define VTCR_INVALID BIT(16)
125 #define VTCR_FUNC(x) (((x) & 0xf) << 12)
126 #define VTCR_VID ((x) & 0xfff)
127
128 enum mt7530_vlan_cmd {
129 /* Read/Write the specified VID entry from VAWD register based
130 * on VID.
131 */
132 MT7530_VTCR_RD_VID = 0,
133 MT7530_VTCR_WR_VID = 1,
134 };
135
136 /* Register for setup vlan and acl write data */
137 #define MT7530_VAWD1 0x94
138 #define PORT_STAG BIT(31)
139 /* Independent VLAN Learning */
140 #define IVL_MAC BIT(30)
141 /* Per VLAN Egress Tag Control */
142 #define VTAG_EN BIT(28)
143 /* VLAN Member Control */
144 #define PORT_MEM(x) (((x) & 0xff) << 16)
145 /* VLAN Entry Valid */
146 #define VLAN_VALID BIT(0)
147 #define PORT_MEM_SHFT 16
148 #define PORT_MEM_MASK 0xff
149
150 #define MT7530_VAWD2 0x98
151 /* Egress Tag Control */
152 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
153 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
154
155 enum mt7530_vlan_egress_attr {
156 MT7530_VLAN_EGRESS_UNTAG = 0,
157 MT7530_VLAN_EGRESS_TAG = 2,
158 MT7530_VLAN_EGRESS_STACK = 3,
159 };
160
161 /* Register for port STP state control */
162 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
163 #define FID_PST(x) ((x) & 0x3)
164 #define FID_PST_MASK FID_PST(0x3)
165
166 enum mt7530_stp_state {
167 MT7530_STP_DISABLED = 0,
168 MT7530_STP_BLOCKING = 1,
169 MT7530_STP_LISTENING = 1,
170 MT7530_STP_LEARNING = 2,
171 MT7530_STP_FORWARDING = 3
172 };
173
174 /* Register for port control */
175 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
176 #define PORT_TX_MIR BIT(9)
177 #define PORT_RX_MIR BIT(8)
178 #define PORT_VLAN(x) ((x) & 0x3)
179
180 enum mt7530_port_mode {
181 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
182 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
183
184 /* Fallback Mode: Forward received frames with ingress ports that do
185 * not belong to the VLAN member. Frames whose VID is not listed on
186 * the VLAN table are forwarded by the PCR_MATRIX members.
187 */
188 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
189
190 /* Security Mode: Discard any frame due to ingress membership
191 * violation or VID missed on the VLAN table.
192 */
193 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
194 };
195
196 #define PCR_MATRIX(x) (((x) & 0xff) << 16)
197 #define PORT_PRI(x) (((x) & 0x7) << 24)
198 #define EG_TAG(x) (((x) & 0x3) << 28)
199 #define PCR_MATRIX_MASK PCR_MATRIX(0xff)
200 #define PCR_MATRIX_CLR PCR_MATRIX(0)
201 #define PCR_PORT_VLAN_MASK PORT_VLAN(3)
202
203 /* Register for port security control */
204 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
205 #define SA_DIS BIT(4)
206
207 /* Register for port vlan control */
208 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
209 #define PORT_SPEC_TAG BIT(5)
210 #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
211 #define PVC_EG_TAG_MASK PVC_EG_TAG(7)
212 #define VLAN_ATTR(x) (((x) & 0x3) << 6)
213 #define VLAN_ATTR_MASK VLAN_ATTR(3)
214
215 enum mt7530_vlan_port_eg_tag {
216 MT7530_VLAN_EG_DISABLED = 0,
217 MT7530_VLAN_EG_CONSISTENT = 1,
218 };
219
220 enum mt7530_vlan_port_attr {
221 MT7530_VLAN_USER = 0,
222 MT7530_VLAN_TRANSPARENT = 3,
223 };
224
225 #define STAG_VPID (((x) & 0xffff) << 16)
226
227 /* Register for port port-and-protocol based vlan 1 control */
228 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
229 #define G0_PORT_VID(x) (((x) & 0xfff) << 0)
230 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
231 #define G0_PORT_VID_DEF G0_PORT_VID(1)
232
233 /* Register for port MAC control register */
234 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
235 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
236 #define PMCR_EXT_PHY BIT(17)
237 #define PMCR_MAC_MODE BIT(16)
238 #define PMCR_FORCE_MODE BIT(15)
239 #define PMCR_TX_EN BIT(14)
240 #define PMCR_RX_EN BIT(13)
241 #define PMCR_BACKOFF_EN BIT(9)
242 #define PMCR_BACKPR_EN BIT(8)
243 #define PMCR_TX_FC_EN BIT(5)
244 #define PMCR_RX_FC_EN BIT(4)
245 #define PMCR_FORCE_SPEED_1000 BIT(3)
246 #define PMCR_FORCE_SPEED_100 BIT(2)
247 #define PMCR_FORCE_FDX BIT(1)
248 #define PMCR_FORCE_LNK BIT(0)
249 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
250 PMCR_FORCE_SPEED_1000)
251 #define MT7531_FORCE_LNK BIT(31)
252 #define MT7531_FORCE_SPD BIT(30)
253 #define MT7531_FORCE_DPX BIT(29)
254 #define MT7531_FORCE_RX_FC BIT(28)
255 #define MT7531_FORCE_TX_FC BIT(27)
256 #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
257 MT7531_FORCE_SPD | \
258 MT7531_FORCE_DPX | \
259 MT7531_FORCE_RX_FC | \
260 MT7531_FORCE_TX_FC)
261 #define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
262 MT7531_FORCE_MODE : \
263 PMCR_FORCE_MODE)
264 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
265 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
266 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
267 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
268 #define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
269 PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
270 PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
271 PMCR_TX_EN | PMCR_RX_EN | \
272 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
273 PMCR_FORCE_SPEED_1000 | \
274 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
275
276 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
277 #define PMSR_EEE1G BIT(7)
278 #define PMSR_EEE100M BIT(6)
279 #define PMSR_RX_FC BIT(5)
280 #define PMSR_TX_FC BIT(4)
281 #define PMSR_SPEED_1000 BIT(3)
282 #define PMSR_SPEED_100 BIT(2)
283 #define PMSR_SPEED_10 0x00
284 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
285 #define PMSR_DPX BIT(1)
286 #define PMSR_LINK BIT(0)
287
288 /* Register for port debug count */
289 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
290 #define MT7531_DIS_CLR BIT(31)
291
292 /* Register for MIB */
293 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
294 #define MT7530_MIB_CCR 0x4fe0
295 #define CCR_MIB_ENABLE BIT(31)
296 #define CCR_RX_OCT_CNT_GOOD BIT(7)
297 #define CCR_RX_OCT_CNT_BAD BIT(6)
298 #define CCR_TX_OCT_CNT_GOOD BIT(5)
299 #define CCR_TX_OCT_CNT_BAD BIT(4)
300 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
301 CCR_RX_OCT_CNT_BAD | \
302 CCR_TX_OCT_CNT_GOOD | \
303 CCR_TX_OCT_CNT_BAD)
304 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
305 CCR_RX_OCT_CNT_GOOD | \
306 CCR_RX_OCT_CNT_BAD | \
307 CCR_TX_OCT_CNT_GOOD | \
308 CCR_TX_OCT_CNT_BAD)
309
310 /* MT7531 SGMII register group */
311 #define MT7531_SGMII_REG_BASE 0x5000
312 #define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
313 ((p) - 5) * 0x1000 + (r))
314
315 /* Register forSGMII PCS_CONTROL_1 */
316 #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
317 #define MT7531_SGMII_LINK_STATUS BIT(18)
318 #define MT7531_SGMII_AN_ENABLE BIT(12)
319 #define MT7531_SGMII_AN_RESTART BIT(9)
320
321 /* Register for SGMII PCS_SPPED_ABILITY */
322 #define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
323 #define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0)
324 #define MT7531_SGMII_TX_CONFIG BIT(0)
325
326 /* Register for SGMII_MODE */
327 #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
328 #define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
329 #define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1)
330 #define MT7531_SGMII_FORCE_DUPLEX BIT(4)
331 #define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2)
332 #define MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
333 #define MT7531_SGMII_FORCE_SPEED_100 BIT(2)
334 #define MT7531_SGMII_FORCE_SPEED_10 0
335 #define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1)
336
337 enum mt7531_sgmii_force_duplex {
338 MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
339 MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
340 };
341
342 /* Fields of QPHY_PWR_STATE_CTRL */
343 #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
344 #define MT7531_SGMII_PHYA_PWD BIT(4)
345
346 /* Values of SGMII SPEED */
347 #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
348 #define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3))
349 #define MT7531_RG_TPHY_SPEED_1_25G 0x0
350 #define MT7531_RG_TPHY_SPEED_3_125G BIT(2)
351
352 /* Register for system reset */
353 #define MT7530_SYS_CTRL 0x7000
354 #define SYS_CTRL_PHY_RST BIT(2)
355 #define SYS_CTRL_SW_RST BIT(1)
356 #define SYS_CTRL_REG_RST BIT(0)
357
358 /* Register for PHY Indirect Access Control */
359 #define MT7531_PHY_IAC 0x701C
360 #define MT7531_PHY_ACS_ST BIT(31)
361 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
362 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
363 #define MT7531_MDIO_CMD_MASK (0x3 << 18)
364 #define MT7531_MDIO_ST_MASK (0x3 << 16)
365 #define MT7531_MDIO_RW_DATA_MASK (0xffff)
366 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
367 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
368 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
369 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
370 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
371
372 enum mt7531_phy_iac_cmd {
373 MT7531_MDIO_ADDR = 0,
374 MT7531_MDIO_WRITE = 1,
375 MT7531_MDIO_READ = 2,
376 MT7531_MDIO_READ_CL45 = 3,
377 };
378
379 /* MDIO_ST: MDIO start field */
380 enum mt7531_mdio_st {
381 MT7531_MDIO_ST_CL45 = 0,
382 MT7531_MDIO_ST_CL22 = 1,
383 };
384
385 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
386 MT7531_MDIO_CMD(MT7531_MDIO_READ))
387 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
388 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
389 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
390 MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
391 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
392 MT7531_MDIO_CMD(MT7531_MDIO_READ))
393 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
394 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
395
396 /* Register for RGMII clock phase */
397 #define MT7531_CLKGEN_CTRL 0x7500
398 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
399 #define CLK_SKEW_OUT_MASK GENMASK(9, 8)
400 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
401 #define CLK_SKEW_IN_MASK GENMASK(7, 6)
402 #define RXCLK_NO_DELAY BIT(5)
403 #define TXCLK_NO_REVERSE BIT(4)
404 #define GP_MODE(x) (((x) & 0x3) << 1)
405 #define GP_MODE_MASK GENMASK(2, 1)
406 #define GP_CLK_EN BIT(0)
407
408 enum mt7531_gp_mode {
409 MT7531_GP_MODE_RGMII = 0,
410 MT7531_GP_MODE_MII = 1,
411 MT7531_GP_MODE_REV_MII = 2
412 };
413
414 enum mt7531_clk_skew {
415 MT7531_CLK_SKEW_NO_CHG = 0,
416 MT7531_CLK_SKEW_DLY_100PPS = 1,
417 MT7531_CLK_SKEW_DLY_200PPS = 2,
418 MT7531_CLK_SKEW_REVERSE = 3,
419 };
420
421 /* Register for hw trap status */
422 #define MT7530_HWTRAP 0x7800
423 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
424 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
425 #define HWTRAP_XTAL_40MHZ (BIT(10))
426 #define HWTRAP_XTAL_20MHZ (BIT(9))
427
428 #define MT7531_HWTRAP 0x7800
429 #define HWTRAP_XTAL_FSEL_MASK BIT(7)
430 #define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
431 #define HWTRAP_XTAL_FSEL_40MHZ 0
432 /* Unique fields of (M)HWSTRAP for MT7531 */
433 #define XTAL_FSEL_S 7
434 #define XTAL_FSEL_M BIT(7)
435 #define PHY_EN BIT(6)
436 #define CHG_STRAP BIT(8)
437
438 /* Register for hw trap modification */
439 #define MT7530_MHWTRAP 0x7804
440 #define MHWTRAP_PHY0_SEL BIT(20)
441 #define MHWTRAP_MANUAL BIT(16)
442 #define MHWTRAP_P5_MAC_SEL BIT(13)
443 #define MHWTRAP_P6_DIS BIT(8)
444 #define MHWTRAP_P5_RGMII_MODE BIT(7)
445 #define MHWTRAP_P5_DIS BIT(6)
446 #define MHWTRAP_PHY_ACCESS BIT(5)
447
448 /* Register for TOP signal control */
449 #define MT7530_TOP_SIG_CTRL 0x7808
450 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
451
452 #define MT7531_TOP_SIG_SR 0x780c
453 #define PAD_DUAL_SGMII_EN BIT(1)
454 #define PAD_MCM_SMI_EN BIT(0)
455
456 #define MT7530_IO_DRV_CR 0x7810
457 #define P5_IO_CLK_DRV(x) ((x) & 0x3)
458 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
459
460 #define MT7531_CHIP_REV 0x781C
461
462 #define MT7531_PLLGP_EN 0x7820
463 #define EN_COREPLL BIT(2)
464 #define SW_CLKSW BIT(1)
465 #define SW_PLLGP BIT(0)
466
467 #define MT7530_P6ECR 0x7830
468 #define P6_INTF_MODE_MASK 0x3
469 #define P6_INTF_MODE(x) ((x) & 0x3)
470
471 #define MT7531_PLLGP_CR0 0x78a8
472 #define RG_COREPLL_EN BIT(22)
473 #define RG_COREPLL_POSDIV_S 23
474 #define RG_COREPLL_POSDIV_M 0x3800000
475 #define RG_COREPLL_SDM_PCW_S 1
476 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
477 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
478
479 /* Registers for RGMII and SGMII PLL clock */
480 #define MT7531_ANA_PLLGP_CR2 0x78b0
481 #define MT7531_ANA_PLLGP_CR5 0x78bc
482
483 /* Registers for TRGMII on the both side */
484 #define MT7530_TRGMII_RCK_CTRL 0x7a00
485 #define RX_RST BIT(31)
486 #define RXC_DQSISEL BIT(30)
487 #define DQSI1_TAP_MASK (0x7f << 8)
488 #define DQSI0_TAP_MASK 0x7f
489 #define DQSI1_TAP(x) (((x) & 0x7f) << 8)
490 #define DQSI0_TAP(x) ((x) & 0x7f)
491
492 #define MT7530_TRGMII_RCK_RTT 0x7a04
493 #define DQS1_GATE BIT(31)
494 #define DQS0_GATE BIT(30)
495
496 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
497 #define BSLIP_EN BIT(31)
498 #define EDGE_CHK BIT(30)
499 #define RD_TAP_MASK 0x7f
500 #define RD_TAP(x) ((x) & 0x7f)
501
502 #define MT7530_TRGMII_TXCTRL 0x7a40
503 #define TRAIN_TXEN BIT(31)
504 #define TXC_INV BIT(30)
505 #define TX_RST BIT(28)
506
507 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
508 #define TD_DM_DRVP(x) ((x) & 0xf)
509 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
510
511 #define MT7530_TRGMII_TCK_CTRL 0x7a78
512 #define TCK_TAP(x) (((x) & 0xf) << 8)
513
514 #define MT7530_P5RGMIIRXCR 0x7b00
515 #define CSR_RGMII_EDGE_ALIGN BIT(8)
516 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
517
518 #define MT7530_P5RGMIITXCR 0x7b04
519 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
520
521 /* Registers for GPIO mode */
522 #define MT7531_GPIO_MODE0 0x7c0c
523 #define MT7531_GPIO0_MASK GENMASK(3, 0)
524 #define MT7531_GPIO0_INTERRUPT 1
525
526 #define MT7531_GPIO_MODE1 0x7c10
527 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
528 #define MT7531_EXT_P_MDC_11 (2 << 12)
529 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
530 #define MT7531_EXT_P_MDIO_12 (2 << 16)
531
532 #define MT7530_CREV 0x7ffc
533 #define CHIP_NAME_SHIFT 16
534 #define MT7530_ID 0x7530
535
536 #define MT7531_CREV 0x781C
537 #define CHIP_REV_M 0x0f
538 #define MT7531_ID 0x7531
539
540 /* Registers for core PLL access through mmd indirect */
541 #define CORE_PLL_GROUP2 0x401
542 #define RG_SYSPLL_EN_NORMAL BIT(15)
543 #define RG_SYSPLL_VODEN BIT(14)
544 #define RG_SYSPLL_LF BIT(13)
545 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
546 #define RG_SYSPLL_LVROD_EN BIT(10)
547 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
548 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
549 #define RG_SYSPLL_FBKSEL BIT(4)
550 #define RT_SYSPLL_EN_AFE_OLT BIT(0)
551
552 #define CORE_PLL_GROUP4 0x403
553 #define RG_SYSPLL_DDSFBK_EN BIT(12)
554 #define RG_SYSPLL_BIAS_EN BIT(11)
555 #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
556 #define MT7531_PHY_PLL_OFF BIT(5)
557 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
558
559 #define MT753X_CTRL_PHY_ADDR 0
560
561 #define CORE_PLL_GROUP5 0x404
562 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
563
564 #define CORE_PLL_GROUP6 0x405
565 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
566
567 #define CORE_PLL_GROUP7 0x406
568 #define RG_LCDDS_PWDB BIT(15)
569 #define RG_LCDDS_ISO_EN BIT(13)
570 #define RG_LCCDS_C(x) (((x) & 0x7) << 4)
571 #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
572
573 #define CORE_PLL_GROUP10 0x409
574 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
575
576 #define CORE_PLL_GROUP11 0x40a
577 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
578
579 #define CORE_GSWPLL_GRP1 0x40d
580 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
581 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
582 #define RG_GSWPLL_EN_PRE BIT(11)
583 #define RG_GSWPLL_FBKSEL BIT(10)
584 #define RG_GSWPLL_BP BIT(9)
585 #define RG_GSWPLL_BR BIT(8)
586 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
587
588 #define CORE_GSWPLL_GRP2 0x40e
589 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
590 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
591
592 #define CORE_TRGMII_GSW_CLK_CG 0x410
593 #define REG_GSWCK_EN BIT(0)
594 #define REG_TRGMIICK_EN BIT(1)
595
596 #define MIB_DESC(_s, _o, _n) \
597 { \
598 .size = (_s), \
599 .offset = (_o), \
600 .name = (_n), \
601 }
602
603 struct mt7530_mib_desc {
604 unsigned int size;
605 unsigned int offset;
606 const char *name;
607 };
608
609 struct mt7530_fdb {
610 u16 vid;
611 u8 port_mask;
612 u8 aging;
613 u8 mac[6];
614 bool noarp;
615 };
616
617 /* struct mt7530_port - This is the main data structure for holding the state
618 * of the port.
619 * @enable: The status used for show port is enabled or not.
620 * @pm: The matrix used to show all connections with the port.
621 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
622 * untagged frames will be assigned to the related VLAN.
623 * @vlan_filtering: The flags indicating whether the port that can recognize
624 * VLAN-tagged frames.
625 */
626 struct mt7530_port {
627 bool enable;
628 u32 pm;
629 u16 pvid;
630 };
631
632 /* Port 5 interface select definitions */
633 enum p5_interface_select {
634 P5_DISABLED = 0,
635 P5_INTF_SEL_PHY_P0,
636 P5_INTF_SEL_PHY_P4,
637 P5_INTF_SEL_GMAC5,
638 P5_INTF_SEL_GMAC5_SGMII,
639 };
640
p5_intf_modes(unsigned int p5_interface)641 static const char *p5_intf_modes(unsigned int p5_interface)
642 {
643 switch (p5_interface) {
644 case P5_DISABLED:
645 return "DISABLED";
646 case P5_INTF_SEL_PHY_P0:
647 return "PHY P0";
648 case P5_INTF_SEL_PHY_P4:
649 return "PHY P4";
650 case P5_INTF_SEL_GMAC5:
651 return "GMAC5";
652 case P5_INTF_SEL_GMAC5_SGMII:
653 return "GMAC5_SGMII";
654 default:
655 return "unknown";
656 }
657 }
658
659 /* struct mt753x_info - This is the main data structure for holding the specific
660 * part for each supported device
661 * @sw_setup: Holding the handler to a device initialization
662 * @phy_read: Holding the way reading PHY port
663 * @phy_write: Holding the way writing PHY port
664 * @pad_setup: Holding the way setting up the bus pad for a certain
665 * MAC port
666 * @phy_mode_supported: Check if the PHY type is being supported on a certain
667 * port
668 * @mac_port_validate: Holding the way to set addition validate type for a
669 * certan MAC port
670 * @mac_port_get_state: Holding the way getting the MAC/PCS state for a certain
671 * MAC port
672 * @mac_port_config: Holding the way setting up the PHY attribute to a
673 * certain MAC port
674 * @mac_pcs_an_restart Holding the way restarting PCS autonegotiation for a
675 * certain MAC port
676 * @mac_pcs_link_up: Holding the way setting up the PHY attribute to the pcs
677 * of the certain MAC port
678 */
679 struct mt753x_info {
680 enum mt753x_id id;
681
682 int (*sw_setup)(struct dsa_switch *ds);
683 int (*phy_read)(struct dsa_switch *ds, int port, int regnum);
684 int (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val);
685 int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
686 int (*cpu_port_config)(struct dsa_switch *ds, int port);
687 bool (*phy_mode_supported)(struct dsa_switch *ds, int port,
688 const struct phylink_link_state *state);
689 void (*mac_port_validate)(struct dsa_switch *ds, int port,
690 unsigned long *supported);
691 int (*mac_port_get_state)(struct dsa_switch *ds, int port,
692 struct phylink_link_state *state);
693 int (*mac_port_config)(struct dsa_switch *ds, int port,
694 unsigned int mode,
695 phy_interface_t interface);
696 void (*mac_pcs_an_restart)(struct dsa_switch *ds, int port);
697 void (*mac_pcs_link_up)(struct dsa_switch *ds, int port,
698 unsigned int mode, phy_interface_t interface,
699 int speed, int duplex);
700 };
701
702 /* struct mt7530_priv - This is the main data structure for holding the state
703 * of the driver
704 * @dev: The device pointer
705 * @ds: The pointer to the dsa core structure
706 * @bus: The bus used for the device and built-in PHY
707 * @rstc: The pointer to reset control used by MCM
708 * @core_pwr: The power supplied into the core
709 * @io_pwr: The power supplied into the I/O
710 * @reset: The descriptor for GPIO line tied to its reset pin
711 * @mcm: Flag for distinguishing if standalone IC or module
712 * coupling
713 * @ports: Holding the state among ports
714 * @reg_mutex: The lock for protecting among process accessing
715 * registers
716 * @p6_interface Holding the current port 6 interface
717 * @p5_intf_sel: Holding the current port 5 interface select
718 */
719 struct mt7530_priv {
720 struct device *dev;
721 struct dsa_switch *ds;
722 struct mii_bus *bus;
723 struct reset_control *rstc;
724 struct regulator *core_pwr;
725 struct regulator *io_pwr;
726 struct gpio_desc *reset;
727 const struct mt753x_info *info;
728 unsigned int id;
729 bool mcm;
730 phy_interface_t p6_interface;
731 phy_interface_t p5_interface;
732 unsigned int p5_intf_sel;
733 u8 mirror_rx;
734 u8 mirror_tx;
735
736 struct mt7530_port ports[MT7530_NUM_PORTS];
737 /* protect among processes for registers access*/
738 struct mutex reg_mutex;
739 };
740
741 struct mt7530_hw_vlan_entry {
742 int port;
743 u8 old_members;
744 bool untagged;
745 };
746
mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry * e,int port,bool untagged)747 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
748 int port, bool untagged)
749 {
750 e->port = port;
751 e->untagged = untagged;
752 }
753
754 typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
755 struct mt7530_hw_vlan_entry *);
756
757 struct mt7530_hw_stats {
758 const char *string;
759 u16 reg;
760 u8 sizeof_stat;
761 };
762
763 struct mt7530_dummy_poll {
764 struct mt7530_priv *priv;
765 u32 reg;
766 };
767
INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll * p,struct mt7530_priv * priv,u32 reg)768 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
769 struct mt7530_priv *priv, u32 reg)
770 {
771 p->priv = priv;
772 p->reg = reg;
773 }
774
775 #endif /* __MT7530_H */
776
