1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77470 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8 #include <linux/errno.h>
9 #include <linux/kernel.h>
10
11 #include "sh_pfc.h"
12
13 #define CPU_ALL_GP(fn, sfx) \
14 PORT_GP_4(0, fn, sfx), \
15 PORT_GP_1(0, 4, fn, sfx), \
16 PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
17 PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
18 PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
19 PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
20 PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
21 PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
22 PORT_GP_1(0, 11, fn, sfx), \
23 PORT_GP_1(0, 12, fn, sfx), \
24 PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
33 PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
34 PORT_GP_23(1, fn, sfx), \
35 PORT_GP_32(2, fn, sfx), \
36 PORT_GP_17(3, fn, sfx), \
37 PORT_GP_1(3, 27, fn, sfx), \
38 PORT_GP_1(3, 28, fn, sfx), \
39 PORT_GP_1(3, 29, fn, sfx), \
40 PORT_GP_14(4, fn, sfx), \
41 PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
42 PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
43 PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
44 PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
45 PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
46 PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
47 PORT_GP_1(4, 20, fn, sfx), \
48 PORT_GP_1(4, 21, fn, sfx), \
49 PORT_GP_1(4, 22, fn, sfx), \
50 PORT_GP_1(4, 23, fn, sfx), \
51 PORT_GP_1(4, 24, fn, sfx), \
52 PORT_GP_1(4, 25, fn, sfx), \
53 PORT_GP_32(5, fn, sfx)
54
55 enum {
56 PINMUX_RESERVED = 0,
57
58 PINMUX_DATA_BEGIN,
59 GP_ALL(DATA),
60 PINMUX_DATA_END,
61
62 PINMUX_FUNCTION_BEGIN,
63 GP_ALL(FN),
64
65 /* GPSR0 */
66 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, FN_CLKOUT,
67 FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8, FN_IP0_15_12, FN_IP0_19_16,
68 FN_IP0_23_20, FN_IP0_27_24, FN_IP0_31_28, FN_MMC0_CLK_SDHI1_CLK,
69 FN_MMC0_CMD_SDHI1_CMD, FN_MMC0_D0_SDHI1_D0, FN_MMC0_D1_SDHI1_D1,
70 FN_MMC0_D2_SDHI1_D2, FN_MMC0_D3_SDHI1_D3, FN_IP1_3_0,
71 FN_IP1_7_4, FN_MMC0_D6, FN_MMC0_D7,
72
73 /* GPSR1 */
74 FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20, FN_IP1_27_24,
75 FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
76 FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24, FN_IP2_31_28, FN_IP3_3_0,
77 FN_IP3_7_4, FN_IP3_11_8, FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20,
78 FN_IP3_27_24, FN_IP3_31_28, FN_IP4_3_0,
79
80 /* GPSR2 */
81 FN_IP4_7_4, FN_IP4_11_8, FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20,
82 FN_IP4_27_24, FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8,
83 FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24, FN_IP5_31_28,
84 FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8, FN_IP6_15_12, FN_IP6_19_16,
85 FN_IP6_23_20, FN_IP6_27_24, FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4,
86 FN_IP7_11_8, FN_IP7_15_12, FN_IP7_19_16, FN_IP7_23_20, FN_IP7_27_24,
87 FN_IP7_31_28, FN_IP8_3_0,
88
89 /* GPSR3 */
90 FN_IP8_7_4, FN_IP8_11_8, FN_IP8_15_12, FN_IP8_19_16, FN_IP8_23_20,
91 FN_IP8_27_24, FN_IP8_31_28, FN_IP9_3_0, FN_IP9_7_4, FN_IP9_11_8,
92 FN_IP9_15_12, FN_IP9_19_16, FN_IP9_23_20, FN_IP9_27_24, FN_IP9_31_28,
93 FN_IP10_3_0, FN_IP10_7_4, FN_IP10_11_8, FN_IP10_15_12, FN_IP10_19_16,
94
95 /* GPSR4 */
96 FN_IP10_23_20, FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4,
97 FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20,
98 FN_IP11_27_24, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4, FN_IP12_11_8,
99 FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20, FN_IP12_27_24,
100 FN_IP12_31_28, FN_IP13_3_0, FN_IP13_7_4, FN_IP13_11_8, FN_IP13_15_12,
101 FN_IP13_19_16, FN_IP13_23_20, FN_IP13_27_24,
102
103 /* GPSR5 */
104 FN_IP13_31_28, FN_IP14_3_0, FN_IP14_7_4, FN_IP14_11_8, FN_IP14_15_12,
105 FN_IP14_19_16, FN_IP14_23_20, FN_IP14_27_24, FN_IP14_31_28,
106 FN_IP15_3_0, FN_IP15_7_4, FN_IP15_11_8, FN_IP15_15_12, FN_IP15_19_16,
107 FN_IP15_23_20, FN_IP15_27_24, FN_IP15_31_28, FN_IP16_3_0, FN_IP16_7_4,
108 FN_IP16_11_8, FN_IP16_15_12, FN_IP16_19_16, FN_IP16_23_20,
109 FN_IP16_27_24, FN_IP16_31_28, FN_IP17_3_0, FN_IP17_7_4, FN_IP17_11_8,
110 FN_IP17_15_12, FN_IP17_19_16, FN_IP17_23_20, FN_IP17_27_24,
111
112 /* IPSR0 */
113 FN_SD0_CLK, FN_SSI_SCK1_C, FN_RX3_C,
114 FN_SD0_CMD, FN_SSI_WS1_C, FN_TX3_C,
115 FN_SD0_DAT0, FN_SSI_SDATA1_C, FN_RX4_E,
116 FN_SD0_DAT1, FN_SSI_SCK0129_B, FN_TX4_E,
117 FN_SD0_DAT2, FN_SSI_WS0129_B, FN_RX5_E,
118 FN_SD0_DAT3, FN_SSI_SDATA0_B, FN_TX5_E,
119 FN_SD0_CD, FN_CAN0_RX_A,
120 FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A,
121
122 /* IPSR1 */
123 FN_MMC0_D4, FN_SD1_CD,
124 FN_MMC0_D5, FN_SD1_WP,
125 FN_D0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B,
126 FN_D1, FN_SDA3_B, FN_TX5_B, FN_MSIOF2_TXD_C, FN_SSI_WS5_B,
127 FN_D2, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, FN_MSIOF2_SCK_C, FN_SSI_SCK5_B,
128 FN_D3, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, FN_MSIOF2_SYNC_C,
129 FN_D4, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C,
130 FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B,
131
132 /* IPSR2 */
133 FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C,
134 FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
135 FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C,
136 FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D,
137 FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B,
138 FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B,
139 FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, FN_CAN_CLK_C,
140 FN_D13, FN_MSIOF2_SYNC_A, FN_RX4_C,
141
142 /* IPSR3 */
143 FN_D14, FN_MSIOF2_SS1, FN_TX4_C, FN_CAN1_RX_B, FN_AVB_AVTP_CAPTURE_A,
144 FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, FN_CAN1_TX_B, FN_IRQ2, FN_AVB_AVTP_MATCH_A,
145 FN_QSPI0_SPCLK, FN_WE0_N,
146 FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N,
147 FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N,
148 FN_QSPI0_IO2, FN_CS0_N,
149 FN_QSPI0_IO3, FN_RD_N,
150 FN_QSPI0_SSL, FN_WE1_N,
151
152 /* IPSR4 */
153 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A,
154 FN_DU0_DR0, FN_RX5_C, FN_SCL2_D, FN_A0,
155 FN_DU0_DR1, FN_TX5_C, FN_SDA2_D, FN_A1,
156 FN_DU0_DR2, FN_RX0_D, FN_SCL0_E, FN_A2,
157 FN_DU0_DR3, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, FN_A3,
158 FN_DU0_DR4, FN_RX1_D, FN_A4,
159 FN_DU0_DR5, FN_TX1_D, FN_PWM1_B, FN_A5,
160 FN_DU0_DR6, FN_RX2_C, FN_A6,
161
162 /* IPSR5 */
163 FN_DU0_DR7, FN_TX2_C, FN_PWM2_B, FN_A7,
164 FN_DU0_DG0, FN_RX3_B, FN_SCL3_D, FN_A8,
165 FN_DU0_DG1, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, FN_A9,
166 FN_DU0_DG2, FN_RX4_D, FN_A10,
167 FN_DU0_DG3, FN_TX4_D, FN_PWM4_B, FN_A11,
168 FN_DU0_DG4, FN_HRX0_A, FN_A12,
169 FN_DU0_DG5, FN_HTX0_A, FN_PWM5_B, FN_A13,
170 FN_DU0_DG6, FN_HRX1_C, FN_A14,
171
172 /* IPSR6 */
173 FN_DU0_DG7, FN_HTX1_C, FN_PWM6_B, FN_A15,
174 FN_DU0_DB0, FN_SCL4_D, FN_CAN0_RX_C, FN_A16,
175 FN_DU0_DB1, FN_SDA4_D, FN_CAN0_TX_C, FN_A17,
176 FN_DU0_DB2, FN_HCTS0_N, FN_A18,
177 FN_DU0_DB3, FN_HRTS0_N, FN_A19,
178 FN_DU0_DB4, FN_HCTS1_N_C, FN_A20,
179 FN_DU0_DB5, FN_HRTS1_N_C, FN_A21,
180 FN_DU0_DB6, FN_A22,
181
182 /* IPSR7 */
183 FN_DU0_DB7, FN_A23,
184 FN_DU0_DOTCLKIN, FN_A24,
185 FN_DU0_DOTCLKOUT0, FN_A25,
186 FN_DU0_DOTCLKOUT1, FN_MSIOF2_RXD_B, FN_CS1_N_A26,
187 FN_DU0_EXHSYNC_DU0_HSYNC, FN_MSIOF2_TXD_B, FN_DREQ0_N,
188 FN_DU0_EXVSYNC_DU0_VSYNC, FN_MSIOF2_SYNC_B, FN_DACK0,
189 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_MSIOF2_SCK_B, FN_DRACK0,
190 FN_DU0_DISP, FN_CAN1_RX_C,
191
192 /* IPSR8 */
193 FN_DU0_CDE, FN_CAN1_TX_C,
194 FN_VI1_CLK, FN_AVB_RX_CLK, FN_ETH_REF_CLK,
195 FN_VI1_DATA0, FN_AVB_RX_DV, FN_ETH_CRS_DV,
196 FN_VI1_DATA1, FN_AVB_RXD0, FN_ETH_RXD0,
197 FN_VI1_DATA2, FN_AVB_RXD1, FN_ETH_RXD1,
198 FN_VI1_DATA3, FN_AVB_RXD2, FN_ETH_MDIO,
199 FN_VI1_DATA4, FN_AVB_RXD3, FN_ETH_RX_ER,
200 FN_VI1_DATA5, FN_AVB_RXD4, FN_ETH_LINK,
201
202 /* IPSR9 */
203 FN_VI1_DATA6, FN_AVB_RXD5, FN_ETH_TXD1,
204 FN_VI1_DATA7, FN_AVB_RXD6, FN_ETH_TX_EN,
205 FN_VI1_CLKENB, FN_SCL3_A, FN_AVB_RXD7, FN_ETH_MAGIC,
206 FN_VI1_FIELD, FN_SDA3_A, FN_AVB_RX_ER, FN_ETH_TXD0,
207 FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, FN_AVB_GTXREFCLK, FN_ETH_MDC,
208 FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_CLK,
209 FN_VI1_DATA8, FN_SCL2_B, FN_AVB_TX_EN,
210 FN_VI1_DATA9, FN_SDA2_B, FN_AVB_TXD0,
211
212 /* IPSR10 */
213 FN_VI1_DATA10, FN_CAN0_RX_B, FN_AVB_TXD1,
214 FN_VI1_DATA11, FN_CAN0_TX_B, FN_AVB_TXD2,
215 FN_AVB_TXD3, FN_AUDIO_CLKA_B, FN_SSI_SCK1_D, FN_RX5_F, FN_MSIOF0_RXD_B,
216 FN_AVB_TXD4, FN_AUDIO_CLKB_B, FN_SSI_WS1_D, FN_TX5_F, FN_MSIOF0_TXD_B,
217 FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, FN_SSI_SDATA1_D, FN_MSIOF0_SCK_B,
218 FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6, FN_CAN1_RX_D, FN_MSIOF0_SYNC_B,
219 FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, FN_CAN1_TX_D, FN_DVC_MUTE,
220 FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, FN_SSI_SCK6_B, FN_VI0_G0,
221
222 /* IPSR11 */
223 FN_SDA1_A, FN_TX4_A, FN_DU1_DR1, FN_SSI_WS6_B, FN_VI0_G1,
224 FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
225 FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
226 FN_MSIOF0_SCK_A, FN_IRQ0, FN_DU1_DR4, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
227 FN_MSIOF0_SYNC_A, FN_PWM1_A, FN_DU1_DR5, FN_QSPI1_IO2, FN_SSI_SDATA7_B,
228 FN_MSIOF0_SS1_A, FN_DU1_DR6, FN_QSPI1_IO3, FN_SSI_SDATA8_B,
229 FN_MSIOF0_SS2_A, FN_DU1_DR7, FN_QSPI1_SSL,
230 FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A,
231
232 /* IPSR12 */
233 FN_HTX1_A, FN_SDA4_A, FN_DU1_DG1, FN_TX0_A,
234 FN_HCTS1_N_A, FN_PWM2_A, FN_DU1_DG2, FN_REMOCON_B,
235 FN_HRTS1_N_A, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1,
236 FN_SD2_CLK, FN_HSCK1, FN_DU1_DG4, FN_SSI_SCK1_B,
237 FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, FN_SSI_SCK2_B, FN_PWM3_A,
238 FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, FN_SSI_SDATA1_B,
239 FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
240 FN_SD2_DAT2, FN_RX2_A, FN_DU1_DB0, FN_SSI_SDATA2_B,
241
242 /* IPSR13 */
243 FN_SD2_DAT3, FN_TX2_A, FN_DU1_DB1, FN_SSI_WS9_B,
244 FN_SD2_CD, FN_SCIF2_SCK_A, FN_DU1_DB2, FN_SSI_SCK9_B,
245 FN_SD2_WP, FN_SCIF3_SCK, FN_DU1_DB3, FN_SSI_SDATA9_B,
246 FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B,
247 FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
248 FN_SCL2_A, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, FN_SSI_SCK4_B,
249 FN_SDA2_A, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
250 FN_SSI_SCK5_A, FN_DU1_DOTCLKOUT1,
251
252 /* IPSR14 */
253 FN_SSI_WS5_A, FN_SCL3_C, FN_DU1_DOTCLKIN,
254 FN_SSI_SDATA5_A, FN_SDA3_C, FN_DU1_DOTCLKOUT0,
255 FN_SSI_SCK6_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
256 FN_SSI_WS6_A, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC,
257 FN_SSI_SDATA6_A, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC,
258 FN_SSI_SCK78_A, FN_SDA4_E, FN_DU1_DISP,
259 FN_SSI_WS78_A, FN_SCL4_E, FN_DU1_CDE,
260 FN_SSI_SDATA7_A, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_VI0_G5,
261
262 /* IPSR15 */
263 FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, FN_VI0_G6,
264 FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, FN_VI0_G7,
265 FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, FN_VI0_R0,
266 FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, FN_DACK1, FN_VI0_R1,
267 FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, FN_CAN1_RX_A, FN_DREQ1_N, FN_VI0_R2,
268 FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, FN_CAN1_TX_A, FN_DREQ2_N, FN_VI0_R3,
269 FN_SSI_SCK4_A, FN_AVB_MAGIC, FN_VI0_R4,
270 FN_SSI_WS4_A, FN_AVB_PHY_INT, FN_VI0_R5,
271
272 /* IPSR16 */
273 FN_SSI_SDATA4_A, FN_AVB_CRS, FN_VI0_R6,
274 FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, FN_DACK2, FN_VI0_CLK, FN_AVB_COL,
275 FN_SSI_SDATA8_A, FN_RX1_B, FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7,
276 FN_SSI_WS1_A, FN_TX1_B, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0,
277 FN_SSI_SDATA1_A, FN_HRX1_B, FN_VI0_DATA1_VI0_B1,
278 FN_SSI_SCK2_A, FN_HTX1_B, FN_AVB_TXD7, FN_VI0_DATA2_VI0_B2,
279 FN_SSI_WS2_A, FN_HCTS1_N_B, FN_AVB_TX_ER, FN_VI0_DATA3_VI0_B3,
280 FN_SSI_SDATA2_A, FN_HRTS1_N_B, FN_VI0_DATA4_VI0_B4,
281
282 /* IPSR17 */
283 FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, FN_EX_WAIT1, FN_VI0_DATA5_VI0_B5,
284 FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, FN_VI0_DATA6_VI0_B6,
285 FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, FN_VI0_DATA7_VI0_B7,
286 FN_AUDIO_CLKA_A, FN_SCL0_B, FN_VI0_CLKENB,
287 FN_AUDIO_CLKB_A, FN_SDA0_B, FN_VI0_FIELD,
288 FN_AUDIO_CLKC_A, FN_SCL4_B, FN_VI0_HSYNC_N,
289 FN_AUDIO_CLKOUT_A, FN_SDA4_B, FN_VI0_VSYNC_N,
290
291 /* MOD_SEL0 */
292 FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
293 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
294 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
295 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
296 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, FN_SEL_I2C04_4,
297 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, FN_SEL_I2C03_4,
298 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
299 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4,
300 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4,
301 FN_SEL_AVB_0, FN_SEL_AVB_1,
302
303 /* MOD_SEL1 */
304 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
305 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, FN_SEL_SCIF5_4, FN_SEL_SCIF5_5,
306 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, FN_SEL_SCIF4_4,
307 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
308 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
309 FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
310 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
311 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
312 FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2,
313 FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
314 FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
315 FN_SEL_RCN_0, FN_SEL_RCN_1,
316 FN_SEL_TMU2_0, FN_SEL_TMU2_1,
317 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
318 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
319 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
320
321 /* MOD_SEL2 */
322 FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2,
323 FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2,
324 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
325 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
326 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
327 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
328 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
329 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
330 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
331 FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
332 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
333 PINMUX_FUNCTION_END,
334
335 PINMUX_MARK_BEGIN,
336
337 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
338 CLKOUT_MARK, MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
339 MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
340 MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D6_MARK,
341 MMC0_D7_MARK,
342
343 /* IPSR0 */
344 SD0_CLK_MARK, SSI_SCK1_C_MARK, RX3_C_MARK,
345 SD0_CMD_MARK, SSI_WS1_C_MARK, TX3_C_MARK,
346 SD0_DAT0_MARK, SSI_SDATA1_C_MARK, RX4_E_MARK,
347 SD0_DAT1_MARK, SSI_SCK0129_B_MARK, TX4_E_MARK,
348 SD0_DAT2_MARK, SSI_WS0129_B_MARK, RX5_E_MARK,
349 SD0_DAT3_MARK, SSI_SDATA0_B_MARK, TX5_E_MARK,
350 SD0_CD_MARK, CAN0_RX_A_MARK,
351 SD0_WP_MARK, IRQ7_MARK, CAN0_TX_A_MARK,
352
353 /* IPSR1 */
354 MMC0_D4_MARK, SD1_CD_MARK,
355 MMC0_D5_MARK, SD1_WP_MARK,
356 D0_MARK, SCL3_B_MARK, RX5_B_MARK, IRQ4_MARK, MSIOF2_RXD_C_MARK, SSI_SDATA5_B_MARK,
357 D1_MARK, SDA3_B_MARK, TX5_B_MARK, MSIOF2_TXD_C_MARK, SSI_WS5_B_MARK,
358 D2_MARK, RX4_B_MARK, SCL0_D_MARK, PWM1_C_MARK, MSIOF2_SCK_C_MARK, SSI_SCK5_B_MARK,
359 D3_MARK, TX4_B_MARK, SDA0_D_MARK, PWM0_A_MARK, MSIOF2_SYNC_C_MARK,
360 D4_MARK, IRQ3_MARK, TCLK1_A_MARK, PWM6_C_MARK,
361 D5_MARK, HRX2_MARK, SCL1_B_MARK, PWM2_C_MARK, TCLK2_B_MARK,
362
363 /* IPSR2 */
364 D6_MARK, HTX2_MARK, SDA1_B_MARK, PWM4_C_MARK,
365 D7_MARK, HSCK2_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
366 D8_MARK, HCTS2_N_MARK, RX1_C_MARK, SCL1_D_MARK, PWM3_C_MARK,
367 D9_MARK, HRTS2_N_MARK, TX1_C_MARK, SDA1_D_MARK,
368 D10_MARK, MSIOF2_RXD_A_MARK, HRX0_B_MARK,
369 D11_MARK, MSIOF2_TXD_A_MARK, HTX0_B_MARK,
370 D12_MARK, MSIOF2_SCK_A_MARK, HSCK0_MARK, CAN_CLK_C_MARK,
371 D13_MARK, MSIOF2_SYNC_A_MARK, RX4_C_MARK,
372
373 /* IPSR3 */
374 D14_MARK, MSIOF2_SS1_MARK, TX4_C_MARK, CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_A_MARK,
375 D15_MARK, MSIOF2_SS2_MARK, PWM4_A_MARK, CAN1_TX_B_MARK, IRQ2_MARK, AVB_AVTP_MATCH_A_MARK,
376 QSPI0_SPCLK_MARK, WE0_N_MARK,
377 QSPI0_MOSI_QSPI0_IO0_MARK, BS_N_MARK,
378 QSPI0_MISO_QSPI0_IO1_MARK, RD_WR_N_MARK,
379 QSPI0_IO2_MARK, CS0_N_MARK,
380 QSPI0_IO3_MARK, RD_N_MARK,
381 QSPI0_SSL_MARK, WE1_N_MARK,
382
383 /* IPSR4 */
384 EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_A_MARK,
385 DU0_DR0_MARK, RX5_C_MARK, SCL2_D_MARK, A0_MARK,
386 DU0_DR1_MARK, TX5_C_MARK, SDA2_D_MARK, A1_MARK,
387 DU0_DR2_MARK, RX0_D_MARK, SCL0_E_MARK, A2_MARK,
388 DU0_DR3_MARK, TX0_D_MARK, SDA0_E_MARK, PWM0_B_MARK, A3_MARK,
389 DU0_DR4_MARK, RX1_D_MARK, A4_MARK,
390 DU0_DR5_MARK, TX1_D_MARK, PWM1_B_MARK, A5_MARK,
391 DU0_DR6_MARK, RX2_C_MARK, A6_MARK,
392
393 /* IPSR5 */
394 DU0_DR7_MARK, TX2_C_MARK, PWM2_B_MARK, A7_MARK,
395 DU0_DG0_MARK, RX3_B_MARK, SCL3_D_MARK, A8_MARK,
396 DU0_DG1_MARK, TX3_B_MARK, SDA3_D_MARK, PWM3_B_MARK, A9_MARK,
397 DU0_DG2_MARK, RX4_D_MARK, A10_MARK,
398 DU0_DG3_MARK, TX4_D_MARK, PWM4_B_MARK, A11_MARK,
399 DU0_DG4_MARK, HRX0_A_MARK, A12_MARK,
400 DU0_DG5_MARK, HTX0_A_MARK, PWM5_B_MARK, A13_MARK,
401 DU0_DG6_MARK, HRX1_C_MARK, A14_MARK,
402
403 /* IPSR6 */
404 DU0_DG7_MARK, HTX1_C_MARK, PWM6_B_MARK, A15_MARK,
405 DU0_DB0_MARK, SCL4_D_MARK, CAN0_RX_C_MARK, A16_MARK,
406 DU0_DB1_MARK, SDA4_D_MARK, CAN0_TX_C_MARK, A17_MARK,
407 DU0_DB2_MARK, HCTS0_N_MARK, A18_MARK,
408 DU0_DB3_MARK, HRTS0_N_MARK, A19_MARK,
409 DU0_DB4_MARK, HCTS1_N_C_MARK, A20_MARK,
410 DU0_DB5_MARK, HRTS1_N_C_MARK, A21_MARK,
411 DU0_DB6_MARK, A22_MARK,
412
413 /* IPSR7 */
414 DU0_DB7_MARK, A23_MARK,
415 DU0_DOTCLKIN_MARK, A24_MARK,
416 DU0_DOTCLKOUT0_MARK, A25_MARK,
417 DU0_DOTCLKOUT1_MARK, MSIOF2_RXD_B_MARK, CS1_N_A26_MARK,
418 DU0_EXHSYNC_DU0_HSYNC_MARK, MSIOF2_TXD_B_MARK, DREQ0_N_MARK,
419 DU0_EXVSYNC_DU0_VSYNC_MARK, MSIOF2_SYNC_B_MARK, DACK0_MARK,
420 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, MSIOF2_SCK_B_MARK, DRACK0_MARK,
421 DU0_DISP_MARK, CAN1_RX_C_MARK,
422
423 /* IPSR8 */
424 DU0_CDE_MARK, CAN1_TX_C_MARK,
425 VI1_CLK_MARK, AVB_RX_CLK_MARK, ETH_REF_CLK_MARK,
426 VI1_DATA0_MARK, AVB_RX_DV_MARK, ETH_CRS_DV_MARK,
427 VI1_DATA1_MARK, AVB_RXD0_MARK, ETH_RXD0_MARK,
428 VI1_DATA2_MARK, AVB_RXD1_MARK, ETH_RXD1_MARK,
429 VI1_DATA3_MARK, AVB_RXD2_MARK, ETH_MDIO_MARK,
430 VI1_DATA4_MARK, AVB_RXD3_MARK, ETH_RX_ER_MARK,
431 VI1_DATA5_MARK, AVB_RXD4_MARK, ETH_LINK_MARK,
432
433 /* IPSR9 */
434 VI1_DATA6_MARK, AVB_RXD5_MARK, ETH_TXD1_MARK,
435 VI1_DATA7_MARK, AVB_RXD6_MARK, ETH_TX_EN_MARK,
436 VI1_CLKENB_MARK, SCL3_A_MARK, AVB_RXD7_MARK, ETH_MAGIC_MARK,
437 VI1_FIELD_MARK, SDA3_A_MARK, AVB_RX_ER_MARK, ETH_TXD0_MARK,
438 VI1_HSYNC_N_MARK, RX0_B_MARK, SCL0_C_MARK, AVB_GTXREFCLK_MARK, ETH_MDC_MARK,
439 VI1_VSYNC_N_MARK, TX0_B_MARK, SDA0_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_CLK_MARK,
440 VI1_DATA8_MARK, SCL2_B_MARK, AVB_TX_EN_MARK,
441 VI1_DATA9_MARK, SDA2_B_MARK, AVB_TXD0_MARK,
442
443 /* IPSR10 */
444 VI1_DATA10_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK,
445 VI1_DATA11_MARK, CAN0_TX_B_MARK, AVB_TXD2_MARK,
446 AVB_TXD3_MARK, AUDIO_CLKA_B_MARK, SSI_SCK1_D_MARK, RX5_F_MARK, MSIOF0_RXD_B_MARK,
447 AVB_TXD4_MARK, AUDIO_CLKB_B_MARK, SSI_WS1_D_MARK, TX5_F_MARK, MSIOF0_TXD_B_MARK,
448 AVB_TXD5_MARK, SCIF_CLK_B_MARK, AUDIO_CLKC_B_MARK, SSI_SDATA1_D_MARK, MSIOF0_SCK_B_MARK,
449 SCL0_A_MARK, RX0_C_MARK, PWM5_A_MARK, TCLK1_B_MARK, AVB_TXD6_MARK, CAN1_RX_D_MARK, MSIOF0_SYNC_B_MARK,
450 SDA0_A_MARK, TX0_C_MARK, IRQ5_MARK, CAN_CLK_A_MARK, AVB_GTX_CLK_MARK, CAN1_TX_D_MARK, DVC_MUTE_MARK,
451 SCL1_A_MARK, RX4_A_MARK, PWM5_D_MARK, DU1_DR0_MARK, SSI_SCK6_B_MARK, VI0_G0_MARK,
452
453 /* IPSR11 */
454 SDA1_A_MARK, TX4_A_MARK, DU1_DR1_MARK, SSI_WS6_B_MARK, VI0_G1_MARK,
455 MSIOF0_RXD_A_MARK, RX5_A_MARK, SCL2_C_MARK, DU1_DR2_MARK, QSPI1_MOSI_QSPI1_IO0_MARK, SSI_SDATA6_B_MARK, VI0_G2_MARK,
456 MSIOF0_TXD_A_MARK, TX5_A_MARK, SDA2_C_MARK, DU1_DR3_MARK, QSPI1_MISO_QSPI1_IO1_MARK, SSI_WS78_B_MARK, VI0_G3_MARK,
457 MSIOF0_SCK_A_MARK, IRQ0_MARK, DU1_DR4_MARK, QSPI1_SPCLK_MARK, SSI_SCK78_B_MARK, VI0_G4_MARK,
458 MSIOF0_SYNC_A_MARK, PWM1_A_MARK, DU1_DR5_MARK, QSPI1_IO2_MARK, SSI_SDATA7_B_MARK,
459 MSIOF0_SS1_A_MARK, DU1_DR6_MARK, QSPI1_IO3_MARK, SSI_SDATA8_B_MARK,
460 MSIOF0_SS2_A_MARK, DU1_DR7_MARK, QSPI1_SSL_MARK,
461 HRX1_A_MARK, SCL4_A_MARK, PWM6_A_MARK, DU1_DG0_MARK, RX0_A_MARK,
462
463 /* IPSR12 */
464 HTX1_A_MARK, SDA4_A_MARK, DU1_DG1_MARK, TX0_A_MARK,
465 HCTS1_N_A_MARK, PWM2_A_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
466 HRTS1_N_A_MARK, DU1_DG3_MARK, SSI_WS1_B_MARK, IRQ1_MARK,
467 SD2_CLK_MARK, HSCK1_MARK, DU1_DG4_MARK, SSI_SCK1_B_MARK,
468 SD2_CMD_MARK, SCIF1_SCK_A_MARK, TCLK2_A_MARK, DU1_DG5_MARK, SSI_SCK2_B_MARK, PWM3_A_MARK,
469 SD2_DAT0_MARK, RX1_A_MARK, SCL1_E_MARK, DU1_DG6_MARK, SSI_SDATA1_B_MARK,
470 SD2_DAT1_MARK, TX1_A_MARK, SDA1_E_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
471 SD2_DAT2_MARK, RX2_A_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
472
473 /* IPSR13 */
474 SD2_DAT3_MARK, TX2_A_MARK, DU1_DB1_MARK, SSI_WS9_B_MARK,
475 SD2_CD_MARK, SCIF2_SCK_A_MARK, DU1_DB2_MARK, SSI_SCK9_B_MARK,
476 SD2_WP_MARK, SCIF3_SCK_MARK, DU1_DB3_MARK, SSI_SDATA9_B_MARK,
477 RX3_A_MARK, SCL1_C_MARK, MSIOF1_RXD_B_MARK, DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SDATA4_B_MARK,
478 TX3_A_MARK, SDA1_C_MARK, MSIOF1_TXD_B_MARK, DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
479 SCL2_A_MARK, MSIOF1_SCK_B_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, SSI_SCK4_B_MARK,
480 SDA2_A_MARK, MSIOF1_SYNC_B_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
481 SSI_SCK5_A_MARK, DU1_DOTCLKOUT1_MARK,
482
483 /* IPSR14 */
484 SSI_WS5_A_MARK, SCL3_C_MARK, DU1_DOTCLKIN_MARK,
485 SSI_SDATA5_A_MARK, SDA3_C_MARK, DU1_DOTCLKOUT0_MARK,
486 SSI_SCK6_A_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
487 SSI_WS6_A_MARK, SCL4_C_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
488 SSI_SDATA6_A_MARK, SDA4_C_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,
489 SSI_SCK78_A_MARK, SDA4_E_MARK, DU1_DISP_MARK,
490 SSI_WS78_A_MARK, SCL4_E_MARK, DU1_CDE_MARK,
491 SSI_SDATA7_A_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, VI0_G5_MARK,
492
493 /* IPSR15 */
494 SSI_SCK0129_A_MARK, MSIOF1_RXD_A_MARK, RX5_D_MARK, VI0_G6_MARK,
495 SSI_WS0129_A_MARK, MSIOF1_TXD_A_MARK, TX5_D_MARK, VI0_G7_MARK,
496 SSI_SDATA0_A_MARK, MSIOF1_SYNC_A_MARK, PWM0_C_MARK, VI0_R0_MARK,
497 SSI_SCK34_MARK, MSIOF1_SCK_A_MARK, AVB_MDC_MARK, DACK1_MARK, VI0_R1_MARK,
498 SSI_WS34_MARK, MSIOF1_SS1_A_MARK, AVB_MDIO_MARK, CAN1_RX_A_MARK, DREQ1_N_MARK, VI0_R2_MARK,
499 SSI_SDATA3_MARK, MSIOF1_SS2_A_MARK, AVB_LINK_MARK, CAN1_TX_A_MARK, DREQ2_N_MARK, VI0_R3_MARK,
500 SSI_SCK4_A_MARK, AVB_MAGIC_MARK, VI0_R4_MARK,
501 SSI_WS4_A_MARK, AVB_PHY_INT_MARK, VI0_R5_MARK,
502
503 /* IPSR16 */
504 SSI_SDATA4_A_MARK, AVB_CRS_MARK, VI0_R6_MARK,
505 SSI_SCK1_A_MARK, SCIF1_SCK_B_MARK, PWM1_D_MARK, IRQ9_MARK, REMOCON_A_MARK, DACK2_MARK, VI0_CLK_MARK, AVB_COL_MARK,
506 SSI_SDATA8_A_MARK, RX1_B_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_B_MARK, VI0_R7_MARK,
507 SSI_WS1_A_MARK, TX1_B_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_B_MARK, VI0_DATA0_VI0_B0_MARK,
508 SSI_SDATA1_A_MARK, HRX1_B_MARK, VI0_DATA1_VI0_B1_MARK,
509 SSI_SCK2_A_MARK, HTX1_B_MARK, AVB_TXD7_MARK, VI0_DATA2_VI0_B2_MARK,
510 SSI_WS2_A_MARK, HCTS1_N_B_MARK, AVB_TX_ER_MARK, VI0_DATA3_VI0_B3_MARK,
511 SSI_SDATA2_A_MARK, HRTS1_N_B_MARK, VI0_DATA4_VI0_B4_MARK,
512
513 /* IPSR17 */
514 SSI_SCK9_A_MARK, RX2_B_MARK, SCL3_E_MARK, EX_WAIT1_MARK, VI0_DATA5_VI0_B5_MARK,
515 SSI_WS9_A_MARK, TX2_B_MARK, SDA3_E_MARK, VI0_DATA6_VI0_B6_MARK,
516 SSI_SDATA9_A_MARK, SCIF2_SCK_B_MARK, PWM2_D_MARK, VI0_DATA7_VI0_B7_MARK,
517 AUDIO_CLKA_A_MARK, SCL0_B_MARK, VI0_CLKENB_MARK,
518 AUDIO_CLKB_A_MARK, SDA0_B_MARK, VI0_FIELD_MARK,
519 AUDIO_CLKC_A_MARK, SCL4_B_MARK, VI0_HSYNC_N_MARK,
520 AUDIO_CLKOUT_A_MARK, SDA4_B_MARK, VI0_VSYNC_N_MARK,
521
522 PINMUX_MARK_END,
523 };
524
525 static const u16 pinmux_data[] = {
526 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
527
528 PINMUX_SINGLE(USB0_PWEN),
529 PINMUX_SINGLE(USB0_OVC),
530 PINMUX_SINGLE(USB1_PWEN),
531 PINMUX_SINGLE(USB1_OVC),
532 PINMUX_SINGLE(CLKOUT),
533 PINMUX_SINGLE(MMC0_CLK_SDHI1_CLK),
534 PINMUX_SINGLE(MMC0_CMD_SDHI1_CMD),
535 PINMUX_SINGLE(MMC0_D0_SDHI1_D0),
536 PINMUX_SINGLE(MMC0_D1_SDHI1_D1),
537 PINMUX_SINGLE(MMC0_D2_SDHI1_D2),
538 PINMUX_SINGLE(MMC0_D3_SDHI1_D3),
539 PINMUX_SINGLE(MMC0_D6),
540 PINMUX_SINGLE(MMC0_D7),
541
542 /* IPSR0 */
543 PINMUX_IPSR_GPSR(IP0_3_0, SD0_CLK),
544 PINMUX_IPSR_MSEL(IP0_3_0, SSI_SCK1_C, SEL_SSI1_2),
545 PINMUX_IPSR_MSEL(IP0_3_0, RX3_C, SEL_SCIF3_2),
546 PINMUX_IPSR_GPSR(IP0_7_4, SD0_CMD),
547 PINMUX_IPSR_MSEL(IP0_7_4, SSI_WS1_C, SEL_SSI1_2),
548 PINMUX_IPSR_MSEL(IP0_7_4, TX3_C, SEL_SCIF3_2),
549 PINMUX_IPSR_GPSR(IP0_11_8, SD0_DAT0),
550 PINMUX_IPSR_MSEL(IP0_11_8, SSI_SDATA1_C, SEL_SSI1_2),
551 PINMUX_IPSR_MSEL(IP0_11_8, RX4_E, SEL_SCIF4_4),
552 PINMUX_IPSR_GPSR(IP0_15_12, SD0_DAT1),
553 PINMUX_IPSR_MSEL(IP0_15_12, SSI_SCK0129_B, SEL_SSI0_1),
554 PINMUX_IPSR_MSEL(IP0_15_12, TX4_E, SEL_SCIF4_4),
555 PINMUX_IPSR_GPSR(IP0_19_16, SD0_DAT2),
556 PINMUX_IPSR_MSEL(IP0_19_16, SSI_WS0129_B, SEL_SSI0_1),
557 PINMUX_IPSR_MSEL(IP0_19_16, RX5_E, SEL_SCIF5_4),
558 PINMUX_IPSR_GPSR(IP0_23_20, SD0_DAT3),
559 PINMUX_IPSR_MSEL(IP0_23_20, SSI_SDATA0_B, SEL_SSI0_1),
560 PINMUX_IPSR_MSEL(IP0_23_20, TX5_E, SEL_SCIF5_4),
561 PINMUX_IPSR_GPSR(IP0_27_24, SD0_CD),
562 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_RX_A, SEL_CAN0_0),
563 PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
564 PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
565 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),
566
567 /* IPSR1 */
568 PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4),
569 PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD),
570 PINMUX_IPSR_GPSR(IP1_7_4, MMC0_D5),
571 PINMUX_IPSR_GPSR(IP1_7_4, SD1_WP),
572 PINMUX_IPSR_GPSR(IP1_11_8, D0),
573 PINMUX_IPSR_MSEL(IP1_11_8, SCL3_B, SEL_I2C03_1),
574 PINMUX_IPSR_MSEL(IP1_11_8, RX5_B, SEL_SCIF5_1),
575 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
576 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF2_RXD_C, SEL_MSIOF2_2),
577 PINMUX_IPSR_MSEL(IP1_11_8, SSI_SDATA5_B, SEL_SSI5_1),
578 PINMUX_IPSR_GPSR(IP1_15_12, D1),
579 PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
580 PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
581 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
582 PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
583 PINMUX_IPSR_GPSR(IP1_19_16, D2),
584 PINMUX_IPSR_MSEL(IP1_19_16, RX4_B, SEL_SCIF4_1),
585 PINMUX_IPSR_MSEL(IP1_19_16, SCL0_D, SEL_I2C00_3),
586 PINMUX_IPSR_GPSR(IP1_19_16, PWM1_C),
587 PINMUX_IPSR_MSEL(IP1_19_16, MSIOF2_SCK_C, SEL_MSIOF2_2),
588 PINMUX_IPSR_MSEL(IP1_19_16, SSI_SCK5_B, SEL_SSI5_1),
589 PINMUX_IPSR_GPSR(IP1_23_20, D3),
590 PINMUX_IPSR_MSEL(IP1_23_20, TX4_B, SEL_SCIF4_1),
591 PINMUX_IPSR_MSEL(IP1_23_20, SDA0_D, SEL_I2C00_3),
592 PINMUX_IPSR_GPSR(IP1_23_20, PWM0_A),
593 PINMUX_IPSR_MSEL(IP1_23_20, MSIOF2_SYNC_C, SEL_MSIOF2_2),
594 PINMUX_IPSR_GPSR(IP1_27_24, D4),
595 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
596 PINMUX_IPSR_MSEL(IP1_27_24, TCLK1_A, SEL_TMU1_0),
597 PINMUX_IPSR_GPSR(IP1_27_24, PWM6_C),
598 PINMUX_IPSR_GPSR(IP1_31_28, D5),
599 PINMUX_IPSR_GPSR(IP1_31_28, HRX2),
600 PINMUX_IPSR_MSEL(IP1_31_28, SCL1_B, SEL_I2C01_1),
601 PINMUX_IPSR_GPSR(IP1_31_28, PWM2_C),
602 PINMUX_IPSR_MSEL(IP1_31_28, TCLK2_B, SEL_TMU2_1),
603
604 /* IPSR2 */
605 PINMUX_IPSR_GPSR(IP2_3_0, D6),
606 PINMUX_IPSR_GPSR(IP2_3_0, HTX2),
607 PINMUX_IPSR_MSEL(IP2_3_0, SDA1_B, SEL_I2C01_1),
608 PINMUX_IPSR_GPSR(IP2_3_0, PWM4_C),
609 PINMUX_IPSR_GPSR(IP2_7_4, D7),
610 PINMUX_IPSR_GPSR(IP2_7_4, HSCK2),
611 PINMUX_IPSR_MSEL(IP2_7_4, SCIF1_SCK_C, SEL_SCIF1_2),
612 PINMUX_IPSR_GPSR(IP2_7_4, IRQ6),
613 PINMUX_IPSR_GPSR(IP2_7_4, PWM5_C),
614 PINMUX_IPSR_GPSR(IP2_11_8, D8),
615 PINMUX_IPSR_GPSR(IP2_11_8, HCTS2_N),
616 PINMUX_IPSR_MSEL(IP2_11_8, RX1_C, SEL_SCIF1_2),
617 PINMUX_IPSR_MSEL(IP2_11_8, SCL1_D, SEL_I2C01_3),
618 PINMUX_IPSR_GPSR(IP2_11_8, PWM3_C),
619 PINMUX_IPSR_GPSR(IP2_15_12, D9),
620 PINMUX_IPSR_GPSR(IP2_15_12, HRTS2_N),
621 PINMUX_IPSR_MSEL(IP2_15_12, TX1_C, SEL_SCIF1_2),
622 PINMUX_IPSR_MSEL(IP2_15_12, SDA1_D, SEL_I2C01_3),
623 PINMUX_IPSR_GPSR(IP2_19_16, D10),
624 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF2_RXD_A, SEL_MSIOF2_0),
625 PINMUX_IPSR_MSEL(IP2_19_16, HRX0_B, SEL_HSCIF0_1),
626 PINMUX_IPSR_GPSR(IP2_23_20, D11),
627 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_TXD_A, SEL_MSIOF2_0),
628 PINMUX_IPSR_MSEL(IP2_23_20, HTX0_B, SEL_HSCIF0_1),
629 PINMUX_IPSR_GPSR(IP2_27_24, D12),
630 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SCK_A, SEL_MSIOF2_0),
631 PINMUX_IPSR_GPSR(IP2_27_24, HSCK0),
632 PINMUX_IPSR_MSEL(IP2_27_24, CAN_CLK_C, SEL_CANCLK_2),
633 PINMUX_IPSR_GPSR(IP2_31_28, D13),
634 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
635 PINMUX_IPSR_MSEL(IP2_31_28, RX4_C, SEL_SCIF4_2),
636
637 /* IPSR3 */
638 PINMUX_IPSR_GPSR(IP3_3_0, D14),
639 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SS1),
640 PINMUX_IPSR_MSEL(IP3_3_0, TX4_C, SEL_SCIF4_2),
641 PINMUX_IPSR_MSEL(IP3_3_0, CAN1_RX_B, SEL_CAN1_1),
642 PINMUX_IPSR_MSEL(IP3_3_0, AVB_AVTP_CAPTURE_A, SEL_AVB_0),
643 PINMUX_IPSR_GPSR(IP3_7_4, D15),
644 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2),
645 PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A),
646 PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1),
647 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
648 PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0),
649 PINMUX_IPSR_GPSR(IP3_11_8, QSPI0_SPCLK),
650 PINMUX_IPSR_GPSR(IP3_11_8, WE0_N),
651 PINMUX_IPSR_GPSR(IP3_15_12, QSPI0_MOSI_QSPI0_IO0),
652 PINMUX_IPSR_GPSR(IP3_15_12, BS_N),
653 PINMUX_IPSR_GPSR(IP3_19_16, QSPI0_MISO_QSPI0_IO1),
654 PINMUX_IPSR_GPSR(IP3_19_16, RD_WR_N),
655 PINMUX_IPSR_GPSR(IP3_23_20, QSPI0_IO2),
656 PINMUX_IPSR_GPSR(IP3_23_20, CS0_N),
657 PINMUX_IPSR_GPSR(IP3_27_24, QSPI0_IO3),
658 PINMUX_IPSR_GPSR(IP3_27_24, RD_N),
659 PINMUX_IPSR_GPSR(IP3_31_28, QSPI0_SSL),
660 PINMUX_IPSR_GPSR(IP3_31_28, WE1_N),
661
662 /* IPSR4 */
663 PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0),
664 PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1),
665 PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0),
666 PINMUX_IPSR_GPSR(IP4_7_4, DU0_DR0),
667 PINMUX_IPSR_MSEL(IP4_7_4, RX5_C, SEL_SCIF5_2),
668 PINMUX_IPSR_MSEL(IP4_7_4, SCL2_D, SEL_I2C02_3),
669 PINMUX_IPSR_GPSR(IP4_7_4, A0),
670 PINMUX_IPSR_GPSR(IP4_11_8, DU0_DR1),
671 PINMUX_IPSR_MSEL(IP4_11_8, TX5_C, SEL_SCIF5_2),
672 PINMUX_IPSR_MSEL(IP4_11_8, SDA2_D, SEL_I2C02_3),
673 PINMUX_IPSR_GPSR(IP4_11_8, A1),
674 PINMUX_IPSR_GPSR(IP4_15_12, DU0_DR2),
675 PINMUX_IPSR_MSEL(IP4_15_12, RX0_D, SEL_SCIF0_3),
676 PINMUX_IPSR_MSEL(IP4_15_12, SCL0_E, SEL_I2C00_4),
677 PINMUX_IPSR_GPSR(IP4_15_12, A2),
678 PINMUX_IPSR_GPSR(IP4_19_16, DU0_DR3),
679 PINMUX_IPSR_MSEL(IP4_19_16, TX0_D, SEL_SCIF0_3),
680 PINMUX_IPSR_MSEL(IP4_19_16, SDA0_E, SEL_I2C00_4),
681 PINMUX_IPSR_GPSR(IP4_19_16, PWM0_B),
682 PINMUX_IPSR_GPSR(IP4_19_16, A3),
683 PINMUX_IPSR_GPSR(IP4_23_20, DU0_DR4),
684 PINMUX_IPSR_MSEL(IP4_23_20, RX1_D, SEL_SCIF1_3),
685 PINMUX_IPSR_GPSR(IP4_23_20, A4),
686 PINMUX_IPSR_GPSR(IP4_27_24, DU0_DR5),
687 PINMUX_IPSR_MSEL(IP4_27_24, TX1_D, SEL_SCIF1_3),
688 PINMUX_IPSR_GPSR(IP4_27_24, PWM1_B),
689 PINMUX_IPSR_GPSR(IP4_27_24, A5),
690 PINMUX_IPSR_GPSR(IP4_31_28, DU0_DR6),
691 PINMUX_IPSR_MSEL(IP4_31_28, RX2_C, SEL_SCIF2_2),
692 PINMUX_IPSR_GPSR(IP4_31_28, A6),
693
694 /* IPSR5 */
695 PINMUX_IPSR_GPSR(IP5_3_0, DU0_DR7),
696 PINMUX_IPSR_MSEL(IP5_3_0, TX2_C, SEL_SCIF2_2),
697 PINMUX_IPSR_GPSR(IP5_3_0, PWM2_B),
698 PINMUX_IPSR_GPSR(IP5_3_0, A7),
699 PINMUX_IPSR_GPSR(IP5_7_4, DU0_DG0),
700 PINMUX_IPSR_MSEL(IP5_7_4, RX3_B, SEL_SCIF3_1),
701 PINMUX_IPSR_MSEL(IP5_7_4, SCL3_D, SEL_I2C03_3),
702 PINMUX_IPSR_GPSR(IP5_7_4, A8),
703 PINMUX_IPSR_GPSR(IP5_11_8, DU0_DG1),
704 PINMUX_IPSR_MSEL(IP5_11_8, TX3_B, SEL_SCIF3_1),
705 PINMUX_IPSR_MSEL(IP5_11_8, SDA3_D, SEL_I2C03_3),
706 PINMUX_IPSR_GPSR(IP5_11_8, PWM3_B),
707 PINMUX_IPSR_GPSR(IP5_11_8, A9),
708 PINMUX_IPSR_GPSR(IP5_15_12, DU0_DG2),
709 PINMUX_IPSR_MSEL(IP5_15_12, RX4_D, SEL_SCIF4_3),
710 PINMUX_IPSR_GPSR(IP5_15_12, A10),
711 PINMUX_IPSR_GPSR(IP5_19_16, DU0_DG3),
712 PINMUX_IPSR_MSEL(IP5_19_16, TX4_D, SEL_SCIF4_3),
713 PINMUX_IPSR_GPSR(IP5_19_16, PWM4_B),
714 PINMUX_IPSR_GPSR(IP5_19_16, A11),
715 PINMUX_IPSR_GPSR(IP5_23_20, DU0_DG4),
716 PINMUX_IPSR_MSEL(IP5_23_20, HRX0_A, SEL_HSCIF0_0),
717 PINMUX_IPSR_GPSR(IP5_23_20, A12),
718 PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5),
719 PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0),
720 PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B),
721 PINMUX_IPSR_GPSR(IP5_27_24, A13),
722 PINMUX_IPSR_GPSR(IP5_31_28, DU0_DG6),
723 PINMUX_IPSR_MSEL(IP5_31_28, HRX1_C, SEL_HSCIF1_2),
724 PINMUX_IPSR_GPSR(IP5_31_28, A14),
725
726 /* IPSR6 */
727 PINMUX_IPSR_GPSR(IP6_3_0, DU0_DG7),
728 PINMUX_IPSR_MSEL(IP6_3_0, HTX1_C, SEL_HSCIF1_2),
729 PINMUX_IPSR_GPSR(IP6_3_0, PWM6_B),
730 PINMUX_IPSR_GPSR(IP6_3_0, A15),
731 PINMUX_IPSR_GPSR(IP6_7_4, DU0_DB0),
732 PINMUX_IPSR_MSEL(IP6_7_4, SCL4_D, SEL_I2C04_3),
733 PINMUX_IPSR_MSEL(IP6_7_4, CAN0_RX_C, SEL_CAN0_2),
734 PINMUX_IPSR_GPSR(IP6_7_4, A16),
735 PINMUX_IPSR_GPSR(IP6_11_8, DU0_DB1),
736 PINMUX_IPSR_MSEL(IP6_11_8, SDA4_D, SEL_I2C04_3),
737 PINMUX_IPSR_MSEL(IP6_11_8, CAN0_TX_C, SEL_CAN0_2),
738 PINMUX_IPSR_GPSR(IP6_11_8, A17),
739 PINMUX_IPSR_GPSR(IP6_15_12, DU0_DB2),
740 PINMUX_IPSR_GPSR(IP6_15_12, HCTS0_N),
741 PINMUX_IPSR_GPSR(IP6_15_12, A18),
742 PINMUX_IPSR_GPSR(IP6_19_16, DU0_DB3),
743 PINMUX_IPSR_GPSR(IP6_19_16, HRTS0_N),
744 PINMUX_IPSR_GPSR(IP6_19_16, A19),
745 PINMUX_IPSR_GPSR(IP6_23_20, DU0_DB4),
746 PINMUX_IPSR_MSEL(IP6_23_20, HCTS1_N_C, SEL_HSCIF1_2),
747 PINMUX_IPSR_GPSR(IP6_23_20, A20),
748 PINMUX_IPSR_GPSR(IP6_27_24, DU0_DB5),
749 PINMUX_IPSR_MSEL(IP6_27_24, HRTS1_N_C, SEL_HSCIF1_2),
750 PINMUX_IPSR_GPSR(IP6_27_24, A21),
751 PINMUX_IPSR_GPSR(IP6_31_28, DU0_DB6),
752 PINMUX_IPSR_GPSR(IP6_31_28, A22),
753
754 /* IPSR7 */
755 PINMUX_IPSR_GPSR(IP7_3_0, DU0_DB7),
756 PINMUX_IPSR_GPSR(IP7_3_0, A23),
757 PINMUX_IPSR_GPSR(IP7_7_4, DU0_DOTCLKIN),
758 PINMUX_IPSR_GPSR(IP7_7_4, A24),
759 PINMUX_IPSR_GPSR(IP7_11_8, DU0_DOTCLKOUT0),
760 PINMUX_IPSR_GPSR(IP7_11_8, A25),
761 PINMUX_IPSR_GPSR(IP7_15_12, DU0_DOTCLKOUT1),
762 PINMUX_IPSR_MSEL(IP7_15_12, MSIOF2_RXD_B, SEL_MSIOF2_1),
763 PINMUX_IPSR_GPSR(IP7_15_12, CS1_N_A26),
764 PINMUX_IPSR_GPSR(IP7_19_16, DU0_EXHSYNC_DU0_HSYNC),
765 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF2_TXD_B, SEL_MSIOF2_1),
766 PINMUX_IPSR_GPSR(IP7_19_16, DREQ0_N),
767 PINMUX_IPSR_GPSR(IP7_23_20, DU0_EXVSYNC_DU0_VSYNC),
768 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF2_SYNC_B, SEL_MSIOF2_1),
769 PINMUX_IPSR_GPSR(IP7_23_20, DACK0),
770 PINMUX_IPSR_GPSR(IP7_27_24, DU0_EXODDF_DU0_ODDF_DISP_CDE),
771 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF2_SCK_B, SEL_MSIOF2_1),
772 PINMUX_IPSR_GPSR(IP7_27_24, DRACK0),
773 PINMUX_IPSR_GPSR(IP7_31_28, DU0_DISP),
774 PINMUX_IPSR_MSEL(IP7_31_28, CAN1_RX_C, SEL_CAN1_2),
775
776 /* IPSR8 */
777 PINMUX_IPSR_GPSR(IP8_3_0, DU0_CDE),
778 PINMUX_IPSR_MSEL(IP8_3_0, CAN1_TX_C, SEL_CAN1_2),
779 PINMUX_IPSR_GPSR(IP8_7_4, VI1_CLK),
780 PINMUX_IPSR_GPSR(IP8_7_4, AVB_RX_CLK),
781 PINMUX_IPSR_GPSR(IP8_7_4, ETH_REF_CLK),
782 PINMUX_IPSR_GPSR(IP8_11_8, VI1_DATA0),
783 PINMUX_IPSR_GPSR(IP8_11_8, AVB_RX_DV),
784 PINMUX_IPSR_GPSR(IP8_11_8, ETH_CRS_DV),
785 PINMUX_IPSR_GPSR(IP8_15_12, VI1_DATA1),
786 PINMUX_IPSR_GPSR(IP8_15_12, AVB_RXD0),
787 PINMUX_IPSR_GPSR(IP8_15_12, ETH_RXD0),
788 PINMUX_IPSR_GPSR(IP8_19_16, VI1_DATA2),
789 PINMUX_IPSR_GPSR(IP8_19_16, AVB_RXD1),
790 PINMUX_IPSR_GPSR(IP8_19_16, ETH_RXD1),
791 PINMUX_IPSR_GPSR(IP8_23_20, VI1_DATA3),
792 PINMUX_IPSR_GPSR(IP8_23_20, AVB_RXD2),
793 PINMUX_IPSR_GPSR(IP8_23_20, ETH_MDIO),
794 PINMUX_IPSR_GPSR(IP8_27_24, VI1_DATA4),
795 PINMUX_IPSR_GPSR(IP8_27_24, AVB_RXD3),
796 PINMUX_IPSR_GPSR(IP8_27_24, ETH_RX_ER),
797 PINMUX_IPSR_GPSR(IP8_31_28, VI1_DATA5),
798 PINMUX_IPSR_GPSR(IP8_31_28, AVB_RXD4),
799 PINMUX_IPSR_GPSR(IP8_31_28, ETH_LINK),
800
801 /* IPSR9 */
802 PINMUX_IPSR_GPSR(IP9_3_0, VI1_DATA6),
803 PINMUX_IPSR_GPSR(IP9_3_0, AVB_RXD5),
804 PINMUX_IPSR_GPSR(IP9_3_0, ETH_TXD1),
805 PINMUX_IPSR_GPSR(IP9_7_4, VI1_DATA7),
806 PINMUX_IPSR_GPSR(IP9_7_4, AVB_RXD6),
807 PINMUX_IPSR_GPSR(IP9_7_4, ETH_TX_EN),
808 PINMUX_IPSR_GPSR(IP9_11_8, VI1_CLKENB),
809 PINMUX_IPSR_MSEL(IP9_11_8, SCL3_A, SEL_I2C03_0),
810 PINMUX_IPSR_GPSR(IP9_11_8, AVB_RXD7),
811 PINMUX_IPSR_GPSR(IP9_11_8, ETH_MAGIC),
812 PINMUX_IPSR_GPSR(IP9_15_12, VI1_FIELD),
813 PINMUX_IPSR_MSEL(IP9_15_12, SDA3_A, SEL_I2C03_0),
814 PINMUX_IPSR_GPSR(IP9_15_12, AVB_RX_ER),
815 PINMUX_IPSR_GPSR(IP9_15_12, ETH_TXD0),
816 PINMUX_IPSR_GPSR(IP9_19_16, VI1_HSYNC_N),
817 PINMUX_IPSR_MSEL(IP9_19_16, RX0_B, SEL_SCIF0_1),
818 PINMUX_IPSR_MSEL(IP9_19_16, SCL0_C, SEL_I2C00_2),
819 PINMUX_IPSR_GPSR(IP9_19_16, AVB_GTXREFCLK),
820 PINMUX_IPSR_GPSR(IP9_19_16, ETH_MDC),
821 PINMUX_IPSR_GPSR(IP9_23_20, VI1_VSYNC_N),
822 PINMUX_IPSR_MSEL(IP9_23_20, TX0_B, SEL_SCIF0_1),
823 PINMUX_IPSR_MSEL(IP9_23_20, SDA0_C, SEL_I2C00_2),
824 PINMUX_IPSR_GPSR(IP9_23_20, AUDIO_CLKOUT_B),
825 PINMUX_IPSR_GPSR(IP9_23_20, AVB_TX_CLK),
826 PINMUX_IPSR_GPSR(IP9_27_24, VI1_DATA8),
827 PINMUX_IPSR_MSEL(IP9_27_24, SCL2_B, SEL_I2C02_1),
828 PINMUX_IPSR_GPSR(IP9_27_24, AVB_TX_EN),
829 PINMUX_IPSR_GPSR(IP9_31_28, VI1_DATA9),
830 PINMUX_IPSR_MSEL(IP9_31_28, SDA2_B, SEL_I2C02_1),
831 PINMUX_IPSR_GPSR(IP9_31_28, AVB_TXD0),
832
833 /* IPSR10 */
834 PINMUX_IPSR_GPSR(IP10_3_0, VI1_DATA10),
835 PINMUX_IPSR_MSEL(IP10_3_0, CAN0_RX_B, SEL_CAN0_1),
836 PINMUX_IPSR_GPSR(IP10_3_0, AVB_TXD1),
837 PINMUX_IPSR_GPSR(IP10_7_4, VI1_DATA11),
838 PINMUX_IPSR_MSEL(IP10_7_4, CAN0_TX_B, SEL_CAN0_1),
839 PINMUX_IPSR_GPSR(IP10_7_4, AVB_TXD2),
840 PINMUX_IPSR_GPSR(IP10_11_8, AVB_TXD3),
841 PINMUX_IPSR_MSEL(IP10_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
842 PINMUX_IPSR_MSEL(IP10_11_8, SSI_SCK1_D, SEL_SSI1_3),
843 PINMUX_IPSR_MSEL(IP10_11_8, RX5_F, SEL_SCIF5_5),
844 PINMUX_IPSR_MSEL(IP10_11_8, MSIOF0_RXD_B, SEL_MSIOF0_1),
845 PINMUX_IPSR_GPSR(IP10_15_12, AVB_TXD4),
846 PINMUX_IPSR_MSEL(IP10_15_12, AUDIO_CLKB_B, SEL_ADGB_1),
847 PINMUX_IPSR_MSEL(IP10_15_12, SSI_WS1_D, SEL_SSI1_3),
848 PINMUX_IPSR_MSEL(IP10_15_12, TX5_F, SEL_SCIF5_5),
849 PINMUX_IPSR_MSEL(IP10_15_12, MSIOF0_TXD_B, SEL_MSIOF0_1),
850 PINMUX_IPSR_GPSR(IP10_19_16, AVB_TXD5),
851 PINMUX_IPSR_MSEL(IP10_19_16, SCIF_CLK_B, SEL_SCIFCLK_1),
852 PINMUX_IPSR_MSEL(IP10_19_16, AUDIO_CLKC_B, SEL_ADGC_1),
853 PINMUX_IPSR_MSEL(IP10_19_16, SSI_SDATA1_D, SEL_SSI1_3),
854 PINMUX_IPSR_MSEL(IP10_19_16, MSIOF0_SCK_B, SEL_MSIOF0_1),
855 PINMUX_IPSR_MSEL(IP10_23_20, SCL0_A, SEL_I2C00_0),
856 PINMUX_IPSR_MSEL(IP10_23_20, RX0_C, SEL_SCIF0_2),
857 PINMUX_IPSR_GPSR(IP10_23_20, PWM5_A),
858 PINMUX_IPSR_MSEL(IP10_23_20, TCLK1_B, SEL_TMU1_1),
859 PINMUX_IPSR_GPSR(IP10_23_20, AVB_TXD6),
860 PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_D, SEL_CAN1_3),
861 PINMUX_IPSR_MSEL(IP10_23_20, MSIOF0_SYNC_B, SEL_MSIOF0_1),
862 PINMUX_IPSR_MSEL(IP10_27_24, SDA0_A, SEL_I2C00_0),
863 PINMUX_IPSR_MSEL(IP10_27_24, TX0_C, SEL_SCIF0_2),
864 PINMUX_IPSR_GPSR(IP10_27_24, IRQ5),
865 PINMUX_IPSR_MSEL(IP10_27_24, CAN_CLK_A, SEL_CANCLK_0),
866 PINMUX_IPSR_GPSR(IP10_27_24, AVB_GTX_CLK),
867 PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_D, SEL_CAN1_3),
868 PINMUX_IPSR_GPSR(IP10_27_24, DVC_MUTE),
869 PINMUX_IPSR_MSEL(IP10_31_28, SCL1_A, SEL_I2C01_0),
870 PINMUX_IPSR_MSEL(IP10_31_28, RX4_A, SEL_SCIF4_0),
871 PINMUX_IPSR_GPSR(IP10_31_28, PWM5_D),
872 PINMUX_IPSR_GPSR(IP10_31_28, DU1_DR0),
873 PINMUX_IPSR_MSEL(IP10_31_28, SSI_SCK6_B, SEL_SSI6_1),
874 PINMUX_IPSR_GPSR(IP10_31_28, VI0_G0),
875
876 /* IPSR11 */
877 PINMUX_IPSR_MSEL(IP11_3_0, SDA1_A, SEL_I2C01_0),
878 PINMUX_IPSR_MSEL(IP11_3_0, TX4_A, SEL_SCIF4_0),
879 PINMUX_IPSR_GPSR(IP11_3_0, DU1_DR1),
880 PINMUX_IPSR_MSEL(IP11_3_0, SSI_WS6_B, SEL_SSI6_1),
881 PINMUX_IPSR_GPSR(IP11_3_0, VI0_G1),
882 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF0_RXD_A, SEL_MSIOF0_0),
883 PINMUX_IPSR_MSEL(IP11_7_4, RX5_A, SEL_SCIF5_0),
884 PINMUX_IPSR_MSEL(IP11_7_4, SCL2_C, SEL_I2C02_2),
885 PINMUX_IPSR_GPSR(IP11_7_4, DU1_DR2),
886 PINMUX_IPSR_GPSR(IP11_7_4, QSPI1_MOSI_QSPI1_IO0),
887 PINMUX_IPSR_MSEL(IP11_7_4, SSI_SDATA6_B, SEL_SSI6_1),
888 PINMUX_IPSR_GPSR(IP11_7_4, VI0_G2),
889 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF0_TXD_A, SEL_MSIOF0_0),
890 PINMUX_IPSR_MSEL(IP11_11_8, TX5_A, SEL_SCIF5_0),
891 PINMUX_IPSR_MSEL(IP11_11_8, SDA2_C, SEL_I2C02_2),
892 PINMUX_IPSR_GPSR(IP11_11_8, DU1_DR3),
893 PINMUX_IPSR_GPSR(IP11_11_8, QSPI1_MISO_QSPI1_IO1),
894 PINMUX_IPSR_MSEL(IP11_11_8, SSI_WS78_B, SEL_SSI7_1),
895 PINMUX_IPSR_GPSR(IP11_11_8, VI0_G3),
896 PINMUX_IPSR_MSEL(IP11_15_12, MSIOF0_SCK_A, SEL_MSIOF0_0),
897 PINMUX_IPSR_GPSR(IP11_15_12, IRQ0),
898 PINMUX_IPSR_GPSR(IP11_15_12, DU1_DR4),
899 PINMUX_IPSR_GPSR(IP11_15_12, QSPI1_SPCLK),
900 PINMUX_IPSR_MSEL(IP11_15_12, SSI_SCK78_B, SEL_SSI7_1),
901 PINMUX_IPSR_GPSR(IP11_15_12, VI0_G4),
902 PINMUX_IPSR_MSEL(IP11_19_16, MSIOF0_SYNC_A, SEL_MSIOF0_0),
903 PINMUX_IPSR_GPSR(IP11_19_16, PWM1_A),
904 PINMUX_IPSR_GPSR(IP11_19_16, DU1_DR5),
905 PINMUX_IPSR_GPSR(IP11_19_16, QSPI1_IO2),
906 PINMUX_IPSR_MSEL(IP11_19_16, SSI_SDATA7_B, SEL_SSI7_1),
907 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF0_SS1_A, SEL_MSIOF0_0),
908 PINMUX_IPSR_GPSR(IP11_23_20, DU1_DR6),
909 PINMUX_IPSR_GPSR(IP11_23_20, QSPI1_IO3),
910 PINMUX_IPSR_MSEL(IP11_23_20, SSI_SDATA8_B, SEL_SSI8_1),
911 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF0_SS2_A, SEL_MSIOF0_0),
912 PINMUX_IPSR_GPSR(IP11_27_24, DU1_DR7),
913 PINMUX_IPSR_GPSR(IP11_27_24, QSPI1_SSL),
914 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_A, SEL_HSCIF1_0),
915 PINMUX_IPSR_MSEL(IP11_31_28, SCL4_A, SEL_I2C04_0),
916 PINMUX_IPSR_GPSR(IP11_31_28, PWM6_A),
917 PINMUX_IPSR_GPSR(IP11_31_28, DU1_DG0),
918 PINMUX_IPSR_MSEL(IP11_31_28, RX0_A, SEL_SCIF0_0),
919
920 /* IPSR12 */
921 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_A, SEL_HSCIF1_0),
922 PINMUX_IPSR_MSEL(IP12_3_0, SDA4_A, SEL_I2C04_0),
923 PINMUX_IPSR_GPSR(IP12_3_0, DU1_DG1),
924 PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0),
925 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_A, SEL_HSCIF1_0),
926 PINMUX_IPSR_GPSR(IP12_7_4, PWM2_A),
927 PINMUX_IPSR_GPSR(IP12_7_4, DU1_DG2),
928 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_B, SEL_RCN_1),
929 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_A, SEL_HSCIF1_0),
930 PINMUX_IPSR_GPSR(IP12_11_8, DU1_DG3),
931 PINMUX_IPSR_MSEL(IP12_11_8, SSI_WS1_B, SEL_SSI1_1),
932 PINMUX_IPSR_GPSR(IP12_11_8, IRQ1),
933 PINMUX_IPSR_GPSR(IP12_15_12, SD2_CLK),
934 PINMUX_IPSR_GPSR(IP12_15_12, HSCK1),
935 PINMUX_IPSR_GPSR(IP12_15_12, DU1_DG4),
936 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SCK1_B, SEL_SSI1_1),
937 PINMUX_IPSR_GPSR(IP12_19_16, SD2_CMD),
938 PINMUX_IPSR_MSEL(IP12_19_16, SCIF1_SCK_A, SEL_SCIF1_0),
939 PINMUX_IPSR_MSEL(IP12_19_16, TCLK2_A, SEL_TMU2_0),
940 PINMUX_IPSR_GPSR(IP12_19_16, DU1_DG5),
941 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SCK2_B, SEL_SSI2_1),
942 PINMUX_IPSR_GPSR(IP12_19_16, PWM3_A),
943 PINMUX_IPSR_GPSR(IP12_23_20, SD2_DAT0),
944 PINMUX_IPSR_MSEL(IP12_23_20, RX1_A, SEL_SCIF1_0),
945 PINMUX_IPSR_MSEL(IP12_23_20, SCL1_E, SEL_I2C01_4),
946 PINMUX_IPSR_GPSR(IP12_23_20, DU1_DG6),
947 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SDATA1_B, SEL_SSI1_1),
948 PINMUX_IPSR_GPSR(IP12_27_24, SD2_DAT1),
949 PINMUX_IPSR_MSEL(IP12_27_24, TX1_A, SEL_SCIF1_0),
950 PINMUX_IPSR_MSEL(IP12_27_24, SDA1_E, SEL_I2C01_4),
951 PINMUX_IPSR_GPSR(IP12_27_24, DU1_DG7),
952 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS2_B, SEL_SSI2_1),
953 PINMUX_IPSR_GPSR(IP12_31_28, SD2_DAT2),
954 PINMUX_IPSR_MSEL(IP12_31_28, RX2_A, SEL_SCIF2_0),
955 PINMUX_IPSR_GPSR(IP12_31_28, DU1_DB0),
956 PINMUX_IPSR_MSEL(IP12_31_28, SSI_SDATA2_B, SEL_SSI2_1),
957
958 /* IPSR13 */
959 PINMUX_IPSR_GPSR(IP13_3_0, SD2_DAT3),
960 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
961 PINMUX_IPSR_GPSR(IP13_3_0, DU1_DB1),
962 PINMUX_IPSR_MSEL(IP13_3_0, SSI_WS9_B, SEL_SSI9_1),
963 PINMUX_IPSR_GPSR(IP13_7_4, SD2_CD),
964 PINMUX_IPSR_MSEL(IP13_7_4, SCIF2_SCK_A, SEL_SCIF2_CLK_0),
965 PINMUX_IPSR_GPSR(IP13_7_4, DU1_DB2),
966 PINMUX_IPSR_MSEL(IP13_7_4, SSI_SCK9_B, SEL_SSI9_1),
967 PINMUX_IPSR_GPSR(IP13_11_8, SD2_WP),
968 PINMUX_IPSR_GPSR(IP13_11_8, SCIF3_SCK),
969 PINMUX_IPSR_GPSR(IP13_11_8, DU1_DB3),
970 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA9_B, SEL_SSI9_1),
971 PINMUX_IPSR_MSEL(IP13_15_12, RX3_A, SEL_SCIF3_0),
972 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_C, SEL_I2C01_2),
973 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_B, SEL_MSIOF1_1),
974 PINMUX_IPSR_GPSR(IP13_15_12, DU1_DB4),
975 PINMUX_IPSR_MSEL(IP13_15_12, AUDIO_CLKA_C, SEL_ADGA_2),
976 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA4_B, SEL_SSI4_1),
977 PINMUX_IPSR_MSEL(IP13_19_16, TX3_A, SEL_SCIF3_0),
978 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_C, SEL_I2C01_2),
979 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_B, SEL_MSIOF1_1),
980 PINMUX_IPSR_GPSR(IP13_19_16, DU1_DB5),
981 PINMUX_IPSR_MSEL(IP13_19_16, AUDIO_CLKB_C, SEL_ADGB_2),
982 PINMUX_IPSR_MSEL(IP13_19_16, SSI_WS4_B, SEL_SSI4_1),
983 PINMUX_IPSR_MSEL(IP13_23_20, SCL2_A, SEL_I2C02_0),
984 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SCK_B, SEL_MSIOF1_1),
985 PINMUX_IPSR_GPSR(IP13_23_20, DU1_DB6),
986 PINMUX_IPSR_MSEL(IP13_23_20, AUDIO_CLKC_C, SEL_ADGC_2),
987 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK4_B, SEL_SSI4_1),
988 PINMUX_IPSR_MSEL(IP13_27_24, SDA2_A, SEL_I2C02_0),
989 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SYNC_B, SEL_MSIOF1_1),
990 PINMUX_IPSR_GPSR(IP13_27_24, DU1_DB7),
991 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT_C),
992 PINMUX_IPSR_MSEL(IP13_31_28, SSI_SCK5_A, SEL_SSI5_0),
993 PINMUX_IPSR_GPSR(IP13_31_28, DU1_DOTCLKOUT1),
994
995 /* IPSR14 */
996 PINMUX_IPSR_MSEL(IP14_3_0, SSI_WS5_A, SEL_SSI5_0),
997 PINMUX_IPSR_MSEL(IP14_3_0, SCL3_C, SEL_I2C03_2),
998 PINMUX_IPSR_GPSR(IP14_3_0, DU1_DOTCLKIN),
999 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA5_A, SEL_SSI5_0),
1000 PINMUX_IPSR_MSEL(IP14_7_4, SDA3_C, SEL_I2C03_2),
1001 PINMUX_IPSR_GPSR(IP14_7_4, DU1_DOTCLKOUT0),
1002 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK6_A, SEL_SSI6_0),
1003 PINMUX_IPSR_GPSR(IP14_11_8, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1004 PINMUX_IPSR_MSEL(IP14_15_12, SSI_WS6_A, SEL_SSI6_0),
1005 PINMUX_IPSR_MSEL(IP14_15_12, SCL4_C, SEL_I2C04_2),
1006 PINMUX_IPSR_GPSR(IP14_15_12, DU1_EXHSYNC_DU1_HSYNC),
1007 PINMUX_IPSR_MSEL(IP14_19_16, SSI_SDATA6_A, SEL_SSI6_0),
1008 PINMUX_IPSR_MSEL(IP14_19_16, SDA4_C, SEL_I2C04_2),
1009 PINMUX_IPSR_GPSR(IP14_19_16, DU1_EXVSYNC_DU1_VSYNC),
1010 PINMUX_IPSR_MSEL(IP14_23_20, SSI_SCK78_A, SEL_SSI7_0),
1011 PINMUX_IPSR_MSEL(IP14_23_20, SDA4_E, SEL_I2C04_4),
1012 PINMUX_IPSR_GPSR(IP14_23_20, DU1_DISP),
1013 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS78_A, SEL_SSI7_0),
1014 PINMUX_IPSR_MSEL(IP14_27_24, SCL4_E, SEL_I2C04_4),
1015 PINMUX_IPSR_GPSR(IP14_27_24, DU1_CDE),
1016 PINMUX_IPSR_MSEL(IP14_31_28, SSI_SDATA7_A, SEL_SSI7_0),
1017 PINMUX_IPSR_GPSR(IP14_31_28, IRQ8),
1018 PINMUX_IPSR_MSEL(IP14_31_28, AUDIO_CLKA_D, SEL_ADGA_3),
1019 PINMUX_IPSR_MSEL(IP14_31_28, CAN_CLK_D, SEL_CANCLK_3),
1020 PINMUX_IPSR_GPSR(IP14_31_28, VI0_G5),
1021
1022 /* IPSR15 */
1023 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SCK0129_A, SEL_SSI0_0),
1024 PINMUX_IPSR_MSEL(IP15_3_0, MSIOF1_RXD_A, SEL_MSIOF1_0),
1025 PINMUX_IPSR_MSEL(IP15_3_0, RX5_D, SEL_SCIF5_3),
1026 PINMUX_IPSR_GPSR(IP15_3_0, VI0_G6),
1027 PINMUX_IPSR_MSEL(IP15_7_4, SSI_WS0129_A, SEL_SSI0_0),
1028 PINMUX_IPSR_MSEL(IP15_7_4, MSIOF1_TXD_A, SEL_MSIOF1_0),
1029 PINMUX_IPSR_MSEL(IP15_7_4, TX5_D, SEL_SCIF5_3),
1030 PINMUX_IPSR_GPSR(IP15_7_4, VI0_G7),
1031 PINMUX_IPSR_MSEL(IP15_11_8, SSI_SDATA0_A, SEL_SSI0_0),
1032 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1033 PINMUX_IPSR_GPSR(IP15_11_8, PWM0_C),
1034 PINMUX_IPSR_GPSR(IP15_11_8, VI0_R0),
1035 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK34),
1036 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_A, SEL_MSIOF1_0),
1037 PINMUX_IPSR_GPSR(IP15_15_12, AVB_MDC),
1038 PINMUX_IPSR_GPSR(IP15_15_12, DACK1),
1039 PINMUX_IPSR_GPSR(IP15_15_12, VI0_R1),
1040 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS34),
1041 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SS1_A, SEL_MSIOF1_0),
1042 PINMUX_IPSR_GPSR(IP15_19_16, AVB_MDIO),
1043 PINMUX_IPSR_MSEL(IP15_19_16, CAN1_RX_A, SEL_CAN1_0),
1044 PINMUX_IPSR_GPSR(IP15_19_16, DREQ1_N),
1045 PINMUX_IPSR_GPSR(IP15_19_16, VI0_R2),
1046 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA3),
1047 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SS2_A, SEL_MSIOF1_0),
1048 PINMUX_IPSR_GPSR(IP15_23_20, AVB_LINK),
1049 PINMUX_IPSR_MSEL(IP15_23_20, CAN1_TX_A, SEL_CAN1_0),
1050 PINMUX_IPSR_GPSR(IP15_23_20, DREQ2_N),
1051 PINMUX_IPSR_GPSR(IP15_23_20, VI0_R3),
1052 PINMUX_IPSR_MSEL(IP15_27_24, SSI_SCK4_A, SEL_SSI4_0),
1053 PINMUX_IPSR_GPSR(IP15_27_24, AVB_MAGIC),
1054 PINMUX_IPSR_GPSR(IP15_27_24, VI0_R4),
1055 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS4_A, SEL_SSI4_0),
1056 PINMUX_IPSR_GPSR(IP15_31_28, AVB_PHY_INT),
1057 PINMUX_IPSR_GPSR(IP15_31_28, VI0_R5),
1058
1059 /* IPSR16 */
1060 PINMUX_IPSR_MSEL(IP16_3_0, SSI_SDATA4_A, SEL_SSI4_0),
1061 PINMUX_IPSR_GPSR(IP16_3_0, AVB_CRS),
1062 PINMUX_IPSR_GPSR(IP16_3_0, VI0_R6),
1063 PINMUX_IPSR_MSEL(IP16_7_4, SSI_SCK1_A, SEL_SSI1_0),
1064 PINMUX_IPSR_MSEL(IP16_7_4, SCIF1_SCK_B, SEL_SCIF1_1),
1065 PINMUX_IPSR_GPSR(IP16_7_4, PWM1_D),
1066 PINMUX_IPSR_GPSR(IP16_7_4, IRQ9),
1067 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_RCN_0),
1068 PINMUX_IPSR_GPSR(IP16_7_4, DACK2),
1069 PINMUX_IPSR_GPSR(IP16_7_4, VI0_CLK),
1070 PINMUX_IPSR_GPSR(IP16_7_4, AVB_COL),
1071 PINMUX_IPSR_MSEL(IP16_11_8, SSI_SDATA8_A, SEL_SSI8_0),
1072 PINMUX_IPSR_MSEL(IP16_11_8, RX1_B, SEL_SCIF1_1),
1073 PINMUX_IPSR_MSEL(IP16_11_8, CAN0_RX_D, SEL_CAN0_3),
1074 PINMUX_IPSR_MSEL(IP16_11_8, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
1075 PINMUX_IPSR_GPSR(IP16_11_8, VI0_R7),
1076 PINMUX_IPSR_MSEL(IP16_15_12, SSI_WS1_A, SEL_SSI1_0),
1077 PINMUX_IPSR_MSEL(IP16_15_12, TX1_B, SEL_SCIF1_1),
1078 PINMUX_IPSR_MSEL(IP16_15_12, CAN0_TX_D, SEL_CAN0_3),
1079 PINMUX_IPSR_MSEL(IP16_15_12, AVB_AVTP_MATCH_B, SEL_AVB_1),
1080 PINMUX_IPSR_GPSR(IP16_15_12, VI0_DATA0_VI0_B0),
1081 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SDATA1_A, SEL_SSI1_0),
1082 PINMUX_IPSR_MSEL(IP16_19_16, HRX1_B, SEL_HSCIF1_1),
1083 PINMUX_IPSR_GPSR(IP16_19_16, VI0_DATA1_VI0_B1),
1084 PINMUX_IPSR_MSEL(IP16_23_20, SSI_SCK2_A, SEL_SSI2_0),
1085 PINMUX_IPSR_MSEL(IP16_23_20, HTX1_B, SEL_HSCIF1_1),
1086 PINMUX_IPSR_GPSR(IP16_23_20, AVB_TXD7),
1087 PINMUX_IPSR_GPSR(IP16_23_20, VI0_DATA2_VI0_B2),
1088 PINMUX_IPSR_MSEL(IP16_27_24, SSI_WS2_A, SEL_SSI2_0),
1089 PINMUX_IPSR_MSEL(IP16_27_24, HCTS1_N_B, SEL_HSCIF1_1),
1090 PINMUX_IPSR_GPSR(IP16_27_24, AVB_TX_ER),
1091 PINMUX_IPSR_GPSR(IP16_27_24, VI0_DATA3_VI0_B3),
1092 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA2_A, SEL_SSI2_0),
1093 PINMUX_IPSR_MSEL(IP16_31_28, HRTS1_N_B, SEL_HSCIF1_1),
1094 PINMUX_IPSR_GPSR(IP16_31_28, VI0_DATA4_VI0_B4),
1095
1096 /* IPSR17 */
1097 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_A, SEL_SSI9_0),
1098 PINMUX_IPSR_MSEL(IP17_3_0, RX2_B, SEL_SCIF2_1),
1099 PINMUX_IPSR_MSEL(IP17_3_0, SCL3_E, SEL_I2C03_4),
1100 PINMUX_IPSR_GPSR(IP17_3_0, EX_WAIT1),
1101 PINMUX_IPSR_GPSR(IP17_3_0, VI0_DATA5_VI0_B5),
1102 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_A, SEL_SSI9_0),
1103 PINMUX_IPSR_MSEL(IP17_7_4, TX2_B, SEL_SCIF2_1),
1104 PINMUX_IPSR_MSEL(IP17_7_4, SDA3_E, SEL_I2C03_4),
1105 PINMUX_IPSR_GPSR(IP17_7_4, VI0_DATA6_VI0_B6),
1106 PINMUX_IPSR_MSEL(IP17_11_8, SSI_SDATA9_A, SEL_SSI9_0),
1107 PINMUX_IPSR_GPSR(IP17_11_8, SCIF2_SCK_B),
1108 PINMUX_IPSR_GPSR(IP17_11_8, PWM2_D),
1109 PINMUX_IPSR_GPSR(IP17_11_8, VI0_DATA7_VI0_B7),
1110 PINMUX_IPSR_MSEL(IP17_15_12, AUDIO_CLKA_A, SEL_ADGA_0),
1111 PINMUX_IPSR_MSEL(IP17_15_12, SCL0_B, SEL_I2C00_1),
1112 PINMUX_IPSR_GPSR(IP17_15_12, VI0_CLKENB),
1113 PINMUX_IPSR_MSEL(IP17_19_16, AUDIO_CLKB_A, SEL_ADGB_0),
1114 PINMUX_IPSR_MSEL(IP17_19_16, SDA0_B, SEL_I2C00_1),
1115 PINMUX_IPSR_GPSR(IP17_19_16, VI0_FIELD),
1116 PINMUX_IPSR_MSEL(IP17_23_20, AUDIO_CLKC_A, SEL_ADGC_0),
1117 PINMUX_IPSR_MSEL(IP17_23_20, SCL4_B, SEL_I2C04_1),
1118 PINMUX_IPSR_GPSR(IP17_23_20, VI0_HSYNC_N),
1119 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_A),
1120 PINMUX_IPSR_MSEL(IP17_27_24, SDA4_B, SEL_I2C04_1),
1121 PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N),
1122 };
1123
1124 static const struct sh_pfc_pin pinmux_pins[] = {
1125 PINMUX_GPIO_GP_ALL(),
1126 };
1127
1128 /* - AVB -------------------------------------------------------------------- */
1129 static const unsigned int avb_col_pins[] = {
1130 RCAR_GP_PIN(5, 18),
1131 };
1132 static const unsigned int avb_col_mux[] = {
1133 AVB_COL_MARK,
1134 };
1135 static const unsigned int avb_crs_pins[] = {
1136 RCAR_GP_PIN(5, 17),
1137 };
1138 static const unsigned int avb_crs_mux[] = {
1139 AVB_CRS_MARK,
1140 };
1141 static const unsigned int avb_link_pins[] = {
1142 RCAR_GP_PIN(5, 14),
1143 };
1144 static const unsigned int avb_link_mux[] = {
1145 AVB_LINK_MARK,
1146 };
1147 static const unsigned int avb_magic_pins[] = {
1148 RCAR_GP_PIN(5, 15),
1149 };
1150 static const unsigned int avb_magic_mux[] = {
1151 AVB_MAGIC_MARK,
1152 };
1153 static const unsigned int avb_phy_int_pins[] = {
1154 RCAR_GP_PIN(5, 16),
1155 };
1156 static const unsigned int avb_phy_int_mux[] = {
1157 AVB_PHY_INT_MARK,
1158 };
1159 static const unsigned int avb_mdio_pins[] = {
1160 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1161 };
1162 static const unsigned int avb_mdio_mux[] = {
1163 AVB_MDC_MARK, AVB_MDIO_MARK,
1164 };
1165 static const unsigned int avb_mii_tx_rx_pins[] = {
1166 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1167 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 13),
1168
1169 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1170 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 1),
1171 RCAR_GP_PIN(3, 10),
1172 };
1173 static const unsigned int avb_mii_tx_rx_mux[] = {
1174 AVB_TX_CLK_MARK, AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1175 AVB_TXD3_MARK, AVB_TX_EN_MARK,
1176
1177 AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1178 AVB_RXD3_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
1179 };
1180 static const unsigned int avb_mii_tx_er_pins[] = {
1181 RCAR_GP_PIN(5, 23),
1182 };
1183 static const unsigned int avb_mii_tx_er_mux[] = {
1184 AVB_TX_ER_MARK,
1185 };
1186 static const unsigned int avb_gmii_tx_rx_pins[] = {
1187 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1188 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1189 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
1190 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(3, 13),
1191 RCAR_GP_PIN(5, 23),
1192
1193 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1194 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
1195 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1196 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 10),
1197 };
1198 static const unsigned int avb_gmii_tx_rx_mux[] = {
1199 AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, AVB_TX_CLK_MARK, AVB_TXD0_MARK,
1200 AVB_TXD1_MARK, AVB_TXD2_MARK, AVB_TXD3_MARK, AVB_TXD4_MARK,
1201 AVB_TXD5_MARK, AVB_TXD6_MARK, AVB_TXD7_MARK, AVB_TX_EN_MARK,
1202 AVB_TX_ER_MARK,
1203
1204 AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1205 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, AVB_RXD6_MARK,
1206 AVB_RXD7_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
1207 };
1208 static const unsigned int avb_avtp_match_a_pins[] = {
1209 RCAR_GP_PIN(1, 15),
1210 };
1211 static const unsigned int avb_avtp_match_a_mux[] = {
1212 AVB_AVTP_MATCH_A_MARK,
1213 };
1214 static const unsigned int avb_avtp_capture_a_pins[] = {
1215 RCAR_GP_PIN(1, 14),
1216 };
1217 static const unsigned int avb_avtp_capture_a_mux[] = {
1218 AVB_AVTP_CAPTURE_A_MARK,
1219 };
1220 static const unsigned int avb_avtp_match_b_pins[] = {
1221 RCAR_GP_PIN(5, 20),
1222 };
1223 static const unsigned int avb_avtp_match_b_mux[] = {
1224 AVB_AVTP_MATCH_B_MARK,
1225 };
1226 static const unsigned int avb_avtp_capture_b_pins[] = {
1227 RCAR_GP_PIN(5, 19),
1228 };
1229 static const unsigned int avb_avtp_capture_b_mux[] = {
1230 AVB_AVTP_CAPTURE_B_MARK,
1231 };
1232 /* - DU --------------------------------------------------------------------- */
1233 static const unsigned int du0_rgb666_pins[] = {
1234 /* R[7:2], G[7:2], B[7:2] */
1235 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
1236 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1237 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1238 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1239 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1240 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1241 };
1242 static const unsigned int du0_rgb666_mux[] = {
1243 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1244 DU0_DR3_MARK, DU0_DR2_MARK,
1245 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1246 DU0_DG3_MARK, DU0_DG2_MARK,
1247 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1248 DU0_DB3_MARK, DU0_DB2_MARK,
1249 };
1250 static const unsigned int du0_rgb888_pins[] = {
1251 /* R[7:0], G[7:0], B[7:0] */
1252 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
1253 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1254 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
1255 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1256 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1257 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
1258 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
1259 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
1260 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
1261 };
1262 static const unsigned int du0_rgb888_mux[] = {
1263 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1264 DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1265 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1266 DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1267 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1268 DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1269 };
1270 static const unsigned int du0_clk0_out_pins[] = {
1271 /* DOTCLKOUT0 */
1272 RCAR_GP_PIN(2, 25),
1273 };
1274 static const unsigned int du0_clk0_out_mux[] = {
1275 DU0_DOTCLKOUT0_MARK
1276 };
1277 static const unsigned int du0_clk1_out_pins[] = {
1278 /* DOTCLKOUT1 */
1279 RCAR_GP_PIN(2, 26),
1280 };
1281 static const unsigned int du0_clk1_out_mux[] = {
1282 DU0_DOTCLKOUT1_MARK
1283 };
1284 static const unsigned int du0_clk_in_pins[] = {
1285 /* CLKIN */
1286 RCAR_GP_PIN(2, 24),
1287 };
1288 static const unsigned int du0_clk_in_mux[] = {
1289 DU0_DOTCLKIN_MARK
1290 };
1291 static const unsigned int du0_sync_pins[] = {
1292 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1293 RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
1294 };
1295 static const unsigned int du0_sync_mux[] = {
1296 DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
1297 };
1298 static const unsigned int du0_oddf_pins[] = {
1299 /* EXODDF/ODDF/DISP/CDE */
1300 RCAR_GP_PIN(2, 29),
1301 };
1302 static const unsigned int du0_oddf_mux[] = {
1303 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
1304 };
1305 static const unsigned int du0_cde_pins[] = {
1306 /* CDE */
1307 RCAR_GP_PIN(2, 31),
1308 };
1309 static const unsigned int du0_cde_mux[] = {
1310 DU0_CDE_MARK,
1311 };
1312 static const unsigned int du0_disp_pins[] = {
1313 /* DISP */
1314 RCAR_GP_PIN(2, 30),
1315 };
1316 static const unsigned int du0_disp_mux[] = {
1317 DU0_DISP_MARK
1318 };
1319 static const unsigned int du1_rgb666_pins[] = {
1320 /* R[7:2], G[7:2], B[7:2] */
1321 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
1322 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1323 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
1324 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
1325 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1326 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1327 };
1328 static const unsigned int du1_rgb666_mux[] = {
1329 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1330 DU1_DR3_MARK, DU1_DR2_MARK,
1331 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1332 DU1_DG3_MARK, DU1_DG2_MARK,
1333 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1334 DU1_DB3_MARK, DU1_DB2_MARK,
1335 };
1336 static const unsigned int du1_rgb888_pins[] = {
1337 /* R[7:0], G[7:0], B[7:0] */
1338 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
1339 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1340 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1341 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
1342 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
1343 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1344 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1345 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1346 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
1347 };
1348 static const unsigned int du1_rgb888_mux[] = {
1349 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1350 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1351 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1352 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1353 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1354 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1355 };
1356 static const unsigned int du1_clk0_out_pins[] = {
1357 /* DOTCLKOUT0 */
1358 RCAR_GP_PIN(5, 2),
1359 };
1360 static const unsigned int du1_clk0_out_mux[] = {
1361 DU1_DOTCLKOUT0_MARK
1362 };
1363 static const unsigned int du1_clk1_out_pins[] = {
1364 /* DOTCLKOUT1 */
1365 RCAR_GP_PIN(5, 0),
1366 };
1367 static const unsigned int du1_clk1_out_mux[] = {
1368 DU1_DOTCLKOUT1_MARK
1369 };
1370 static const unsigned int du1_clk_in_pins[] = {
1371 /* DOTCLKIN */
1372 RCAR_GP_PIN(5, 1),
1373 };
1374 static const unsigned int du1_clk_in_mux[] = {
1375 DU1_DOTCLKIN_MARK
1376 };
1377 static const unsigned int du1_sync_pins[] = {
1378 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1379 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4),
1380 };
1381 static const unsigned int du1_sync_mux[] = {
1382 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1383 };
1384 static const unsigned int du1_oddf_pins[] = {
1385 /* EXODDF/ODDF/DISP/CDE */
1386 RCAR_GP_PIN(5, 3),
1387 };
1388 static const unsigned int du1_oddf_mux[] = {
1389 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1390 };
1391 static const unsigned int du1_cde_pins[] = {
1392 /* CDE */
1393 RCAR_GP_PIN(5, 7),
1394 };
1395 static const unsigned int du1_cde_mux[] = {
1396 DU1_CDE_MARK
1397 };
1398 static const unsigned int du1_disp_pins[] = {
1399 /* DISP */
1400 RCAR_GP_PIN(5, 6),
1401 };
1402 static const unsigned int du1_disp_mux[] = {
1403 DU1_DISP_MARK
1404 };
1405 /* - I2C0 ------------------------------------------------------------------- */
1406 static const unsigned int i2c0_a_pins[] = {
1407 /* SCL, SDA */
1408 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1409 };
1410 static const unsigned int i2c0_a_mux[] = {
1411 SCL0_A_MARK, SDA0_A_MARK,
1412 };
1413 static const unsigned int i2c0_b_pins[] = {
1414 /* SCL, SDA */
1415 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1416 };
1417 static const unsigned int i2c0_b_mux[] = {
1418 SCL0_B_MARK, SDA0_B_MARK,
1419 };
1420 static const unsigned int i2c0_c_pins[] = {
1421 /* SCL, SDA */
1422 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1423 };
1424 static const unsigned int i2c0_c_mux[] = {
1425 SCL0_C_MARK, SDA0_C_MARK,
1426 };
1427 static const unsigned int i2c0_d_pins[] = {
1428 /* SCL, SDA */
1429 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
1430 };
1431 static const unsigned int i2c0_d_mux[] = {
1432 SCL0_D_MARK, SDA0_D_MARK,
1433 };
1434 static const unsigned int i2c0_e_pins[] = {
1435 /* SCL, SDA */
1436 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1437 };
1438 static const unsigned int i2c0_e_mux[] = {
1439 SCL0_E_MARK, SDA0_E_MARK,
1440 };
1441 /* - I2C1 ------------------------------------------------------------------- */
1442 static const unsigned int i2c1_a_pins[] = {
1443 /* SCL, SDA */
1444 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1445 };
1446 static const unsigned int i2c1_a_mux[] = {
1447 SCL1_A_MARK, SDA1_A_MARK,
1448 };
1449 static const unsigned int i2c1_b_pins[] = {
1450 /* SCL, SDA */
1451 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
1452 };
1453 static const unsigned int i2c1_b_mux[] = {
1454 SCL1_B_MARK, SDA1_B_MARK,
1455 };
1456 static const unsigned int i2c1_c_pins[] = {
1457 /* SCL, SDA */
1458 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1459 };
1460 static const unsigned int i2c1_c_mux[] = {
1461 SCL1_C_MARK, SDA1_C_MARK,
1462 };
1463 static const unsigned int i2c1_d_pins[] = {
1464 /* SCL, SDA */
1465 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1466 };
1467 static const unsigned int i2c1_d_mux[] = {
1468 SCL1_D_MARK, SDA1_D_MARK,
1469 };
1470 static const unsigned int i2c1_e_pins[] = {
1471 /* SCL, SDA */
1472 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1473 };
1474 static const unsigned int i2c1_e_mux[] = {
1475 SCL1_E_MARK, SDA1_E_MARK,
1476 };
1477 /* - I2C2 ------------------------------------------------------------------- */
1478 static const unsigned int i2c2_a_pins[] = {
1479 /* SCL, SDA */
1480 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
1481 };
1482 static const unsigned int i2c2_a_mux[] = {
1483 SCL2_A_MARK, SDA2_A_MARK,
1484 };
1485 static const unsigned int i2c2_b_pins[] = {
1486 /* SCL, SDA */
1487 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1488 };
1489 static const unsigned int i2c2_b_mux[] = {
1490 SCL2_B_MARK, SDA2_B_MARK,
1491 };
1492 static const unsigned int i2c2_c_pins[] = {
1493 /* SCL, SDA */
1494 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1495 };
1496 static const unsigned int i2c2_c_mux[] = {
1497 SCL2_C_MARK, SDA2_C_MARK,
1498 };
1499 static const unsigned int i2c2_d_pins[] = {
1500 /* SCL, SDA */
1501 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1502 };
1503 static const unsigned int i2c2_d_mux[] = {
1504 SCL2_D_MARK, SDA2_D_MARK,
1505 };
1506 /* - I2C3 ------------------------------------------------------------------- */
1507 static const unsigned int i2c3_a_pins[] = {
1508 /* SCL, SDA */
1509 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1510 };
1511 static const unsigned int i2c3_a_mux[] = {
1512 SCL3_A_MARK, SDA3_A_MARK,
1513 };
1514 static const unsigned int i2c3_b_pins[] = {
1515 /* SCL, SDA */
1516 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
1517 };
1518 static const unsigned int i2c3_b_mux[] = {
1519 SCL3_B_MARK, SDA3_B_MARK,
1520 };
1521 static const unsigned int i2c3_c_pins[] = {
1522 /* SCL, SDA */
1523 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1524 };
1525 static const unsigned int i2c3_c_mux[] = {
1526 SCL3_C_MARK, SDA3_C_MARK,
1527 };
1528 static const unsigned int i2c3_d_pins[] = {
1529 /* SCL, SDA */
1530 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1531 };
1532 static const unsigned int i2c3_d_mux[] = {
1533 SCL3_D_MARK, SDA3_D_MARK,
1534 };
1535 static const unsigned int i2c3_e_pins[] = {
1536 /* SCL, SDA */
1537 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
1538 };
1539 static const unsigned int i2c3_e_mux[] = {
1540 SCL3_E_MARK, SDA3_E_MARK,
1541 };
1542 /* - I2C4 ------------------------------------------------------------------- */
1543 static const unsigned int i2c4_a_pins[] = {
1544 /* SCL, SDA */
1545 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1546 };
1547 static const unsigned int i2c4_a_mux[] = {
1548 SCL4_A_MARK, SDA4_A_MARK,
1549 };
1550 static const unsigned int i2c4_b_pins[] = {
1551 /* SCL, SDA */
1552 RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 31),
1553 };
1554 static const unsigned int i2c4_b_mux[] = {
1555 SCL4_B_MARK, SDA4_B_MARK,
1556 };
1557 static const unsigned int i2c4_c_pins[] = {
1558 /* SCL, SDA */
1559 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1560 };
1561 static const unsigned int i2c4_c_mux[] = {
1562 SCL4_C_MARK, SDA4_C_MARK,
1563 };
1564 static const unsigned int i2c4_d_pins[] = {
1565 /* SCL, SDA */
1566 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1567 };
1568 static const unsigned int i2c4_d_mux[] = {
1569 SCL4_D_MARK, SDA4_D_MARK,
1570 };
1571 static const unsigned int i2c4_e_pins[] = {
1572 /* SCL, SDA */
1573 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 6),
1574 };
1575 static const unsigned int i2c4_e_mux[] = {
1576 SCL4_E_MARK, SDA4_E_MARK,
1577 };
1578 /* - MMC -------------------------------------------------------------------- */
1579 static const unsigned int mmc_data1_pins[] = {
1580 /* D0 */
1581 RCAR_GP_PIN(0, 15),
1582 };
1583 static const unsigned int mmc_data1_mux[] = {
1584 MMC0_D0_SDHI1_D0_MARK,
1585 };
1586 static const unsigned int mmc_data4_pins[] = {
1587 /* D[0:3] */
1588 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1589 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1590 };
1591 static const unsigned int mmc_data4_mux[] = {
1592 MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
1593 MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
1594 };
1595 static const unsigned int mmc_data8_pins[] = {
1596 /* D[0:3] */
1597 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1598 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1599 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
1600 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
1601 };
1602 static const unsigned int mmc_data8_mux[] = {
1603 MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
1604 MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
1605 MMC0_D4_MARK, MMC0_D5_MARK,
1606 MMC0_D6_MARK, MMC0_D7_MARK,
1607 };
1608 static const unsigned int mmc_ctrl_pins[] = {
1609 /* CLK, CMD */
1610 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1611 };
1612 static const unsigned int mmc_ctrl_mux[] = {
1613 MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
1614 };
1615 /* - QSPI ------------------------------------------------------------------- */
1616 static const unsigned int qspi0_ctrl_pins[] = {
1617 /* SPCLK, SSL */
1618 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 21),
1619 };
1620 static const unsigned int qspi0_ctrl_mux[] = {
1621 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1622 };
1623 static const unsigned int qspi0_data2_pins[] = {
1624 /* MOSI_IO0, MISO_IO1 */
1625 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
1626 };
1627 static const unsigned int qspi0_data2_mux[] = {
1628 QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
1629 };
1630 static const unsigned int qspi0_data4_pins[] = {
1631 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1632 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
1633 RCAR_GP_PIN(1, 20),
1634 };
1635 static const unsigned int qspi0_data4_mux[] = {
1636 QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
1637 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1638 };
1639 static const unsigned int qspi1_ctrl_pins[] = {
1640 /* SPCLK, SSL */
1641 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9),
1642 };
1643 static const unsigned int qspi1_ctrl_mux[] = {
1644 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1645 };
1646 static const unsigned int qspi1_data2_pins[] = {
1647 /* MOSI_IO0, MISO_IO1 */
1648 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1649 };
1650 static const unsigned int qspi1_data2_mux[] = {
1651 QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
1652 };
1653 static const unsigned int qspi1_data4_pins[] = {
1654 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1655 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1656 RCAR_GP_PIN(4, 8),
1657 };
1658 static const unsigned int qspi1_data4_mux[] = {
1659 QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
1660 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1661 };
1662 /* - SCIF0 ------------------------------------------------------------------ */
1663 static const unsigned int scif0_data_a_pins[] = {
1664 /* RX, TX */
1665 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1666 };
1667 static const unsigned int scif0_data_a_mux[] = {
1668 RX0_A_MARK, TX0_A_MARK,
1669 };
1670 static const unsigned int scif0_data_b_pins[] = {
1671 /* RX, TX */
1672 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1673 };
1674 static const unsigned int scif0_data_b_mux[] = {
1675 RX0_B_MARK, TX0_B_MARK,
1676 };
1677 static const unsigned int scif0_data_c_pins[] = {
1678 /* RX, TX */
1679 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1680 };
1681 static const unsigned int scif0_data_c_mux[] = {
1682 RX0_C_MARK, TX0_C_MARK,
1683 };
1684 static const unsigned int scif0_data_d_pins[] = {
1685 /* RX, TX */
1686 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1687 };
1688 static const unsigned int scif0_data_d_mux[] = {
1689 RX0_D_MARK, TX0_D_MARK,
1690 };
1691 /* - SCIF1 ------------------------------------------------------------------ */
1692 static const unsigned int scif1_data_a_pins[] = {
1693 /* RX, TX */
1694 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1695 };
1696 static const unsigned int scif1_data_a_mux[] = {
1697 RX1_A_MARK, TX1_A_MARK,
1698 };
1699 static const unsigned int scif1_clk_a_pins[] = {
1700 /* SCK */
1701 RCAR_GP_PIN(4, 15),
1702 };
1703 static const unsigned int scif1_clk_a_mux[] = {
1704 SCIF1_SCK_A_MARK,
1705 };
1706 static const unsigned int scif1_data_b_pins[] = {
1707 /* RX, TX */
1708 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1709 };
1710 static const unsigned int scif1_data_b_mux[] = {
1711 RX1_B_MARK, TX1_B_MARK,
1712 };
1713 static const unsigned int scif1_clk_b_pins[] = {
1714 /* SCK */
1715 RCAR_GP_PIN(5, 18),
1716 };
1717 static const unsigned int scif1_clk_b_mux[] = {
1718 SCIF1_SCK_B_MARK,
1719 };
1720 static const unsigned int scif1_data_c_pins[] = {
1721 /* RX, TX */
1722 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1723 };
1724 static const unsigned int scif1_data_c_mux[] = {
1725 RX1_C_MARK, TX1_C_MARK,
1726 };
1727 static const unsigned int scif1_clk_c_pins[] = {
1728 /* SCK */
1729 RCAR_GP_PIN(1, 7),
1730 };
1731 static const unsigned int scif1_clk_c_mux[] = {
1732 SCIF1_SCK_C_MARK,
1733 };
1734 static const unsigned int scif1_data_d_pins[] = {
1735 /* RX, TX */
1736 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1737 };
1738 static const unsigned int scif1_data_d_mux[] = {
1739 RX1_D_MARK, TX1_D_MARK,
1740 };
1741 /* - SCIF2 ------------------------------------------------------------------ */
1742 static const unsigned int scif2_data_a_pins[] = {
1743 /* RX, TX */
1744 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1745 };
1746 static const unsigned int scif2_data_a_mux[] = {
1747 RX2_A_MARK, TX2_A_MARK,
1748 };
1749 static const unsigned int scif2_clk_a_pins[] = {
1750 /* SCK */
1751 RCAR_GP_PIN(4, 20),
1752 };
1753 static const unsigned int scif2_clk_a_mux[] = {
1754 SCIF2_SCK_A_MARK,
1755 };
1756 static const unsigned int scif2_data_b_pins[] = {
1757 /* RX, TX */
1758 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
1759 };
1760 static const unsigned int scif2_data_b_mux[] = {
1761 RX2_B_MARK, TX2_B_MARK,
1762 };
1763 static const unsigned int scif2_clk_b_pins[] = {
1764 /* SCK */
1765 RCAR_GP_PIN(5, 27),
1766 };
1767 static const unsigned int scif2_clk_b_mux[] = {
1768 SCIF2_SCK_B_MARK,
1769 };
1770 static const unsigned int scif2_data_c_pins[] = {
1771 /* RX, TX */
1772 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1773 };
1774 static const unsigned int scif2_data_c_mux[] = {
1775 RX2_C_MARK, TX2_C_MARK,
1776 };
1777 /* - SCIF3 ------------------------------------------------------------------ */
1778 static const unsigned int scif3_data_a_pins[] = {
1779 /* RX, TX */
1780 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1781 };
1782 static const unsigned int scif3_data_a_mux[] = {
1783 RX3_A_MARK, TX3_A_MARK,
1784 };
1785 static const unsigned int scif3_clk_pins[] = {
1786 /* SCK */
1787 RCAR_GP_PIN(4, 21),
1788 };
1789 static const unsigned int scif3_clk_mux[] = {
1790 SCIF3_SCK_MARK,
1791 };
1792 static const unsigned int scif3_data_b_pins[] = {
1793 /* RX, TX */
1794 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1795 };
1796 static const unsigned int scif3_data_b_mux[] = {
1797 RX3_B_MARK, TX3_B_MARK,
1798 };
1799 static const unsigned int scif3_data_c_pins[] = {
1800 /* RX, TX */
1801 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1802 };
1803 static const unsigned int scif3_data_c_mux[] = {
1804 RX3_C_MARK, TX3_C_MARK,
1805 };
1806 /* - SCIF4 ------------------------------------------------------------------ */
1807 static const unsigned int scif4_data_a_pins[] = {
1808 /* RX, TX */
1809 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1810 };
1811 static const unsigned int scif4_data_a_mux[] = {
1812 RX4_A_MARK, TX4_A_MARK,
1813 };
1814 static const unsigned int scif4_data_b_pins[] = {
1815 /* RX, TX */
1816 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
1817 };
1818 static const unsigned int scif4_data_b_mux[] = {
1819 RX4_B_MARK, TX4_B_MARK,
1820 };
1821 static const unsigned int scif4_data_c_pins[] = {
1822 /* RX, TX */
1823 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
1824 };
1825 static const unsigned int scif4_data_c_mux[] = {
1826 RX4_C_MARK, TX4_C_MARK,
1827 };
1828 static const unsigned int scif4_data_d_pins[] = {
1829 /* RX, TX */
1830 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1831 };
1832 static const unsigned int scif4_data_d_mux[] = {
1833 RX4_D_MARK, TX4_D_MARK,
1834 };
1835 static const unsigned int scif4_data_e_pins[] = {
1836 /* RX, TX */
1837 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1838 };
1839 static const unsigned int scif4_data_e_mux[] = {
1840 RX4_E_MARK, TX4_E_MARK,
1841 };
1842 /* - SCIF5 ------------------------------------------------------------------ */
1843 static const unsigned int scif5_data_a_pins[] = {
1844 /* RX, TX */
1845 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1846 };
1847 static const unsigned int scif5_data_a_mux[] = {
1848 RX5_A_MARK, TX5_A_MARK,
1849 };
1850 static const unsigned int scif5_data_b_pins[] = {
1851 /* RX, TX */
1852 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
1853 };
1854 static const unsigned int scif5_data_b_mux[] = {
1855 RX5_B_MARK, TX5_B_MARK,
1856 };
1857 static const unsigned int scif5_data_c_pins[] = {
1858 /* RX, TX */
1859 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1860 };
1861 static const unsigned int scif5_data_c_mux[] = {
1862 RX5_C_MARK, TX5_C_MARK,
1863 };
1864 static const unsigned int scif5_data_d_pins[] = {
1865 /* RX, TX */
1866 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1867 };
1868 static const unsigned int scif5_data_d_mux[] = {
1869 RX5_D_MARK, TX5_D_MARK,
1870 };
1871 static const unsigned int scif5_data_e_pins[] = {
1872 /* RX, TX */
1873 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1874 };
1875 static const unsigned int scif5_data_e_mux[] = {
1876 RX5_E_MARK, TX5_E_MARK,
1877 };
1878 static const unsigned int scif5_data_f_pins[] = {
1879 /* RX, TX */
1880 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
1881 };
1882 static const unsigned int scif5_data_f_mux[] = {
1883 RX5_F_MARK, TX5_F_MARK,
1884 };
1885 /* - SCIF Clock ------------------------------------------------------------- */
1886 static const unsigned int scif_clk_a_pins[] = {
1887 /* SCIF_CLK */
1888 RCAR_GP_PIN(1, 22),
1889 };
1890 static const unsigned int scif_clk_a_mux[] = {
1891 SCIF_CLK_A_MARK,
1892 };
1893 static const unsigned int scif_clk_b_pins[] = {
1894 /* SCIF_CLK */
1895 RCAR_GP_PIN(3, 29),
1896 };
1897 static const unsigned int scif_clk_b_mux[] = {
1898 SCIF_CLK_B_MARK,
1899 };
1900 /* - SDHI0 ------------------------------------------------------------------ */
1901 static const unsigned int sdhi0_data1_pins[] = {
1902 /* D0 */
1903 RCAR_GP_PIN(0, 7),
1904 };
1905 static const unsigned int sdhi0_data1_mux[] = {
1906 SD0_DAT0_MARK,
1907 };
1908 static const unsigned int sdhi0_data4_pins[] = {
1909 /* D[0:3] */
1910 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1911 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1912 };
1913 static const unsigned int sdhi0_data4_mux[] = {
1914 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1915 };
1916 static const unsigned int sdhi0_ctrl_pins[] = {
1917 /* CLK, CMD */
1918 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1919 };
1920 static const unsigned int sdhi0_ctrl_mux[] = {
1921 SD0_CLK_MARK, SD0_CMD_MARK,
1922 };
1923 static const unsigned int sdhi0_cd_pins[] = {
1924 /* CD */
1925 RCAR_GP_PIN(0, 11),
1926 };
1927 static const unsigned int sdhi0_cd_mux[] = {
1928 SD0_CD_MARK,
1929 };
1930 static const unsigned int sdhi0_wp_pins[] = {
1931 /* WP */
1932 RCAR_GP_PIN(0, 12),
1933 };
1934 static const unsigned int sdhi0_wp_mux[] = {
1935 SD0_WP_MARK,
1936 };
1937 /* - SDHI1 ------------------------------------------------------------------ */
1938 static const unsigned int sdhi1_data1_pins[] = {
1939 /* D0 */
1940 RCAR_GP_PIN(0, 15),
1941 };
1942 static const unsigned int sdhi1_data1_mux[] = {
1943 MMC0_D0_SDHI1_D0_MARK,
1944 };
1945 static const unsigned int sdhi1_data4_pins[] = {
1946 /* D[0:3] */
1947 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1948 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
1949 };
1950 static const unsigned int sdhi1_data4_mux[] = {
1951 MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
1952 MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
1953 };
1954 static const unsigned int sdhi1_ctrl_pins[] = {
1955 /* CLK, CMD */
1956 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1957 };
1958 static const unsigned int sdhi1_ctrl_mux[] = {
1959 MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
1960 };
1961 static const unsigned int sdhi1_cd_pins[] = {
1962 /* CD */
1963 RCAR_GP_PIN(0, 19),
1964 };
1965 static const unsigned int sdhi1_cd_mux[] = {
1966 SD1_CD_MARK,
1967 };
1968 static const unsigned int sdhi1_wp_pins[] = {
1969 /* WP */
1970 RCAR_GP_PIN(0, 20),
1971 };
1972 static const unsigned int sdhi1_wp_mux[] = {
1973 SD1_WP_MARK,
1974 };
1975 /* - SDHI2 ------------------------------------------------------------------ */
1976 static const unsigned int sdhi2_data1_pins[] = {
1977 /* D0 */
1978 RCAR_GP_PIN(4, 16),
1979 };
1980 static const unsigned int sdhi2_data1_mux[] = {
1981 SD2_DAT0_MARK,
1982 };
1983 static const unsigned int sdhi2_data4_pins[] = {
1984 /* D[0:3] */
1985 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1986 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
1987 };
1988 static const unsigned int sdhi2_data4_mux[] = {
1989 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
1990 };
1991 static const unsigned int sdhi2_ctrl_pins[] = {
1992 /* CLK, CMD */
1993 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1994 };
1995 static const unsigned int sdhi2_ctrl_mux[] = {
1996 SD2_CLK_MARK, SD2_CMD_MARK,
1997 };
1998 static const unsigned int sdhi2_cd_pins[] = {
1999 /* CD */
2000 RCAR_GP_PIN(4, 20),
2001 };
2002 static const unsigned int sdhi2_cd_mux[] = {
2003 SD2_CD_MARK,
2004 };
2005 static const unsigned int sdhi2_wp_pins[] = {
2006 /* WP */
2007 RCAR_GP_PIN(4, 21),
2008 };
2009 static const unsigned int sdhi2_wp_mux[] = {
2010 SD2_WP_MARK,
2011 };
2012 /* - USB0 ------------------------------------------------------------------- */
2013 static const unsigned int usb0_pins[] = {
2014 RCAR_GP_PIN(0, 0), /* PWEN */
2015 RCAR_GP_PIN(0, 1), /* OVC */
2016 };
2017 static const unsigned int usb0_mux[] = {
2018 USB0_PWEN_MARK,
2019 USB0_OVC_MARK,
2020 };
2021 /* - USB1 ------------------------------------------------------------------- */
2022 static const unsigned int usb1_pins[] = {
2023 RCAR_GP_PIN(0, 2), /* PWEN */
2024 RCAR_GP_PIN(0, 3), /* OVC */
2025 };
2026 static const unsigned int usb1_mux[] = {
2027 USB1_PWEN_MARK,
2028 USB1_OVC_MARK,
2029 };
2030 /* - VIN0 ------------------------------------------------------------------- */
2031 static const union vin_data vin0_data_pins = {
2032 .data24 = {
2033 /* B */
2034 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2035 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2036 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2037 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
2038 /* G */
2039 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2040 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2041 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
2042 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
2043 /* R */
2044 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2045 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2046 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2047 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2048 },
2049 };
2050 static const union vin_data vin0_data_mux = {
2051 .data24 = {
2052 /* B */
2053 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
2054 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2055 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2056 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2057 /* G */
2058 VI0_G0_MARK, VI0_G1_MARK,
2059 VI0_G2_MARK, VI0_G3_MARK,
2060 VI0_G4_MARK, VI0_G5_MARK,
2061 VI0_G6_MARK, VI0_G7_MARK,
2062 /* R */
2063 VI0_R0_MARK, VI0_R1_MARK,
2064 VI0_R2_MARK, VI0_R3_MARK,
2065 VI0_R4_MARK, VI0_R5_MARK,
2066 VI0_R6_MARK, VI0_R7_MARK,
2067 },
2068 };
2069 static const unsigned int vin0_data18_pins[] = {
2070 /* B */
2071 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2072 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2073 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
2074 /* G */
2075 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2076 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
2077 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
2078 /* R */
2079 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2080 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2081 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2082 };
2083 static const unsigned int vin0_data18_mux[] = {
2084 /* B */
2085 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2086 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2087 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2088 /* G */
2089 VI0_G2_MARK, VI0_G3_MARK,
2090 VI0_G4_MARK, VI0_G5_MARK,
2091 VI0_G6_MARK, VI0_G7_MARK,
2092 /* R */
2093 VI0_R2_MARK, VI0_R3_MARK,
2094 VI0_R4_MARK, VI0_R5_MARK,
2095 VI0_R6_MARK, VI0_R7_MARK,
2096 };
2097 static const unsigned int vin0_sync_pins[] = {
2098 RCAR_GP_PIN(5, 30), /* HSYNC */
2099 RCAR_GP_PIN(5, 31), /* VSYNC */
2100 };
2101 static const unsigned int vin0_sync_mux[] = {
2102 VI0_HSYNC_N_MARK,
2103 VI0_VSYNC_N_MARK,
2104 };
2105 static const unsigned int vin0_field_pins[] = {
2106 RCAR_GP_PIN(5, 29),
2107 };
2108 static const unsigned int vin0_field_mux[] = {
2109 VI0_FIELD_MARK,
2110 };
2111 static const unsigned int vin0_clkenb_pins[] = {
2112 RCAR_GP_PIN(5, 28),
2113 };
2114 static const unsigned int vin0_clkenb_mux[] = {
2115 VI0_CLKENB_MARK,
2116 };
2117 static const unsigned int vin0_clk_pins[] = {
2118 RCAR_GP_PIN(5, 18),
2119 };
2120 static const unsigned int vin0_clk_mux[] = {
2121 VI0_CLK_MARK,
2122 };
2123 /* - VIN1 ------------------------------------------------------------------- */
2124 static const union vin_data vin1_data_pins = {
2125 .data12 = {
2126 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
2127 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
2128 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2129 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2130 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2131 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2132 },
2133 };
2134 static const union vin_data vin1_data_mux = {
2135 .data12 = {
2136 VI1_DATA0_MARK, VI1_DATA1_MARK,
2137 VI1_DATA2_MARK, VI1_DATA3_MARK,
2138 VI1_DATA4_MARK, VI1_DATA5_MARK,
2139 VI1_DATA6_MARK, VI1_DATA7_MARK,
2140 VI1_DATA8_MARK, VI1_DATA9_MARK,
2141 VI1_DATA10_MARK, VI1_DATA11_MARK,
2142 },
2143 };
2144 static const unsigned int vin1_sync_pins[] = {
2145 RCAR_GP_PIN(3, 11), /* HSYNC */
2146 RCAR_GP_PIN(3, 12), /* VSYNC */
2147 };
2148 static const unsigned int vin1_sync_mux[] = {
2149 VI1_HSYNC_N_MARK,
2150 VI1_VSYNC_N_MARK,
2151 };
2152 static const unsigned int vin1_field_pins[] = {
2153 RCAR_GP_PIN(3, 10),
2154 };
2155 static const unsigned int vin1_field_mux[] = {
2156 VI1_FIELD_MARK,
2157 };
2158 static const unsigned int vin1_clkenb_pins[] = {
2159 RCAR_GP_PIN(3, 9),
2160 };
2161 static const unsigned int vin1_clkenb_mux[] = {
2162 VI1_CLKENB_MARK,
2163 };
2164 static const unsigned int vin1_clk_pins[] = {
2165 RCAR_GP_PIN(3, 0),
2166 };
2167 static const unsigned int vin1_clk_mux[] = {
2168 VI1_CLK_MARK,
2169 };
2170
2171 static const struct sh_pfc_pin_group pinmux_groups[] = {
2172 SH_PFC_PIN_GROUP(avb_col),
2173 SH_PFC_PIN_GROUP(avb_crs),
2174 SH_PFC_PIN_GROUP(avb_link),
2175 SH_PFC_PIN_GROUP(avb_magic),
2176 SH_PFC_PIN_GROUP(avb_phy_int),
2177 SH_PFC_PIN_GROUP(avb_mdio),
2178 SH_PFC_PIN_GROUP(avb_mii_tx_rx),
2179 SH_PFC_PIN_GROUP(avb_mii_tx_er),
2180 SH_PFC_PIN_GROUP(avb_gmii_tx_rx),
2181 SH_PFC_PIN_GROUP(avb_avtp_match_a),
2182 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
2183 SH_PFC_PIN_GROUP(avb_avtp_match_b),
2184 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
2185 SH_PFC_PIN_GROUP(du0_rgb666),
2186 SH_PFC_PIN_GROUP(du0_rgb888),
2187 SH_PFC_PIN_GROUP(du0_clk0_out),
2188 SH_PFC_PIN_GROUP(du0_clk1_out),
2189 SH_PFC_PIN_GROUP(du0_clk_in),
2190 SH_PFC_PIN_GROUP(du0_sync),
2191 SH_PFC_PIN_GROUP(du0_oddf),
2192 SH_PFC_PIN_GROUP(du0_cde),
2193 SH_PFC_PIN_GROUP(du0_disp),
2194 SH_PFC_PIN_GROUP(du1_rgb666),
2195 SH_PFC_PIN_GROUP(du1_rgb888),
2196 SH_PFC_PIN_GROUP(du1_clk0_out),
2197 SH_PFC_PIN_GROUP(du1_clk1_out),
2198 SH_PFC_PIN_GROUP(du1_clk_in),
2199 SH_PFC_PIN_GROUP(du1_sync),
2200 SH_PFC_PIN_GROUP(du1_oddf),
2201 SH_PFC_PIN_GROUP(du1_cde),
2202 SH_PFC_PIN_GROUP(du1_disp),
2203 SH_PFC_PIN_GROUP(i2c0_a),
2204 SH_PFC_PIN_GROUP(i2c0_b),
2205 SH_PFC_PIN_GROUP(i2c0_c),
2206 SH_PFC_PIN_GROUP(i2c0_d),
2207 SH_PFC_PIN_GROUP(i2c0_e),
2208 SH_PFC_PIN_GROUP(i2c1_a),
2209 SH_PFC_PIN_GROUP(i2c1_b),
2210 SH_PFC_PIN_GROUP(i2c1_c),
2211 SH_PFC_PIN_GROUP(i2c1_d),
2212 SH_PFC_PIN_GROUP(i2c1_e),
2213 SH_PFC_PIN_GROUP(i2c2_a),
2214 SH_PFC_PIN_GROUP(i2c2_b),
2215 SH_PFC_PIN_GROUP(i2c2_c),
2216 SH_PFC_PIN_GROUP(i2c2_d),
2217 SH_PFC_PIN_GROUP(i2c3_a),
2218 SH_PFC_PIN_GROUP(i2c3_b),
2219 SH_PFC_PIN_GROUP(i2c3_c),
2220 SH_PFC_PIN_GROUP(i2c3_d),
2221 SH_PFC_PIN_GROUP(i2c3_e),
2222 SH_PFC_PIN_GROUP(i2c4_a),
2223 SH_PFC_PIN_GROUP(i2c4_b),
2224 SH_PFC_PIN_GROUP(i2c4_c),
2225 SH_PFC_PIN_GROUP(i2c4_d),
2226 SH_PFC_PIN_GROUP(i2c4_e),
2227 SH_PFC_PIN_GROUP(mmc_data1),
2228 SH_PFC_PIN_GROUP(mmc_data4),
2229 SH_PFC_PIN_GROUP(mmc_data8),
2230 SH_PFC_PIN_GROUP(mmc_ctrl),
2231 SH_PFC_PIN_GROUP(qspi0_ctrl),
2232 SH_PFC_PIN_GROUP(qspi0_data2),
2233 SH_PFC_PIN_GROUP(qspi0_data4),
2234 SH_PFC_PIN_GROUP(qspi1_ctrl),
2235 SH_PFC_PIN_GROUP(qspi1_data2),
2236 SH_PFC_PIN_GROUP(qspi1_data4),
2237 SH_PFC_PIN_GROUP(scif0_data_a),
2238 SH_PFC_PIN_GROUP(scif0_data_b),
2239 SH_PFC_PIN_GROUP(scif0_data_c),
2240 SH_PFC_PIN_GROUP(scif0_data_d),
2241 SH_PFC_PIN_GROUP(scif1_data_a),
2242 SH_PFC_PIN_GROUP(scif1_clk_a),
2243 SH_PFC_PIN_GROUP(scif1_data_b),
2244 SH_PFC_PIN_GROUP(scif1_clk_b),
2245 SH_PFC_PIN_GROUP(scif1_data_c),
2246 SH_PFC_PIN_GROUP(scif1_clk_c),
2247 SH_PFC_PIN_GROUP(scif1_data_d),
2248 SH_PFC_PIN_GROUP(scif2_data_a),
2249 SH_PFC_PIN_GROUP(scif2_clk_a),
2250 SH_PFC_PIN_GROUP(scif2_data_b),
2251 SH_PFC_PIN_GROUP(scif2_clk_b),
2252 SH_PFC_PIN_GROUP(scif2_data_c),
2253 SH_PFC_PIN_GROUP(scif3_data_a),
2254 SH_PFC_PIN_GROUP(scif3_clk),
2255 SH_PFC_PIN_GROUP(scif3_data_b),
2256 SH_PFC_PIN_GROUP(scif3_data_c),
2257 SH_PFC_PIN_GROUP(scif4_data_a),
2258 SH_PFC_PIN_GROUP(scif4_data_b),
2259 SH_PFC_PIN_GROUP(scif4_data_c),
2260 SH_PFC_PIN_GROUP(scif4_data_d),
2261 SH_PFC_PIN_GROUP(scif4_data_e),
2262 SH_PFC_PIN_GROUP(scif5_data_a),
2263 SH_PFC_PIN_GROUP(scif5_data_b),
2264 SH_PFC_PIN_GROUP(scif5_data_c),
2265 SH_PFC_PIN_GROUP(scif5_data_d),
2266 SH_PFC_PIN_GROUP(scif5_data_e),
2267 SH_PFC_PIN_GROUP(scif5_data_f),
2268 SH_PFC_PIN_GROUP(scif_clk_a),
2269 SH_PFC_PIN_GROUP(scif_clk_b),
2270 SH_PFC_PIN_GROUP(sdhi0_data1),
2271 SH_PFC_PIN_GROUP(sdhi0_data4),
2272 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2273 SH_PFC_PIN_GROUP(sdhi0_cd),
2274 SH_PFC_PIN_GROUP(sdhi0_wp),
2275 SH_PFC_PIN_GROUP(sdhi1_data1),
2276 SH_PFC_PIN_GROUP(sdhi1_data4),
2277 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2278 SH_PFC_PIN_GROUP(sdhi1_cd),
2279 SH_PFC_PIN_GROUP(sdhi1_wp),
2280 SH_PFC_PIN_GROUP(sdhi2_data1),
2281 SH_PFC_PIN_GROUP(sdhi2_data4),
2282 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2283 SH_PFC_PIN_GROUP(sdhi2_cd),
2284 SH_PFC_PIN_GROUP(sdhi2_wp),
2285 SH_PFC_PIN_GROUP(usb0),
2286 SH_PFC_PIN_GROUP(usb1),
2287 VIN_DATA_PIN_GROUP(vin0_data, 24),
2288 VIN_DATA_PIN_GROUP(vin0_data, 20),
2289 SH_PFC_PIN_GROUP(vin0_data18),
2290 VIN_DATA_PIN_GROUP(vin0_data, 16),
2291 VIN_DATA_PIN_GROUP(vin0_data, 12),
2292 VIN_DATA_PIN_GROUP(vin0_data, 10),
2293 VIN_DATA_PIN_GROUP(vin0_data, 8),
2294 SH_PFC_PIN_GROUP(vin0_sync),
2295 SH_PFC_PIN_GROUP(vin0_field),
2296 SH_PFC_PIN_GROUP(vin0_clkenb),
2297 SH_PFC_PIN_GROUP(vin0_clk),
2298 VIN_DATA_PIN_GROUP(vin1_data, 12),
2299 VIN_DATA_PIN_GROUP(vin1_data, 10),
2300 VIN_DATA_PIN_GROUP(vin1_data, 8),
2301 SH_PFC_PIN_GROUP(vin1_sync),
2302 SH_PFC_PIN_GROUP(vin1_field),
2303 SH_PFC_PIN_GROUP(vin1_clkenb),
2304 SH_PFC_PIN_GROUP(vin1_clk),
2305 };
2306
2307 static const char * const avb_groups[] = {
2308 "avb_col",
2309 "avb_crs",
2310 "avb_link",
2311 "avb_magic",
2312 "avb_phy_int",
2313 "avb_mdio",
2314 "avb_mii_tx_rx",
2315 "avb_mii_tx_er",
2316 "avb_gmii_tx_rx",
2317 "avb_avtp_match_a",
2318 "avb_avtp_capture_a",
2319 "avb_avtp_match_b",
2320 "avb_avtp_capture_b",
2321 };
2322
2323 static const char * const du0_groups[] = {
2324 "du0_rgb666",
2325 "du0_rgb888",
2326 "du0_clk0_out",
2327 "du0_clk1_out",
2328 "du0_clk_in",
2329 "du0_sync",
2330 "du0_oddf",
2331 "du0_cde",
2332 "du0_disp",
2333 };
2334
2335 static const char * const du1_groups[] = {
2336 "du1_rgb666",
2337 "du1_rgb888",
2338 "du1_clk0_out",
2339 "du1_clk1_out",
2340 "du1_clk_in",
2341 "du1_sync",
2342 "du1_oddf",
2343 "du1_cde",
2344 "du1_disp",
2345 };
2346
2347 static const char * const i2c0_groups[] = {
2348 "i2c0_a",
2349 "i2c0_b",
2350 "i2c0_c",
2351 "i2c0_d",
2352 "i2c0_e",
2353 };
2354
2355 static const char * const i2c1_groups[] = {
2356 "i2c1_a",
2357 "i2c1_b",
2358 "i2c1_c",
2359 "i2c1_d",
2360 "i2c1_e",
2361 };
2362
2363 static const char * const i2c2_groups[] = {
2364 "i2c2_a",
2365 "i2c2_b",
2366 "i2c2_c",
2367 "i2c2_d",
2368 };
2369
2370 static const char * const i2c3_groups[] = {
2371 "i2c3_a",
2372 "i2c3_b",
2373 "i2c3_c",
2374 "i2c3_d",
2375 "i2c3_e",
2376 };
2377
2378 static const char * const i2c4_groups[] = {
2379 "i2c4_a",
2380 "i2c4_b",
2381 "i2c4_c",
2382 "i2c4_d",
2383 "i2c4_e",
2384 };
2385
2386 static const char * const mmc_groups[] = {
2387 "mmc_data1",
2388 "mmc_data4",
2389 "mmc_data8",
2390 "mmc_ctrl",
2391 };
2392
2393 static const char * const qspi0_groups[] = {
2394 "qspi0_ctrl",
2395 "qspi0_data2",
2396 "qspi0_data4",
2397 };
2398
2399 static const char * const qspi1_groups[] = {
2400 "qspi1_ctrl",
2401 "qspi1_data2",
2402 "qspi1_data4",
2403 };
2404
2405 static const char * const scif0_groups[] = {
2406 "scif0_data_a",
2407 "scif0_data_b",
2408 "scif0_data_c",
2409 "scif0_data_d",
2410 };
2411
2412 static const char * const scif1_groups[] = {
2413 "scif1_data_a",
2414 "scif1_clk_a",
2415 "scif1_data_b",
2416 "scif1_clk_b",
2417 "scif1_data_c",
2418 "scif1_clk_c",
2419 "scif1_data_d",
2420 };
2421
2422 static const char * const scif2_groups[] = {
2423 "scif2_data_a",
2424 "scif2_clk_a",
2425 "scif2_data_b",
2426 "scif2_clk_b",
2427 "scif2_data_c",
2428 };
2429
2430 static const char * const scif3_groups[] = {
2431 "scif3_data_a",
2432 "scif3_clk",
2433 "scif3_data_b",
2434 "scif3_data_c",
2435 };
2436
2437 static const char * const scif4_groups[] = {
2438 "scif4_data_a",
2439 "scif4_data_b",
2440 "scif4_data_c",
2441 "scif4_data_d",
2442 "scif4_data_e",
2443 };
2444
2445 static const char * const scif5_groups[] = {
2446 "scif5_data_a",
2447 "scif5_data_b",
2448 "scif5_data_c",
2449 "scif5_data_d",
2450 "scif5_data_e",
2451 "scif5_data_f",
2452 };
2453
2454 static const char * const scif_clk_groups[] = {
2455 "scif_clk_a",
2456 "scif_clk_b",
2457 };
2458
2459 static const char * const sdhi0_groups[] = {
2460 "sdhi0_data1",
2461 "sdhi0_data4",
2462 "sdhi0_ctrl",
2463 "sdhi0_cd",
2464 "sdhi0_wp",
2465 };
2466
2467 static const char * const sdhi1_groups[] = {
2468 "sdhi1_data1",
2469 "sdhi1_data4",
2470 "sdhi1_ctrl",
2471 "sdhi1_cd",
2472 "sdhi1_wp",
2473 };
2474
2475 static const char * const sdhi2_groups[] = {
2476 "sdhi2_data1",
2477 "sdhi2_data4",
2478 "sdhi2_ctrl",
2479 "sdhi2_cd",
2480 "sdhi2_wp",
2481 };
2482
2483 static const char * const usb0_groups[] = {
2484 "usb0",
2485 };
2486
2487 static const char * const usb1_groups[] = {
2488 "usb1",
2489 };
2490
2491 static const char * const vin0_groups[] = {
2492 "vin0_data24",
2493 "vin0_data20",
2494 "vin0_data18",
2495 "vin0_data16",
2496 "vin0_data12",
2497 "vin0_data10",
2498 "vin0_data8",
2499 "vin0_sync",
2500 "vin0_field",
2501 "vin0_clkenb",
2502 "vin0_clk",
2503 };
2504
2505 static const char * const vin1_groups[] = {
2506 "vin1_data12",
2507 "vin1_data10",
2508 "vin1_data8",
2509 "vin1_sync",
2510 "vin1_field",
2511 "vin1_clkenb",
2512 "vin1_clk",
2513 };
2514
2515 static const struct sh_pfc_function pinmux_functions[] = {
2516 SH_PFC_FUNCTION(avb),
2517 SH_PFC_FUNCTION(du0),
2518 SH_PFC_FUNCTION(du1),
2519 SH_PFC_FUNCTION(i2c0),
2520 SH_PFC_FUNCTION(i2c1),
2521 SH_PFC_FUNCTION(i2c2),
2522 SH_PFC_FUNCTION(i2c3),
2523 SH_PFC_FUNCTION(i2c4),
2524 SH_PFC_FUNCTION(mmc),
2525 SH_PFC_FUNCTION(qspi0),
2526 SH_PFC_FUNCTION(qspi1),
2527 SH_PFC_FUNCTION(scif0),
2528 SH_PFC_FUNCTION(scif1),
2529 SH_PFC_FUNCTION(scif2),
2530 SH_PFC_FUNCTION(scif3),
2531 SH_PFC_FUNCTION(scif4),
2532 SH_PFC_FUNCTION(scif5),
2533 SH_PFC_FUNCTION(scif_clk),
2534 SH_PFC_FUNCTION(sdhi0),
2535 SH_PFC_FUNCTION(sdhi1),
2536 SH_PFC_FUNCTION(sdhi2),
2537 SH_PFC_FUNCTION(usb0),
2538 SH_PFC_FUNCTION(usb1),
2539 SH_PFC_FUNCTION(vin0),
2540 SH_PFC_FUNCTION(vin1),
2541 };
2542
2543 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2544 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
2545 0, 0,
2546 0, 0,
2547 0, 0,
2548 0, 0,
2549 0, 0,
2550 0, 0,
2551 0, 0,
2552 0, 0,
2553 0, 0,
2554 GP_0_22_FN, FN_MMC0_D7,
2555 GP_0_21_FN, FN_MMC0_D6,
2556 GP_0_20_FN, FN_IP1_7_4,
2557 GP_0_19_FN, FN_IP1_3_0,
2558 GP_0_18_FN, FN_MMC0_D3_SDHI1_D3,
2559 GP_0_17_FN, FN_MMC0_D2_SDHI1_D2,
2560 GP_0_16_FN, FN_MMC0_D1_SDHI1_D1,
2561 GP_0_15_FN, FN_MMC0_D0_SDHI1_D0,
2562 GP_0_14_FN, FN_MMC0_CMD_SDHI1_CMD,
2563 GP_0_13_FN, FN_MMC0_CLK_SDHI1_CLK,
2564 GP_0_12_FN, FN_IP0_31_28,
2565 GP_0_11_FN, FN_IP0_27_24,
2566 GP_0_10_FN, FN_IP0_23_20,
2567 GP_0_9_FN, FN_IP0_19_16,
2568 GP_0_8_FN, FN_IP0_15_12,
2569 GP_0_7_FN, FN_IP0_11_8,
2570 GP_0_6_FN, FN_IP0_7_4,
2571 GP_0_5_FN, FN_IP0_3_0,
2572 GP_0_4_FN, FN_CLKOUT,
2573 GP_0_3_FN, FN_USB1_OVC,
2574 GP_0_2_FN, FN_USB1_PWEN,
2575 GP_0_1_FN, FN_USB0_OVC,
2576 GP_0_0_FN, FN_USB0_PWEN, ))
2577 },
2578 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
2579 0, 0,
2580 0, 0,
2581 0, 0,
2582 0, 0,
2583 0, 0,
2584 0, 0,
2585 0, 0,
2586 0, 0,
2587 0, 0,
2588 GP_1_22_FN, FN_IP4_3_0,
2589 GP_1_21_FN, FN_IP3_31_28,
2590 GP_1_20_FN, FN_IP3_27_24,
2591 GP_1_19_FN, FN_IP3_23_20,
2592 GP_1_18_FN, FN_IP3_19_16,
2593 GP_1_17_FN, FN_IP3_15_12,
2594 GP_1_16_FN, FN_IP3_11_8,
2595 GP_1_15_FN, FN_IP3_7_4,
2596 GP_1_14_FN, FN_IP3_3_0,
2597 GP_1_13_FN, FN_IP2_31_28,
2598 GP_1_12_FN, FN_IP2_27_24,
2599 GP_1_11_FN, FN_IP2_23_20,
2600 GP_1_10_FN, FN_IP2_19_16,
2601 GP_1_9_FN, FN_IP2_15_12,
2602 GP_1_8_FN, FN_IP2_11_8,
2603 GP_1_7_FN, FN_IP2_7_4,
2604 GP_1_6_FN, FN_IP2_3_0,
2605 GP_1_5_FN, FN_IP1_31_28,
2606 GP_1_4_FN, FN_IP1_27_24,
2607 GP_1_3_FN, FN_IP1_23_20,
2608 GP_1_2_FN, FN_IP1_19_16,
2609 GP_1_1_FN, FN_IP1_15_12,
2610 GP_1_0_FN, FN_IP1_11_8, ))
2611 },
2612 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
2613 GP_2_31_FN, FN_IP8_3_0,
2614 GP_2_30_FN, FN_IP7_31_28,
2615 GP_2_29_FN, FN_IP7_27_24,
2616 GP_2_28_FN, FN_IP7_23_20,
2617 GP_2_27_FN, FN_IP7_19_16,
2618 GP_2_26_FN, FN_IP7_15_12,
2619 GP_2_25_FN, FN_IP7_11_8,
2620 GP_2_24_FN, FN_IP7_7_4,
2621 GP_2_23_FN, FN_IP7_3_0,
2622 GP_2_22_FN, FN_IP6_31_28,
2623 GP_2_21_FN, FN_IP6_27_24,
2624 GP_2_20_FN, FN_IP6_23_20,
2625 GP_2_19_FN, FN_IP6_19_16,
2626 GP_2_18_FN, FN_IP6_15_12,
2627 GP_2_17_FN, FN_IP6_11_8,
2628 GP_2_16_FN, FN_IP6_7_4,
2629 GP_2_15_FN, FN_IP6_3_0,
2630 GP_2_14_FN, FN_IP5_31_28,
2631 GP_2_13_FN, FN_IP5_27_24,
2632 GP_2_12_FN, FN_IP5_23_20,
2633 GP_2_11_FN, FN_IP5_19_16,
2634 GP_2_10_FN, FN_IP5_15_12,
2635 GP_2_9_FN, FN_IP5_11_8,
2636 GP_2_8_FN, FN_IP5_7_4,
2637 GP_2_7_FN, FN_IP5_3_0,
2638 GP_2_6_FN, FN_IP4_31_28,
2639 GP_2_5_FN, FN_IP4_27_24,
2640 GP_2_4_FN, FN_IP4_23_20,
2641 GP_2_3_FN, FN_IP4_19_16,
2642 GP_2_2_FN, FN_IP4_15_12,
2643 GP_2_1_FN, FN_IP4_11_8,
2644 GP_2_0_FN, FN_IP4_7_4, ))
2645 },
2646 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
2647 0, 0,
2648 0, 0,
2649 GP_3_29_FN, FN_IP10_19_16,
2650 GP_3_28_FN, FN_IP10_15_12,
2651 GP_3_27_FN, FN_IP10_11_8,
2652 0, 0,
2653 0, 0,
2654 0, 0,
2655 0, 0,
2656 0, 0,
2657 0, 0,
2658 0, 0,
2659 0, 0,
2660 0, 0,
2661 0, 0,
2662 GP_3_16_FN, FN_IP10_7_4,
2663 GP_3_15_FN, FN_IP10_3_0,
2664 GP_3_14_FN, FN_IP9_31_28,
2665 GP_3_13_FN, FN_IP9_27_24,
2666 GP_3_12_FN, FN_IP9_23_20,
2667 GP_3_11_FN, FN_IP9_19_16,
2668 GP_3_10_FN, FN_IP9_15_12,
2669 GP_3_9_FN, FN_IP9_11_8,
2670 GP_3_8_FN, FN_IP9_7_4,
2671 GP_3_7_FN, FN_IP9_3_0,
2672 GP_3_6_FN, FN_IP8_31_28,
2673 GP_3_5_FN, FN_IP8_27_24,
2674 GP_3_4_FN, FN_IP8_23_20,
2675 GP_3_3_FN, FN_IP8_19_16,
2676 GP_3_2_FN, FN_IP8_15_12,
2677 GP_3_1_FN, FN_IP8_11_8,
2678 GP_3_0_FN, FN_IP8_7_4, ))
2679 },
2680 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
2681 0, 0,
2682 0, 0,
2683 0, 0,
2684 0, 0,
2685 0, 0,
2686 0, 0,
2687 GP_4_25_FN, FN_IP13_27_24,
2688 GP_4_24_FN, FN_IP13_23_20,
2689 GP_4_23_FN, FN_IP13_19_16,
2690 GP_4_22_FN, FN_IP13_15_12,
2691 GP_4_21_FN, FN_IP13_11_8,
2692 GP_4_20_FN, FN_IP13_7_4,
2693 GP_4_19_FN, FN_IP13_3_0,
2694 GP_4_18_FN, FN_IP12_31_28,
2695 GP_4_17_FN, FN_IP12_27_24,
2696 GP_4_16_FN, FN_IP12_23_20,
2697 GP_4_15_FN, FN_IP12_19_16,
2698 GP_4_14_FN, FN_IP12_15_12,
2699 GP_4_13_FN, FN_IP12_11_8,
2700 GP_4_12_FN, FN_IP12_7_4,
2701 GP_4_11_FN, FN_IP12_3_0,
2702 GP_4_10_FN, FN_IP11_31_28,
2703 GP_4_9_FN, FN_IP11_27_24,
2704 GP_4_8_FN, FN_IP11_23_20,
2705 GP_4_7_FN, FN_IP11_19_16,
2706 GP_4_6_FN, FN_IP11_15_12,
2707 GP_4_5_FN, FN_IP11_11_8,
2708 GP_4_4_FN, FN_IP11_7_4,
2709 GP_4_3_FN, FN_IP11_3_0,
2710 GP_4_2_FN, FN_IP10_31_28,
2711 GP_4_1_FN, FN_IP10_27_24,
2712 GP_4_0_FN, FN_IP10_23_20, ))
2713 },
2714 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
2715 GP_5_31_FN, FN_IP17_27_24,
2716 GP_5_30_FN, FN_IP17_23_20,
2717 GP_5_29_FN, FN_IP17_19_16,
2718 GP_5_28_FN, FN_IP17_15_12,
2719 GP_5_27_FN, FN_IP17_11_8,
2720 GP_5_26_FN, FN_IP17_7_4,
2721 GP_5_25_FN, FN_IP17_3_0,
2722 GP_5_24_FN, FN_IP16_31_28,
2723 GP_5_23_FN, FN_IP16_27_24,
2724 GP_5_22_FN, FN_IP16_23_20,
2725 GP_5_21_FN, FN_IP16_19_16,
2726 GP_5_20_FN, FN_IP16_15_12,
2727 GP_5_19_FN, FN_IP16_11_8,
2728 GP_5_18_FN, FN_IP16_7_4,
2729 GP_5_17_FN, FN_IP16_3_0,
2730 GP_5_16_FN, FN_IP15_31_28,
2731 GP_5_15_FN, FN_IP15_27_24,
2732 GP_5_14_FN, FN_IP15_23_20,
2733 GP_5_13_FN, FN_IP15_19_16,
2734 GP_5_12_FN, FN_IP15_15_12,
2735 GP_5_11_FN, FN_IP15_11_8,
2736 GP_5_10_FN, FN_IP15_7_4,
2737 GP_5_9_FN, FN_IP15_3_0,
2738 GP_5_8_FN, FN_IP14_31_28,
2739 GP_5_7_FN, FN_IP14_27_24,
2740 GP_5_6_FN, FN_IP14_23_20,
2741 GP_5_5_FN, FN_IP14_19_16,
2742 GP_5_4_FN, FN_IP14_15_12,
2743 GP_5_3_FN, FN_IP14_11_8,
2744 GP_5_2_FN, FN_IP14_7_4,
2745 GP_5_1_FN, FN_IP14_3_0,
2746 GP_5_0_FN, FN_IP13_31_28, ))
2747 },
2748 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2749 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2750 GROUP(
2751 /* IP0_31_28 [4] */
2752 FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
2753 0, 0, 0, 0, 0, 0, 0, 0,
2754 /* IP0_27_24 [4] */
2755 FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0,
2756 0, 0, 0, 0, 0, 0, 0, 0,
2757 /* IP0_23_20 [4] */
2758 FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0,
2759 0, 0, 0, 0, 0, 0, 0, 0,
2760 /* IP0_19_16 [4] */
2761 FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0,
2762 0, 0, 0, 0, 0, 0, 0, 0,
2763 /* IP0_15_12 [4] */
2764 FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0,
2765 0, 0, 0, 0, 0, 0, 0, 0,
2766 /* IP0_11_8 [4] */
2767 FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0,
2768 0, 0, 0, 0, 0, 0, 0, 0,
2769 /* IP0_7_4 [4] */
2770 FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0,
2771 0, 0, 0, 0, 0, 0, 0, 0,
2772 /* IP0_3_0 [4] */
2773 FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
2774 0, 0, 0, 0, 0, 0, 0, 0, ))
2775 },
2776 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2777 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2778 GROUP(
2779 /* IP1_31_28 [4] */
2780 FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
2781 0, 0, 0, 0, 0, 0, 0, 0,
2782 /* IP1_27_24 [4] */
2783 FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0,
2784 0, 0, 0, 0, 0, 0, 0, 0,
2785 /* IP1_23_20 [4] */
2786 FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A,
2787 FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2788 /* IP1_19_16 [4] */
2789 FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C,
2790 FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2791 /* IP1_15_12 [4] */
2792 FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C,
2793 FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2794 /* IP1_11_8 [4] */
2795 FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4,
2796 FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2797 /* IP1_7_4 [4] */
2798 FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0,
2799 0, 0, 0, 0, 0, 0, 0, 0,
2800 /* IP1_3_0 [4] */
2801 FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
2802 0, 0, 0, 0, 0, 0, 0, 0, ))
2803 },
2804 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2805 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2806 GROUP(
2807 /* IP2_31_28 [4] */
2808 FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
2809 0, 0, 0, 0, 0, 0, 0,
2810 /* IP2_27_24 [4] */
2811 FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C,
2812 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2813 /* IP2_23_20 [4] */
2814 FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0,
2815 0, 0, 0, 0, 0, 0, 0,
2816 /* IP2_19_16 [4] */
2817 FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0,
2818 0, 0, 0, 0, 0, 0, 0,
2819 /* IP2_15_12 [4] */
2820 FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0,
2821 0, 0, 0, 0, 0, 0, 0, 0, 0,
2822 /* IP2_11_8 [4] */
2823 FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0,
2824 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2825 /* IP2_7_4 [4] */
2826 FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
2827 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2828 /* IP2_3_0 [4] */
2829 FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
2830 0, 0, 0, 0, 0, 0, 0, 0, ))
2831 },
2832 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2833 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2834 GROUP(
2835 /* IP3_31_28 [4] */
2836 FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2837 0, 0,
2838 /* IP3_27_24 [4] */
2839 FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2840 0, 0,
2841 /* IP3_23_20 [4] */
2842 FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2843 0, 0,
2844 /* IP3_19_16 [4] */
2845 FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2846 0, 0, 0, 0,
2847 /* IP3_15_12 [4] */
2848 FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2849 0, 0, 0,
2850 /* IP3_11_8 [4] */
2851 FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2852 0, 0,
2853 /* IP3_7_4 [4] */
2854 FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2,
2855 FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2856 /* IP3_3_0 [4] */
2857 FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
2858 0, FN_AVB_AVTP_CAPTURE_A,
2859 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2860 },
2861 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2862 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2863 GROUP(
2864 /* IP4_31_28 [4] */
2865 FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
2866 0, 0, 0, 0, 0, 0, 0, 0,
2867 /* IP4_27_24 [4] */
2868 FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0,
2869 0, 0, 0, 0, 0, 0, 0, 0,
2870 /* IP4_23_20 [4] */
2871 FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0,
2872 0, 0, 0, 0, 0,
2873 /* IP4_19_16 [4] */
2874 FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0,
2875 FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2876 /* IP4_15_12 [4] */
2877 FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0,
2878 0, 0, 0, 0, 0, 0, 0, 0,
2879 /* IP4_11_8 [4] */
2880 FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0,
2881 0, 0, 0, 0, 0, 0, 0, 0,
2882 /* IP4_7_4 [4] */
2883 FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0,
2884 0, 0, 0, 0, 0, 0, 0, 0,
2885 /* IP4_3_0 [4] */
2886 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
2887 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2888 },
2889 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2890 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2891 GROUP(
2892 /* IP5_31_28 [4] */
2893 FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0,
2894 0, 0, 0, 0, 0, 0,
2895 /* IP5_27_24 [4] */
2896 FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13,
2897 0, 0, 0, 0, 0, 0, 0, 0, 0,
2898 /* IP5_23_20 [4] */
2899 FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0,
2900 0, 0, 0, 0, 0, 0,
2901 /* IP5_19_16 [4] */
2902 FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0,
2903 0, 0, 0, 0, 0, 0, 0, 0,
2904 /* IP5_15_12 [4] */
2905 FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0,
2906 0, 0, 0, 0, 0, 0,
2907 /* IP5_11_8 [4] */
2908 FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0,
2909 FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2910 /* IP5_7_4 [4] */
2911 FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0,
2912 0, 0, 0, 0, 0, 0, 0, 0,
2913 /* IP5_3_0 [4] */
2914 FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
2915 0, 0, 0, 0, 0, 0, 0, 0, ))
2916 },
2917 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2918 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2919 GROUP(
2920 /* IP6_31_28 [4] */
2921 FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
2922 0, 0, 0, 0, 0, 0, 0,
2923 /* IP6_27_24 [4] */
2924 FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0,
2925 FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2926 /* IP6_23_20 [4] */
2927 FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0,
2928 FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2929 /* IP6_19_16 [4] */
2930 FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0,
2931 0, 0, 0, 0, 0, 0,
2932 /* IP6_15_12 [4] */
2933 FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0,
2934 0, 0, 0, 0, 0, 0,
2935 /* IP6_11_8 [4] */
2936 FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17,
2937 0, 0, 0, 0, 0, 0, 0, 0, 0,
2938 /* IP6_7_4 [4] */
2939 FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16,
2940 0, 0, 0, 0, 0, 0, 0, 0, 0,
2941 /* IP6_3_0 [4] */
2942 FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15,
2943 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
2944 },
2945 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2946 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2947 GROUP(
2948 /* IP7_31_28 [4] */
2949 FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
2950 0, 0, 0, 0, 0,
2951 /* IP7_27_24 [4] */
2952 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B,
2953 0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2954 /* IP7_23_20 [4] */
2955 FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0,
2956 0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2957 /* IP7_19_16 [4] */
2958 FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0,
2959 0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2960 /* IP7_15_12 [4] */
2961 FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0,
2962 FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2963 /* IP7_11_8 [4] */
2964 FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0,
2965 0, 0, 0, 0, 0,
2966 /* IP7_7_4 [4] */
2967 FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0,
2968 0, 0, 0, 0, 0, 0,
2969 /* IP7_3_0 [4] */
2970 FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
2971 0, 0, 0, 0, 0, 0, 0, ))
2972 },
2973 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
2974 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
2975 GROUP(
2976 /* IP8_31_28 [4] */
2977 FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
2978 0, 0, 0, 0, 0, 0,
2979 /* IP8_27_24 [4] */
2980 FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0,
2981 0, 0, 0, 0, 0, 0,
2982 /* IP8_23_20 [4] */
2983 FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0,
2984 0, 0, 0, 0, 0, 0,
2985 /* IP8_19_16 [4] */
2986 FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0,
2987 0, 0, 0, 0, 0, 0,
2988 /* IP8_15_12 [4] */
2989 FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0,
2990 0, 0, 0, 0, 0, 0,
2991 /* IP8_11_8 [4] */
2992 FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0,
2993 0, 0, 0, 0, 0, 0, 0,
2994 /* IP8_7_4 [4] */
2995 FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0,
2996 0, 0, 0, 0, 0, 0, 0,
2997 /* IP8_3_0 [4] */
2998 FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
2999 0, 0, 0, 0, ))
3000 },
3001 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
3002 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3003 GROUP(
3004 /* IP9_31_28 [4] */
3005 FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
3006 0, 0, 0, 0, 0,
3007 /* IP9_27_24 [4] */
3008 FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0,
3009 0, 0, 0, 0, 0,
3010 /* IP9_23_20 [4] */
3011 FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B,
3012 FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3013 /* IP9_19_16 [4] */
3014 FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK,
3015 FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3016 /* IP9_15_12 [4] */
3017 FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0,
3018 0, 0, 0, 0, 0, 0, 0, 0, 0,
3019 /* IP9_11_8 [4] */
3020 FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0,
3021 0, 0, 0, 0, 0, 0, 0, 0, 0,
3022 /* IP9_7_4 [4] */
3023 FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0,
3024 0, 0, 0, 0, 0, 0,
3025 /* IP9_3_0 [4] */
3026 FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
3027 0, 0, 0, 0, 0, 0, ))
3028 },
3029 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
3030 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3031 GROUP(
3032 /* IP10_31_28 [4] */
3033 FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
3034 FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
3035 /* IP10_27_24 [4] */
3036 FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK,
3037 FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3038 /* IP10_23_20 [4] */
3039 FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6,
3040 FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3041 /* IP10_19_16 [4] */
3042 FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0,
3043 FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0,
3044 0, 0,
3045 /* IP10_15_12 [4] */
3046 FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F,
3047 FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3048 /* IP10_11_8 [4] */
3049 FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F,
3050 FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3051 /* IP10_7_4 [4] */
3052 FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0,
3053 0, 0, 0, 0, 0, 0, 0,
3054 /* IP10_3_0 [4] */
3055 FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
3056 0, 0, 0, 0, 0, 0, 0, ))
3057 },
3058 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
3059 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3060 GROUP(
3061 /* IP11_31_28 [4] */
3062 FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
3063 0, 0, 0, 0, 0, 0, 0, 0, 0,
3064 /* IP11_27_24 [4] */
3065 FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0,
3066 FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3067 /* IP11_23_20 [4] */
3068 FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0,
3069 FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3070 /* IP11_19_16 [4] */
3071 FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5,
3072 0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0,
3073 0, 0, 0, 0,
3074 /* IP11_15_12 [4] */
3075 FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4,
3076 0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
3077 0, 0, 0, 0, 0, 0, 0, 0,
3078 /* IP11_11_8 [4] */
3079 FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0,
3080 FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
3081 0, 0, 0, 0, 0, 0, 0, 0,
3082 /* IP11_7_4 [4] */
3083 FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0,
3084 FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
3085 0, 0, 0, 0, 0, 0, 0, 0,
3086 /* IP11_3_0 [4] */
3087 FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
3088 FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
3089 },
3090 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
3091 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3092 GROUP(
3093 /* IP12_31_28 [4] */
3094 FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
3095 0, 0, 0, 0, 0, 0, 0, 0, 0,
3096 /* IP12_27_24 [4] */
3097 FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
3098 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3099 /* IP12_23_20 [4] */
3100 FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6,
3101 FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3102 /* IP12_19_16 [4] */
3103 FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5,
3104 FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3105 /* IP12_15_12 [4] */
3106 FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0,
3107 0, 0, 0, 0, 0, 0, 0, 0,
3108 /* IP12_11_8 [4] */
3109 FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0,
3110 0, 0, 0, 0, 0, 0, 0, 0,
3111 /* IP12_7_4 [4] */
3112 FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B,
3113 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3114 /* IP12_3_0 [4] */
3115 FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
3116 0, 0, 0, 0, 0, 0, ))
3117 },
3118 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
3119 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3120 GROUP(
3121 /* IP13_31_28 [4] */
3122 FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
3123 0, 0, 0, 0, 0,
3124 /* IP13_27_24 [4] */
3125 FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
3126 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3127 /* IP13_23_20 [4] */
3128 FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C,
3129 FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3130 /* IP13_19_16 [4] */
3131 FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5,
3132 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3133 /* IP13_15_12 [4] */
3134 FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4,
3135 FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0,
3136 0, 0,
3137 /* IP13_11_8 [4] */
3138 FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0,
3139 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3140 /* IP13_7_4 [4] */
3141 FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0,
3142 0, 0, 0, 0, 0, 0, 0, 0, 0,
3143 /* IP13_3_0 [4] */
3144 FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
3145 0, 0, 0, 0, 0, 0, 0, 0, ))
3146 },
3147 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
3148 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3149 GROUP(
3150 /* IP14_31_28 [4] */
3151 FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
3152 FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3153 /* IP14_27_24 [4] */
3154 FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0,
3155 0, 0, 0, 0, 0,
3156 /* IP14_23_20 [4] */
3157 FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0,
3158 0, 0, 0, 0, 0, 0,
3159 /* IP14_19_16 [4] */
3160 FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0,
3161 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3162 /* IP14_15_12 [4] */
3163 FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0,
3164 0, 0, 0, 0, 0, 0, 0, 0, 0,
3165 /* IP14_11_8 [4] */
3166 FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0,
3167 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3168 /* IP14_7_4 [4] */
3169 FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0,
3170 0, 0, 0, 0, 0, 0, 0, 0, 0,
3171 /* IP14_3_0 [4] */
3172 FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
3173 0, 0, 0, 0, 0, 0, ))
3174 },
3175 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
3176 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3177 GROUP(
3178 /* IP15_31_28 [4] */
3179 FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
3180 0, 0, 0, 0, 0, 0,
3181 /* IP15_27_24 [4] */
3182 FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0,
3183 0, 0, 0, 0, 0, 0,
3184 /* IP15_23_20 [4] */
3185 FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A,
3186 FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3187 /* IP15_19_16 [4] */
3188 FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A,
3189 FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3190 /* IP15_15_12 [4] */
3191 FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1,
3192 FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3193 /* IP15_11_8 [4] */
3194 FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0,
3195 FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3196 /* IP15_7_4 [4] */
3197 FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0,
3198 FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3199 /* IP15_3_0 [4] */
3200 FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
3201 FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
3202 },
3203 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
3204 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3205 GROUP(
3206 /* IP16_31_28 [4] */
3207 FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
3208 FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3209 /* IP16_27_24 [4] */
3210 FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER,
3211 FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3212 /* IP16_23_20 [4] */
3213 FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7,
3214 FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3215 /* IP16_19_16 [4] */
3216 FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1,
3217 0, 0, 0, 0, 0, 0, 0, 0, 0,
3218 /* IP16_15_12 [4] */
3219 FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D,
3220 FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0,
3221 0, 0, 0,
3222 /* IP16_11_8 [4] */
3223 FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D,
3224 FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3225 /* IP16_7_4 [4] */
3226 FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A,
3227 FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
3228 /* IP16_3_0 [4] */
3229 FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
3230 0, 0, 0, 0, 0, 0, ))
3231 },
3232 { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
3233 GROUP(4, 4, 4, 4, 4, 4, 4, 4),
3234 GROUP(
3235 /* IP17_31_28 [4] */
3236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3237 /* IP17_27_24 [4] */
3238 FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
3239 FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3240 /* IP17_23_20 [4] */
3241 FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0,
3242 FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3243 /* IP17_19_16 [4] */
3244 FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0,
3245 FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3246 /* IP17_15_12 [4] */
3247 FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0,
3248 FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3249 /* IP17_11_8 [4] */
3250 FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0,
3251 FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3252 /* IP17_7_4 [4] */
3253 FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0,
3254 FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3255 /* IP17_3_0 [4] */
3256 FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
3257 FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
3258 },
3259 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
3260 GROUP(1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1,
3261 3, 3, 1, 2, 3, 3, 1),
3262 GROUP(
3263 /* RESERVED [1] */
3264 0, 0,
3265 /* RESERVED [1] */
3266 0, 0,
3267 /* RESERVED [1] */
3268 0, 0,
3269 /* RESERVED [1] */
3270 0, 0,
3271 /* RESERVED [1] */
3272 0, 0,
3273 /* SEL_ADGA [2] */
3274 FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
3275 /* RESERVED [1] */
3276 0, 0,
3277 /* RESERVED [1] */
3278 0, 0,
3279 /* SEL_CANCLK [2] */
3280 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
3281 FN_SEL_CANCLK_3,
3282 /* SEL_CAN1 [2] */
3283 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
3284 /* SEL_CAN0 [2] */
3285 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
3286 /* RESERVED [1] */
3287 0, 0,
3288 /* SEL_I2C04 [3] */
3289 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
3290 FN_SEL_I2C04_4, 0, 0, 0,
3291 /* SEL_I2C03 [3] */
3292 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
3293 FN_SEL_I2C03_4, 0, 0, 0,
3294 /* RESERVED [1] */
3295 0, 0,
3296 /* SEL_I2C02 [2] */
3297 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
3298 /* SEL_I2C01 [3] */
3299 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
3300 FN_SEL_I2C01_4, 0, 0, 0,
3301 /* SEL_I2C00 [3] */
3302 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
3303 FN_SEL_I2C00_4, 0, 0, 0,
3304 /* SEL_AVB [1] */
3305 FN_SEL_AVB_0, FN_SEL_AVB_1, ))
3306 },
3307 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
3308 GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, 1, 1, 1,
3309 1, 1, 2, 1, 1, 2, 2, 1),
3310 GROUP(
3311 /* SEL_SCIFCLK [1] */
3312 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
3313 /* SEL_SCIF5 [3] */
3314 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
3315 FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0,
3316 /* SEL_SCIF4 [3] */
3317 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
3318 FN_SEL_SCIF4_4, 0, 0, 0,
3319 /* SEL_SCIF3 [2] */
3320 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0,
3321 /* SEL_SCIF2 [2] */
3322 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
3323 /* SEL_SCIF2_CLK [1] */
3324 FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
3325 /* SEL_SCIF1 [2] */
3326 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
3327 /* SEL_SCIF0 [2] */
3328 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
3329 /* SEL_MSIOF2 [2] */
3330 FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
3331 /* RESERVED [1] */
3332 0, 0,
3333 /* SEL_MSIOF1 [1] */
3334 FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
3335 /* RESERVED [1] */
3336 0, 0,
3337 /* SEL_MSIOF0 [1] */
3338 FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
3339 /* SEL_RCN [1] */
3340 FN_SEL_RCN_0, FN_SEL_RCN_1,
3341 /* RESERVED [2] */
3342 0, 0, 0, 0,
3343 /* SEL_TMU2 [1] */
3344 FN_SEL_TMU2_0, FN_SEL_TMU2_1,
3345 /* SEL_TMU1 [1] */
3346 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
3347 /* RESERVED [2] */
3348 0, 0, 0, 0,
3349 /* SEL_HSCIF1 [2] */
3350 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
3351 /* SEL_HSCIF0 [1] */
3352 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ))
3353 },
3354 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
3355 GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
3356 2, 2, 2, 2, 2, 2, 2, 2, 2),
3357 GROUP(
3358 /* RESERVED [1] */
3359 0, 0,
3360 /* RESERVED [1] */
3361 0, 0,
3362 /* RESERVED [1] */
3363 0, 0,
3364 /* RESERVED [1] */
3365 0, 0,
3366 /* RESERVED [1] */
3367 0, 0,
3368 /* RESERVED [1] */
3369 0, 0,
3370 /* RESERVED [1] */
3371 0, 0,
3372 /* RESERVED [1] */
3373 0, 0,
3374 /* RESERVED [1] */
3375 0, 0,
3376 /* RESERVED [1] */
3377 0, 0,
3378 /* SEL_ADGB [2] */
3379 FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
3380 /* SEL_ADGC [2] */
3381 FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0,
3382 /* SEL_SSI9 [2] */
3383 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0,
3384 /* SEL_SSI8 [2] */
3385 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0,
3386 /* SEL_SSI7 [2] */
3387 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0,
3388 /* SEL_SSI6 [2] */
3389 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0,
3390 /* SEL_SSI5 [2] */
3391 FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0,
3392 /* SEL_SSI4 [2] */
3393 FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0,
3394 /* SEL_SSI2 [2] */
3395 FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0,
3396 /* SEL_SSI1 [2] */
3397 FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
3398 /* SEL_SSI0 [2] */
3399 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
3400 },
3401 { },
3402 };
3403
r8a77470_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)3404 static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
3405 u32 *pocctrl)
3406 {
3407 int bit = -EINVAL;
3408
3409 *pocctrl = 0xe60600b0;
3410
3411 if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10))
3412 bit = 0;
3413
3414 if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22))
3415 bit = 2;
3416
3417 if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19))
3418 bit = 1;
3419
3420 return bit;
3421 }
3422
3423 static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
3424 .pin_to_pocctrl = r8a77470_pin_to_pocctrl,
3425 };
3426
3427 #ifdef CONFIG_PINCTRL_PFC_R8A77470
3428 const struct sh_pfc_soc_info r8a77470_pinmux_info = {
3429 .name = "r8a77470_pfc",
3430 .ops = &r8a77470_pinmux_ops,
3431 .unlock_reg = 0xe6060000, /* PMMR */
3432
3433 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3434
3435 .pins = pinmux_pins,
3436 .nr_pins = ARRAY_SIZE(pinmux_pins),
3437 .groups = pinmux_groups,
3438 .nr_groups = ARRAY_SIZE(pinmux_groups),
3439 .functions = pinmux_functions,
3440 .nr_functions = ARRAY_SIZE(pinmux_functions),
3441
3442 .cfg_regs = pinmux_config_regs,
3443
3444 .pinmux_data = pinmux_data,
3445 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3446 };
3447 #endif
3448
