1 /*
2 * r8a7791/r8a7743 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2014-2017 Cogent Embedded, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2
9 * as published by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13
14 #include "sh_pfc.h"
15
16 /*
17 * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
18 * which case they support both 3.3V and 1.8V signalling.
19 */
20 #define CPU_ALL_PORT(fn, sfx) \
21 PORT_GP_32(0, fn, sfx), \
22 PORT_GP_26(1, fn, sfx), \
23 PORT_GP_32(2, fn, sfx), \
24 PORT_GP_32(3, fn, sfx), \
25 PORT_GP_32(4, fn, sfx), \
26 PORT_GP_32(5, fn, sfx), \
27 PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_1(6, 24, fn, sfx), \
29 PORT_GP_1(6, 25, fn, sfx), \
30 PORT_GP_1(6, 26, fn, sfx), \
31 PORT_GP_1(6, 27, fn, sfx), \
32 PORT_GP_1(6, 28, fn, sfx), \
33 PORT_GP_1(6, 29, fn, sfx), \
34 PORT_GP_1(6, 30, fn, sfx), \
35 PORT_GP_1(6, 31, fn, sfx), \
36 PORT_GP_26(7, fn, sfx)
37
38 enum {
39 PINMUX_RESERVED = 0,
40
41 PINMUX_DATA_BEGIN,
42 GP_ALL(DATA),
43 PINMUX_DATA_END,
44
45 PINMUX_FUNCTION_BEGIN,
46 GP_ALL(FN),
47
48 /* GPSR0 */
49 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
50 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
51 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
52 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
53 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
54 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
55
56 /* GPSR1 */
57 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
58 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
59 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
60 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
61 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
62 FN_IP3_21_20,
63
64 /* GPSR2 */
65 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
66 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
67 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
68 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
69 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
70 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
71 FN_IP6_5_3, FN_IP6_7_6,
72
73 /* GPSR3 */
74 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
75 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
76 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
77 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
78 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
79 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
80 FN_IP9_18_17,
81
82 /* GPSR4 */
83 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
84 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
85 FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
86 FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
87 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
88 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
89 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
90 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
91
92 /* GPSR5 */
93 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
94 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
95 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
96 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
97 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
98 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
99 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
100
101 /* GPSR6 */
102 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
103 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
104 FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
105 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
106 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
107 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
108 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
109 FN_USB1_OVC, FN_DU0_DOTCLKIN,
110
111 /* GPSR7 */
112 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
113 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
114 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
115 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
116 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
117 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
118
119 /* IPSR0 */
120 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
121 FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
122 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
123 FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
124 FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
125 FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
126
127 /* IPSR1 */
128 FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL,
129 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
130 FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
131 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
132 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
133 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
134 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
135 FN_A15, FN_BPFCLK_C,
136 FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
137 FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
138 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
139
140 /* IPSR2 */
141 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
142 FN_A20, FN_SPCLK,
143 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
144 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
145 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
146 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
147 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
148 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
149 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA,
150 FN_EX_CS1_N, FN_MSIOF2_SCK,
151 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
152 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
153
154 /* IPSR3 */
155 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
156 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
157 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
158 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
159 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
160 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
161 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
162 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
163 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
164 FN_DREQ0, FN_PWM3, FN_TPU_TO3,
165 FN_DACK0, FN_DRACK0, FN_REMOCON,
166 FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
167 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
168 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
169 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
170
171 /* IPSR4 */
172 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
173 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
174 FN_GLO_I0_D,
175 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
176 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
177 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
178 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
179 FN_GLO_Q1_D, FN_HCTS1_N_E,
180 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
181 FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
182 FN_SSI_SCK4, FN_GLO_SS_D,
183 FN_SSI_WS4, FN_GLO_RFON_D,
184 FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
185 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
186 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
187
188 /* IPSR5 */
189 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
190 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
191 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
192 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
193 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
194 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
195 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
196 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
197 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
198 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
199 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
200 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
201 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
202 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
203 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
204
205 /* IPSR6 */
206 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
207 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
208 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
209 FN_SCIFA2_RXD, FN_FMIN_E,
210 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
211 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
212 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
213 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
214 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
215 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
216 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
217 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
218 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
219 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
220
221 /* IPSR7 */
222 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
223 FN_SCIF_CLK_B, FN_GPS_MAG_D,
224 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
225 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
226 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
227 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
228 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
229 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
230 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
231 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
232 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
233 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
234 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
235 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
236 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
237 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
238 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
239 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
240
241 /* IPSR8 */
242 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
243 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
244 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
245 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
246 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
247 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
248 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
249 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
250 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
251 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
252 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
253 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
254 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
255 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
256 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
257 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
258 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
259
260 /* IPSR9 */
261 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
262 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
263 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
264 FN_DU1_DOTCLKOUT0, FN_QCLK,
265 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
266 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
267 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
268 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
269 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
270 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
271 FN_DU1_DISP, FN_QPOLA,
272 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
273 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
274 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
275 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
276 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
277 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
278 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
279 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
280
281 /* IPSR10 */
282 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
283 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
284 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
285 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
286 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
287 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
288 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
289 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
290 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
291 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
292 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
293 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
294 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
295 FN_TS_SDATA0_C, FN_ATACS11_N,
296 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
297 FN_TS_SCK0_C, FN_ATAG1_N,
298 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
299 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
300 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
301
302 /* IPSR11 */
303 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
304 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
305 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
306 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
307 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
308 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
309 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
310 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
311 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
312 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
313 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
314 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
315 FN_VI1_DATA7, FN_AVB_MDC,
316 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C,
317 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C,
318
319 /* IPSR12 */
320 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL,
321 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
322 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
323 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
324 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
325 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
326 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
327 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
328 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
329 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
330 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
331 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
332 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
333 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
334 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
335 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
336 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
337
338 /* IPSR13 */
339 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
340 FN_ADICLK_B, FN_MSIOF0_SS1_C,
341 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
342 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
343 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
344 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
345 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
346 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
347 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
348 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
349 FN_SCIFA5_TXD_B, FN_TX3_C,
350 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
351 FN_SCIFA5_RXD_B, FN_RX3_C,
352 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
353 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
354 FN_SD1_DATA3, FN_IERX_B,
355 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
356
357 /* IPSR14 */
358 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C,
359 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
360 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
361 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
362 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
363 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
364 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
365 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
366 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
367 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
368 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
369 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
370 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
371 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
372
373 /* IPSR15 */
374 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
375 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
376 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
377 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
378 FN_PWM5_B, FN_SCIFA3_TXD_C,
379 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
380 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
381 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
382 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
383 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
384 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
385 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
386 FN_TCLK2, FN_VI1_DATA3_C,
387 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
388 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
389
390 /* IPSR16 */
391 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
392 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
393 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
394 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
395 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
396
397 /* MOD_SEL */
398 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
399 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
400 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
401 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
402 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
403 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
404 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
405 FN_SEL_QSP_0, FN_SEL_QSP_1,
406 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
407 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
408 FN_SEL_HSCIF1_4,
409 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
410 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
411 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
412 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
413 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
414
415 /* MOD_SEL2 */
416 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
417 FN_SEL_SCIF0_4,
418 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
419 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
420 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
421 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
422 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
423 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
424 FN_SEL_ADG_0, FN_SEL_ADG_1,
425 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
426 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
427 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
428 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
429 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
430 FN_SEL_SIM_0, FN_SEL_SIM_1,
431 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
432
433 /* MOD_SEL3 */
434 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
435 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
436 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
437 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
438 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
439 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
440 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
441 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
442 FN_SEL_MMC_0, FN_SEL_MMC_1,
443 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
444 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
445 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
446 FN_SEL_I2C1_4,
447 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2,
448
449 /* MOD_SEL4 */
450 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
451 FN_SEL_SOF1_4,
452 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
453 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
454 FN_SEL_RAD_0, FN_SEL_RAD_1,
455 FN_SEL_RCN_0, FN_SEL_RCN_1,
456 FN_SEL_RSP_0, FN_SEL_RSP_1,
457 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
458 FN_SEL_SCIF2_4,
459 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
460 FN_SEL_SOF2_4,
461 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
462 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
463 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
464 PINMUX_FUNCTION_END,
465
466 PINMUX_MARK_BEGIN,
467
468 EX_CS0_N_MARK, RD_N_MARK,
469
470 AUDIO_CLKA_MARK,
471
472 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
473 VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
474 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
475
476 SD1_CLK_MARK,
477
478 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
479 DU0_DOTCLKIN_MARK,
480
481 /* IPSR0 */
482 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
483 D6_MARK, D7_MARK, D8_MARK,
484 D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
485 A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK,
486 PWM2_B_MARK,
487 A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
488 A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
489 A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
490
491 /* IPSR1 */
492 A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK,
493 A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
494 A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
495 A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
496 A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
497 A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
498 A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
499 A15_MARK, BPFCLK_C_MARK,
500 A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
501 A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
502 A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
503
504 /* IPSR2 */
505 A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
506 SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
507 A20_MARK, SPCLK_MARK,
508 A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
509 A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
510 A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
511 A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
512 A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
513 RX1_MARK, SCIFA1_RXD_MARK,
514 CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK,
515 CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK,
516 EX_CS1_N_MARK, MSIOF2_SCK_MARK,
517 EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
518 EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
519 ATAG0_N_MARK, EX_WAIT1_MARK,
520
521 /* IPSR3 */
522 EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
523 EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
524 SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
525 BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
526 SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
527 RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
528 SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
529 WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
530 WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
531 EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
532 DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
533 DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
534 SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
535 SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
536 SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
537 SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
538 SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
539 SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
540
541 /* IPSR4 */
542 SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
543 SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
544 MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
545 SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
546 MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
547 SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
548 SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
549 HSCK1_E_MARK,
550 SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
551 GLO_Q1_D_MARK, HCTS1_N_E_MARK,
552 SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
553 SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
554 SSI_SCK4_MARK, GLO_SS_D_MARK,
555 SSI_WS4_MARK, GLO_RFON_D_MARK,
556 SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
557 SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
558 MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
559
560 /* IPSR5 */
561 SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
562 MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
563 SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
564 MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
565 SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
566 MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
567 SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
568 SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
569 SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
570 SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
571 SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
572 SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
573 SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
574 SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
575 SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
576
577 /* IPSR6 */
578 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
579 SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
580 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
581 SCIFA2_RXD_MARK, FMIN_E_MARK,
582 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
583 IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
584 IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
585 IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
586 IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
587 IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
588 MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
589 IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
590 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
591 I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
592 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
593 GPS_CLK_C_MARK, GPS_CLK_D_MARK,
594 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
595 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
596
597 /* IPSR7 */
598 IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
599 SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
600 DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
601 SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
602 DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
603 SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
604 DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
605 DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
606 DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
607 DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
608 DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
609 DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
610 DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
611 SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
612 DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
613 SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
614 DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
615 SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
616
617 /* IPSR8 */
618 DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
619 DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
620 SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
621 DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
622 SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
623 DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
624 SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
625 DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
626 SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
627 DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
628 SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
629 DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
630 SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
631 DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
632 SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
633 DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
634 DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
635 DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
636
637 /* IPSR9 */
638 DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
639 DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
640 SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
641 DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
642 DU1_DOTCLKOUT0_MARK, QCLK_MARK,
643 DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
644 TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
645 DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
646 DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
647 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
648 CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
649 DU1_DISP_MARK, QPOLA_MARK,
650 DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
651 VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
652 VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
653 VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
654 VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
655 VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
656 VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
657 HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
658
659 /* IPSR10 */
660 VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
661 HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
662 VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
663 HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
664 VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
665 HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
666 VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
667 HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
668 VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
669 CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
670 VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
671 VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
672 VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
673 TS_SDATA0_C_MARK, ATACS11_N_MARK,
674 VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
675 TS_SCK0_C_MARK, ATAG1_N_MARK,
676 VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
677 VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
678 VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
679 I2C1_SCL_D_MARK,
680
681 /* IPSR11 */
682 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
683 I2C1_SDA_D_MARK,
684 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
685 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
686 I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
687 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
688 TX4_B_MARK, SCIFA4_TXD_B_MARK,
689 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
690 RX4_B_MARK, SCIFA4_RXD_B_MARK,
691 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
692 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
693 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
694 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
695 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
696 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
697 VI1_DATA7_MARK, AVB_MDC_MARK,
698 ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK,
699 ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK,
700
701 /* IPSR12 */
702 ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK,
703 ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK,
704 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
705 I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK,
706 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
707 I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK,
708 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
709 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
710 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
711 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
712 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
713 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
714 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
715 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
716 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
717 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
718 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
719 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
720
721 /* IPSR13 */
722 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
723 ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
724 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
725 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
726 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
727 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
728 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
729 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
730 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
731 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
732 SCIFA5_TXD_B_MARK, TX3_C_MARK,
733 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
734 SCIFA5_RXD_B_MARK, RX3_C_MARK,
735 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
736 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
737 SD1_DATA3_MARK, IERX_B_MARK,
738 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
739
740 /* IPSR14 */
741 SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK,
742 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
743 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
744 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
745 SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK,
746 SCIFA5_TXD_C_MARK,
747 SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
748 SCIFA5_RXD_C_MARK,
749 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
750 VI1_CLK_C_MARK, VI1_G0_B_MARK,
751 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
752 VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
753 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
754 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
755 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
756 VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
757 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
758 VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
759
760 /* IPSR15 */
761 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
762 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
763 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
764 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
765 PWM5_B_MARK, SCIFA3_TXD_C_MARK,
766 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
767 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
768 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
769 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
770 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
771 TCLK1_MARK, VI1_DATA1_C_MARK,
772 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
773 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
774 TCLK2_MARK, VI1_DATA3_C_MARK,
775 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
776 CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
777 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
778 CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
779
780 /* IPSR16 */
781 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
782 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
783 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
784 GLO_SS_C_MARK, VI1_DATA7_C_MARK,
785 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
786 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
787 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
788 PINMUX_MARK_END,
789 };
790
791 static const u16 pinmux_data[] = {
792 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
793
794 PINMUX_SINGLE(EX_CS0_N),
795 PINMUX_SINGLE(RD_N),
796 PINMUX_SINGLE(AUDIO_CLKA),
797 PINMUX_SINGLE(VI0_CLK),
798 PINMUX_SINGLE(VI0_DATA0_VI0_B0),
799 PINMUX_SINGLE(VI0_DATA1_VI0_B1),
800 PINMUX_SINGLE(VI0_DATA2_VI0_B2),
801 PINMUX_SINGLE(VI0_DATA4_VI0_B4),
802 PINMUX_SINGLE(VI0_DATA5_VI0_B5),
803 PINMUX_SINGLE(VI0_DATA6_VI0_B6),
804 PINMUX_SINGLE(VI0_DATA7_VI0_B7),
805 PINMUX_SINGLE(USB0_PWEN),
806 PINMUX_SINGLE(USB0_OVC),
807 PINMUX_SINGLE(USB1_PWEN),
808 PINMUX_SINGLE(USB1_OVC),
809 PINMUX_SINGLE(DU0_DOTCLKIN),
810 PINMUX_SINGLE(SD1_CLK),
811
812 /* IPSR0 */
813 PINMUX_IPSR_GPSR(IP0_0, D0),
814 PINMUX_IPSR_GPSR(IP0_1, D1),
815 PINMUX_IPSR_GPSR(IP0_2, D2),
816 PINMUX_IPSR_GPSR(IP0_3, D3),
817 PINMUX_IPSR_GPSR(IP0_4, D4),
818 PINMUX_IPSR_GPSR(IP0_5, D5),
819 PINMUX_IPSR_GPSR(IP0_6, D6),
820 PINMUX_IPSR_GPSR(IP0_7, D7),
821 PINMUX_IPSR_GPSR(IP0_8, D8),
822 PINMUX_IPSR_GPSR(IP0_9, D9),
823 PINMUX_IPSR_GPSR(IP0_10, D10),
824 PINMUX_IPSR_GPSR(IP0_11, D11),
825 PINMUX_IPSR_GPSR(IP0_12, D12),
826 PINMUX_IPSR_GPSR(IP0_13, D13),
827 PINMUX_IPSR_GPSR(IP0_14, D14),
828 PINMUX_IPSR_GPSR(IP0_15, D15),
829 PINMUX_IPSR_GPSR(IP0_18_16, A0),
830 PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
831 PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
832 PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
833 PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
834 PINMUX_IPSR_GPSR(IP0_20_19, A1),
835 PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
836 PINMUX_IPSR_GPSR(IP0_22_21, A2),
837 PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
838 PINMUX_IPSR_GPSR(IP0_24_23, A3),
839 PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
840 PINMUX_IPSR_GPSR(IP0_26_25, A4),
841 PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
842 PINMUX_IPSR_GPSR(IP0_28_27, A5),
843 PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
844 PINMUX_IPSR_GPSR(IP0_30_29, A6),
845 PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
846
847 /* IPSR1 */
848 PINMUX_IPSR_GPSR(IP1_1_0, A7),
849 PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
850 PINMUX_IPSR_GPSR(IP1_3_2, A8),
851 PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
852 PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0),
853 PINMUX_IPSR_GPSR(IP1_5_4, A9),
854 PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
855 PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0),
856 PINMUX_IPSR_GPSR(IP1_7_6, A10),
857 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
858 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
859 PINMUX_IPSR_GPSR(IP1_10_8, A11),
860 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
861 PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
862 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
863 PINMUX_IPSR_GPSR(IP1_13_11, A12),
864 PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
865 PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
866 PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
867 PINMUX_IPSR_GPSR(IP1_16_14, A13),
868 PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
869 PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
870 PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
871 PINMUX_IPSR_GPSR(IP1_19_17, A14),
872 PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
873 PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
874 PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
875 PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
876 PINMUX_IPSR_GPSR(IP1_22_20, A15),
877 PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
878 PINMUX_IPSR_GPSR(IP1_25_23, A16),
879 PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
880 PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
881 PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
882 PINMUX_IPSR_GPSR(IP1_28_26, A17),
883 PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
884 PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2),
885 PINMUX_IPSR_GPSR(IP1_31_29, A18),
886 PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
887 PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
888 PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
889
890 /* IPSR2 */
891 PINMUX_IPSR_GPSR(IP2_2_0, A19),
892 PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
893 PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
894 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
895 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
896 PINMUX_IPSR_GPSR(IP2_2_0, A20),
897 PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
898 PINMUX_IPSR_GPSR(IP2_6_5, A21),
899 PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
900 PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
901 PINMUX_IPSR_GPSR(IP2_9_7, A22),
902 PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
903 PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
904 PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
905 PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
906 PINMUX_IPSR_GPSR(IP2_12_10, A23),
907 PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
908 PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
909 PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
910 PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
911 PINMUX_IPSR_GPSR(IP2_15_13, A24),
912 PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
913 PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
914 PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
915 PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
916 PINMUX_IPSR_GPSR(IP2_18_16, A25),
917 PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
918 PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
919 PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
920 PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
921 PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
922 PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
923 PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
924 PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0),
925 PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
926 PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
927 PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0),
928 PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
929 PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
930 PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
931 PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
932 PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
933 PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
934 PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
935 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
936 PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
937 PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
938
939 /* IPSR3 */
940 PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
941 PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
942 PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
943 PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
944 PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
945 PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
946 PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
947 PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
948 PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
949 PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
950 PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
951 PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
952 PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
953 PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
954 PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
955 PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
956 PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
957 PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
958 PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
959 PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
960 PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
961 PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
962 PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
963 PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
964 PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
965 PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
966 PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
967 PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
968 PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
969 PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
970 PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
971 PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
972 PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
973 PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
974 PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
975 PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
976 PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
977 PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
978 PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
979 PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
980 PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
981 PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
982 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
983 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
984 PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
985 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
986 PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
987 PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
988 PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
989 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
990 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
991 PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
992 PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
993 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
994 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
995 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
996
997 /* IPSR4 */
998 PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
999 PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1),
1000 PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1),
1001 PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
1002 PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
1003 PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
1004 PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
1005 PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
1006 PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
1007 PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
1008 PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
1009 PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
1010 PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
1011 PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
1012 PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
1013 PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
1014 PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
1015 PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
1016 PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
1017 PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
1018 PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1019 PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1020 PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
1021 PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
1022 PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
1023 PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1024 PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1025 PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1026 PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
1027 PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
1028 PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1029 PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1030 PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
1031 PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
1032 PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
1033 PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
1034 PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
1035 PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1036 PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
1037 PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1038 PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
1039 PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1040 PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
1041 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1042 PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1043 PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1044 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1045 PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
1046
1047 /* IPSR5 */
1048 PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
1049 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1050 PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1051 PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1052 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1053 PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
1054 PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
1055 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1056 PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1057 PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1058 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1059 PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
1060 PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
1061 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1062 PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1063 PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1064 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1065 PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
1066 PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
1067 PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1068 PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1069 PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
1070 PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
1071 PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1072 PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1073 PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
1074 PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1075 PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1076 PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1077 PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1078 PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1079 PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1080 PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1081 PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1082 PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1083 PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1084 PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1085 PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1086 PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1087 PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1088 PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1089 PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1090 PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1091 PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1092 PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1093 PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1094 PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1095 PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1096 PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1097
1098 /* IPSR6 */
1099 PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1100 PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1101 PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1102 PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1103 PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
1104 PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1105 PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
1106 PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1107 PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1108 PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1109 PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1110 PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1111 PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
1112 PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1113 PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
1114 PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1115 PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
1116 PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1117 PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
1118 PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
1119 PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1120 PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
1121 PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
1122 PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1123 PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
1124 PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
1125 PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
1126 PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1127 PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
1128 PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
1129 PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1130 PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
1131 PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1132 PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
1133 PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
1134 PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1135 PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
1136 PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1137 PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
1138 PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1139 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1140 PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4),
1141 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1142 PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
1143 PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1144 PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1145 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1146 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1147 PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
1148 PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1149 PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1150 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1151 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1152
1153 /* IPSR7 */
1154 PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
1155 PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1156 PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1157 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1158 PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1159 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1160 PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
1161 PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
1162 PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1163 PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1164 PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1165 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1166 PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
1167 PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
1168 PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1169 PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1170 PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1171 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1172 PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
1173 PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
1174 PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1175 PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
1176 PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
1177 PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1178 PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
1179 PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
1180 PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1181 PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
1182 PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
1183 PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1184 PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
1185 PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
1186 PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1187 PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
1188 PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
1189 PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1190 PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
1191 PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
1192 PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1193 PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1194 PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1195 PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1196 PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
1197 PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
1198 PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1199 PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1200 PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1201 PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1202 PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
1203 PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
1204 PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1205 PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
1206 PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1207 PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1208
1209 /* IPSR8 */
1210 PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
1211 PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
1212 PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1213 PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1214 PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
1215 PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
1216 PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1217 PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1218 PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1219 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1220 PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
1221 PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
1222 PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1223 PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1224 PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1225 PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1226 PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
1227 PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
1228 PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1229 PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1230 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1231 PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
1232 PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
1233 PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1234 PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1235 PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1236 PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
1237 PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
1238 PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1239 PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1240 PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1241 PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1242 PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
1243 PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
1244 PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1245 PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1246 PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1247 PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1248 PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
1249 PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
1250 PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1251 PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
1252 PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1253 PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1254 PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
1255 PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
1256 PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1257 PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
1258 PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
1259 PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1260 PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1261 PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
1262 PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
1263 PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1264 PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1265 PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1266
1267 /* IPSR9 */
1268 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
1269 PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
1270 PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
1271 PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1272 PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1273 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
1274 PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
1275 PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
1276 PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1277 PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1278 PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1279 PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
1280 PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
1281 PINMUX_IPSR_GPSR(IP9_7, QCLK),
1282 PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
1283 PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
1284 PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1285 PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1286 PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
1287 PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
1288 PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1289 PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
1290 PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1291 PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
1292 PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1293 PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
1294 PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1295 PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1296 PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
1297 PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
1298 PINMUX_IPSR_GPSR(IP9_16, QPOLA),
1299 PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
1300 PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
1301 PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
1302 PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
1303 PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1304 PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1305 PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1306 PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
1307 PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1308 PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1309 PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1310 PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
1311 PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1312 PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1313 PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1314 PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
1315 PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1316 PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1317 PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1318 PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
1319 PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1320 PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1321 PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
1322 PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
1323 PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1324 PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
1325 PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1326 PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1327 PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
1328
1329 /* IPSR10 */
1330 PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
1331 PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
1332 PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1333 PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
1334 PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1335 PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1336 PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
1337 PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
1338 PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
1339 PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1340 PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
1341 PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1342 PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1343 PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
1344 PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
1345 PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
1346 PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1347 PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
1348 PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1349 PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1350 PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
1351 PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
1352 PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
1353 PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1354 PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1355 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1356 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1357 PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
1358 PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
1359 PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1360 PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1361 PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1362 PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1363 PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1364 PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
1365 PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
1366 PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1367 PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
1368 PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
1369 PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1370 PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
1371 PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
1372 PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1373 PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1374 PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
1375 PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
1376 PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
1377 PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1378 PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1379 PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
1380 PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
1381 PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
1382 PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1383 PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1384 PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
1385 PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
1386 PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1387 PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1388 PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
1389 PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
1390 PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1391 PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1392 PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
1393
1394 /* IPSR11 */
1395 PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
1396 PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
1397 PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1398 PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1399 PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
1400 PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
1401 PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
1402 PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1403 PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1404 PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
1405 PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
1406 PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1407 PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1408 PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1409 PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
1410 PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1411 PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1412 PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1413 PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
1414 PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1415 PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1416 PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1417 PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1418 PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
1419 PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1420 PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1421 PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1422 PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1423 PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
1424 PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1425 PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1426 PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
1427 PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1428 PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1429 PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
1430 PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1431 PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
1432 PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1433 PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
1434 PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1435 PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
1436 PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1437 PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
1438 PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1439 PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
1440 PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1441 PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
1442 PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1443 PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
1444 PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1445 PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
1446 PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
1447 PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
1448 PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2),
1449 PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
1450 PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
1451 PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2),
1452
1453 /* IPSR12 */
1454 PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
1455 PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
1456 PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0),
1457 PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0),
1458 PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
1459 PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
1460 PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0),
1461 PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0),
1462 PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
1463 PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
1464 PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1465 PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3),
1466 PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1467 PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
1468 PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
1469 PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1470 PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3),
1471 PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1472 PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
1473 PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
1474 PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1475 PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1476 PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1477 PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
1478 PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
1479 PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1480 PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1481 PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1482 PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
1483 PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
1484 PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1485 PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1486 PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
1487 PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
1488 PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1489 PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
1490 PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
1491 PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1492 PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
1493 PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
1494 PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1495 PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1496 PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
1497 PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1498 PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1499 PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1500 PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1501 PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
1502 PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1503 PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1504 PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1505
1506 /* IPSR13 */
1507 PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1508 PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
1509 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1510 PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1511 PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1512 PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1513 PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
1514 PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1515 PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1516 PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1517 PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
1518 PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1519 PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1520 PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1521 PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
1522 PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
1523 PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1524 PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1525 PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
1526 PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1527 PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
1528 PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1529 PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
1530 PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1531 PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
1532 PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1533 PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
1534 PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1535 PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
1536 PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1537 PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
1538 PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1539 PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1540 PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1541 PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1542 PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1543 PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
1544 PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1545 PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1546 PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1547 PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1548 PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1549 PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
1550 PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1551 PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
1552 PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1553 PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
1554 PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1555 PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
1556 PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1557 PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
1558 PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1559 PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
1560 PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
1561 PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
1562 PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2),
1563
1564 /* IPSR14 */
1565 PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
1566 PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
1567 PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2),
1568 PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
1569 PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
1570 PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
1571 PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
1572 PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
1573 PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
1574 PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
1575 PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
1576 PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
1577 PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
1578 PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
1579 PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
1580 PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
1581 PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
1582 PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2),
1583 PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1584 PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1585 PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
1586 PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
1587 PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2),
1588 PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1589 PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1590 PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1591 PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1592 PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1593 PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1594 PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
1595 PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1596 PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1597 PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1598 PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1599 PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
1600 PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1601 PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1602 PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1603 PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
1604 PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1605 PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1606 PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1607 PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
1608 PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1609 PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1610 PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1611 PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1612 PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1613 PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
1614 PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
1615 PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1616 PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1617 PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1618 PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1619 PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1620 PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
1621 PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
1622
1623 /* IPSR15 */
1624 PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1625 PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1626 PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1627 PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
1628 PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1629 PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1630 PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1631 PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1632 PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1633 PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1634 PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1635 PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1636 PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
1637 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1638 PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1639 PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1640 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1641 PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
1642 PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
1643 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1644 PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1645 PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1646 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1647 PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
1648 PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
1649 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1650 PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1651 PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1652 PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1653 PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1654 PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1655 PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1656 PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1657 PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1658 PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1659 PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1660 PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1661 PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1662 PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1663 PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
1664 PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1665 PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1666 PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1667 PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1668 PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1669 PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1670 PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1671 PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1672 PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1673 PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1674 PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1675
1676 /* IPSR16 */
1677 PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1678 PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1679 PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
1680 PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1681 PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1682 PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1683 PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1684 PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
1685 PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1686 PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1687 PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1688 PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1689 PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
1690 PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1691 PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1692 PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
1693 PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
1694 PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1695 PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1696 PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
1697 PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
1698 PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1699 };
1700
1701 static const struct sh_pfc_pin pinmux_pins[] = {
1702 PINMUX_GPIO_GP_ALL(),
1703 };
1704
1705 /* - ADI -------------------------------------------------------------------- */
1706 static const unsigned int adi_common_pins[] = {
1707 /* ADIDATA, ADICS/SAMP, ADICLK */
1708 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
1709 };
1710 static const unsigned int adi_common_mux[] = {
1711 /* ADIDATA, ADICS/SAMP, ADICLK */
1712 ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
1713 };
1714 static const unsigned int adi_chsel0_pins[] = {
1715 /* ADICHS 0 */
1716 RCAR_GP_PIN(6, 27),
1717 };
1718 static const unsigned int adi_chsel0_mux[] = {
1719 /* ADICHS 0 */
1720 ADICHS0_MARK,
1721 };
1722 static const unsigned int adi_chsel1_pins[] = {
1723 /* ADICHS 1 */
1724 RCAR_GP_PIN(6, 28),
1725 };
1726 static const unsigned int adi_chsel1_mux[] = {
1727 /* ADICHS 1 */
1728 ADICHS1_MARK,
1729 };
1730 static const unsigned int adi_chsel2_pins[] = {
1731 /* ADICHS 2 */
1732 RCAR_GP_PIN(6, 29),
1733 };
1734 static const unsigned int adi_chsel2_mux[] = {
1735 /* ADICHS 2 */
1736 ADICHS2_MARK,
1737 };
1738 static const unsigned int adi_common_b_pins[] = {
1739 /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1740 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1741 };
1742 static const unsigned int adi_common_b_mux[] = {
1743 /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1744 ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
1745 };
1746 static const unsigned int adi_chsel0_b_pins[] = {
1747 /* ADICHS B 0 */
1748 RCAR_GP_PIN(5, 28),
1749 };
1750 static const unsigned int adi_chsel0_b_mux[] = {
1751 /* ADICHS B 0 */
1752 ADICHS0_B_MARK,
1753 };
1754 static const unsigned int adi_chsel1_b_pins[] = {
1755 /* ADICHS B 1 */
1756 RCAR_GP_PIN(5, 29),
1757 };
1758 static const unsigned int adi_chsel1_b_mux[] = {
1759 /* ADICHS B 1 */
1760 ADICHS1_B_MARK,
1761 };
1762 static const unsigned int adi_chsel2_b_pins[] = {
1763 /* ADICHS B 2 */
1764 RCAR_GP_PIN(5, 30),
1765 };
1766 static const unsigned int adi_chsel2_b_mux[] = {
1767 /* ADICHS B 2 */
1768 ADICHS2_B_MARK,
1769 };
1770
1771 /* - Audio Clock ------------------------------------------------------------ */
1772 static const unsigned int audio_clk_a_pins[] = {
1773 /* CLK */
1774 RCAR_GP_PIN(2, 28),
1775 };
1776
1777 static const unsigned int audio_clk_a_mux[] = {
1778 AUDIO_CLKA_MARK,
1779 };
1780
1781 static const unsigned int audio_clk_b_pins[] = {
1782 /* CLK */
1783 RCAR_GP_PIN(2, 29),
1784 };
1785
1786 static const unsigned int audio_clk_b_mux[] = {
1787 AUDIO_CLKB_MARK,
1788 };
1789
1790 static const unsigned int audio_clk_b_b_pins[] = {
1791 /* CLK */
1792 RCAR_GP_PIN(7, 20),
1793 };
1794
1795 static const unsigned int audio_clk_b_b_mux[] = {
1796 AUDIO_CLKB_B_MARK,
1797 };
1798
1799 static const unsigned int audio_clk_c_pins[] = {
1800 /* CLK */
1801 RCAR_GP_PIN(2, 30),
1802 };
1803
1804 static const unsigned int audio_clk_c_mux[] = {
1805 AUDIO_CLKC_MARK,
1806 };
1807
1808 static const unsigned int audio_clkout_pins[] = {
1809 /* CLK */
1810 RCAR_GP_PIN(2, 31),
1811 };
1812
1813 static const unsigned int audio_clkout_mux[] = {
1814 AUDIO_CLKOUT_MARK,
1815 };
1816
1817 /* - AVB -------------------------------------------------------------------- */
1818 static const unsigned int avb_link_pins[] = {
1819 RCAR_GP_PIN(5, 14),
1820 };
1821 static const unsigned int avb_link_mux[] = {
1822 AVB_LINK_MARK,
1823 };
1824 static const unsigned int avb_magic_pins[] = {
1825 RCAR_GP_PIN(5, 11),
1826 };
1827 static const unsigned int avb_magic_mux[] = {
1828 AVB_MAGIC_MARK,
1829 };
1830 static const unsigned int avb_phy_int_pins[] = {
1831 RCAR_GP_PIN(5, 16),
1832 };
1833 static const unsigned int avb_phy_int_mux[] = {
1834 AVB_PHY_INT_MARK,
1835 };
1836 static const unsigned int avb_mdio_pins[] = {
1837 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
1838 };
1839 static const unsigned int avb_mdio_mux[] = {
1840 AVB_MDC_MARK, AVB_MDIO_MARK,
1841 };
1842 static const unsigned int avb_mii_pins[] = {
1843 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1844 RCAR_GP_PIN(5, 21),
1845
1846 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1847 RCAR_GP_PIN(5, 3),
1848
1849 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1850 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1851 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1852 };
1853 static const unsigned int avb_mii_mux[] = {
1854 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1855 AVB_TXD3_MARK,
1856
1857 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1858 AVB_RXD3_MARK,
1859
1860 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1861 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1862 AVB_TX_CLK_MARK, AVB_COL_MARK,
1863 };
1864 static const unsigned int avb_gmii_pins[] = {
1865 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1866 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1867 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1868
1869 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1870 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1871 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1872
1873 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1874 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
1875 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
1876 RCAR_GP_PIN(5, 29),
1877 };
1878 static const unsigned int avb_gmii_mux[] = {
1879 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1880 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1881 AVB_TXD6_MARK, AVB_TXD7_MARK,
1882
1883 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1884 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1885 AVB_RXD6_MARK, AVB_RXD7_MARK,
1886
1887 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1888 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1889 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1890 AVB_COL_MARK,
1891 };
1892
1893 /* - CAN -------------------------------------------------------------------- */
1894
1895 static const unsigned int can0_data_pins[] = {
1896 /* TX, RX */
1897 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1898 };
1899
1900 static const unsigned int can0_data_mux[] = {
1901 CAN0_TX_MARK, CAN0_RX_MARK,
1902 };
1903
1904 static const unsigned int can0_data_b_pins[] = {
1905 /* TX, RX */
1906 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1907 };
1908
1909 static const unsigned int can0_data_b_mux[] = {
1910 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1911 };
1912
1913 static const unsigned int can0_data_c_pins[] = {
1914 /* TX, RX */
1915 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1916 };
1917
1918 static const unsigned int can0_data_c_mux[] = {
1919 CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1920 };
1921
1922 static const unsigned int can0_data_d_pins[] = {
1923 /* TX, RX */
1924 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1925 };
1926
1927 static const unsigned int can0_data_d_mux[] = {
1928 CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1929 };
1930
1931 static const unsigned int can0_data_e_pins[] = {
1932 /* TX, RX */
1933 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1934 };
1935
1936 static const unsigned int can0_data_e_mux[] = {
1937 CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1938 };
1939
1940 static const unsigned int can0_data_f_pins[] = {
1941 /* TX, RX */
1942 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1943 };
1944
1945 static const unsigned int can0_data_f_mux[] = {
1946 CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1947 };
1948
1949 static const unsigned int can1_data_pins[] = {
1950 /* TX, RX */
1951 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1952 };
1953
1954 static const unsigned int can1_data_mux[] = {
1955 CAN1_TX_MARK, CAN1_RX_MARK,
1956 };
1957
1958 static const unsigned int can1_data_b_pins[] = {
1959 /* TX, RX */
1960 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1961 };
1962
1963 static const unsigned int can1_data_b_mux[] = {
1964 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1965 };
1966
1967 static const unsigned int can1_data_c_pins[] = {
1968 /* TX, RX */
1969 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1970 };
1971
1972 static const unsigned int can1_data_c_mux[] = {
1973 CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1974 };
1975
1976 static const unsigned int can1_data_d_pins[] = {
1977 /* TX, RX */
1978 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1979 };
1980
1981 static const unsigned int can1_data_d_mux[] = {
1982 CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1983 };
1984
1985 static const unsigned int can_clk_pins[] = {
1986 /* CLK */
1987 RCAR_GP_PIN(7, 2),
1988 };
1989
1990 static const unsigned int can_clk_mux[] = {
1991 CAN_CLK_MARK,
1992 };
1993
1994 static const unsigned int can_clk_b_pins[] = {
1995 /* CLK */
1996 RCAR_GP_PIN(5, 21),
1997 };
1998
1999 static const unsigned int can_clk_b_mux[] = {
2000 CAN_CLK_B_MARK,
2001 };
2002
2003 static const unsigned int can_clk_c_pins[] = {
2004 /* CLK */
2005 RCAR_GP_PIN(4, 30),
2006 };
2007
2008 static const unsigned int can_clk_c_mux[] = {
2009 CAN_CLK_C_MARK,
2010 };
2011
2012 static const unsigned int can_clk_d_pins[] = {
2013 /* CLK */
2014 RCAR_GP_PIN(7, 19),
2015 };
2016
2017 static const unsigned int can_clk_d_mux[] = {
2018 CAN_CLK_D_MARK,
2019 };
2020
2021 /* - DU --------------------------------------------------------------------- */
2022 static const unsigned int du_rgb666_pins[] = {
2023 /* R[7:2], G[7:2], B[7:2] */
2024 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2025 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2026 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2027 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2028 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2029 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2030 };
2031 static const unsigned int du_rgb666_mux[] = {
2032 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2033 DU1_DR3_MARK, DU1_DR2_MARK,
2034 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2035 DU1_DG3_MARK, DU1_DG2_MARK,
2036 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2037 DU1_DB3_MARK, DU1_DB2_MARK,
2038 };
2039 static const unsigned int du_rgb888_pins[] = {
2040 /* R[7:0], G[7:0], B[7:0] */
2041 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2042 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2043 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2044 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2045 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2046 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2047 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2048 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2049 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2050 };
2051 static const unsigned int du_rgb888_mux[] = {
2052 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2053 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
2054 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2055 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
2056 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2057 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
2058 };
2059 static const unsigned int du_clk_out_0_pins[] = {
2060 /* CLKOUT */
2061 RCAR_GP_PIN(3, 25),
2062 };
2063 static const unsigned int du_clk_out_0_mux[] = {
2064 DU1_DOTCLKOUT0_MARK
2065 };
2066 static const unsigned int du_clk_out_1_pins[] = {
2067 /* CLKOUT */
2068 RCAR_GP_PIN(3, 26),
2069 };
2070 static const unsigned int du_clk_out_1_mux[] = {
2071 DU1_DOTCLKOUT1_MARK
2072 };
2073 static const unsigned int du_sync_pins[] = {
2074 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2075 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
2076 };
2077 static const unsigned int du_sync_mux[] = {
2078 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
2079 };
2080 static const unsigned int du_oddf_pins[] = {
2081 /* EXDISP/EXODDF/EXCDE */
2082 RCAR_GP_PIN(3, 29),
2083 };
2084 static const unsigned int du_oddf_mux[] = {
2085 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
2086 };
2087 static const unsigned int du_cde_pins[] = {
2088 /* CDE */
2089 RCAR_GP_PIN(3, 31),
2090 };
2091 static const unsigned int du_cde_mux[] = {
2092 DU1_CDE_MARK,
2093 };
2094 static const unsigned int du_disp_pins[] = {
2095 /* DISP */
2096 RCAR_GP_PIN(3, 30),
2097 };
2098 static const unsigned int du_disp_mux[] = {
2099 DU1_DISP_MARK,
2100 };
2101 static const unsigned int du0_clk_in_pins[] = {
2102 /* CLKIN */
2103 RCAR_GP_PIN(6, 31),
2104 };
2105 static const unsigned int du0_clk_in_mux[] = {
2106 DU0_DOTCLKIN_MARK
2107 };
2108 static const unsigned int du1_clk_in_pins[] = {
2109 /* CLKIN */
2110 RCAR_GP_PIN(3, 24),
2111 };
2112 static const unsigned int du1_clk_in_mux[] = {
2113 DU1_DOTCLKIN_MARK
2114 };
2115 static const unsigned int du1_clk_in_b_pins[] = {
2116 /* CLKIN */
2117 RCAR_GP_PIN(7, 19),
2118 };
2119 static const unsigned int du1_clk_in_b_mux[] = {
2120 DU1_DOTCLKIN_B_MARK,
2121 };
2122 static const unsigned int du1_clk_in_c_pins[] = {
2123 /* CLKIN */
2124 RCAR_GP_PIN(7, 20),
2125 };
2126 static const unsigned int du1_clk_in_c_mux[] = {
2127 DU1_DOTCLKIN_C_MARK,
2128 };
2129 /* - ETH -------------------------------------------------------------------- */
2130 static const unsigned int eth_link_pins[] = {
2131 /* LINK */
2132 RCAR_GP_PIN(5, 18),
2133 };
2134 static const unsigned int eth_link_mux[] = {
2135 ETH_LINK_MARK,
2136 };
2137 static const unsigned int eth_magic_pins[] = {
2138 /* MAGIC */
2139 RCAR_GP_PIN(5, 22),
2140 };
2141 static const unsigned int eth_magic_mux[] = {
2142 ETH_MAGIC_MARK,
2143 };
2144 static const unsigned int eth_mdio_pins[] = {
2145 /* MDC, MDIO */
2146 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
2147 };
2148 static const unsigned int eth_mdio_mux[] = {
2149 ETH_MDC_MARK, ETH_MDIO_MARK,
2150 };
2151 static const unsigned int eth_rmii_pins[] = {
2152 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2153 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2154 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2155 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2156 };
2157 static const unsigned int eth_rmii_mux[] = {
2158 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2159 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
2160 };
2161
2162 /* - HSCIF0 ----------------------------------------------------------------- */
2163 static const unsigned int hscif0_data_pins[] = {
2164 /* RX, TX */
2165 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2166 };
2167 static const unsigned int hscif0_data_mux[] = {
2168 HRX0_MARK, HTX0_MARK,
2169 };
2170 static const unsigned int hscif0_clk_pins[] = {
2171 /* SCK */
2172 RCAR_GP_PIN(7, 2),
2173 };
2174 static const unsigned int hscif0_clk_mux[] = {
2175 HSCK0_MARK,
2176 };
2177 static const unsigned int hscif0_ctrl_pins[] = {
2178 /* RTS, CTS */
2179 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2180 };
2181 static const unsigned int hscif0_ctrl_mux[] = {
2182 HRTS0_N_MARK, HCTS0_N_MARK,
2183 };
2184 static const unsigned int hscif0_data_b_pins[] = {
2185 /* RX, TX */
2186 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2187 };
2188 static const unsigned int hscif0_data_b_mux[] = {
2189 HRX0_B_MARK, HTX0_B_MARK,
2190 };
2191 static const unsigned int hscif0_ctrl_b_pins[] = {
2192 /* RTS, CTS */
2193 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2194 };
2195 static const unsigned int hscif0_ctrl_b_mux[] = {
2196 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2197 };
2198 static const unsigned int hscif0_data_c_pins[] = {
2199 /* RX, TX */
2200 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2201 };
2202 static const unsigned int hscif0_data_c_mux[] = {
2203 HRX0_C_MARK, HTX0_C_MARK,
2204 };
2205 static const unsigned int hscif0_clk_c_pins[] = {
2206 /* SCK */
2207 RCAR_GP_PIN(5, 31),
2208 };
2209 static const unsigned int hscif0_clk_c_mux[] = {
2210 HSCK0_C_MARK,
2211 };
2212 /* - HSCIF1 ----------------------------------------------------------------- */
2213 static const unsigned int hscif1_data_pins[] = {
2214 /* RX, TX */
2215 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2216 };
2217 static const unsigned int hscif1_data_mux[] = {
2218 HRX1_MARK, HTX1_MARK,
2219 };
2220 static const unsigned int hscif1_clk_pins[] = {
2221 /* SCK */
2222 RCAR_GP_PIN(7, 7),
2223 };
2224 static const unsigned int hscif1_clk_mux[] = {
2225 HSCK1_MARK,
2226 };
2227 static const unsigned int hscif1_ctrl_pins[] = {
2228 /* RTS, CTS */
2229 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2230 };
2231 static const unsigned int hscif1_ctrl_mux[] = {
2232 HRTS1_N_MARK, HCTS1_N_MARK,
2233 };
2234 static const unsigned int hscif1_data_b_pins[] = {
2235 /* RX, TX */
2236 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2237 };
2238 static const unsigned int hscif1_data_b_mux[] = {
2239 HRX1_B_MARK, HTX1_B_MARK,
2240 };
2241 static const unsigned int hscif1_data_c_pins[] = {
2242 /* RX, TX */
2243 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2244 };
2245 static const unsigned int hscif1_data_c_mux[] = {
2246 HRX1_C_MARK, HTX1_C_MARK,
2247 };
2248 static const unsigned int hscif1_clk_c_pins[] = {
2249 /* SCK */
2250 RCAR_GP_PIN(7, 16),
2251 };
2252 static const unsigned int hscif1_clk_c_mux[] = {
2253 HSCK1_C_MARK,
2254 };
2255 static const unsigned int hscif1_ctrl_c_pins[] = {
2256 /* RTS, CTS */
2257 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2258 };
2259 static const unsigned int hscif1_ctrl_c_mux[] = {
2260 HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2261 };
2262 static const unsigned int hscif1_data_d_pins[] = {
2263 /* RX, TX */
2264 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2265 };
2266 static const unsigned int hscif1_data_d_mux[] = {
2267 HRX1_D_MARK, HTX1_D_MARK,
2268 };
2269 static const unsigned int hscif1_data_e_pins[] = {
2270 /* RX, TX */
2271 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2272 };
2273 static const unsigned int hscif1_data_e_mux[] = {
2274 HRX1_C_MARK, HTX1_C_MARK,
2275 };
2276 static const unsigned int hscif1_clk_e_pins[] = {
2277 /* SCK */
2278 RCAR_GP_PIN(2, 6),
2279 };
2280 static const unsigned int hscif1_clk_e_mux[] = {
2281 HSCK1_E_MARK,
2282 };
2283 static const unsigned int hscif1_ctrl_e_pins[] = {
2284 /* RTS, CTS */
2285 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2286 };
2287 static const unsigned int hscif1_ctrl_e_mux[] = {
2288 HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2289 };
2290 /* - HSCIF2 ----------------------------------------------------------------- */
2291 static const unsigned int hscif2_data_pins[] = {
2292 /* RX, TX */
2293 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2294 };
2295 static const unsigned int hscif2_data_mux[] = {
2296 HRX2_MARK, HTX2_MARK,
2297 };
2298 static const unsigned int hscif2_clk_pins[] = {
2299 /* SCK */
2300 RCAR_GP_PIN(4, 15),
2301 };
2302 static const unsigned int hscif2_clk_mux[] = {
2303 HSCK2_MARK,
2304 };
2305 static const unsigned int hscif2_ctrl_pins[] = {
2306 /* RTS, CTS */
2307 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2308 };
2309 static const unsigned int hscif2_ctrl_mux[] = {
2310 HRTS2_N_MARK, HCTS2_N_MARK,
2311 };
2312 static const unsigned int hscif2_data_b_pins[] = {
2313 /* RX, TX */
2314 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2315 };
2316 static const unsigned int hscif2_data_b_mux[] = {
2317 HRX2_B_MARK, HTX2_B_MARK,
2318 };
2319 static const unsigned int hscif2_ctrl_b_pins[] = {
2320 /* RTS, CTS */
2321 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2322 };
2323 static const unsigned int hscif2_ctrl_b_mux[] = {
2324 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2325 };
2326 static const unsigned int hscif2_data_c_pins[] = {
2327 /* RX, TX */
2328 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2329 };
2330 static const unsigned int hscif2_data_c_mux[] = {
2331 HRX2_C_MARK, HTX2_C_MARK,
2332 };
2333 static const unsigned int hscif2_clk_c_pins[] = {
2334 /* SCK */
2335 RCAR_GP_PIN(5, 31),
2336 };
2337 static const unsigned int hscif2_clk_c_mux[] = {
2338 HSCK2_C_MARK,
2339 };
2340 static const unsigned int hscif2_data_d_pins[] = {
2341 /* RX, TX */
2342 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2343 };
2344 static const unsigned int hscif2_data_d_mux[] = {
2345 HRX2_B_MARK, HTX2_D_MARK,
2346 };
2347 /* - I2C0 ------------------------------------------------------------------- */
2348 static const unsigned int i2c0_pins[] = {
2349 /* SCL, SDA */
2350 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2351 };
2352 static const unsigned int i2c0_mux[] = {
2353 I2C0_SCL_MARK, I2C0_SDA_MARK,
2354 };
2355 static const unsigned int i2c0_b_pins[] = {
2356 /* SCL, SDA */
2357 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2358 };
2359 static const unsigned int i2c0_b_mux[] = {
2360 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2361 };
2362 static const unsigned int i2c0_c_pins[] = {
2363 /* SCL, SDA */
2364 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2365 };
2366 static const unsigned int i2c0_c_mux[] = {
2367 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2368 };
2369 /* - I2C1 ------------------------------------------------------------------- */
2370 static const unsigned int i2c1_pins[] = {
2371 /* SCL, SDA */
2372 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2373 };
2374 static const unsigned int i2c1_mux[] = {
2375 I2C1_SCL_MARK, I2C1_SDA_MARK,
2376 };
2377 static const unsigned int i2c1_b_pins[] = {
2378 /* SCL, SDA */
2379 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2380 };
2381 static const unsigned int i2c1_b_mux[] = {
2382 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2383 };
2384 static const unsigned int i2c1_c_pins[] = {
2385 /* SCL, SDA */
2386 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2387 };
2388 static const unsigned int i2c1_c_mux[] = {
2389 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2390 };
2391 static const unsigned int i2c1_d_pins[] = {
2392 /* SCL, SDA */
2393 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2394 };
2395 static const unsigned int i2c1_d_mux[] = {
2396 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2397 };
2398 static const unsigned int i2c1_e_pins[] = {
2399 /* SCL, SDA */
2400 RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2401 };
2402 static const unsigned int i2c1_e_mux[] = {
2403 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2404 };
2405 /* - I2C2 ------------------------------------------------------------------- */
2406 static const unsigned int i2c2_pins[] = {
2407 /* SCL, SDA */
2408 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2409 };
2410 static const unsigned int i2c2_mux[] = {
2411 I2C2_SCL_MARK, I2C2_SDA_MARK,
2412 };
2413 static const unsigned int i2c2_b_pins[] = {
2414 /* SCL, SDA */
2415 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2416 };
2417 static const unsigned int i2c2_b_mux[] = {
2418 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2419 };
2420 static const unsigned int i2c2_c_pins[] = {
2421 /* SCL, SDA */
2422 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2423 };
2424 static const unsigned int i2c2_c_mux[] = {
2425 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2426 };
2427 static const unsigned int i2c2_d_pins[] = {
2428 /* SCL, SDA */
2429 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2430 };
2431 static const unsigned int i2c2_d_mux[] = {
2432 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2433 };
2434 /* - I2C3 ------------------------------------------------------------------- */
2435 static const unsigned int i2c3_pins[] = {
2436 /* SCL, SDA */
2437 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2438 };
2439 static const unsigned int i2c3_mux[] = {
2440 I2C3_SCL_MARK, I2C3_SDA_MARK,
2441 };
2442 static const unsigned int i2c3_b_pins[] = {
2443 /* SCL, SDA */
2444 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2445 };
2446 static const unsigned int i2c3_b_mux[] = {
2447 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2448 };
2449 static const unsigned int i2c3_c_pins[] = {
2450 /* SCL, SDA */
2451 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2452 };
2453 static const unsigned int i2c3_c_mux[] = {
2454 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2455 };
2456 static const unsigned int i2c3_d_pins[] = {
2457 /* SCL, SDA */
2458 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2459 };
2460 static const unsigned int i2c3_d_mux[] = {
2461 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2462 };
2463 /* - I2C4 ------------------------------------------------------------------- */
2464 static const unsigned int i2c4_pins[] = {
2465 /* SCL, SDA */
2466 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2467 };
2468 static const unsigned int i2c4_mux[] = {
2469 I2C4_SCL_MARK, I2C4_SDA_MARK,
2470 };
2471 static const unsigned int i2c4_b_pins[] = {
2472 /* SCL, SDA */
2473 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2474 };
2475 static const unsigned int i2c4_b_mux[] = {
2476 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2477 };
2478 static const unsigned int i2c4_c_pins[] = {
2479 /* SCL, SDA */
2480 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2481 };
2482 static const unsigned int i2c4_c_mux[] = {
2483 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2484 };
2485 /* - I2C7 ------------------------------------------------------------------- */
2486 static const unsigned int i2c7_pins[] = {
2487 /* SCL, SDA */
2488 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2489 };
2490 static const unsigned int i2c7_mux[] = {
2491 IIC0_SCL_MARK, IIC0_SDA_MARK,
2492 };
2493 static const unsigned int i2c7_b_pins[] = {
2494 /* SCL, SDA */
2495 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2496 };
2497 static const unsigned int i2c7_b_mux[] = {
2498 IIC0_SCL_B_MARK, IIC0_SDA_B_MARK,
2499 };
2500 static const unsigned int i2c7_c_pins[] = {
2501 /* SCL, SDA */
2502 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2503 };
2504 static const unsigned int i2c7_c_mux[] = {
2505 IIC0_SCL_C_MARK, IIC0_SDA_C_MARK,
2506 };
2507 /* - I2C8 ------------------------------------------------------------------- */
2508 static const unsigned int i2c8_pins[] = {
2509 /* SCL, SDA */
2510 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2511 };
2512 static const unsigned int i2c8_mux[] = {
2513 IIC1_SCL_MARK, IIC1_SDA_MARK,
2514 };
2515 static const unsigned int i2c8_b_pins[] = {
2516 /* SCL, SDA */
2517 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2518 };
2519 static const unsigned int i2c8_b_mux[] = {
2520 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2521 };
2522 static const unsigned int i2c8_c_pins[] = {
2523 /* SCL, SDA */
2524 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2525 };
2526 static const unsigned int i2c8_c_mux[] = {
2527 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2528 };
2529 /* - INTC ------------------------------------------------------------------- */
2530 static const unsigned int intc_irq0_pins[] = {
2531 /* IRQ */
2532 RCAR_GP_PIN(7, 10),
2533 };
2534 static const unsigned int intc_irq0_mux[] = {
2535 IRQ0_MARK,
2536 };
2537 static const unsigned int intc_irq1_pins[] = {
2538 /* IRQ */
2539 RCAR_GP_PIN(7, 11),
2540 };
2541 static const unsigned int intc_irq1_mux[] = {
2542 IRQ1_MARK,
2543 };
2544 static const unsigned int intc_irq2_pins[] = {
2545 /* IRQ */
2546 RCAR_GP_PIN(7, 12),
2547 };
2548 static const unsigned int intc_irq2_mux[] = {
2549 IRQ2_MARK,
2550 };
2551 static const unsigned int intc_irq3_pins[] = {
2552 /* IRQ */
2553 RCAR_GP_PIN(7, 13),
2554 };
2555 static const unsigned int intc_irq3_mux[] = {
2556 IRQ3_MARK,
2557 };
2558 /* - MLB+ ------------------------------------------------------------------- */
2559 static const unsigned int mlb_3pin_pins[] = {
2560 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2561 };
2562 static const unsigned int mlb_3pin_mux[] = {
2563 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2564 };
2565 /* - MMCIF ------------------------------------------------------------------ */
2566 static const unsigned int mmc_data1_pins[] = {
2567 /* D[0] */
2568 RCAR_GP_PIN(6, 18),
2569 };
2570 static const unsigned int mmc_data1_mux[] = {
2571 MMC_D0_MARK,
2572 };
2573 static const unsigned int mmc_data4_pins[] = {
2574 /* D[0:3] */
2575 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2576 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2577 };
2578 static const unsigned int mmc_data4_mux[] = {
2579 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2580 };
2581 static const unsigned int mmc_data8_pins[] = {
2582 /* D[0:7] */
2583 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2584 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2585 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2586 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2587 };
2588 static const unsigned int mmc_data8_mux[] = {
2589 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2590 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2591 };
2592 static const unsigned int mmc_data8_b_pins[] = {
2593 /* D[0:7] */
2594 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2595 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2596 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2597 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
2598 };
2599 static const unsigned int mmc_data8_b_mux[] = {
2600 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2601 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
2602 };
2603 static const unsigned int mmc_ctrl_pins[] = {
2604 /* CLK, CMD */
2605 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2606 };
2607 static const unsigned int mmc_ctrl_mux[] = {
2608 MMC_CLK_MARK, MMC_CMD_MARK,
2609 };
2610 /* - MSIOF0 ----------------------------------------------------------------- */
2611 static const unsigned int msiof0_clk_pins[] = {
2612 /* SCK */
2613 RCAR_GP_PIN(6, 24),
2614 };
2615 static const unsigned int msiof0_clk_mux[] = {
2616 MSIOF0_SCK_MARK,
2617 };
2618 static const unsigned int msiof0_sync_pins[] = {
2619 /* SYNC */
2620 RCAR_GP_PIN(6, 25),
2621 };
2622 static const unsigned int msiof0_sync_mux[] = {
2623 MSIOF0_SYNC_MARK,
2624 };
2625 static const unsigned int msiof0_ss1_pins[] = {
2626 /* SS1 */
2627 RCAR_GP_PIN(6, 28),
2628 };
2629 static const unsigned int msiof0_ss1_mux[] = {
2630 MSIOF0_SS1_MARK,
2631 };
2632 static const unsigned int msiof0_ss2_pins[] = {
2633 /* SS2 */
2634 RCAR_GP_PIN(6, 29),
2635 };
2636 static const unsigned int msiof0_ss2_mux[] = {
2637 MSIOF0_SS2_MARK,
2638 };
2639 static const unsigned int msiof0_rx_pins[] = {
2640 /* RXD */
2641 RCAR_GP_PIN(6, 27),
2642 };
2643 static const unsigned int msiof0_rx_mux[] = {
2644 MSIOF0_RXD_MARK,
2645 };
2646 static const unsigned int msiof0_tx_pins[] = {
2647 /* TXD */
2648 RCAR_GP_PIN(6, 26),
2649 };
2650 static const unsigned int msiof0_tx_mux[] = {
2651 MSIOF0_TXD_MARK,
2652 };
2653
2654 static const unsigned int msiof0_clk_b_pins[] = {
2655 /* SCK */
2656 RCAR_GP_PIN(0, 16),
2657 };
2658 static const unsigned int msiof0_clk_b_mux[] = {
2659 MSIOF0_SCK_B_MARK,
2660 };
2661 static const unsigned int msiof0_sync_b_pins[] = {
2662 /* SYNC */
2663 RCAR_GP_PIN(0, 17),
2664 };
2665 static const unsigned int msiof0_sync_b_mux[] = {
2666 MSIOF0_SYNC_B_MARK,
2667 };
2668 static const unsigned int msiof0_ss1_b_pins[] = {
2669 /* SS1 */
2670 RCAR_GP_PIN(0, 18),
2671 };
2672 static const unsigned int msiof0_ss1_b_mux[] = {
2673 MSIOF0_SS1_B_MARK,
2674 };
2675 static const unsigned int msiof0_ss2_b_pins[] = {
2676 /* SS2 */
2677 RCAR_GP_PIN(0, 19),
2678 };
2679 static const unsigned int msiof0_ss2_b_mux[] = {
2680 MSIOF0_SS2_B_MARK,
2681 };
2682 static const unsigned int msiof0_rx_b_pins[] = {
2683 /* RXD */
2684 RCAR_GP_PIN(0, 21),
2685 };
2686 static const unsigned int msiof0_rx_b_mux[] = {
2687 MSIOF0_RXD_B_MARK,
2688 };
2689 static const unsigned int msiof0_tx_b_pins[] = {
2690 /* TXD */
2691 RCAR_GP_PIN(0, 20),
2692 };
2693 static const unsigned int msiof0_tx_b_mux[] = {
2694 MSIOF0_TXD_B_MARK,
2695 };
2696
2697 static const unsigned int msiof0_clk_c_pins[] = {
2698 /* SCK */
2699 RCAR_GP_PIN(5, 26),
2700 };
2701 static const unsigned int msiof0_clk_c_mux[] = {
2702 MSIOF0_SCK_C_MARK,
2703 };
2704 static const unsigned int msiof0_sync_c_pins[] = {
2705 /* SYNC */
2706 RCAR_GP_PIN(5, 25),
2707 };
2708 static const unsigned int msiof0_sync_c_mux[] = {
2709 MSIOF0_SYNC_C_MARK,
2710 };
2711 static const unsigned int msiof0_ss1_c_pins[] = {
2712 /* SS1 */
2713 RCAR_GP_PIN(5, 27),
2714 };
2715 static const unsigned int msiof0_ss1_c_mux[] = {
2716 MSIOF0_SS1_C_MARK,
2717 };
2718 static const unsigned int msiof0_ss2_c_pins[] = {
2719 /* SS2 */
2720 RCAR_GP_PIN(5, 28),
2721 };
2722 static const unsigned int msiof0_ss2_c_mux[] = {
2723 MSIOF0_SS2_C_MARK,
2724 };
2725 static const unsigned int msiof0_rx_c_pins[] = {
2726 /* RXD */
2727 RCAR_GP_PIN(5, 29),
2728 };
2729 static const unsigned int msiof0_rx_c_mux[] = {
2730 MSIOF0_RXD_C_MARK,
2731 };
2732 static const unsigned int msiof0_tx_c_pins[] = {
2733 /* TXD */
2734 RCAR_GP_PIN(5, 30),
2735 };
2736 static const unsigned int msiof0_tx_c_mux[] = {
2737 MSIOF0_TXD_C_MARK,
2738 };
2739 /* - MSIOF1 ----------------------------------------------------------------- */
2740 static const unsigned int msiof1_clk_pins[] = {
2741 /* SCK */
2742 RCAR_GP_PIN(0, 22),
2743 };
2744 static const unsigned int msiof1_clk_mux[] = {
2745 MSIOF1_SCK_MARK,
2746 };
2747 static const unsigned int msiof1_sync_pins[] = {
2748 /* SYNC */
2749 RCAR_GP_PIN(0, 23),
2750 };
2751 static const unsigned int msiof1_sync_mux[] = {
2752 MSIOF1_SYNC_MARK,
2753 };
2754 static const unsigned int msiof1_ss1_pins[] = {
2755 /* SS1 */
2756 RCAR_GP_PIN(0, 24),
2757 };
2758 static const unsigned int msiof1_ss1_mux[] = {
2759 MSIOF1_SS1_MARK,
2760 };
2761 static const unsigned int msiof1_ss2_pins[] = {
2762 /* SS2 */
2763 RCAR_GP_PIN(0, 25),
2764 };
2765 static const unsigned int msiof1_ss2_mux[] = {
2766 MSIOF1_SS2_MARK,
2767 };
2768 static const unsigned int msiof1_rx_pins[] = {
2769 /* RXD */
2770 RCAR_GP_PIN(0, 27),
2771 };
2772 static const unsigned int msiof1_rx_mux[] = {
2773 MSIOF1_RXD_MARK,
2774 };
2775 static const unsigned int msiof1_tx_pins[] = {
2776 /* TXD */
2777 RCAR_GP_PIN(0, 26),
2778 };
2779 static const unsigned int msiof1_tx_mux[] = {
2780 MSIOF1_TXD_MARK,
2781 };
2782
2783 static const unsigned int msiof1_clk_b_pins[] = {
2784 /* SCK */
2785 RCAR_GP_PIN(2, 29),
2786 };
2787 static const unsigned int msiof1_clk_b_mux[] = {
2788 MSIOF1_SCK_B_MARK,
2789 };
2790 static const unsigned int msiof1_sync_b_pins[] = {
2791 /* SYNC */
2792 RCAR_GP_PIN(2, 30),
2793 };
2794 static const unsigned int msiof1_sync_b_mux[] = {
2795 MSIOF1_SYNC_B_MARK,
2796 };
2797 static const unsigned int msiof1_ss1_b_pins[] = {
2798 /* SS1 */
2799 RCAR_GP_PIN(2, 31),
2800 };
2801 static const unsigned int msiof1_ss1_b_mux[] = {
2802 MSIOF1_SS1_B_MARK,
2803 };
2804 static const unsigned int msiof1_ss2_b_pins[] = {
2805 /* SS2 */
2806 RCAR_GP_PIN(7, 16),
2807 };
2808 static const unsigned int msiof1_ss2_b_mux[] = {
2809 MSIOF1_SS2_B_MARK,
2810 };
2811 static const unsigned int msiof1_rx_b_pins[] = {
2812 /* RXD */
2813 RCAR_GP_PIN(7, 18),
2814 };
2815 static const unsigned int msiof1_rx_b_mux[] = {
2816 MSIOF1_RXD_B_MARK,
2817 };
2818 static const unsigned int msiof1_tx_b_pins[] = {
2819 /* TXD */
2820 RCAR_GP_PIN(7, 17),
2821 };
2822 static const unsigned int msiof1_tx_b_mux[] = {
2823 MSIOF1_TXD_B_MARK,
2824 };
2825
2826 static const unsigned int msiof1_clk_c_pins[] = {
2827 /* SCK */
2828 RCAR_GP_PIN(2, 15),
2829 };
2830 static const unsigned int msiof1_clk_c_mux[] = {
2831 MSIOF1_SCK_C_MARK,
2832 };
2833 static const unsigned int msiof1_sync_c_pins[] = {
2834 /* SYNC */
2835 RCAR_GP_PIN(2, 16),
2836 };
2837 static const unsigned int msiof1_sync_c_mux[] = {
2838 MSIOF1_SYNC_C_MARK,
2839 };
2840 static const unsigned int msiof1_rx_c_pins[] = {
2841 /* RXD */
2842 RCAR_GP_PIN(2, 18),
2843 };
2844 static const unsigned int msiof1_rx_c_mux[] = {
2845 MSIOF1_RXD_C_MARK,
2846 };
2847 static const unsigned int msiof1_tx_c_pins[] = {
2848 /* TXD */
2849 RCAR_GP_PIN(2, 17),
2850 };
2851 static const unsigned int msiof1_tx_c_mux[] = {
2852 MSIOF1_TXD_C_MARK,
2853 };
2854
2855 static const unsigned int msiof1_clk_d_pins[] = {
2856 /* SCK */
2857 RCAR_GP_PIN(0, 28),
2858 };
2859 static const unsigned int msiof1_clk_d_mux[] = {
2860 MSIOF1_SCK_D_MARK,
2861 };
2862 static const unsigned int msiof1_sync_d_pins[] = {
2863 /* SYNC */
2864 RCAR_GP_PIN(0, 30),
2865 };
2866 static const unsigned int msiof1_sync_d_mux[] = {
2867 MSIOF1_SYNC_D_MARK,
2868 };
2869 static const unsigned int msiof1_ss1_d_pins[] = {
2870 /* SS1 */
2871 RCAR_GP_PIN(0, 29),
2872 };
2873 static const unsigned int msiof1_ss1_d_mux[] = {
2874 MSIOF1_SS1_D_MARK,
2875 };
2876 static const unsigned int msiof1_rx_d_pins[] = {
2877 /* RXD */
2878 RCAR_GP_PIN(0, 27),
2879 };
2880 static const unsigned int msiof1_rx_d_mux[] = {
2881 MSIOF1_RXD_D_MARK,
2882 };
2883 static const unsigned int msiof1_tx_d_pins[] = {
2884 /* TXD */
2885 RCAR_GP_PIN(0, 26),
2886 };
2887 static const unsigned int msiof1_tx_d_mux[] = {
2888 MSIOF1_TXD_D_MARK,
2889 };
2890
2891 static const unsigned int msiof1_clk_e_pins[] = {
2892 /* SCK */
2893 RCAR_GP_PIN(5, 18),
2894 };
2895 static const unsigned int msiof1_clk_e_mux[] = {
2896 MSIOF1_SCK_E_MARK,
2897 };
2898 static const unsigned int msiof1_sync_e_pins[] = {
2899 /* SYNC */
2900 RCAR_GP_PIN(5, 19),
2901 };
2902 static const unsigned int msiof1_sync_e_mux[] = {
2903 MSIOF1_SYNC_E_MARK,
2904 };
2905 static const unsigned int msiof1_rx_e_pins[] = {
2906 /* RXD */
2907 RCAR_GP_PIN(5, 17),
2908 };
2909 static const unsigned int msiof1_rx_e_mux[] = {
2910 MSIOF1_RXD_E_MARK,
2911 };
2912 static const unsigned int msiof1_tx_e_pins[] = {
2913 /* TXD */
2914 RCAR_GP_PIN(5, 20),
2915 };
2916 static const unsigned int msiof1_tx_e_mux[] = {
2917 MSIOF1_TXD_E_MARK,
2918 };
2919 /* - MSIOF2 ----------------------------------------------------------------- */
2920 static const unsigned int msiof2_clk_pins[] = {
2921 /* SCK */
2922 RCAR_GP_PIN(1, 13),
2923 };
2924 static const unsigned int msiof2_clk_mux[] = {
2925 MSIOF2_SCK_MARK,
2926 };
2927 static const unsigned int msiof2_sync_pins[] = {
2928 /* SYNC */
2929 RCAR_GP_PIN(1, 14),
2930 };
2931 static const unsigned int msiof2_sync_mux[] = {
2932 MSIOF2_SYNC_MARK,
2933 };
2934 static const unsigned int msiof2_ss1_pins[] = {
2935 /* SS1 */
2936 RCAR_GP_PIN(1, 17),
2937 };
2938 static const unsigned int msiof2_ss1_mux[] = {
2939 MSIOF2_SS1_MARK,
2940 };
2941 static const unsigned int msiof2_ss2_pins[] = {
2942 /* SS2 */
2943 RCAR_GP_PIN(1, 18),
2944 };
2945 static const unsigned int msiof2_ss2_mux[] = {
2946 MSIOF2_SS2_MARK,
2947 };
2948 static const unsigned int msiof2_rx_pins[] = {
2949 /* RXD */
2950 RCAR_GP_PIN(1, 16),
2951 };
2952 static const unsigned int msiof2_rx_mux[] = {
2953 MSIOF2_RXD_MARK,
2954 };
2955 static const unsigned int msiof2_tx_pins[] = {
2956 /* TXD */
2957 RCAR_GP_PIN(1, 15),
2958 };
2959 static const unsigned int msiof2_tx_mux[] = {
2960 MSIOF2_TXD_MARK,
2961 };
2962
2963 static const unsigned int msiof2_clk_b_pins[] = {
2964 /* SCK */
2965 RCAR_GP_PIN(3, 0),
2966 };
2967 static const unsigned int msiof2_clk_b_mux[] = {
2968 MSIOF2_SCK_B_MARK,
2969 };
2970 static const unsigned int msiof2_sync_b_pins[] = {
2971 /* SYNC */
2972 RCAR_GP_PIN(3, 1),
2973 };
2974 static const unsigned int msiof2_sync_b_mux[] = {
2975 MSIOF2_SYNC_B_MARK,
2976 };
2977 static const unsigned int msiof2_ss1_b_pins[] = {
2978 /* SS1 */
2979 RCAR_GP_PIN(3, 8),
2980 };
2981 static const unsigned int msiof2_ss1_b_mux[] = {
2982 MSIOF2_SS1_B_MARK,
2983 };
2984 static const unsigned int msiof2_ss2_b_pins[] = {
2985 /* SS2 */
2986 RCAR_GP_PIN(3, 9),
2987 };
2988 static const unsigned int msiof2_ss2_b_mux[] = {
2989 MSIOF2_SS2_B_MARK,
2990 };
2991 static const unsigned int msiof2_rx_b_pins[] = {
2992 /* RXD */
2993 RCAR_GP_PIN(3, 17),
2994 };
2995 static const unsigned int msiof2_rx_b_mux[] = {
2996 MSIOF2_RXD_B_MARK,
2997 };
2998 static const unsigned int msiof2_tx_b_pins[] = {
2999 /* TXD */
3000 RCAR_GP_PIN(3, 16),
3001 };
3002 static const unsigned int msiof2_tx_b_mux[] = {
3003 MSIOF2_TXD_B_MARK,
3004 };
3005
3006 static const unsigned int msiof2_clk_c_pins[] = {
3007 /* SCK */
3008 RCAR_GP_PIN(2, 2),
3009 };
3010 static const unsigned int msiof2_clk_c_mux[] = {
3011 MSIOF2_SCK_C_MARK,
3012 };
3013 static const unsigned int msiof2_sync_c_pins[] = {
3014 /* SYNC */
3015 RCAR_GP_PIN(2, 3),
3016 };
3017 static const unsigned int msiof2_sync_c_mux[] = {
3018 MSIOF2_SYNC_C_MARK,
3019 };
3020 static const unsigned int msiof2_rx_c_pins[] = {
3021 /* RXD */
3022 RCAR_GP_PIN(2, 5),
3023 };
3024 static const unsigned int msiof2_rx_c_mux[] = {
3025 MSIOF2_RXD_C_MARK,
3026 };
3027 static const unsigned int msiof2_tx_c_pins[] = {
3028 /* TXD */
3029 RCAR_GP_PIN(2, 4),
3030 };
3031 static const unsigned int msiof2_tx_c_mux[] = {
3032 MSIOF2_TXD_C_MARK,
3033 };
3034
3035 static const unsigned int msiof2_clk_d_pins[] = {
3036 /* SCK */
3037 RCAR_GP_PIN(2, 14),
3038 };
3039 static const unsigned int msiof2_clk_d_mux[] = {
3040 MSIOF2_SCK_D_MARK,
3041 };
3042 static const unsigned int msiof2_sync_d_pins[] = {
3043 /* SYNC */
3044 RCAR_GP_PIN(2, 15),
3045 };
3046 static const unsigned int msiof2_sync_d_mux[] = {
3047 MSIOF2_SYNC_D_MARK,
3048 };
3049 static const unsigned int msiof2_ss1_d_pins[] = {
3050 /* SS1 */
3051 RCAR_GP_PIN(2, 17),
3052 };
3053 static const unsigned int msiof2_ss1_d_mux[] = {
3054 MSIOF2_SS1_D_MARK,
3055 };
3056 static const unsigned int msiof2_ss2_d_pins[] = {
3057 /* SS2 */
3058 RCAR_GP_PIN(2, 19),
3059 };
3060 static const unsigned int msiof2_ss2_d_mux[] = {
3061 MSIOF2_SS2_D_MARK,
3062 };
3063 static const unsigned int msiof2_rx_d_pins[] = {
3064 /* RXD */
3065 RCAR_GP_PIN(2, 18),
3066 };
3067 static const unsigned int msiof2_rx_d_mux[] = {
3068 MSIOF2_RXD_D_MARK,
3069 };
3070 static const unsigned int msiof2_tx_d_pins[] = {
3071 /* TXD */
3072 RCAR_GP_PIN(2, 16),
3073 };
3074 static const unsigned int msiof2_tx_d_mux[] = {
3075 MSIOF2_TXD_D_MARK,
3076 };
3077
3078 static const unsigned int msiof2_clk_e_pins[] = {
3079 /* SCK */
3080 RCAR_GP_PIN(7, 15),
3081 };
3082 static const unsigned int msiof2_clk_e_mux[] = {
3083 MSIOF2_SCK_E_MARK,
3084 };
3085 static const unsigned int msiof2_sync_e_pins[] = {
3086 /* SYNC */
3087 RCAR_GP_PIN(7, 16),
3088 };
3089 static const unsigned int msiof2_sync_e_mux[] = {
3090 MSIOF2_SYNC_E_MARK,
3091 };
3092 static const unsigned int msiof2_rx_e_pins[] = {
3093 /* RXD */
3094 RCAR_GP_PIN(7, 14),
3095 };
3096 static const unsigned int msiof2_rx_e_mux[] = {
3097 MSIOF2_RXD_E_MARK,
3098 };
3099 static const unsigned int msiof2_tx_e_pins[] = {
3100 /* TXD */
3101 RCAR_GP_PIN(7, 13),
3102 };
3103 static const unsigned int msiof2_tx_e_mux[] = {
3104 MSIOF2_TXD_E_MARK,
3105 };
3106 /* - PWM -------------------------------------------------------------------- */
3107 static const unsigned int pwm0_pins[] = {
3108 RCAR_GP_PIN(6, 14),
3109 };
3110 static const unsigned int pwm0_mux[] = {
3111 PWM0_MARK,
3112 };
3113 static const unsigned int pwm0_b_pins[] = {
3114 RCAR_GP_PIN(5, 30),
3115 };
3116 static const unsigned int pwm0_b_mux[] = {
3117 PWM0_B_MARK,
3118 };
3119 static const unsigned int pwm1_pins[] = {
3120 RCAR_GP_PIN(1, 17),
3121 };
3122 static const unsigned int pwm1_mux[] = {
3123 PWM1_MARK,
3124 };
3125 static const unsigned int pwm1_b_pins[] = {
3126 RCAR_GP_PIN(6, 15),
3127 };
3128 static const unsigned int pwm1_b_mux[] = {
3129 PWM1_B_MARK,
3130 };
3131 static const unsigned int pwm2_pins[] = {
3132 RCAR_GP_PIN(1, 18),
3133 };
3134 static const unsigned int pwm2_mux[] = {
3135 PWM2_MARK,
3136 };
3137 static const unsigned int pwm2_b_pins[] = {
3138 RCAR_GP_PIN(0, 16),
3139 };
3140 static const unsigned int pwm2_b_mux[] = {
3141 PWM2_B_MARK,
3142 };
3143 static const unsigned int pwm3_pins[] = {
3144 RCAR_GP_PIN(1, 24),
3145 };
3146 static const unsigned int pwm3_mux[] = {
3147 PWM3_MARK,
3148 };
3149 static const unsigned int pwm4_pins[] = {
3150 RCAR_GP_PIN(3, 26),
3151 };
3152 static const unsigned int pwm4_mux[] = {
3153 PWM4_MARK,
3154 };
3155 static const unsigned int pwm4_b_pins[] = {
3156 RCAR_GP_PIN(3, 31),
3157 };
3158 static const unsigned int pwm4_b_mux[] = {
3159 PWM4_B_MARK,
3160 };
3161 static const unsigned int pwm5_pins[] = {
3162 RCAR_GP_PIN(7, 21),
3163 };
3164 static const unsigned int pwm5_mux[] = {
3165 PWM5_MARK,
3166 };
3167 static const unsigned int pwm5_b_pins[] = {
3168 RCAR_GP_PIN(7, 20),
3169 };
3170 static const unsigned int pwm5_b_mux[] = {
3171 PWM5_B_MARK,
3172 };
3173 static const unsigned int pwm6_pins[] = {
3174 RCAR_GP_PIN(7, 22),
3175 };
3176 static const unsigned int pwm6_mux[] = {
3177 PWM6_MARK,
3178 };
3179 /* - QSPI ------------------------------------------------------------------- */
3180 static const unsigned int qspi_ctrl_pins[] = {
3181 /* SPCLK, SSL */
3182 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3183 };
3184 static const unsigned int qspi_ctrl_mux[] = {
3185 SPCLK_MARK, SSL_MARK,
3186 };
3187 static const unsigned int qspi_data2_pins[] = {
3188 /* MOSI_IO0, MISO_IO1 */
3189 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3190 };
3191 static const unsigned int qspi_data2_mux[] = {
3192 MOSI_IO0_MARK, MISO_IO1_MARK,
3193 };
3194 static const unsigned int qspi_data4_pins[] = {
3195 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3196 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3197 RCAR_GP_PIN(1, 8),
3198 };
3199 static const unsigned int qspi_data4_mux[] = {
3200 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
3201 };
3202
3203 static const unsigned int qspi_ctrl_b_pins[] = {
3204 /* SPCLK, SSL */
3205 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3206 };
3207 static const unsigned int qspi_ctrl_b_mux[] = {
3208 SPCLK_B_MARK, SSL_B_MARK,
3209 };
3210 static const unsigned int qspi_data2_b_pins[] = {
3211 /* MOSI_IO0, MISO_IO1 */
3212 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3213 };
3214 static const unsigned int qspi_data2_b_mux[] = {
3215 MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3216 };
3217 static const unsigned int qspi_data4_b_pins[] = {
3218 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3219 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3220 RCAR_GP_PIN(6, 4),
3221 };
3222 static const unsigned int qspi_data4_b_mux[] = {
3223 SPCLK_B_MARK, MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3224 IO2_B_MARK, IO3_B_MARK, SSL_B_MARK,
3225 };
3226 /* - SCIF0 ------------------------------------------------------------------ */
3227 static const unsigned int scif0_data_pins[] = {
3228 /* RX, TX */
3229 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3230 };
3231 static const unsigned int scif0_data_mux[] = {
3232 RX0_MARK, TX0_MARK,
3233 };
3234 static const unsigned int scif0_data_b_pins[] = {
3235 /* RX, TX */
3236 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3237 };
3238 static const unsigned int scif0_data_b_mux[] = {
3239 RX0_B_MARK, TX0_B_MARK,
3240 };
3241 static const unsigned int scif0_data_c_pins[] = {
3242 /* RX, TX */
3243 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3244 };
3245 static const unsigned int scif0_data_c_mux[] = {
3246 RX0_C_MARK, TX0_C_MARK,
3247 };
3248 static const unsigned int scif0_data_d_pins[] = {
3249 /* RX, TX */
3250 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3251 };
3252 static const unsigned int scif0_data_d_mux[] = {
3253 RX0_D_MARK, TX0_D_MARK,
3254 };
3255 static const unsigned int scif0_data_e_pins[] = {
3256 /* RX, TX */
3257 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3258 };
3259 static const unsigned int scif0_data_e_mux[] = {
3260 RX0_E_MARK, TX0_E_MARK,
3261 };
3262 /* - SCIF1 ------------------------------------------------------------------ */
3263 static const unsigned int scif1_data_pins[] = {
3264 /* RX, TX */
3265 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3266 };
3267 static const unsigned int scif1_data_mux[] = {
3268 RX1_MARK, TX1_MARK,
3269 };
3270 static const unsigned int scif1_data_b_pins[] = {
3271 /* RX, TX */
3272 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3273 };
3274 static const unsigned int scif1_data_b_mux[] = {
3275 RX1_B_MARK, TX1_B_MARK,
3276 };
3277 static const unsigned int scif1_clk_b_pins[] = {
3278 /* SCK */
3279 RCAR_GP_PIN(3, 10),
3280 };
3281 static const unsigned int scif1_clk_b_mux[] = {
3282 SCIF1_SCK_B_MARK,
3283 };
3284 static const unsigned int scif1_data_c_pins[] = {
3285 /* RX, TX */
3286 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3287 };
3288 static const unsigned int scif1_data_c_mux[] = {
3289 RX1_C_MARK, TX1_C_MARK,
3290 };
3291 static const unsigned int scif1_data_d_pins[] = {
3292 /* RX, TX */
3293 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3294 };
3295 static const unsigned int scif1_data_d_mux[] = {
3296 RX1_D_MARK, TX1_D_MARK,
3297 };
3298 /* - SCIF2 ------------------------------------------------------------------ */
3299 static const unsigned int scif2_data_pins[] = {
3300 /* RX, TX */
3301 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3302 };
3303 static const unsigned int scif2_data_mux[] = {
3304 RX2_MARK, TX2_MARK,
3305 };
3306 static const unsigned int scif2_data_b_pins[] = {
3307 /* RX, TX */
3308 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3309 };
3310 static const unsigned int scif2_data_b_mux[] = {
3311 RX2_B_MARK, TX2_B_MARK,
3312 };
3313 static const unsigned int scif2_clk_b_pins[] = {
3314 /* SCK */
3315 RCAR_GP_PIN(3, 18),
3316 };
3317 static const unsigned int scif2_clk_b_mux[] = {
3318 SCIF2_SCK_B_MARK,
3319 };
3320 static const unsigned int scif2_data_c_pins[] = {
3321 /* RX, TX */
3322 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3323 };
3324 static const unsigned int scif2_data_c_mux[] = {
3325 RX2_C_MARK, TX2_C_MARK,
3326 };
3327 static const unsigned int scif2_data_e_pins[] = {
3328 /* RX, TX */
3329 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3330 };
3331 static const unsigned int scif2_data_e_mux[] = {
3332 RX2_E_MARK, TX2_E_MARK,
3333 };
3334 /* - SCIF3 ------------------------------------------------------------------ */
3335 static const unsigned int scif3_data_pins[] = {
3336 /* RX, TX */
3337 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3338 };
3339 static const unsigned int scif3_data_mux[] = {
3340 RX3_MARK, TX3_MARK,
3341 };
3342 static const unsigned int scif3_clk_pins[] = {
3343 /* SCK */
3344 RCAR_GP_PIN(3, 23),
3345 };
3346 static const unsigned int scif3_clk_mux[] = {
3347 SCIF3_SCK_MARK,
3348 };
3349 static const unsigned int scif3_data_b_pins[] = {
3350 /* RX, TX */
3351 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3352 };
3353 static const unsigned int scif3_data_b_mux[] = {
3354 RX3_B_MARK, TX3_B_MARK,
3355 };
3356 static const unsigned int scif3_clk_b_pins[] = {
3357 /* SCK */
3358 RCAR_GP_PIN(4, 8),
3359 };
3360 static const unsigned int scif3_clk_b_mux[] = {
3361 SCIF3_SCK_B_MARK,
3362 };
3363 static const unsigned int scif3_data_c_pins[] = {
3364 /* RX, TX */
3365 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3366 };
3367 static const unsigned int scif3_data_c_mux[] = {
3368 RX3_C_MARK, TX3_C_MARK,
3369 };
3370 static const unsigned int scif3_data_d_pins[] = {
3371 /* RX, TX */
3372 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3373 };
3374 static const unsigned int scif3_data_d_mux[] = {
3375 RX3_D_MARK, TX3_D_MARK,
3376 };
3377 /* - SCIF4 ------------------------------------------------------------------ */
3378 static const unsigned int scif4_data_pins[] = {
3379 /* RX, TX */
3380 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3381 };
3382 static const unsigned int scif4_data_mux[] = {
3383 RX4_MARK, TX4_MARK,
3384 };
3385 static const unsigned int scif4_data_b_pins[] = {
3386 /* RX, TX */
3387 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3388 };
3389 static const unsigned int scif4_data_b_mux[] = {
3390 RX4_B_MARK, TX4_B_MARK,
3391 };
3392 static const unsigned int scif4_data_c_pins[] = {
3393 /* RX, TX */
3394 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3395 };
3396 static const unsigned int scif4_data_c_mux[] = {
3397 RX4_C_MARK, TX4_C_MARK,
3398 };
3399 /* - SCIF5 ------------------------------------------------------------------ */
3400 static const unsigned int scif5_data_pins[] = {
3401 /* RX, TX */
3402 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3403 };
3404 static const unsigned int scif5_data_mux[] = {
3405 RX5_MARK, TX5_MARK,
3406 };
3407 static const unsigned int scif5_data_b_pins[] = {
3408 /* RX, TX */
3409 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3410 };
3411 static const unsigned int scif5_data_b_mux[] = {
3412 RX5_B_MARK, TX5_B_MARK,
3413 };
3414 /* - SCIFA0 ----------------------------------------------------------------- */
3415 static const unsigned int scifa0_data_pins[] = {
3416 /* RXD, TXD */
3417 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3418 };
3419 static const unsigned int scifa0_data_mux[] = {
3420 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
3421 };
3422 static const unsigned int scifa0_data_b_pins[] = {
3423 /* RXD, TXD */
3424 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3425 };
3426 static const unsigned int scifa0_data_b_mux[] = {
3427 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
3428 };
3429 /* - SCIFA1 ----------------------------------------------------------------- */
3430 static const unsigned int scifa1_data_pins[] = {
3431 /* RXD, TXD */
3432 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3433 };
3434 static const unsigned int scifa1_data_mux[] = {
3435 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
3436 };
3437 static const unsigned int scifa1_clk_pins[] = {
3438 /* SCK */
3439 RCAR_GP_PIN(3, 10),
3440 };
3441 static const unsigned int scifa1_clk_mux[] = {
3442 SCIFA1_SCK_MARK,
3443 };
3444 static const unsigned int scifa1_data_b_pins[] = {
3445 /* RXD, TXD */
3446 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3447 };
3448 static const unsigned int scifa1_data_b_mux[] = {
3449 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3450 };
3451 static const unsigned int scifa1_clk_b_pins[] = {
3452 /* SCK */
3453 RCAR_GP_PIN(1, 0),
3454 };
3455 static const unsigned int scifa1_clk_b_mux[] = {
3456 SCIFA1_SCK_B_MARK,
3457 };
3458 static const unsigned int scifa1_data_c_pins[] = {
3459 /* RXD, TXD */
3460 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3461 };
3462 static const unsigned int scifa1_data_c_mux[] = {
3463 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3464 };
3465 /* - SCIFA2 ----------------------------------------------------------------- */
3466 static const unsigned int scifa2_data_pins[] = {
3467 /* RXD, TXD */
3468 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3469 };
3470 static const unsigned int scifa2_data_mux[] = {
3471 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3472 };
3473 static const unsigned int scifa2_clk_pins[] = {
3474 /* SCK */
3475 RCAR_GP_PIN(3, 18),
3476 };
3477 static const unsigned int scifa2_clk_mux[] = {
3478 SCIFA2_SCK_MARK,
3479 };
3480 static const unsigned int scifa2_data_b_pins[] = {
3481 /* RXD, TXD */
3482 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3483 };
3484 static const unsigned int scifa2_data_b_mux[] = {
3485 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3486 };
3487 /* - SCIFA3 ----------------------------------------------------------------- */
3488 static const unsigned int scifa3_data_pins[] = {
3489 /* RXD, TXD */
3490 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3491 };
3492 static const unsigned int scifa3_data_mux[] = {
3493 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3494 };
3495 static const unsigned int scifa3_clk_pins[] = {
3496 /* SCK */
3497 RCAR_GP_PIN(3, 23),
3498 };
3499 static const unsigned int scifa3_clk_mux[] = {
3500 SCIFA3_SCK_MARK,
3501 };
3502 static const unsigned int scifa3_data_b_pins[] = {
3503 /* RXD, TXD */
3504 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3505 };
3506 static const unsigned int scifa3_data_b_mux[] = {
3507 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3508 };
3509 static const unsigned int scifa3_clk_b_pins[] = {
3510 /* SCK */
3511 RCAR_GP_PIN(4, 8),
3512 };
3513 static const unsigned int scifa3_clk_b_mux[] = {
3514 SCIFA3_SCK_B_MARK,
3515 };
3516 static const unsigned int scifa3_data_c_pins[] = {
3517 /* RXD, TXD */
3518 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3519 };
3520 static const unsigned int scifa3_data_c_mux[] = {
3521 SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
3522 };
3523 static const unsigned int scifa3_clk_c_pins[] = {
3524 /* SCK */
3525 RCAR_GP_PIN(7, 22),
3526 };
3527 static const unsigned int scifa3_clk_c_mux[] = {
3528 SCIFA3_SCK_C_MARK,
3529 };
3530 /* - SCIFA4 ----------------------------------------------------------------- */
3531 static const unsigned int scifa4_data_pins[] = {
3532 /* RXD, TXD */
3533 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3534 };
3535 static const unsigned int scifa4_data_mux[] = {
3536 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3537 };
3538 static const unsigned int scifa4_data_b_pins[] = {
3539 /* RXD, TXD */
3540 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3541 };
3542 static const unsigned int scifa4_data_b_mux[] = {
3543 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3544 };
3545 static const unsigned int scifa4_data_c_pins[] = {
3546 /* RXD, TXD */
3547 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3548 };
3549 static const unsigned int scifa4_data_c_mux[] = {
3550 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3551 };
3552 /* - SCIFA5 ----------------------------------------------------------------- */
3553 static const unsigned int scifa5_data_pins[] = {
3554 /* RXD, TXD */
3555 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3556 };
3557 static const unsigned int scifa5_data_mux[] = {
3558 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3559 };
3560 static const unsigned int scifa5_data_b_pins[] = {
3561 /* RXD, TXD */
3562 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3563 };
3564 static const unsigned int scifa5_data_b_mux[] = {
3565 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3566 };
3567 static const unsigned int scifa5_data_c_pins[] = {
3568 /* RXD, TXD */
3569 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3570 };
3571 static const unsigned int scifa5_data_c_mux[] = {
3572 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3573 };
3574 /* - SCIFB0 ----------------------------------------------------------------- */
3575 static const unsigned int scifb0_data_pins[] = {
3576 /* RXD, TXD */
3577 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3578 };
3579 static const unsigned int scifb0_data_mux[] = {
3580 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3581 };
3582 static const unsigned int scifb0_clk_pins[] = {
3583 /* SCK */
3584 RCAR_GP_PIN(7, 2),
3585 };
3586 static const unsigned int scifb0_clk_mux[] = {
3587 SCIFB0_SCK_MARK,
3588 };
3589 static const unsigned int scifb0_ctrl_pins[] = {
3590 /* RTS, CTS */
3591 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3592 };
3593 static const unsigned int scifb0_ctrl_mux[] = {
3594 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3595 };
3596 static const unsigned int scifb0_data_b_pins[] = {
3597 /* RXD, TXD */
3598 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3599 };
3600 static const unsigned int scifb0_data_b_mux[] = {
3601 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3602 };
3603 static const unsigned int scifb0_clk_b_pins[] = {
3604 /* SCK */
3605 RCAR_GP_PIN(5, 31),
3606 };
3607 static const unsigned int scifb0_clk_b_mux[] = {
3608 SCIFB0_SCK_B_MARK,
3609 };
3610 static const unsigned int scifb0_ctrl_b_pins[] = {
3611 /* RTS, CTS */
3612 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3613 };
3614 static const unsigned int scifb0_ctrl_b_mux[] = {
3615 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3616 };
3617 static const unsigned int scifb0_data_c_pins[] = {
3618 /* RXD, TXD */
3619 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3620 };
3621 static const unsigned int scifb0_data_c_mux[] = {
3622 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3623 };
3624 static const unsigned int scifb0_clk_c_pins[] = {
3625 /* SCK */
3626 RCAR_GP_PIN(2, 30),
3627 };
3628 static const unsigned int scifb0_clk_c_mux[] = {
3629 SCIFB0_SCK_C_MARK,
3630 };
3631 static const unsigned int scifb0_data_d_pins[] = {
3632 /* RXD, TXD */
3633 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3634 };
3635 static const unsigned int scifb0_data_d_mux[] = {
3636 SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3637 };
3638 static const unsigned int scifb0_clk_d_pins[] = {
3639 /* SCK */
3640 RCAR_GP_PIN(4, 17),
3641 };
3642 static const unsigned int scifb0_clk_d_mux[] = {
3643 SCIFB0_SCK_D_MARK,
3644 };
3645 /* - SCIFB1 ----------------------------------------------------------------- */
3646 static const unsigned int scifb1_data_pins[] = {
3647 /* RXD, TXD */
3648 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3649 };
3650 static const unsigned int scifb1_data_mux[] = {
3651 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3652 };
3653 static const unsigned int scifb1_clk_pins[] = {
3654 /* SCK */
3655 RCAR_GP_PIN(7, 7),
3656 };
3657 static const unsigned int scifb1_clk_mux[] = {
3658 SCIFB1_SCK_MARK,
3659 };
3660 static const unsigned int scifb1_ctrl_pins[] = {
3661 /* RTS, CTS */
3662 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3663 };
3664 static const unsigned int scifb1_ctrl_mux[] = {
3665 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3666 };
3667 static const unsigned int scifb1_data_b_pins[] = {
3668 /* RXD, TXD */
3669 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3670 };
3671 static const unsigned int scifb1_data_b_mux[] = {
3672 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3673 };
3674 static const unsigned int scifb1_clk_b_pins[] = {
3675 /* SCK */
3676 RCAR_GP_PIN(1, 3),
3677 };
3678 static const unsigned int scifb1_clk_b_mux[] = {
3679 SCIFB1_SCK_B_MARK,
3680 };
3681 static const unsigned int scifb1_data_c_pins[] = {
3682 /* RXD, TXD */
3683 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3684 };
3685 static const unsigned int scifb1_data_c_mux[] = {
3686 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3687 };
3688 static const unsigned int scifb1_clk_c_pins[] = {
3689 /* SCK */
3690 RCAR_GP_PIN(7, 11),
3691 };
3692 static const unsigned int scifb1_clk_c_mux[] = {
3693 SCIFB1_SCK_C_MARK,
3694 };
3695 static const unsigned int scifb1_data_d_pins[] = {
3696 /* RXD, TXD */
3697 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3698 };
3699 static const unsigned int scifb1_data_d_mux[] = {
3700 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3701 };
3702 /* - SCIFB2 ----------------------------------------------------------------- */
3703 static const unsigned int scifb2_data_pins[] = {
3704 /* RXD, TXD */
3705 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3706 };
3707 static const unsigned int scifb2_data_mux[] = {
3708 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3709 };
3710 static const unsigned int scifb2_clk_pins[] = {
3711 /* SCK */
3712 RCAR_GP_PIN(4, 15),
3713 };
3714 static const unsigned int scifb2_clk_mux[] = {
3715 SCIFB2_SCK_MARK,
3716 };
3717 static const unsigned int scifb2_ctrl_pins[] = {
3718 /* RTS, CTS */
3719 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3720 };
3721 static const unsigned int scifb2_ctrl_mux[] = {
3722 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3723 };
3724 static const unsigned int scifb2_data_b_pins[] = {
3725 /* RXD, TXD */
3726 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3727 };
3728 static const unsigned int scifb2_data_b_mux[] = {
3729 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3730 };
3731 static const unsigned int scifb2_clk_b_pins[] = {
3732 /* SCK */
3733 RCAR_GP_PIN(5, 31),
3734 };
3735 static const unsigned int scifb2_clk_b_mux[] = {
3736 SCIFB2_SCK_B_MARK,
3737 };
3738 static const unsigned int scifb2_ctrl_b_pins[] = {
3739 /* RTS, CTS */
3740 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3741 };
3742 static const unsigned int scifb2_ctrl_b_mux[] = {
3743 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3744 };
3745 static const unsigned int scifb2_data_c_pins[] = {
3746 /* RXD, TXD */
3747 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3748 };
3749 static const unsigned int scifb2_data_c_mux[] = {
3750 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3751 };
3752 static const unsigned int scifb2_clk_c_pins[] = {
3753 /* SCK */
3754 RCAR_GP_PIN(5, 27),
3755 };
3756 static const unsigned int scifb2_clk_c_mux[] = {
3757 SCIFB2_SCK_C_MARK,
3758 };
3759 static const unsigned int scifb2_data_d_pins[] = {
3760 /* RXD, TXD */
3761 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3762 };
3763 static const unsigned int scifb2_data_d_mux[] = {
3764 SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3765 };
3766
3767 /* - SCIF Clock ------------------------------------------------------------- */
3768 static const unsigned int scif_clk_pins[] = {
3769 /* SCIF_CLK */
3770 RCAR_GP_PIN(2, 29),
3771 };
3772 static const unsigned int scif_clk_mux[] = {
3773 SCIF_CLK_MARK,
3774 };
3775 static const unsigned int scif_clk_b_pins[] = {
3776 /* SCIF_CLK */
3777 RCAR_GP_PIN(7, 19),
3778 };
3779 static const unsigned int scif_clk_b_mux[] = {
3780 SCIF_CLK_B_MARK,
3781 };
3782
3783 /* - SDHI0 ------------------------------------------------------------------ */
3784 static const unsigned int sdhi0_data1_pins[] = {
3785 /* D0 */
3786 RCAR_GP_PIN(6, 2),
3787 };
3788 static const unsigned int sdhi0_data1_mux[] = {
3789 SD0_DATA0_MARK,
3790 };
3791 static const unsigned int sdhi0_data4_pins[] = {
3792 /* D[0:3] */
3793 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3794 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3795 };
3796 static const unsigned int sdhi0_data4_mux[] = {
3797 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3798 };
3799 static const unsigned int sdhi0_ctrl_pins[] = {
3800 /* CLK, CMD */
3801 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3802 };
3803 static const unsigned int sdhi0_ctrl_mux[] = {
3804 SD0_CLK_MARK, SD0_CMD_MARK,
3805 };
3806 static const unsigned int sdhi0_cd_pins[] = {
3807 /* CD */
3808 RCAR_GP_PIN(6, 6),
3809 };
3810 static const unsigned int sdhi0_cd_mux[] = {
3811 SD0_CD_MARK,
3812 };
3813 static const unsigned int sdhi0_wp_pins[] = {
3814 /* WP */
3815 RCAR_GP_PIN(6, 7),
3816 };
3817 static const unsigned int sdhi0_wp_mux[] = {
3818 SD0_WP_MARK,
3819 };
3820 /* - SDHI1 ------------------------------------------------------------------ */
3821 static const unsigned int sdhi1_data1_pins[] = {
3822 /* D0 */
3823 RCAR_GP_PIN(6, 10),
3824 };
3825 static const unsigned int sdhi1_data1_mux[] = {
3826 SD1_DATA0_MARK,
3827 };
3828 static const unsigned int sdhi1_data4_pins[] = {
3829 /* D[0:3] */
3830 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3831 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3832 };
3833 static const unsigned int sdhi1_data4_mux[] = {
3834 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3835 };
3836 static const unsigned int sdhi1_ctrl_pins[] = {
3837 /* CLK, CMD */
3838 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3839 };
3840 static const unsigned int sdhi1_ctrl_mux[] = {
3841 SD1_CLK_MARK, SD1_CMD_MARK,
3842 };
3843 static const unsigned int sdhi1_cd_pins[] = {
3844 /* CD */
3845 RCAR_GP_PIN(6, 14),
3846 };
3847 static const unsigned int sdhi1_cd_mux[] = {
3848 SD1_CD_MARK,
3849 };
3850 static const unsigned int sdhi1_wp_pins[] = {
3851 /* WP */
3852 RCAR_GP_PIN(6, 15),
3853 };
3854 static const unsigned int sdhi1_wp_mux[] = {
3855 SD1_WP_MARK,
3856 };
3857 /* - SDHI2 ------------------------------------------------------------------ */
3858 static const unsigned int sdhi2_data1_pins[] = {
3859 /* D0 */
3860 RCAR_GP_PIN(6, 18),
3861 };
3862 static const unsigned int sdhi2_data1_mux[] = {
3863 SD2_DATA0_MARK,
3864 };
3865 static const unsigned int sdhi2_data4_pins[] = {
3866 /* D[0:3] */
3867 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3868 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3869 };
3870 static const unsigned int sdhi2_data4_mux[] = {
3871 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3872 };
3873 static const unsigned int sdhi2_ctrl_pins[] = {
3874 /* CLK, CMD */
3875 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3876 };
3877 static const unsigned int sdhi2_ctrl_mux[] = {
3878 SD2_CLK_MARK, SD2_CMD_MARK,
3879 };
3880 static const unsigned int sdhi2_cd_pins[] = {
3881 /* CD */
3882 RCAR_GP_PIN(6, 22),
3883 };
3884 static const unsigned int sdhi2_cd_mux[] = {
3885 SD2_CD_MARK,
3886 };
3887 static const unsigned int sdhi2_wp_pins[] = {
3888 /* WP */
3889 RCAR_GP_PIN(6, 23),
3890 };
3891 static const unsigned int sdhi2_wp_mux[] = {
3892 SD2_WP_MARK,
3893 };
3894
3895 /* - SSI -------------------------------------------------------------------- */
3896 static const unsigned int ssi0_data_pins[] = {
3897 /* SDATA */
3898 RCAR_GP_PIN(2, 2),
3899 };
3900
3901 static const unsigned int ssi0_data_mux[] = {
3902 SSI_SDATA0_MARK,
3903 };
3904
3905 static const unsigned int ssi0_data_b_pins[] = {
3906 /* SDATA */
3907 RCAR_GP_PIN(3, 4),
3908 };
3909
3910 static const unsigned int ssi0_data_b_mux[] = {
3911 SSI_SDATA0_B_MARK,
3912 };
3913
3914 static const unsigned int ssi0129_ctrl_pins[] = {
3915 /* SCK, WS */
3916 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3917 };
3918
3919 static const unsigned int ssi0129_ctrl_mux[] = {
3920 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3921 };
3922
3923 static const unsigned int ssi0129_ctrl_b_pins[] = {
3924 /* SCK, WS */
3925 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3926 };
3927
3928 static const unsigned int ssi0129_ctrl_b_mux[] = {
3929 SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3930 };
3931
3932 static const unsigned int ssi1_data_pins[] = {
3933 /* SDATA */
3934 RCAR_GP_PIN(2, 5),
3935 };
3936
3937 static const unsigned int ssi1_data_mux[] = {
3938 SSI_SDATA1_MARK,
3939 };
3940
3941 static const unsigned int ssi1_data_b_pins[] = {
3942 /* SDATA */
3943 RCAR_GP_PIN(3, 7),
3944 };
3945
3946 static const unsigned int ssi1_data_b_mux[] = {
3947 SSI_SDATA1_B_MARK,
3948 };
3949
3950 static const unsigned int ssi1_ctrl_pins[] = {
3951 /* SCK, WS */
3952 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3953 };
3954
3955 static const unsigned int ssi1_ctrl_mux[] = {
3956 SSI_SCK1_MARK, SSI_WS1_MARK,
3957 };
3958
3959 static const unsigned int ssi1_ctrl_b_pins[] = {
3960 /* SCK, WS */
3961 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3962 };
3963
3964 static const unsigned int ssi1_ctrl_b_mux[] = {
3965 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3966 };
3967
3968 static const unsigned int ssi2_data_pins[] = {
3969 /* SDATA */
3970 RCAR_GP_PIN(2, 8),
3971 };
3972
3973 static const unsigned int ssi2_data_mux[] = {
3974 SSI_SDATA2_MARK,
3975 };
3976
3977 static const unsigned int ssi2_ctrl_pins[] = {
3978 /* SCK, WS */
3979 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3980 };
3981
3982 static const unsigned int ssi2_ctrl_mux[] = {
3983 SSI_SCK2_MARK, SSI_WS2_MARK,
3984 };
3985
3986 static const unsigned int ssi3_data_pins[] = {
3987 /* SDATA */
3988 RCAR_GP_PIN(2, 11),
3989 };
3990
3991 static const unsigned int ssi3_data_mux[] = {
3992 SSI_SDATA3_MARK,
3993 };
3994
3995 static const unsigned int ssi34_ctrl_pins[] = {
3996 /* SCK, WS */
3997 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
3998 };
3999
4000 static const unsigned int ssi34_ctrl_mux[] = {
4001 SSI_SCK34_MARK, SSI_WS34_MARK,
4002 };
4003
4004 static const unsigned int ssi4_data_pins[] = {
4005 /* SDATA */
4006 RCAR_GP_PIN(2, 14),
4007 };
4008
4009 static const unsigned int ssi4_data_mux[] = {
4010 SSI_SDATA4_MARK,
4011 };
4012
4013 static const unsigned int ssi4_ctrl_pins[] = {
4014 /* SCK, WS */
4015 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
4016 };
4017
4018 static const unsigned int ssi4_ctrl_mux[] = {
4019 SSI_SCK4_MARK, SSI_WS4_MARK,
4020 };
4021
4022 static const unsigned int ssi5_data_pins[] = {
4023 /* SDATA */
4024 RCAR_GP_PIN(2, 17),
4025 };
4026
4027 static const unsigned int ssi5_data_mux[] = {
4028 SSI_SDATA5_MARK,
4029 };
4030
4031 static const unsigned int ssi5_ctrl_pins[] = {
4032 /* SCK, WS */
4033 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4034 };
4035
4036 static const unsigned int ssi5_ctrl_mux[] = {
4037 SSI_SCK5_MARK, SSI_WS5_MARK,
4038 };
4039
4040 static const unsigned int ssi6_data_pins[] = {
4041 /* SDATA */
4042 RCAR_GP_PIN(2, 20),
4043 };
4044
4045 static const unsigned int ssi6_data_mux[] = {
4046 SSI_SDATA6_MARK,
4047 };
4048
4049 static const unsigned int ssi6_ctrl_pins[] = {
4050 /* SCK, WS */
4051 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
4052 };
4053
4054 static const unsigned int ssi6_ctrl_mux[] = {
4055 SSI_SCK6_MARK, SSI_WS6_MARK,
4056 };
4057
4058 static const unsigned int ssi7_data_pins[] = {
4059 /* SDATA */
4060 RCAR_GP_PIN(2, 23),
4061 };
4062
4063 static const unsigned int ssi7_data_mux[] = {
4064 SSI_SDATA7_MARK,
4065 };
4066
4067 static const unsigned int ssi7_data_b_pins[] = {
4068 /* SDATA */
4069 RCAR_GP_PIN(3, 12),
4070 };
4071
4072 static const unsigned int ssi7_data_b_mux[] = {
4073 SSI_SDATA7_B_MARK,
4074 };
4075
4076 static const unsigned int ssi78_ctrl_pins[] = {
4077 /* SCK, WS */
4078 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
4079 };
4080
4081 static const unsigned int ssi78_ctrl_mux[] = {
4082 SSI_SCK78_MARK, SSI_WS78_MARK,
4083 };
4084
4085 static const unsigned int ssi78_ctrl_b_pins[] = {
4086 /* SCK, WS */
4087 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4088 };
4089
4090 static const unsigned int ssi78_ctrl_b_mux[] = {
4091 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
4092 };
4093
4094 static const unsigned int ssi8_data_pins[] = {
4095 /* SDATA */
4096 RCAR_GP_PIN(2, 24),
4097 };
4098
4099 static const unsigned int ssi8_data_mux[] = {
4100 SSI_SDATA8_MARK,
4101 };
4102
4103 static const unsigned int ssi8_data_b_pins[] = {
4104 /* SDATA */
4105 RCAR_GP_PIN(3, 13),
4106 };
4107
4108 static const unsigned int ssi8_data_b_mux[] = {
4109 SSI_SDATA8_B_MARK,
4110 };
4111
4112 static const unsigned int ssi9_data_pins[] = {
4113 /* SDATA */
4114 RCAR_GP_PIN(2, 27),
4115 };
4116
4117 static const unsigned int ssi9_data_mux[] = {
4118 SSI_SDATA9_MARK,
4119 };
4120
4121 static const unsigned int ssi9_data_b_pins[] = {
4122 /* SDATA */
4123 RCAR_GP_PIN(3, 18),
4124 };
4125
4126 static const unsigned int ssi9_data_b_mux[] = {
4127 SSI_SDATA9_B_MARK,
4128 };
4129
4130 static const unsigned int ssi9_ctrl_pins[] = {
4131 /* SCK, WS */
4132 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
4133 };
4134
4135 static const unsigned int ssi9_ctrl_mux[] = {
4136 SSI_SCK9_MARK, SSI_WS9_MARK,
4137 };
4138
4139 static const unsigned int ssi9_ctrl_b_pins[] = {
4140 /* SCK, WS */
4141 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
4142 };
4143
4144 static const unsigned int ssi9_ctrl_b_mux[] = {
4145 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4146 };
4147
4148 /* - TPU -------------------------------------------------------------------- */
4149 static const unsigned int tpu_to0_pins[] = {
4150 RCAR_GP_PIN(6, 14),
4151 };
4152 static const unsigned int tpu_to0_mux[] = {
4153 TPU_TO0_MARK,
4154 };
4155 static const unsigned int tpu_to1_pins[] = {
4156 RCAR_GP_PIN(1, 17),
4157 };
4158 static const unsigned int tpu_to1_mux[] = {
4159 TPU_TO1_MARK,
4160 };
4161 static const unsigned int tpu_to2_pins[] = {
4162 RCAR_GP_PIN(1, 18),
4163 };
4164 static const unsigned int tpu_to2_mux[] = {
4165 TPU_TO2_MARK,
4166 };
4167 static const unsigned int tpu_to3_pins[] = {
4168 RCAR_GP_PIN(1, 24),
4169 };
4170 static const unsigned int tpu_to3_mux[] = {
4171 TPU_TO3_MARK,
4172 };
4173
4174 /* - USB0 ------------------------------------------------------------------- */
4175 static const unsigned int usb0_pins[] = {
4176 RCAR_GP_PIN(7, 23), /* PWEN */
4177 RCAR_GP_PIN(7, 24), /* OVC */
4178 };
4179 static const unsigned int usb0_mux[] = {
4180 USB0_PWEN_MARK,
4181 USB0_OVC_MARK,
4182 };
4183 /* - USB1 ------------------------------------------------------------------- */
4184 static const unsigned int usb1_pins[] = {
4185 RCAR_GP_PIN(7, 25), /* PWEN */
4186 RCAR_GP_PIN(6, 30), /* OVC */
4187 };
4188 static const unsigned int usb1_mux[] = {
4189 USB1_PWEN_MARK,
4190 USB1_OVC_MARK,
4191 };
4192 /* - VIN0 ------------------------------------------------------------------- */
4193 static const union vin_data vin0_data_pins = {
4194 .data24 = {
4195 /* B */
4196 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4197 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4198 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4199 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4200 /* G */
4201 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4202 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4203 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4204 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4205 /* R */
4206 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4207 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4208 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4209 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4210 },
4211 };
4212 static const union vin_data vin0_data_mux = {
4213 .data24 = {
4214 /* B */
4215 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4216 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4217 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4218 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4219 /* G */
4220 VI0_G0_MARK, VI0_G1_MARK,
4221 VI0_G2_MARK, VI0_G3_MARK,
4222 VI0_G4_MARK, VI0_G5_MARK,
4223 VI0_G6_MARK, VI0_G7_MARK,
4224 /* R */
4225 VI0_R0_MARK, VI0_R1_MARK,
4226 VI0_R2_MARK, VI0_R3_MARK,
4227 VI0_R4_MARK, VI0_R5_MARK,
4228 VI0_R6_MARK, VI0_R7_MARK,
4229 },
4230 };
4231 static const unsigned int vin0_data18_pins[] = {
4232 /* B */
4233 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4234 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4235 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4236 /* G */
4237 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4238 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4239 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4240 /* R */
4241 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4242 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4243 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4244 };
4245 static const unsigned int vin0_data18_mux[] = {
4246 /* B */
4247 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4248 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4249 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4250 /* G */
4251 VI0_G2_MARK, VI0_G3_MARK,
4252 VI0_G4_MARK, VI0_G5_MARK,
4253 VI0_G6_MARK, VI0_G7_MARK,
4254 /* R */
4255 VI0_R2_MARK, VI0_R3_MARK,
4256 VI0_R4_MARK, VI0_R5_MARK,
4257 VI0_R6_MARK, VI0_R7_MARK,
4258 };
4259 static const unsigned int vin0_sync_pins[] = {
4260 RCAR_GP_PIN(4, 3), /* HSYNC */
4261 RCAR_GP_PIN(4, 4), /* VSYNC */
4262 };
4263 static const unsigned int vin0_sync_mux[] = {
4264 VI0_HSYNC_N_MARK,
4265 VI0_VSYNC_N_MARK,
4266 };
4267 static const unsigned int vin0_field_pins[] = {
4268 RCAR_GP_PIN(4, 2),
4269 };
4270 static const unsigned int vin0_field_mux[] = {
4271 VI0_FIELD_MARK,
4272 };
4273 static const unsigned int vin0_clkenb_pins[] = {
4274 RCAR_GP_PIN(4, 1),
4275 };
4276 static const unsigned int vin0_clkenb_mux[] = {
4277 VI0_CLKENB_MARK,
4278 };
4279 static const unsigned int vin0_clk_pins[] = {
4280 RCAR_GP_PIN(4, 0),
4281 };
4282 static const unsigned int vin0_clk_mux[] = {
4283 VI0_CLK_MARK,
4284 };
4285 /* - VIN1 ----------------------------------------------------------------- */
4286 static const unsigned int vin1_data8_pins[] = {
4287 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4288 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4289 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4290 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4291 };
4292 static const unsigned int vin1_data8_mux[] = {
4293 VI1_DATA0_MARK, VI1_DATA1_MARK,
4294 VI1_DATA2_MARK, VI1_DATA3_MARK,
4295 VI1_DATA4_MARK, VI1_DATA5_MARK,
4296 VI1_DATA6_MARK, VI1_DATA7_MARK,
4297 };
4298 static const unsigned int vin1_sync_pins[] = {
4299 RCAR_GP_PIN(5, 0), /* HSYNC */
4300 RCAR_GP_PIN(5, 1), /* VSYNC */
4301 };
4302 static const unsigned int vin1_sync_mux[] = {
4303 VI1_HSYNC_N_MARK,
4304 VI1_VSYNC_N_MARK,
4305 };
4306 static const unsigned int vin1_field_pins[] = {
4307 RCAR_GP_PIN(5, 3),
4308 };
4309 static const unsigned int vin1_field_mux[] = {
4310 VI1_FIELD_MARK,
4311 };
4312 static const unsigned int vin1_clkenb_pins[] = {
4313 RCAR_GP_PIN(5, 2),
4314 };
4315 static const unsigned int vin1_clkenb_mux[] = {
4316 VI1_CLKENB_MARK,
4317 };
4318 static const unsigned int vin1_clk_pins[] = {
4319 RCAR_GP_PIN(5, 4),
4320 };
4321 static const unsigned int vin1_clk_mux[] = {
4322 VI1_CLK_MARK,
4323 };
4324 static const union vin_data vin1_b_data_pins = {
4325 .data24 = {
4326 /* B */
4327 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4328 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4329 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4330 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4331 /* G */
4332 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4333 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4334 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4335 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4336 /* R */
4337 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4338 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4339 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4340 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4341 },
4342 };
4343 static const union vin_data vin1_b_data_mux = {
4344 .data24 = {
4345 /* B */
4346 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4347 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4348 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4349 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4350 /* G */
4351 VI1_G0_B_MARK, VI1_G1_B_MARK,
4352 VI1_G2_B_MARK, VI1_G3_B_MARK,
4353 VI1_G4_B_MARK, VI1_G5_B_MARK,
4354 VI1_G6_B_MARK, VI1_G7_B_MARK,
4355 /* R */
4356 VI1_R0_B_MARK, VI1_R1_B_MARK,
4357 VI1_R2_B_MARK, VI1_R3_B_MARK,
4358 VI1_R4_B_MARK, VI1_R5_B_MARK,
4359 VI1_R6_B_MARK, VI1_R7_B_MARK,
4360 },
4361 };
4362 static const unsigned int vin1_b_data18_pins[] = {
4363 /* B */
4364 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4365 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4366 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4367 /* G */
4368 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4369 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4370 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4371 /* R */
4372 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4373 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4374 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4375 };
4376 static const unsigned int vin1_b_data18_mux[] = {
4377 /* B */
4378 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4379 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4380 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4381 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4382 /* G */
4383 VI1_G0_B_MARK, VI1_G1_B_MARK,
4384 VI1_G2_B_MARK, VI1_G3_B_MARK,
4385 VI1_G4_B_MARK, VI1_G5_B_MARK,
4386 VI1_G6_B_MARK, VI1_G7_B_MARK,
4387 /* R */
4388 VI1_R0_B_MARK, VI1_R1_B_MARK,
4389 VI1_R2_B_MARK, VI1_R3_B_MARK,
4390 VI1_R4_B_MARK, VI1_R5_B_MARK,
4391 VI1_R6_B_MARK, VI1_R7_B_MARK,
4392 };
4393 static const unsigned int vin1_b_sync_pins[] = {
4394 RCAR_GP_PIN(3, 17), /* HSYNC */
4395 RCAR_GP_PIN(3, 18), /* VSYNC */
4396 };
4397 static const unsigned int vin1_b_sync_mux[] = {
4398 VI1_HSYNC_N_B_MARK,
4399 VI1_VSYNC_N_B_MARK,
4400 };
4401 static const unsigned int vin1_b_field_pins[] = {
4402 RCAR_GP_PIN(3, 20),
4403 };
4404 static const unsigned int vin1_b_field_mux[] = {
4405 VI1_FIELD_B_MARK,
4406 };
4407 static const unsigned int vin1_b_clkenb_pins[] = {
4408 RCAR_GP_PIN(3, 19),
4409 };
4410 static const unsigned int vin1_b_clkenb_mux[] = {
4411 VI1_CLKENB_B_MARK,
4412 };
4413 static const unsigned int vin1_b_clk_pins[] = {
4414 RCAR_GP_PIN(3, 16),
4415 };
4416 static const unsigned int vin1_b_clk_mux[] = {
4417 VI1_CLK_B_MARK,
4418 };
4419 /* - VIN2 ----------------------------------------------------------------- */
4420 static const unsigned int vin2_data8_pins[] = {
4421 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4422 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4423 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4424 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4425 };
4426 static const unsigned int vin2_data8_mux[] = {
4427 VI2_DATA0_MARK, VI2_DATA1_MARK,
4428 VI2_DATA2_MARK, VI2_DATA3_MARK,
4429 VI2_DATA4_MARK, VI2_DATA5_MARK,
4430 VI2_DATA6_MARK, VI2_DATA7_MARK,
4431 };
4432 static const unsigned int vin2_sync_pins[] = {
4433 RCAR_GP_PIN(4, 15), /* HSYNC */
4434 RCAR_GP_PIN(4, 16), /* VSYNC */
4435 };
4436 static const unsigned int vin2_sync_mux[] = {
4437 VI2_HSYNC_N_MARK,
4438 VI2_VSYNC_N_MARK,
4439 };
4440 static const unsigned int vin2_field_pins[] = {
4441 RCAR_GP_PIN(4, 18),
4442 };
4443 static const unsigned int vin2_field_mux[] = {
4444 VI2_FIELD_MARK,
4445 };
4446 static const unsigned int vin2_clkenb_pins[] = {
4447 RCAR_GP_PIN(4, 17),
4448 };
4449 static const unsigned int vin2_clkenb_mux[] = {
4450 VI2_CLKENB_MARK,
4451 };
4452 static const unsigned int vin2_clk_pins[] = {
4453 RCAR_GP_PIN(4, 19),
4454 };
4455 static const unsigned int vin2_clk_mux[] = {
4456 VI2_CLK_MARK,
4457 };
4458
4459 static const struct {
4460 struct sh_pfc_pin_group common[346];
4461 struct sh_pfc_pin_group r8a779x[9];
4462 } pinmux_groups = {
4463 .common = {
4464 SH_PFC_PIN_GROUP(audio_clk_a),
4465 SH_PFC_PIN_GROUP(audio_clk_b),
4466 SH_PFC_PIN_GROUP(audio_clk_b_b),
4467 SH_PFC_PIN_GROUP(audio_clk_c),
4468 SH_PFC_PIN_GROUP(audio_clkout),
4469 SH_PFC_PIN_GROUP(avb_link),
4470 SH_PFC_PIN_GROUP(avb_magic),
4471 SH_PFC_PIN_GROUP(avb_phy_int),
4472 SH_PFC_PIN_GROUP(avb_mdio),
4473 SH_PFC_PIN_GROUP(avb_mii),
4474 SH_PFC_PIN_GROUP(avb_gmii),
4475 SH_PFC_PIN_GROUP(can0_data),
4476 SH_PFC_PIN_GROUP(can0_data_b),
4477 SH_PFC_PIN_GROUP(can0_data_c),
4478 SH_PFC_PIN_GROUP(can0_data_d),
4479 SH_PFC_PIN_GROUP(can0_data_e),
4480 SH_PFC_PIN_GROUP(can0_data_f),
4481 SH_PFC_PIN_GROUP(can1_data),
4482 SH_PFC_PIN_GROUP(can1_data_b),
4483 SH_PFC_PIN_GROUP(can1_data_c),
4484 SH_PFC_PIN_GROUP(can1_data_d),
4485 SH_PFC_PIN_GROUP(can_clk),
4486 SH_PFC_PIN_GROUP(can_clk_b),
4487 SH_PFC_PIN_GROUP(can_clk_c),
4488 SH_PFC_PIN_GROUP(can_clk_d),
4489 SH_PFC_PIN_GROUP(du_rgb666),
4490 SH_PFC_PIN_GROUP(du_rgb888),
4491 SH_PFC_PIN_GROUP(du_clk_out_0),
4492 SH_PFC_PIN_GROUP(du_clk_out_1),
4493 SH_PFC_PIN_GROUP(du_sync),
4494 SH_PFC_PIN_GROUP(du_oddf),
4495 SH_PFC_PIN_GROUP(du_cde),
4496 SH_PFC_PIN_GROUP(du_disp),
4497 SH_PFC_PIN_GROUP(du0_clk_in),
4498 SH_PFC_PIN_GROUP(du1_clk_in),
4499 SH_PFC_PIN_GROUP(du1_clk_in_b),
4500 SH_PFC_PIN_GROUP(du1_clk_in_c),
4501 SH_PFC_PIN_GROUP(eth_link),
4502 SH_PFC_PIN_GROUP(eth_magic),
4503 SH_PFC_PIN_GROUP(eth_mdio),
4504 SH_PFC_PIN_GROUP(eth_rmii),
4505 SH_PFC_PIN_GROUP(hscif0_data),
4506 SH_PFC_PIN_GROUP(hscif0_clk),
4507 SH_PFC_PIN_GROUP(hscif0_ctrl),
4508 SH_PFC_PIN_GROUP(hscif0_data_b),
4509 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4510 SH_PFC_PIN_GROUP(hscif0_data_c),
4511 SH_PFC_PIN_GROUP(hscif0_clk_c),
4512 SH_PFC_PIN_GROUP(hscif1_data),
4513 SH_PFC_PIN_GROUP(hscif1_clk),
4514 SH_PFC_PIN_GROUP(hscif1_ctrl),
4515 SH_PFC_PIN_GROUP(hscif1_data_b),
4516 SH_PFC_PIN_GROUP(hscif1_data_c),
4517 SH_PFC_PIN_GROUP(hscif1_clk_c),
4518 SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4519 SH_PFC_PIN_GROUP(hscif1_data_d),
4520 SH_PFC_PIN_GROUP(hscif1_data_e),
4521 SH_PFC_PIN_GROUP(hscif1_clk_e),
4522 SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4523 SH_PFC_PIN_GROUP(hscif2_data),
4524 SH_PFC_PIN_GROUP(hscif2_clk),
4525 SH_PFC_PIN_GROUP(hscif2_ctrl),
4526 SH_PFC_PIN_GROUP(hscif2_data_b),
4527 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4528 SH_PFC_PIN_GROUP(hscif2_data_c),
4529 SH_PFC_PIN_GROUP(hscif2_clk_c),
4530 SH_PFC_PIN_GROUP(hscif2_data_d),
4531 SH_PFC_PIN_GROUP(i2c0),
4532 SH_PFC_PIN_GROUP(i2c0_b),
4533 SH_PFC_PIN_GROUP(i2c0_c),
4534 SH_PFC_PIN_GROUP(i2c1),
4535 SH_PFC_PIN_GROUP(i2c1_b),
4536 SH_PFC_PIN_GROUP(i2c1_c),
4537 SH_PFC_PIN_GROUP(i2c1_d),
4538 SH_PFC_PIN_GROUP(i2c1_e),
4539 SH_PFC_PIN_GROUP(i2c2),
4540 SH_PFC_PIN_GROUP(i2c2_b),
4541 SH_PFC_PIN_GROUP(i2c2_c),
4542 SH_PFC_PIN_GROUP(i2c2_d),
4543 SH_PFC_PIN_GROUP(i2c3),
4544 SH_PFC_PIN_GROUP(i2c3_b),
4545 SH_PFC_PIN_GROUP(i2c3_c),
4546 SH_PFC_PIN_GROUP(i2c3_d),
4547 SH_PFC_PIN_GROUP(i2c4),
4548 SH_PFC_PIN_GROUP(i2c4_b),
4549 SH_PFC_PIN_GROUP(i2c4_c),
4550 SH_PFC_PIN_GROUP(i2c7),
4551 SH_PFC_PIN_GROUP(i2c7_b),
4552 SH_PFC_PIN_GROUP(i2c7_c),
4553 SH_PFC_PIN_GROUP(i2c8),
4554 SH_PFC_PIN_GROUP(i2c8_b),
4555 SH_PFC_PIN_GROUP(i2c8_c),
4556 SH_PFC_PIN_GROUP(intc_irq0),
4557 SH_PFC_PIN_GROUP(intc_irq1),
4558 SH_PFC_PIN_GROUP(intc_irq2),
4559 SH_PFC_PIN_GROUP(intc_irq3),
4560 SH_PFC_PIN_GROUP(mmc_data1),
4561 SH_PFC_PIN_GROUP(mmc_data4),
4562 SH_PFC_PIN_GROUP(mmc_data8),
4563 SH_PFC_PIN_GROUP(mmc_data8_b),
4564 SH_PFC_PIN_GROUP(mmc_ctrl),
4565 SH_PFC_PIN_GROUP(msiof0_clk),
4566 SH_PFC_PIN_GROUP(msiof0_sync),
4567 SH_PFC_PIN_GROUP(msiof0_ss1),
4568 SH_PFC_PIN_GROUP(msiof0_ss2),
4569 SH_PFC_PIN_GROUP(msiof0_rx),
4570 SH_PFC_PIN_GROUP(msiof0_tx),
4571 SH_PFC_PIN_GROUP(msiof0_clk_b),
4572 SH_PFC_PIN_GROUP(msiof0_sync_b),
4573 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4574 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4575 SH_PFC_PIN_GROUP(msiof0_rx_b),
4576 SH_PFC_PIN_GROUP(msiof0_tx_b),
4577 SH_PFC_PIN_GROUP(msiof0_clk_c),
4578 SH_PFC_PIN_GROUP(msiof0_sync_c),
4579 SH_PFC_PIN_GROUP(msiof0_ss1_c),
4580 SH_PFC_PIN_GROUP(msiof0_ss2_c),
4581 SH_PFC_PIN_GROUP(msiof0_rx_c),
4582 SH_PFC_PIN_GROUP(msiof0_tx_c),
4583 SH_PFC_PIN_GROUP(msiof1_clk),
4584 SH_PFC_PIN_GROUP(msiof1_sync),
4585 SH_PFC_PIN_GROUP(msiof1_ss1),
4586 SH_PFC_PIN_GROUP(msiof1_ss2),
4587 SH_PFC_PIN_GROUP(msiof1_rx),
4588 SH_PFC_PIN_GROUP(msiof1_tx),
4589 SH_PFC_PIN_GROUP(msiof1_clk_b),
4590 SH_PFC_PIN_GROUP(msiof1_sync_b),
4591 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4592 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4593 SH_PFC_PIN_GROUP(msiof1_rx_b),
4594 SH_PFC_PIN_GROUP(msiof1_tx_b),
4595 SH_PFC_PIN_GROUP(msiof1_clk_c),
4596 SH_PFC_PIN_GROUP(msiof1_sync_c),
4597 SH_PFC_PIN_GROUP(msiof1_rx_c),
4598 SH_PFC_PIN_GROUP(msiof1_tx_c),
4599 SH_PFC_PIN_GROUP(msiof1_clk_d),
4600 SH_PFC_PIN_GROUP(msiof1_sync_d),
4601 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4602 SH_PFC_PIN_GROUP(msiof1_rx_d),
4603 SH_PFC_PIN_GROUP(msiof1_tx_d),
4604 SH_PFC_PIN_GROUP(msiof1_clk_e),
4605 SH_PFC_PIN_GROUP(msiof1_sync_e),
4606 SH_PFC_PIN_GROUP(msiof1_rx_e),
4607 SH_PFC_PIN_GROUP(msiof1_tx_e),
4608 SH_PFC_PIN_GROUP(msiof2_clk),
4609 SH_PFC_PIN_GROUP(msiof2_sync),
4610 SH_PFC_PIN_GROUP(msiof2_ss1),
4611 SH_PFC_PIN_GROUP(msiof2_ss2),
4612 SH_PFC_PIN_GROUP(msiof2_rx),
4613 SH_PFC_PIN_GROUP(msiof2_tx),
4614 SH_PFC_PIN_GROUP(msiof2_clk_b),
4615 SH_PFC_PIN_GROUP(msiof2_sync_b),
4616 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4617 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4618 SH_PFC_PIN_GROUP(msiof2_rx_b),
4619 SH_PFC_PIN_GROUP(msiof2_tx_b),
4620 SH_PFC_PIN_GROUP(msiof2_clk_c),
4621 SH_PFC_PIN_GROUP(msiof2_sync_c),
4622 SH_PFC_PIN_GROUP(msiof2_rx_c),
4623 SH_PFC_PIN_GROUP(msiof2_tx_c),
4624 SH_PFC_PIN_GROUP(msiof2_clk_d),
4625 SH_PFC_PIN_GROUP(msiof2_sync_d),
4626 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4627 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4628 SH_PFC_PIN_GROUP(msiof2_rx_d),
4629 SH_PFC_PIN_GROUP(msiof2_tx_d),
4630 SH_PFC_PIN_GROUP(msiof2_clk_e),
4631 SH_PFC_PIN_GROUP(msiof2_sync_e),
4632 SH_PFC_PIN_GROUP(msiof2_rx_e),
4633 SH_PFC_PIN_GROUP(msiof2_tx_e),
4634 SH_PFC_PIN_GROUP(pwm0),
4635 SH_PFC_PIN_GROUP(pwm0_b),
4636 SH_PFC_PIN_GROUP(pwm1),
4637 SH_PFC_PIN_GROUP(pwm1_b),
4638 SH_PFC_PIN_GROUP(pwm2),
4639 SH_PFC_PIN_GROUP(pwm2_b),
4640 SH_PFC_PIN_GROUP(pwm3),
4641 SH_PFC_PIN_GROUP(pwm4),
4642 SH_PFC_PIN_GROUP(pwm4_b),
4643 SH_PFC_PIN_GROUP(pwm5),
4644 SH_PFC_PIN_GROUP(pwm5_b),
4645 SH_PFC_PIN_GROUP(pwm6),
4646 SH_PFC_PIN_GROUP(qspi_ctrl),
4647 SH_PFC_PIN_GROUP(qspi_data2),
4648 SH_PFC_PIN_GROUP(qspi_data4),
4649 SH_PFC_PIN_GROUP(qspi_ctrl_b),
4650 SH_PFC_PIN_GROUP(qspi_data2_b),
4651 SH_PFC_PIN_GROUP(qspi_data4_b),
4652 SH_PFC_PIN_GROUP(scif0_data),
4653 SH_PFC_PIN_GROUP(scif0_data_b),
4654 SH_PFC_PIN_GROUP(scif0_data_c),
4655 SH_PFC_PIN_GROUP(scif0_data_d),
4656 SH_PFC_PIN_GROUP(scif0_data_e),
4657 SH_PFC_PIN_GROUP(scif1_data),
4658 SH_PFC_PIN_GROUP(scif1_data_b),
4659 SH_PFC_PIN_GROUP(scif1_clk_b),
4660 SH_PFC_PIN_GROUP(scif1_data_c),
4661 SH_PFC_PIN_GROUP(scif1_data_d),
4662 SH_PFC_PIN_GROUP(scif2_data),
4663 SH_PFC_PIN_GROUP(scif2_data_b),
4664 SH_PFC_PIN_GROUP(scif2_clk_b),
4665 SH_PFC_PIN_GROUP(scif2_data_c),
4666 SH_PFC_PIN_GROUP(scif2_data_e),
4667 SH_PFC_PIN_GROUP(scif3_data),
4668 SH_PFC_PIN_GROUP(scif3_clk),
4669 SH_PFC_PIN_GROUP(scif3_data_b),
4670 SH_PFC_PIN_GROUP(scif3_clk_b),
4671 SH_PFC_PIN_GROUP(scif3_data_c),
4672 SH_PFC_PIN_GROUP(scif3_data_d),
4673 SH_PFC_PIN_GROUP(scif4_data),
4674 SH_PFC_PIN_GROUP(scif4_data_b),
4675 SH_PFC_PIN_GROUP(scif4_data_c),
4676 SH_PFC_PIN_GROUP(scif5_data),
4677 SH_PFC_PIN_GROUP(scif5_data_b),
4678 SH_PFC_PIN_GROUP(scifa0_data),
4679 SH_PFC_PIN_GROUP(scifa0_data_b),
4680 SH_PFC_PIN_GROUP(scifa1_data),
4681 SH_PFC_PIN_GROUP(scifa1_clk),
4682 SH_PFC_PIN_GROUP(scifa1_data_b),
4683 SH_PFC_PIN_GROUP(scifa1_clk_b),
4684 SH_PFC_PIN_GROUP(scifa1_data_c),
4685 SH_PFC_PIN_GROUP(scifa2_data),
4686 SH_PFC_PIN_GROUP(scifa2_clk),
4687 SH_PFC_PIN_GROUP(scifa2_data_b),
4688 SH_PFC_PIN_GROUP(scifa3_data),
4689 SH_PFC_PIN_GROUP(scifa3_clk),
4690 SH_PFC_PIN_GROUP(scifa3_data_b),
4691 SH_PFC_PIN_GROUP(scifa3_clk_b),
4692 SH_PFC_PIN_GROUP(scifa3_data_c),
4693 SH_PFC_PIN_GROUP(scifa3_clk_c),
4694 SH_PFC_PIN_GROUP(scifa4_data),
4695 SH_PFC_PIN_GROUP(scifa4_data_b),
4696 SH_PFC_PIN_GROUP(scifa4_data_c),
4697 SH_PFC_PIN_GROUP(scifa5_data),
4698 SH_PFC_PIN_GROUP(scifa5_data_b),
4699 SH_PFC_PIN_GROUP(scifa5_data_c),
4700 SH_PFC_PIN_GROUP(scifb0_data),
4701 SH_PFC_PIN_GROUP(scifb0_clk),
4702 SH_PFC_PIN_GROUP(scifb0_ctrl),
4703 SH_PFC_PIN_GROUP(scifb0_data_b),
4704 SH_PFC_PIN_GROUP(scifb0_clk_b),
4705 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4706 SH_PFC_PIN_GROUP(scifb0_data_c),
4707 SH_PFC_PIN_GROUP(scifb0_clk_c),
4708 SH_PFC_PIN_GROUP(scifb0_data_d),
4709 SH_PFC_PIN_GROUP(scifb0_clk_d),
4710 SH_PFC_PIN_GROUP(scifb1_data),
4711 SH_PFC_PIN_GROUP(scifb1_clk),
4712 SH_PFC_PIN_GROUP(scifb1_ctrl),
4713 SH_PFC_PIN_GROUP(scifb1_data_b),
4714 SH_PFC_PIN_GROUP(scifb1_clk_b),
4715 SH_PFC_PIN_GROUP(scifb1_data_c),
4716 SH_PFC_PIN_GROUP(scifb1_clk_c),
4717 SH_PFC_PIN_GROUP(scifb1_data_d),
4718 SH_PFC_PIN_GROUP(scifb2_data),
4719 SH_PFC_PIN_GROUP(scifb2_clk),
4720 SH_PFC_PIN_GROUP(scifb2_ctrl),
4721 SH_PFC_PIN_GROUP(scifb2_data_b),
4722 SH_PFC_PIN_GROUP(scifb2_clk_b),
4723 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4724 SH_PFC_PIN_GROUP(scifb2_data_c),
4725 SH_PFC_PIN_GROUP(scifb2_clk_c),
4726 SH_PFC_PIN_GROUP(scifb2_data_d),
4727 SH_PFC_PIN_GROUP(scif_clk),
4728 SH_PFC_PIN_GROUP(scif_clk_b),
4729 SH_PFC_PIN_GROUP(sdhi0_data1),
4730 SH_PFC_PIN_GROUP(sdhi0_data4),
4731 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4732 SH_PFC_PIN_GROUP(sdhi0_cd),
4733 SH_PFC_PIN_GROUP(sdhi0_wp),
4734 SH_PFC_PIN_GROUP(sdhi1_data1),
4735 SH_PFC_PIN_GROUP(sdhi1_data4),
4736 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4737 SH_PFC_PIN_GROUP(sdhi1_cd),
4738 SH_PFC_PIN_GROUP(sdhi1_wp),
4739 SH_PFC_PIN_GROUP(sdhi2_data1),
4740 SH_PFC_PIN_GROUP(sdhi2_data4),
4741 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4742 SH_PFC_PIN_GROUP(sdhi2_cd),
4743 SH_PFC_PIN_GROUP(sdhi2_wp),
4744 SH_PFC_PIN_GROUP(ssi0_data),
4745 SH_PFC_PIN_GROUP(ssi0_data_b),
4746 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4747 SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4748 SH_PFC_PIN_GROUP(ssi1_data),
4749 SH_PFC_PIN_GROUP(ssi1_data_b),
4750 SH_PFC_PIN_GROUP(ssi1_ctrl),
4751 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4752 SH_PFC_PIN_GROUP(ssi2_data),
4753 SH_PFC_PIN_GROUP(ssi2_ctrl),
4754 SH_PFC_PIN_GROUP(ssi3_data),
4755 SH_PFC_PIN_GROUP(ssi34_ctrl),
4756 SH_PFC_PIN_GROUP(ssi4_data),
4757 SH_PFC_PIN_GROUP(ssi4_ctrl),
4758 SH_PFC_PIN_GROUP(ssi5_data),
4759 SH_PFC_PIN_GROUP(ssi5_ctrl),
4760 SH_PFC_PIN_GROUP(ssi6_data),
4761 SH_PFC_PIN_GROUP(ssi6_ctrl),
4762 SH_PFC_PIN_GROUP(ssi7_data),
4763 SH_PFC_PIN_GROUP(ssi7_data_b),
4764 SH_PFC_PIN_GROUP(ssi78_ctrl),
4765 SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4766 SH_PFC_PIN_GROUP(ssi8_data),
4767 SH_PFC_PIN_GROUP(ssi8_data_b),
4768 SH_PFC_PIN_GROUP(ssi9_data),
4769 SH_PFC_PIN_GROUP(ssi9_data_b),
4770 SH_PFC_PIN_GROUP(ssi9_ctrl),
4771 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4772 SH_PFC_PIN_GROUP(tpu_to0),
4773 SH_PFC_PIN_GROUP(tpu_to1),
4774 SH_PFC_PIN_GROUP(tpu_to2),
4775 SH_PFC_PIN_GROUP(tpu_to3),
4776 SH_PFC_PIN_GROUP(usb0),
4777 SH_PFC_PIN_GROUP(usb1),
4778 VIN_DATA_PIN_GROUP(vin0_data, 24),
4779 VIN_DATA_PIN_GROUP(vin0_data, 20),
4780 SH_PFC_PIN_GROUP(vin0_data18),
4781 VIN_DATA_PIN_GROUP(vin0_data, 16),
4782 VIN_DATA_PIN_GROUP(vin0_data, 12),
4783 VIN_DATA_PIN_GROUP(vin0_data, 10),
4784 VIN_DATA_PIN_GROUP(vin0_data, 8),
4785 SH_PFC_PIN_GROUP(vin0_sync),
4786 SH_PFC_PIN_GROUP(vin0_field),
4787 SH_PFC_PIN_GROUP(vin0_clkenb),
4788 SH_PFC_PIN_GROUP(vin0_clk),
4789 SH_PFC_PIN_GROUP(vin1_data8),
4790 SH_PFC_PIN_GROUP(vin1_sync),
4791 SH_PFC_PIN_GROUP(vin1_field),
4792 SH_PFC_PIN_GROUP(vin1_clkenb),
4793 SH_PFC_PIN_GROUP(vin1_clk),
4794 VIN_DATA_PIN_GROUP(vin1_b_data, 24),
4795 VIN_DATA_PIN_GROUP(vin1_b_data, 20),
4796 SH_PFC_PIN_GROUP(vin1_b_data18),
4797 VIN_DATA_PIN_GROUP(vin1_b_data, 16),
4798 VIN_DATA_PIN_GROUP(vin1_b_data, 12),
4799 VIN_DATA_PIN_GROUP(vin1_b_data, 10),
4800 VIN_DATA_PIN_GROUP(vin1_b_data, 8),
4801 SH_PFC_PIN_GROUP(vin1_b_sync),
4802 SH_PFC_PIN_GROUP(vin1_b_field),
4803 SH_PFC_PIN_GROUP(vin1_b_clkenb),
4804 SH_PFC_PIN_GROUP(vin1_b_clk),
4805 SH_PFC_PIN_GROUP(vin2_data8),
4806 SH_PFC_PIN_GROUP(vin2_sync),
4807 SH_PFC_PIN_GROUP(vin2_field),
4808 SH_PFC_PIN_GROUP(vin2_clkenb),
4809 SH_PFC_PIN_GROUP(vin2_clk),
4810 },
4811 .r8a779x = {
4812 SH_PFC_PIN_GROUP(adi_common),
4813 SH_PFC_PIN_GROUP(adi_chsel0),
4814 SH_PFC_PIN_GROUP(adi_chsel1),
4815 SH_PFC_PIN_GROUP(adi_chsel2),
4816 SH_PFC_PIN_GROUP(adi_common_b),
4817 SH_PFC_PIN_GROUP(adi_chsel0_b),
4818 SH_PFC_PIN_GROUP(adi_chsel1_b),
4819 SH_PFC_PIN_GROUP(adi_chsel2_b),
4820 SH_PFC_PIN_GROUP(mlb_3pin),
4821 }
4822 };
4823
4824 static const char * const adi_groups[] = {
4825 "adi_common",
4826 "adi_chsel0",
4827 "adi_chsel1",
4828 "adi_chsel2",
4829 "adi_common_b",
4830 "adi_chsel0_b",
4831 "adi_chsel1_b",
4832 "adi_chsel2_b",
4833 };
4834
4835 static const char * const audio_clk_groups[] = {
4836 "audio_clk_a",
4837 "audio_clk_b",
4838 "audio_clk_b_b",
4839 "audio_clk_c",
4840 "audio_clkout",
4841 };
4842
4843 static const char * const avb_groups[] = {
4844 "avb_link",
4845 "avb_magic",
4846 "avb_phy_int",
4847 "avb_mdio",
4848 "avb_mii",
4849 "avb_gmii",
4850 };
4851
4852 static const char * const can0_groups[] = {
4853 "can0_data",
4854 "can0_data_b",
4855 "can0_data_c",
4856 "can0_data_d",
4857 "can0_data_e",
4858 "can0_data_f",
4859 /*
4860 * Retained for backwards compatibility, use can_clk_groups in new
4861 * designs.
4862 */
4863 "can_clk",
4864 "can_clk_b",
4865 "can_clk_c",
4866 "can_clk_d",
4867 };
4868
4869 static const char * const can1_groups[] = {
4870 "can1_data",
4871 "can1_data_b",
4872 "can1_data_c",
4873 "can1_data_d",
4874 /*
4875 * Retained for backwards compatibility, use can_clk_groups in new
4876 * designs.
4877 */
4878 "can_clk",
4879 "can_clk_b",
4880 "can_clk_c",
4881 "can_clk_d",
4882 };
4883
4884 /*
4885 * can_clk_groups allows for independent configuration, use can_clk function
4886 * in new designs.
4887 */
4888 static const char * const can_clk_groups[] = {
4889 "can_clk",
4890 "can_clk_b",
4891 "can_clk_c",
4892 "can_clk_d",
4893 };
4894
4895 static const char * const du_groups[] = {
4896 "du_rgb666",
4897 "du_rgb888",
4898 "du_clk_out_0",
4899 "du_clk_out_1",
4900 "du_sync",
4901 "du_oddf",
4902 "du_cde",
4903 "du_disp",
4904 };
4905
4906 static const char * const du0_groups[] = {
4907 "du0_clk_in",
4908 };
4909
4910 static const char * const du1_groups[] = {
4911 "du1_clk_in",
4912 "du1_clk_in_b",
4913 "du1_clk_in_c",
4914 };
4915
4916 static const char * const eth_groups[] = {
4917 "eth_link",
4918 "eth_magic",
4919 "eth_mdio",
4920 "eth_rmii",
4921 };
4922
4923 static const char * const hscif0_groups[] = {
4924 "hscif0_data",
4925 "hscif0_clk",
4926 "hscif0_ctrl",
4927 "hscif0_data_b",
4928 "hscif0_ctrl_b",
4929 "hscif0_data_c",
4930 "hscif0_clk_c",
4931 };
4932
4933 static const char * const hscif1_groups[] = {
4934 "hscif1_data",
4935 "hscif1_clk",
4936 "hscif1_ctrl",
4937 "hscif1_data_b",
4938 "hscif1_data_c",
4939 "hscif1_clk_c",
4940 "hscif1_ctrl_c",
4941 "hscif1_data_d",
4942 "hscif1_data_e",
4943 "hscif1_clk_e",
4944 "hscif1_ctrl_e",
4945 };
4946
4947 static const char * const hscif2_groups[] = {
4948 "hscif2_data",
4949 "hscif2_clk",
4950 "hscif2_ctrl",
4951 "hscif2_data_b",
4952 "hscif2_ctrl_b",
4953 "hscif2_data_c",
4954 "hscif2_clk_c",
4955 "hscif2_data_d",
4956 };
4957
4958 static const char * const i2c0_groups[] = {
4959 "i2c0",
4960 "i2c0_b",
4961 "i2c0_c",
4962 };
4963
4964 static const char * const i2c1_groups[] = {
4965 "i2c1",
4966 "i2c1_b",
4967 "i2c1_c",
4968 "i2c1_d",
4969 "i2c1_e",
4970 };
4971
4972 static const char * const i2c2_groups[] = {
4973 "i2c2",
4974 "i2c2_b",
4975 "i2c2_c",
4976 "i2c2_d",
4977 };
4978
4979 static const char * const i2c3_groups[] = {
4980 "i2c3",
4981 "i2c3_b",
4982 "i2c3_c",
4983 "i2c3_d",
4984 };
4985
4986 static const char * const i2c4_groups[] = {
4987 "i2c4",
4988 "i2c4_b",
4989 "i2c4_c",
4990 };
4991
4992 static const char * const i2c7_groups[] = {
4993 "i2c7",
4994 "i2c7_b",
4995 "i2c7_c",
4996 };
4997
4998 static const char * const i2c8_groups[] = {
4999 "i2c8",
5000 "i2c8_b",
5001 "i2c8_c",
5002 };
5003
5004 static const char * const intc_groups[] = {
5005 "intc_irq0",
5006 "intc_irq1",
5007 "intc_irq2",
5008 "intc_irq3",
5009 };
5010
5011 static const char * const mlb_groups[] = {
5012 "mlb_3pin",
5013 };
5014
5015 static const char * const mmc_groups[] = {
5016 "mmc_data1",
5017 "mmc_data4",
5018 "mmc_data8",
5019 "mmc_data8_b",
5020 "mmc_ctrl",
5021 };
5022
5023 static const char * const msiof0_groups[] = {
5024 "msiof0_clk",
5025 "msiof0_sync",
5026 "msiof0_ss1",
5027 "msiof0_ss2",
5028 "msiof0_rx",
5029 "msiof0_tx",
5030 "msiof0_clk_b",
5031 "msiof0_sync_b",
5032 "msiof0_ss1_b",
5033 "msiof0_ss2_b",
5034 "msiof0_rx_b",
5035 "msiof0_tx_b",
5036 "msiof0_clk_c",
5037 "msiof0_sync_c",
5038 "msiof0_ss1_c",
5039 "msiof0_ss2_c",
5040 "msiof0_rx_c",
5041 "msiof0_tx_c",
5042 };
5043
5044 static const char * const msiof1_groups[] = {
5045 "msiof1_clk",
5046 "msiof1_sync",
5047 "msiof1_ss1",
5048 "msiof1_ss2",
5049 "msiof1_rx",
5050 "msiof1_tx",
5051 "msiof1_clk_b",
5052 "msiof1_sync_b",
5053 "msiof1_ss1_b",
5054 "msiof1_ss2_b",
5055 "msiof1_rx_b",
5056 "msiof1_tx_b",
5057 "msiof1_clk_c",
5058 "msiof1_sync_c",
5059 "msiof1_rx_c",
5060 "msiof1_tx_c",
5061 "msiof1_clk_d",
5062 "msiof1_sync_d",
5063 "msiof1_ss1_d",
5064 "msiof1_rx_d",
5065 "msiof1_tx_d",
5066 "msiof1_clk_e",
5067 "msiof1_sync_e",
5068 "msiof1_rx_e",
5069 "msiof1_tx_e",
5070 };
5071
5072 static const char * const msiof2_groups[] = {
5073 "msiof2_clk",
5074 "msiof2_sync",
5075 "msiof2_ss1",
5076 "msiof2_ss2",
5077 "msiof2_rx",
5078 "msiof2_tx",
5079 "msiof2_clk_b",
5080 "msiof2_sync_b",
5081 "msiof2_ss1_b",
5082 "msiof2_ss2_b",
5083 "msiof2_rx_b",
5084 "msiof2_tx_b",
5085 "msiof2_clk_c",
5086 "msiof2_sync_c",
5087 "msiof2_rx_c",
5088 "msiof2_tx_c",
5089 "msiof2_clk_d",
5090 "msiof2_sync_d",
5091 "msiof2_ss1_d",
5092 "msiof2_ss2_d",
5093 "msiof2_rx_d",
5094 "msiof2_tx_d",
5095 "msiof2_clk_e",
5096 "msiof2_sync_e",
5097 "msiof2_rx_e",
5098 "msiof2_tx_e",
5099 };
5100
5101 static const char * const pwm0_groups[] = {
5102 "pwm0",
5103 "pwm0_b",
5104 };
5105
5106 static const char * const pwm1_groups[] = {
5107 "pwm1",
5108 "pwm1_b",
5109 };
5110
5111 static const char * const pwm2_groups[] = {
5112 "pwm2",
5113 "pwm2_b",
5114 };
5115
5116 static const char * const pwm3_groups[] = {
5117 "pwm3",
5118 };
5119
5120 static const char * const pwm4_groups[] = {
5121 "pwm4",
5122 "pwm4_b",
5123 };
5124
5125 static const char * const pwm5_groups[] = {
5126 "pwm5",
5127 "pwm5_b",
5128 };
5129
5130 static const char * const pwm6_groups[] = {
5131 "pwm6",
5132 };
5133
5134 static const char * const qspi_groups[] = {
5135 "qspi_ctrl",
5136 "qspi_data2",
5137 "qspi_data4",
5138 "qspi_ctrl_b",
5139 "qspi_data2_b",
5140 "qspi_data4_b",
5141 };
5142
5143 static const char * const scif0_groups[] = {
5144 "scif0_data",
5145 "scif0_data_b",
5146 "scif0_data_c",
5147 "scif0_data_d",
5148 "scif0_data_e",
5149 };
5150
5151 static const char * const scif1_groups[] = {
5152 "scif1_data",
5153 "scif1_data_b",
5154 "scif1_clk_b",
5155 "scif1_data_c",
5156 "scif1_data_d",
5157 };
5158
5159 static const char * const scif2_groups[] = {
5160 "scif2_data",
5161 "scif2_data_b",
5162 "scif2_clk_b",
5163 "scif2_data_c",
5164 "scif2_data_e",
5165 };
5166 static const char * const scif3_groups[] = {
5167 "scif3_data",
5168 "scif3_clk",
5169 "scif3_data_b",
5170 "scif3_clk_b",
5171 "scif3_data_c",
5172 "scif3_data_d",
5173 };
5174 static const char * const scif4_groups[] = {
5175 "scif4_data",
5176 "scif4_data_b",
5177 "scif4_data_c",
5178 };
5179 static const char * const scif5_groups[] = {
5180 "scif5_data",
5181 "scif5_data_b",
5182 };
5183 static const char * const scifa0_groups[] = {
5184 "scifa0_data",
5185 "scifa0_data_b",
5186 };
5187 static const char * const scifa1_groups[] = {
5188 "scifa1_data",
5189 "scifa1_clk",
5190 "scifa1_data_b",
5191 "scifa1_clk_b",
5192 "scifa1_data_c",
5193 };
5194 static const char * const scifa2_groups[] = {
5195 "scifa2_data",
5196 "scifa2_clk",
5197 "scifa2_data_b",
5198 };
5199 static const char * const scifa3_groups[] = {
5200 "scifa3_data",
5201 "scifa3_clk",
5202 "scifa3_data_b",
5203 "scifa3_clk_b",
5204 "scifa3_data_c",
5205 "scifa3_clk_c",
5206 };
5207 static const char * const scifa4_groups[] = {
5208 "scifa4_data",
5209 "scifa4_data_b",
5210 "scifa4_data_c",
5211 };
5212 static const char * const scifa5_groups[] = {
5213 "scifa5_data",
5214 "scifa5_data_b",
5215 "scifa5_data_c",
5216 };
5217 static const char * const scifb0_groups[] = {
5218 "scifb0_data",
5219 "scifb0_clk",
5220 "scifb0_ctrl",
5221 "scifb0_data_b",
5222 "scifb0_clk_b",
5223 "scifb0_ctrl_b",
5224 "scifb0_data_c",
5225 "scifb0_clk_c",
5226 "scifb0_data_d",
5227 "scifb0_clk_d",
5228 };
5229 static const char * const scifb1_groups[] = {
5230 "scifb1_data",
5231 "scifb1_clk",
5232 "scifb1_ctrl",
5233 "scifb1_data_b",
5234 "scifb1_clk_b",
5235 "scifb1_data_c",
5236 "scifb1_clk_c",
5237 "scifb1_data_d",
5238 };
5239 static const char * const scifb2_groups[] = {
5240 "scifb2_data",
5241 "scifb2_clk",
5242 "scifb2_ctrl",
5243 "scifb2_data_b",
5244 "scifb2_clk_b",
5245 "scifb2_ctrl_b",
5246 "scifb0_data_c",
5247 "scifb2_clk_c",
5248 "scifb2_data_d",
5249 };
5250
5251 static const char * const scif_clk_groups[] = {
5252 "scif_clk",
5253 "scif_clk_b",
5254 };
5255
5256 static const char * const sdhi0_groups[] = {
5257 "sdhi0_data1",
5258 "sdhi0_data4",
5259 "sdhi0_ctrl",
5260 "sdhi0_cd",
5261 "sdhi0_wp",
5262 };
5263
5264 static const char * const sdhi1_groups[] = {
5265 "sdhi1_data1",
5266 "sdhi1_data4",
5267 "sdhi1_ctrl",
5268 "sdhi1_cd",
5269 "sdhi1_wp",
5270 };
5271
5272 static const char * const sdhi2_groups[] = {
5273 "sdhi2_data1",
5274 "sdhi2_data4",
5275 "sdhi2_ctrl",
5276 "sdhi2_cd",
5277 "sdhi2_wp",
5278 };
5279
5280 static const char * const ssi_groups[] = {
5281 "ssi0_data",
5282 "ssi0_data_b",
5283 "ssi0129_ctrl",
5284 "ssi0129_ctrl_b",
5285 "ssi1_data",
5286 "ssi1_data_b",
5287 "ssi1_ctrl",
5288 "ssi1_ctrl_b",
5289 "ssi2_data",
5290 "ssi2_ctrl",
5291 "ssi3_data",
5292 "ssi34_ctrl",
5293 "ssi4_data",
5294 "ssi4_ctrl",
5295 "ssi5_data",
5296 "ssi5_ctrl",
5297 "ssi6_data",
5298 "ssi6_ctrl",
5299 "ssi7_data",
5300 "ssi7_data_b",
5301 "ssi78_ctrl",
5302 "ssi78_ctrl_b",
5303 "ssi8_data",
5304 "ssi8_data_b",
5305 "ssi9_data",
5306 "ssi9_data_b",
5307 "ssi9_ctrl",
5308 "ssi9_ctrl_b",
5309 };
5310
5311 static const char * const tpu_groups[] = {
5312 "tpu_to0",
5313 "tpu_to1",
5314 "tpu_to2",
5315 "tpu_to3",
5316 };
5317
5318 static const char * const usb0_groups[] = {
5319 "usb0",
5320 };
5321 static const char * const usb1_groups[] = {
5322 "usb1",
5323 };
5324
5325 static const char * const vin0_groups[] = {
5326 "vin0_data24",
5327 "vin0_data20",
5328 "vin0_data18",
5329 "vin0_data16",
5330 "vin0_data12",
5331 "vin0_data10",
5332 "vin0_data8",
5333 "vin0_sync",
5334 "vin0_field",
5335 "vin0_clkenb",
5336 "vin0_clk",
5337 };
5338
5339 static const char * const vin1_groups[] = {
5340 "vin1_data8",
5341 "vin1_sync",
5342 "vin1_field",
5343 "vin1_clkenb",
5344 "vin1_clk",
5345 "vin1_b_data24",
5346 "vin1_b_data20",
5347 "vin1_b_data18",
5348 "vin1_b_data16",
5349 "vin1_b_data12",
5350 "vin1_b_data10",
5351 "vin1_b_data8",
5352 "vin1_b_sync",
5353 "vin1_b_field",
5354 "vin1_b_clkenb",
5355 "vin1_b_clk",
5356 };
5357
5358 static const char * const vin2_groups[] = {
5359 "vin2_data8",
5360 "vin2_sync",
5361 "vin2_field",
5362 "vin2_clkenb",
5363 "vin2_clk",
5364 };
5365
5366 static const struct {
5367 struct sh_pfc_function common[58];
5368 struct sh_pfc_function r8a779x[2];
5369 } pinmux_functions = {
5370 .common = {
5371 SH_PFC_FUNCTION(audio_clk),
5372 SH_PFC_FUNCTION(avb),
5373 SH_PFC_FUNCTION(can0),
5374 SH_PFC_FUNCTION(can1),
5375 SH_PFC_FUNCTION(can_clk),
5376 SH_PFC_FUNCTION(du),
5377 SH_PFC_FUNCTION(du0),
5378 SH_PFC_FUNCTION(du1),
5379 SH_PFC_FUNCTION(eth),
5380 SH_PFC_FUNCTION(hscif0),
5381 SH_PFC_FUNCTION(hscif1),
5382 SH_PFC_FUNCTION(hscif2),
5383 SH_PFC_FUNCTION(i2c0),
5384 SH_PFC_FUNCTION(i2c1),
5385 SH_PFC_FUNCTION(i2c2),
5386 SH_PFC_FUNCTION(i2c3),
5387 SH_PFC_FUNCTION(i2c4),
5388 SH_PFC_FUNCTION(i2c7),
5389 SH_PFC_FUNCTION(i2c8),
5390 SH_PFC_FUNCTION(intc),
5391 SH_PFC_FUNCTION(mmc),
5392 SH_PFC_FUNCTION(msiof0),
5393 SH_PFC_FUNCTION(msiof1),
5394 SH_PFC_FUNCTION(msiof2),
5395 SH_PFC_FUNCTION(pwm0),
5396 SH_PFC_FUNCTION(pwm1),
5397 SH_PFC_FUNCTION(pwm2),
5398 SH_PFC_FUNCTION(pwm3),
5399 SH_PFC_FUNCTION(pwm4),
5400 SH_PFC_FUNCTION(pwm5),
5401 SH_PFC_FUNCTION(pwm6),
5402 SH_PFC_FUNCTION(qspi),
5403 SH_PFC_FUNCTION(scif0),
5404 SH_PFC_FUNCTION(scif1),
5405 SH_PFC_FUNCTION(scif2),
5406 SH_PFC_FUNCTION(scif3),
5407 SH_PFC_FUNCTION(scif4),
5408 SH_PFC_FUNCTION(scif5),
5409 SH_PFC_FUNCTION(scifa0),
5410 SH_PFC_FUNCTION(scifa1),
5411 SH_PFC_FUNCTION(scifa2),
5412 SH_PFC_FUNCTION(scifa3),
5413 SH_PFC_FUNCTION(scifa4),
5414 SH_PFC_FUNCTION(scifa5),
5415 SH_PFC_FUNCTION(scifb0),
5416 SH_PFC_FUNCTION(scifb1),
5417 SH_PFC_FUNCTION(scifb2),
5418 SH_PFC_FUNCTION(scif_clk),
5419 SH_PFC_FUNCTION(sdhi0),
5420 SH_PFC_FUNCTION(sdhi1),
5421 SH_PFC_FUNCTION(sdhi2),
5422 SH_PFC_FUNCTION(ssi),
5423 SH_PFC_FUNCTION(tpu),
5424 SH_PFC_FUNCTION(usb0),
5425 SH_PFC_FUNCTION(usb1),
5426 SH_PFC_FUNCTION(vin0),
5427 SH_PFC_FUNCTION(vin1),
5428 SH_PFC_FUNCTION(vin2),
5429 },
5430 .r8a779x = {
5431 SH_PFC_FUNCTION(adi),
5432 SH_PFC_FUNCTION(mlb),
5433 }
5434 };
5435
5436 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5437 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
5438 GP_0_31_FN, FN_IP1_22_20,
5439 GP_0_30_FN, FN_IP1_19_17,
5440 GP_0_29_FN, FN_IP1_16_14,
5441 GP_0_28_FN, FN_IP1_13_11,
5442 GP_0_27_FN, FN_IP1_10_8,
5443 GP_0_26_FN, FN_IP1_7_6,
5444 GP_0_25_FN, FN_IP1_5_4,
5445 GP_0_24_FN, FN_IP1_3_2,
5446 GP_0_23_FN, FN_IP1_1_0,
5447 GP_0_22_FN, FN_IP0_30_29,
5448 GP_0_21_FN, FN_IP0_28_27,
5449 GP_0_20_FN, FN_IP0_26_25,
5450 GP_0_19_FN, FN_IP0_24_23,
5451 GP_0_18_FN, FN_IP0_22_21,
5452 GP_0_17_FN, FN_IP0_20_19,
5453 GP_0_16_FN, FN_IP0_18_16,
5454 GP_0_15_FN, FN_IP0_15,
5455 GP_0_14_FN, FN_IP0_14,
5456 GP_0_13_FN, FN_IP0_13,
5457 GP_0_12_FN, FN_IP0_12,
5458 GP_0_11_FN, FN_IP0_11,
5459 GP_0_10_FN, FN_IP0_10,
5460 GP_0_9_FN, FN_IP0_9,
5461 GP_0_8_FN, FN_IP0_8,
5462 GP_0_7_FN, FN_IP0_7,
5463 GP_0_6_FN, FN_IP0_6,
5464 GP_0_5_FN, FN_IP0_5,
5465 GP_0_4_FN, FN_IP0_4,
5466 GP_0_3_FN, FN_IP0_3,
5467 GP_0_2_FN, FN_IP0_2,
5468 GP_0_1_FN, FN_IP0_1,
5469 GP_0_0_FN, FN_IP0_0, }
5470 },
5471 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
5472 0, 0,
5473 0, 0,
5474 0, 0,
5475 0, 0,
5476 0, 0,
5477 0, 0,
5478 GP_1_25_FN, FN_IP3_21_20,
5479 GP_1_24_FN, FN_IP3_19_18,
5480 GP_1_23_FN, FN_IP3_17_16,
5481 GP_1_22_FN, FN_IP3_15_14,
5482 GP_1_21_FN, FN_IP3_13_12,
5483 GP_1_20_FN, FN_IP3_11_9,
5484 GP_1_19_FN, FN_RD_N,
5485 GP_1_18_FN, FN_IP3_8_6,
5486 GP_1_17_FN, FN_IP3_5_3,
5487 GP_1_16_FN, FN_IP3_2_0,
5488 GP_1_15_FN, FN_IP2_29_27,
5489 GP_1_14_FN, FN_IP2_26_25,
5490 GP_1_13_FN, FN_IP2_24_23,
5491 GP_1_12_FN, FN_EX_CS0_N,
5492 GP_1_11_FN, FN_IP2_22_21,
5493 GP_1_10_FN, FN_IP2_20_19,
5494 GP_1_9_FN, FN_IP2_18_16,
5495 GP_1_8_FN, FN_IP2_15_13,
5496 GP_1_7_FN, FN_IP2_12_10,
5497 GP_1_6_FN, FN_IP2_9_7,
5498 GP_1_5_FN, FN_IP2_6_5,
5499 GP_1_4_FN, FN_IP2_4_3,
5500 GP_1_3_FN, FN_IP2_2_0,
5501 GP_1_2_FN, FN_IP1_31_29,
5502 GP_1_1_FN, FN_IP1_28_26,
5503 GP_1_0_FN, FN_IP1_25_23, }
5504 },
5505 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
5506 GP_2_31_FN, FN_IP6_7_6,
5507 GP_2_30_FN, FN_IP6_5_3,
5508 GP_2_29_FN, FN_IP6_2_0,
5509 GP_2_28_FN, FN_AUDIO_CLKA,
5510 GP_2_27_FN, FN_IP5_31_29,
5511 GP_2_26_FN, FN_IP5_28_26,
5512 GP_2_25_FN, FN_IP5_25_24,
5513 GP_2_24_FN, FN_IP5_23_22,
5514 GP_2_23_FN, FN_IP5_21_20,
5515 GP_2_22_FN, FN_IP5_19_17,
5516 GP_2_21_FN, FN_IP5_16_15,
5517 GP_2_20_FN, FN_IP5_14_12,
5518 GP_2_19_FN, FN_IP5_11_9,
5519 GP_2_18_FN, FN_IP5_8_6,
5520 GP_2_17_FN, FN_IP5_5_3,
5521 GP_2_16_FN, FN_IP5_2_0,
5522 GP_2_15_FN, FN_IP4_30_28,
5523 GP_2_14_FN, FN_IP4_27_26,
5524 GP_2_13_FN, FN_IP4_25_24,
5525 GP_2_12_FN, FN_IP4_23_22,
5526 GP_2_11_FN, FN_IP4_21,
5527 GP_2_10_FN, FN_IP4_20,
5528 GP_2_9_FN, FN_IP4_19,
5529 GP_2_8_FN, FN_IP4_18_16,
5530 GP_2_7_FN, FN_IP4_15_13,
5531 GP_2_6_FN, FN_IP4_12_10,
5532 GP_2_5_FN, FN_IP4_9_8,
5533 GP_2_4_FN, FN_IP4_7_5,
5534 GP_2_3_FN, FN_IP4_4_2,
5535 GP_2_2_FN, FN_IP4_1_0,
5536 GP_2_1_FN, FN_IP3_30_28,
5537 GP_2_0_FN, FN_IP3_27_25 }
5538 },
5539 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
5540 GP_3_31_FN, FN_IP9_18_17,
5541 GP_3_30_FN, FN_IP9_16,
5542 GP_3_29_FN, FN_IP9_15_13,
5543 GP_3_28_FN, FN_IP9_12,
5544 GP_3_27_FN, FN_IP9_11,
5545 GP_3_26_FN, FN_IP9_10_8,
5546 GP_3_25_FN, FN_IP9_7,
5547 GP_3_24_FN, FN_IP9_6,
5548 GP_3_23_FN, FN_IP9_5_3,
5549 GP_3_22_FN, FN_IP9_2_0,
5550 GP_3_21_FN, FN_IP8_30_28,
5551 GP_3_20_FN, FN_IP8_27_26,
5552 GP_3_19_FN, FN_IP8_25_24,
5553 GP_3_18_FN, FN_IP8_23_21,
5554 GP_3_17_FN, FN_IP8_20_18,
5555 GP_3_16_FN, FN_IP8_17_15,
5556 GP_3_15_FN, FN_IP8_14_12,
5557 GP_3_14_FN, FN_IP8_11_9,
5558 GP_3_13_FN, FN_IP8_8_6,
5559 GP_3_12_FN, FN_IP8_5_3,
5560 GP_3_11_FN, FN_IP8_2_0,
5561 GP_3_10_FN, FN_IP7_29_27,
5562 GP_3_9_FN, FN_IP7_26_24,
5563 GP_3_8_FN, FN_IP7_23_21,
5564 GP_3_7_FN, FN_IP7_20_19,
5565 GP_3_6_FN, FN_IP7_18_17,
5566 GP_3_5_FN, FN_IP7_16_15,
5567 GP_3_4_FN, FN_IP7_14_13,
5568 GP_3_3_FN, FN_IP7_12_11,
5569 GP_3_2_FN, FN_IP7_10_9,
5570 GP_3_1_FN, FN_IP7_8_6,
5571 GP_3_0_FN, FN_IP7_5_3 }
5572 },
5573 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
5574 GP_4_31_FN, FN_IP15_5_4,
5575 GP_4_30_FN, FN_IP15_3_2,
5576 GP_4_29_FN, FN_IP15_1_0,
5577 GP_4_28_FN, FN_IP11_8_6,
5578 GP_4_27_FN, FN_IP11_5_3,
5579 GP_4_26_FN, FN_IP11_2_0,
5580 GP_4_25_FN, FN_IP10_31_29,
5581 GP_4_24_FN, FN_IP10_28_27,
5582 GP_4_23_FN, FN_IP10_26_25,
5583 GP_4_22_FN, FN_IP10_24_22,
5584 GP_4_21_FN, FN_IP10_21_19,
5585 GP_4_20_FN, FN_IP10_18_17,
5586 GP_4_19_FN, FN_IP10_16_15,
5587 GP_4_18_FN, FN_IP10_14_12,
5588 GP_4_17_FN, FN_IP10_11_9,
5589 GP_4_16_FN, FN_IP10_8_6,
5590 GP_4_15_FN, FN_IP10_5_3,
5591 GP_4_14_FN, FN_IP10_2_0,
5592 GP_4_13_FN, FN_IP9_31_29,
5593 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
5594 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
5595 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
5596 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
5597 GP_4_8_FN, FN_IP9_28_27,
5598 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
5599 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
5600 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
5601 GP_4_4_FN, FN_IP9_26_25,
5602 GP_4_3_FN, FN_IP9_24_23,
5603 GP_4_2_FN, FN_IP9_22_21,
5604 GP_4_1_FN, FN_IP9_20_19,
5605 GP_4_0_FN, FN_VI0_CLK }
5606 },
5607 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
5608 GP_5_31_FN, FN_IP3_24_22,
5609 GP_5_30_FN, FN_IP13_9_7,
5610 GP_5_29_FN, FN_IP13_6_5,
5611 GP_5_28_FN, FN_IP13_4_3,
5612 GP_5_27_FN, FN_IP13_2_0,
5613 GP_5_26_FN, FN_IP12_29_27,
5614 GP_5_25_FN, FN_IP12_26_24,
5615 GP_5_24_FN, FN_IP12_23_22,
5616 GP_5_23_FN, FN_IP12_21_20,
5617 GP_5_22_FN, FN_IP12_19_18,
5618 GP_5_21_FN, FN_IP12_17_16,
5619 GP_5_20_FN, FN_IP12_15_13,
5620 GP_5_19_FN, FN_IP12_12_10,
5621 GP_5_18_FN, FN_IP12_9_7,
5622 GP_5_17_FN, FN_IP12_6_4,
5623 GP_5_16_FN, FN_IP12_3_2,
5624 GP_5_15_FN, FN_IP12_1_0,
5625 GP_5_14_FN, FN_IP11_31_30,
5626 GP_5_13_FN, FN_IP11_29_28,
5627 GP_5_12_FN, FN_IP11_27,
5628 GP_5_11_FN, FN_IP11_26,
5629 GP_5_10_FN, FN_IP11_25,
5630 GP_5_9_FN, FN_IP11_24,
5631 GP_5_8_FN, FN_IP11_23,
5632 GP_5_7_FN, FN_IP11_22,
5633 GP_5_6_FN, FN_IP11_21,
5634 GP_5_5_FN, FN_IP11_20,
5635 GP_5_4_FN, FN_IP11_19,
5636 GP_5_3_FN, FN_IP11_18_17,
5637 GP_5_2_FN, FN_IP11_16_15,
5638 GP_5_1_FN, FN_IP11_14_12,
5639 GP_5_0_FN, FN_IP11_11_9 }
5640 },
5641 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
5642 GP_6_31_FN, FN_DU0_DOTCLKIN,
5643 GP_6_30_FN, FN_USB1_OVC,
5644 GP_6_29_FN, FN_IP14_31_29,
5645 GP_6_28_FN, FN_IP14_28_26,
5646 GP_6_27_FN, FN_IP14_25_23,
5647 GP_6_26_FN, FN_IP14_22_20,
5648 GP_6_25_FN, FN_IP14_19_17,
5649 GP_6_24_FN, FN_IP14_16_14,
5650 GP_6_23_FN, FN_IP14_13_11,
5651 GP_6_22_FN, FN_IP14_10_8,
5652 GP_6_21_FN, FN_IP14_7,
5653 GP_6_20_FN, FN_IP14_6,
5654 GP_6_19_FN, FN_IP14_5,
5655 GP_6_18_FN, FN_IP14_4,
5656 GP_6_17_FN, FN_IP14_3,
5657 GP_6_16_FN, FN_IP14_2,
5658 GP_6_15_FN, FN_IP14_1_0,
5659 GP_6_14_FN, FN_IP13_30_28,
5660 GP_6_13_FN, FN_IP13_27,
5661 GP_6_12_FN, FN_IP13_26,
5662 GP_6_11_FN, FN_IP13_25,
5663 GP_6_10_FN, FN_IP13_24_23,
5664 GP_6_9_FN, FN_IP13_22,
5665 GP_6_8_FN, FN_SD1_CLK,
5666 GP_6_7_FN, FN_IP13_21_19,
5667 GP_6_6_FN, FN_IP13_18_16,
5668 GP_6_5_FN, FN_IP13_15,
5669 GP_6_4_FN, FN_IP13_14,
5670 GP_6_3_FN, FN_IP13_13,
5671 GP_6_2_FN, FN_IP13_12,
5672 GP_6_1_FN, FN_IP13_11,
5673 GP_6_0_FN, FN_IP13_10 }
5674 },
5675 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
5676 0, 0,
5677 0, 0,
5678 0, 0,
5679 0, 0,
5680 0, 0,
5681 0, 0,
5682 GP_7_25_FN, FN_USB1_PWEN,
5683 GP_7_24_FN, FN_USB0_OVC,
5684 GP_7_23_FN, FN_USB0_PWEN,
5685 GP_7_22_FN, FN_IP15_14_12,
5686 GP_7_21_FN, FN_IP15_11_9,
5687 GP_7_20_FN, FN_IP15_8_6,
5688 GP_7_19_FN, FN_IP7_2_0,
5689 GP_7_18_FN, FN_IP6_29_27,
5690 GP_7_17_FN, FN_IP6_26_24,
5691 GP_7_16_FN, FN_IP6_23_21,
5692 GP_7_15_FN, FN_IP6_20_19,
5693 GP_7_14_FN, FN_IP6_18_16,
5694 GP_7_13_FN, FN_IP6_15_14,
5695 GP_7_12_FN, FN_IP6_13_12,
5696 GP_7_11_FN, FN_IP6_11_10,
5697 GP_7_10_FN, FN_IP6_9_8,
5698 GP_7_9_FN, FN_IP16_11_10,
5699 GP_7_8_FN, FN_IP16_9_8,
5700 GP_7_7_FN, FN_IP16_7_6,
5701 GP_7_6_FN, FN_IP16_5_3,
5702 GP_7_5_FN, FN_IP16_2_0,
5703 GP_7_4_FN, FN_IP15_29_27,
5704 GP_7_3_FN, FN_IP15_26_24,
5705 GP_7_2_FN, FN_IP15_23_21,
5706 GP_7_1_FN, FN_IP15_20_18,
5707 GP_7_0_FN, FN_IP15_17_15 }
5708 },
5709 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5710 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
5711 1, 1, 1, 1, 1, 1, 1, 1) {
5712 /* IP0_31 [1] */
5713 0, 0,
5714 /* IP0_30_29 [2] */
5715 FN_A6, FN_MSIOF1_SCK,
5716 0, 0,
5717 /* IP0_28_27 [2] */
5718 FN_A5, FN_MSIOF0_RXD_B,
5719 0, 0,
5720 /* IP0_26_25 [2] */
5721 FN_A4, FN_MSIOF0_TXD_B,
5722 0, 0,
5723 /* IP0_24_23 [2] */
5724 FN_A3, FN_MSIOF0_SS2_B,
5725 0, 0,
5726 /* IP0_22_21 [2] */
5727 FN_A2, FN_MSIOF0_SS1_B,
5728 0, 0,
5729 /* IP0_20_19 [2] */
5730 FN_A1, FN_MSIOF0_SYNC_B,
5731 0, 0,
5732 /* IP0_18_16 [3] */
5733 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
5734 0, 0, 0,
5735 /* IP0_15 [1] */
5736 FN_D15, 0,
5737 /* IP0_14 [1] */
5738 FN_D14, 0,
5739 /* IP0_13 [1] */
5740 FN_D13, 0,
5741 /* IP0_12 [1] */
5742 FN_D12, 0,
5743 /* IP0_11 [1] */
5744 FN_D11, 0,
5745 /* IP0_10 [1] */
5746 FN_D10, 0,
5747 /* IP0_9 [1] */
5748 FN_D9, 0,
5749 /* IP0_8 [1] */
5750 FN_D8, 0,
5751 /* IP0_7 [1] */
5752 FN_D7, 0,
5753 /* IP0_6 [1] */
5754 FN_D6, 0,
5755 /* IP0_5 [1] */
5756 FN_D5, 0,
5757 /* IP0_4 [1] */
5758 FN_D4, 0,
5759 /* IP0_3 [1] */
5760 FN_D3, 0,
5761 /* IP0_2 [1] */
5762 FN_D2, 0,
5763 /* IP0_1 [1] */
5764 FN_D1, 0,
5765 /* IP0_0 [1] */
5766 FN_D0, 0, }
5767 },
5768 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5769 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5770 /* IP1_31_29 [3] */
5771 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5772 0, 0, 0,
5773 /* IP1_28_26 [3] */
5774 FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
5775 0, 0, 0, 0,
5776 /* IP1_25_23 [3] */
5777 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5778 0, 0, 0,
5779 /* IP1_22_20 [3] */
5780 FN_A15, FN_BPFCLK_C,
5781 0, 0, 0, 0, 0, 0,
5782 /* IP1_19_17 [3] */
5783 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
5784 0, 0, 0,
5785 /* IP1_16_14 [3] */
5786 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
5787 0, 0, 0, 0,
5788 /* IP1_13_11 [3] */
5789 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
5790 0, 0, 0, 0,
5791 /* IP1_10_8 [3] */
5792 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
5793 0, 0, 0, 0,
5794 /* IP1_7_6 [2] */
5795 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5796 /* IP1_5_4 [2] */
5797 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
5798 /* IP1_3_2 [2] */
5799 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
5800 /* IP1_1_0 [2] */
5801 FN_A7, FN_MSIOF1_SYNC,
5802 0, 0, }
5803 },
5804 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5805 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
5806 /* IP2_31_30 [2] */
5807 0, 0, 0, 0,
5808 /* IP2_29_27 [3] */
5809 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
5810 FN_ATAG0_N, 0, FN_EX_WAIT1,
5811 0, 0,
5812 /* IP2_26_25 [2] */
5813 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5814 /* IP2_24_23 [2] */
5815 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5816 /* IP2_22_21 [2] */
5817 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
5818 /* IP2_20_19 [2] */
5819 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
5820 /* IP2_18_16 [3] */
5821 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
5822 0, 0,
5823 /* IP2_15_13 [3] */
5824 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
5825 0, 0, 0,
5826 /* IP2_12_10 [3] */
5827 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
5828 0, 0, 0,
5829 /* IP2_9_7 [3] */
5830 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
5831 0, 0, 0,
5832 /* IP2_6_5 [2] */
5833 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5834 /* IP2_4_3 [2] */
5835 FN_A20, FN_SPCLK, 0, 0,
5836 /* IP2_2_0 [3] */
5837 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5838 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
5839 },
5840 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5841 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
5842 /* IP3_31 [1] */
5843 0, 0,
5844 /* IP3_30_28 [3] */
5845 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
5846 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5847 0, 0, 0,
5848 /* IP3_27_25 [3] */
5849 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5850 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5851 0, 0, 0,
5852 /* IP3_24_22 [3] */
5853 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5854 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5855 /* IP3_21_20 [2] */
5856 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5857 /* IP3_19_18 [2] */
5858 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5859 /* IP3_17_16 [2] */
5860 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5861 /* IP3_15_14 [2] */
5862 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5863 /* IP3_13_12 [2] */
5864 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5865 /* IP3_11_9 [3] */
5866 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5867 0, 0, 0,
5868 /* IP3_8_6 [3] */
5869 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5870 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5871 /* IP3_5_3 [3] */
5872 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5873 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5874 /* IP3_2_0 [3] */
5875 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5876 0, 0, 0, }
5877 },
5878 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5879 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
5880 /* IP4_31 [1] */
5881 0, 0,
5882 /* IP4_30_28 [3] */
5883 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5884 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5885 0, 0,
5886 /* IP4_27_26 [2] */
5887 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5888 /* IP4_25_24 [2] */
5889 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5890 /* IP4_23_22 [2] */
5891 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5892 /* IP4_21 [1] */
5893 FN_SSI_SDATA3, 0,
5894 /* IP4_20 [1] */
5895 FN_SSI_WS34, 0,
5896 /* IP4_19 [1] */
5897 FN_SSI_SCK34, 0,
5898 /* IP4_18_16 [3] */
5899 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5900 0, 0, 0, 0,
5901 /* IP4_15_13 [3] */
5902 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
5903 FN_GLO_Q1_D, FN_HCTS1_N_E,
5904 0, 0,
5905 /* IP4_12_10 [3] */
5906 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5907 0, 0, 0,
5908 /* IP4_9_8 [2] */
5909 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
5910 /* IP4_7_5 [3] */
5911 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
5912 FN_GLO_I1_D, 0, 0, 0,
5913 /* IP4_4_2 [3] */
5914 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B,
5915 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5916 0, 0, 0,
5917 /* IP4_1_0 [2] */
5918 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, }
5919 },
5920 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5921 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
5922 /* IP5_31_29 [3] */
5923 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5924 0, 0, 0, 0, 0,
5925 /* IP5_28_26 [3] */
5926 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5927 0, 0, 0, 0,
5928 /* IP5_25_24 [2] */
5929 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5930 /* IP5_23_22 [2] */
5931 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5932 /* IP5_21_20 [2] */
5933 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5934 /* IP5_19_17 [3] */
5935 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5936 0, 0, 0, 0,
5937 /* IP5_16_15 [2] */
5938 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5939 /* IP5_14_12 [3] */
5940 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5941 0, 0, 0, 0,
5942 /* IP5_11_9 [3] */
5943 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
5944 0, 0, 0, 0,
5945 /* IP5_8_6 [3] */
5946 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
5947 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
5948 0, 0,
5949 /* IP5_5_3 [3] */
5950 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
5951 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
5952 0, 0,
5953 /* IP5_2_0 [3] */
5954 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5955 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5956 0, 0, }
5957 },
5958 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5959 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
5960 /* IP6_31_30 [2] */
5961 0, 0, 0, 0,
5962 /* IP6_29_27 [3] */
5963 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
5964 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
5965 0, 0, 0,
5966 /* IP6_26_24 [3] */
5967 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
5968 FN_GPS_CLK_C, FN_GPS_CLK_D,
5969 0, 0, 0,
5970 /* IP6_23_21 [3] */
5971 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
5972 FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
5973 0, 0, 0,
5974 /* IP6_20_19 [2] */
5975 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
5976 /* IP6_18_16 [3] */
5977 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
5978 FN_INTC_IRQ4_N, 0, 0, 0,
5979 /* IP6_15_14 [2] */
5980 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
5981 /* IP6_13_12 [2] */
5982 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
5983 /* IP6_11_10 [2] */
5984 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
5985 /* IP6_9_8 [2] */
5986 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
5987 /* IP6_7_6 [2] */
5988 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
5989 /* IP6_5_3 [3] */
5990 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
5991 FN_SCIFA2_RXD, FN_FMIN_E,
5992 0, 0,
5993 /* IP6_2_0 [3] */
5994 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
5995 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
5996 0, 0, }
5997 },
5998 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5999 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
6000 /* IP7_31_30 [2] */
6001 0, 0, 0, 0,
6002 /* IP7_29_27 [3] */
6003 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
6004 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
6005 0, 0,
6006 /* IP7_26_24 [3] */
6007 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
6008 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
6009 0, 0,
6010 /* IP7_23_21 [3] */
6011 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
6012 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
6013 0, 0,
6014 /* IP7_20_19 [2] */
6015 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
6016 /* IP7_18_17 [2] */
6017 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
6018 /* IP7_16_15 [2] */
6019 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
6020 /* IP7_14_13 [2] */
6021 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
6022 /* IP7_12_11 [2] */
6023 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
6024 /* IP7_10_9 [2] */
6025 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
6026 /* IP7_8_6 [3] */
6027 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
6028 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
6029 0, 0,
6030 /* IP7_5_3 [3] */
6031 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
6032 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
6033 0, 0,
6034 /* IP7_2_0 [3] */
6035 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
6036 FN_SCIF_CLK_B, FN_GPS_MAG_D,
6037 0, 0, }
6038 },
6039 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6040 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
6041 /* IP8_31 [1] */
6042 0, 0,
6043 /* IP8_30_28 [3] */
6044 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
6045 0, 0, 0,
6046 /* IP8_27_26 [2] */
6047 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
6048 /* IP8_25_24 [2] */
6049 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
6050 /* IP8_23_21 [3] */
6051 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
6052 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
6053 0, 0,
6054 /* IP8_20_18 [3] */
6055 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
6056 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
6057 0, 0,
6058 /* IP8_17_15 [3] */
6059 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
6060 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
6061 0, 0,
6062 /* IP8_14_12 [3] */
6063 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
6064 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
6065 0, 0, 0,
6066 /* IP8_11_9 [3] */
6067 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
6068 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
6069 0, 0, 0,
6070 /* IP8_8_6 [3] */
6071 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
6072 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
6073 0, 0,
6074 /* IP8_5_3 [3] */
6075 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
6076 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
6077 0, 0,
6078 /* IP8_2_0 [3] */
6079 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
6080 0, 0, 0, }
6081 },
6082 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
6083 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
6084 /* IP9_31_29 [3] */
6085 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
6086 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
6087 /* IP9_28_27 [2] */
6088 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
6089 /* IP9_26_25 [2] */
6090 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
6091 /* IP9_24_23 [2] */
6092 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
6093 /* IP9_22_21 [2] */
6094 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
6095 /* IP9_20_19 [2] */
6096 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
6097 /* IP9_18_17 [2] */
6098 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
6099 /* IP9_16 [1] */
6100 FN_DU1_DISP, FN_QPOLA,
6101 /* IP9_15_13 [3] */
6102 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
6103 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
6104 0, 0, 0,
6105 /* IP9_12 [1] */
6106 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
6107 /* IP9_11 [1] */
6108 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
6109 /* IP9_10_8 [3] */
6110 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
6111 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
6112 0, 0,
6113 /* IP9_7 [1] */
6114 FN_DU1_DOTCLKOUT0, FN_QCLK,
6115 /* IP9_6 [1] */
6116 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
6117 /* IP9_5_3 [3] */
6118 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C,
6119 FN_SCIF3_SCK, FN_SCIFA3_SCK,
6120 0, 0, 0,
6121 /* IP9_2_0 [3] */
6122 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
6123 0, 0, 0, }
6124 },
6125 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
6126 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
6127 /* IP10_31_29 [3] */
6128 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
6129 0, 0, 0,
6130 /* IP10_28_27 [2] */
6131 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
6132 /* IP10_26_25 [2] */
6133 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
6134 /* IP10_24_22 [3] */
6135 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
6136 0, 0, 0,
6137 /* IP10_21_19 [3] */
6138 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
6139 FN_TS_SDATA0_C, FN_ATACS11_N,
6140 0, 0, 0,
6141 /* IP10_18_17 [2] */
6142 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
6143 /* IP10_16_15 [2] */
6144 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
6145 /* IP10_14_12 [3] */
6146 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
6147 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
6148 /* IP10_11_9 [3] */
6149 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
6150 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
6151 0, 0,
6152 /* IP10_8_6 [3] */
6153 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
6154 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
6155 /* IP10_5_3 [3] */
6156 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
6157 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
6158 /* IP10_2_0 [3] */
6159 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
6160 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
6161 },
6162 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
6163 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
6164 3, 3, 3, 3, 3) {
6165 /* IP11_31_30 [2] */
6166 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
6167 /* IP11_29_28 [2] */
6168 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
6169 /* IP11_27 [1] */
6170 FN_VI1_DATA7, FN_AVB_MDC,
6171 /* IP11_26 [1] */
6172 FN_VI1_DATA6, FN_AVB_MAGIC,
6173 /* IP11_25 [1] */
6174 FN_VI1_DATA5, FN_AVB_RX_DV,
6175 /* IP11_24 [1] */
6176 FN_VI1_DATA4, FN_AVB_MDIO,
6177 /* IP11_23 [1] */
6178 FN_VI1_DATA3, FN_AVB_RX_ER,
6179 /* IP11_22 [1] */
6180 FN_VI1_DATA2, FN_AVB_RXD7,
6181 /* IP11_21 [1] */
6182 FN_VI1_DATA1, FN_AVB_RXD6,
6183 /* IP11_20 [1] */
6184 FN_VI1_DATA0, FN_AVB_RXD5,
6185 /* IP11_19 [1] */
6186 FN_VI1_CLK, FN_AVB_RXD4,
6187 /* IP11_18_17 [2] */
6188 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
6189 /* IP11_16_15 [2] */
6190 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
6191 /* IP11_14_12 [3] */
6192 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
6193 FN_RX4_B, FN_SCIFA4_RXD_B,
6194 0, 0, 0,
6195 /* IP11_11_9 [3] */
6196 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
6197 FN_TX4_B, FN_SCIFA4_TXD_B,
6198 0, 0, 0,
6199 /* IP11_8_6 [3] */
6200 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
6201 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6202 /* IP11_5_3 [3] */
6203 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
6204 0, 0, 0,
6205 /* IP11_2_0 [3] */
6206 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
6207 FN_I2C1_SDA_D, 0, 0, 0, }
6208 },
6209 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6210 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
6211 /* IP12_31_30 [2] */
6212 0, 0, 0, 0,
6213 /* IP12_29_27 [3] */
6214 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
6215 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
6216 0, 0, 0,
6217 /* IP12_26_24 [3] */
6218 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
6219 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
6220 0, 0, 0,
6221 /* IP12_23_22 [2] */
6222 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6223 /* IP12_21_20 [2] */
6224 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6225 /* IP12_19_18 [2] */
6226 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6227 /* IP12_17_16 [2] */
6228 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
6229 /* IP12_15_13 [3] */
6230 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
6231 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
6232 0, 0, 0,
6233 /* IP12_12_10 [3] */
6234 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
6235 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
6236 0, 0, 0,
6237 /* IP12_9_7 [3] */
6238 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
6239 FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
6240 0, 0, 0,
6241 /* IP12_6_4 [3] */
6242 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
6243 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
6244 0, 0, 0,
6245 /* IP12_3_2 [2] */
6246 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
6247 /* IP12_1_0 [2] */
6248 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, }
6249 },
6250 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6251 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
6252 3, 2, 2, 3) {
6253 /* IP13_31 [1] */
6254 0, 0,
6255 /* IP13_30_28 [3] */
6256 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
6257 0, 0, 0, 0,
6258 /* IP13_27 [1] */
6259 FN_SD1_DATA3, FN_IERX_B,
6260 /* IP13_26 [1] */
6261 FN_SD1_DATA2, FN_IECLK_B,
6262 /* IP13_25 [1] */
6263 FN_SD1_DATA1, FN_IETX_B,
6264 /* IP13_24_23 [2] */
6265 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6266 /* IP13_22 [1] */
6267 FN_SD1_CMD, FN_REMOCON_B,
6268 /* IP13_21_19 [3] */
6269 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
6270 FN_SCIFA5_RXD_B, FN_RX3_C,
6271 0, 0,
6272 /* IP13_18_16 [3] */
6273 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
6274 FN_SCIFA5_TXD_B, FN_TX3_C,
6275 0, 0,
6276 /* IP13_15 [1] */
6277 FN_SD0_DATA3, FN_SSL_B,
6278 /* IP13_14 [1] */
6279 FN_SD0_DATA2, FN_IO3_B,
6280 /* IP13_13 [1] */
6281 FN_SD0_DATA1, FN_IO2_B,
6282 /* IP13_12 [1] */
6283 FN_SD0_DATA0, FN_MISO_IO1_B,
6284 /* IP13_11 [1] */
6285 FN_SD0_CMD, FN_MOSI_IO0_B,
6286 /* IP13_10 [1] */
6287 FN_SD0_CLK, FN_SPCLK_B,
6288 /* IP13_9_7 [3] */
6289 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
6290 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
6291 0, 0, 0,
6292 /* IP13_6_5 [2] */
6293 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
6294 /* IP13_4_3 [2] */
6295 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
6296 /* IP13_2_0 [3] */
6297 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6298 FN_ADICLK_B, FN_MSIOF0_SS1_C,
6299 0, 0, 0, }
6300 },
6301 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6302 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
6303 /* IP14_31_29 [3] */
6304 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6305 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
6306 /* IP14_28_26 [3] */
6307 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
6308 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
6309 /* IP14_25_23 [3] */
6310 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6311 0, 0, 0,
6312 /* IP14_22_20 [3] */
6313 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6314 0, 0, 0,
6315 /* IP14_19_17 [3] */
6316 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6317 FN_VI1_CLKENB_C, FN_VI1_G1_B,
6318 0, 0,
6319 /* IP14_16_14 [3] */
6320 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6321 FN_VI1_CLK_C, FN_VI1_G0_B,
6322 0, 0,
6323 /* IP14_13_11 [3] */
6324 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
6325 0, 0, 0,
6326 /* IP14_10_8 [3] */
6327 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
6328 0, 0, 0,
6329 /* IP14_7 [1] */
6330 FN_SD2_DATA3, FN_MMC_D3,
6331 /* IP14_6 [1] */
6332 FN_SD2_DATA2, FN_MMC_D2,
6333 /* IP14_5 [1] */
6334 FN_SD2_DATA1, FN_MMC_D1,
6335 /* IP14_4 [1] */
6336 FN_SD2_DATA0, FN_MMC_D0,
6337 /* IP14_3 [1] */
6338 FN_SD2_CMD, FN_MMC_CMD,
6339 /* IP14_2 [1] */
6340 FN_SD2_CLK, FN_MMC_CLK,
6341 /* IP14_1_0 [2] */
6342 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, }
6343 },
6344 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6345 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
6346 /* IP15_31_30 [2] */
6347 0, 0, 0, 0,
6348 /* IP15_29_27 [3] */
6349 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6350 FN_CAN0_TX_B, FN_VI1_DATA5_C,
6351 0, 0,
6352 /* IP15_26_24 [3] */
6353 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6354 FN_CAN0_RX_B, FN_VI1_DATA4_C,
6355 0, 0,
6356 /* IP15_23_21 [3] */
6357 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6358 FN_TCLK2, FN_VI1_DATA3_C, 0,
6359 /* IP15_20_18 [3] */
6360 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6361 0, 0, 0,
6362 /* IP15_17_15 [3] */
6363 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6364 FN_TCLK1, FN_VI1_DATA1_C,
6365 0, 0,
6366 /* IP15_14_12 [3] */
6367 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
6368 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
6369 0, 0,
6370 /* IP15_11_9 [3] */
6371 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
6372 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
6373 0, 0,
6374 /* IP15_8_6 [3] */
6375 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
6376 FN_PWM5_B, FN_SCIFA3_TXD_C,
6377 0, 0, 0,
6378 /* IP15_5_4 [2] */
6379 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6380 /* IP15_3_2 [2] */
6381 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6382 /* IP15_1_0 [2] */
6383 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
6384 },
6385 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6386 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
6387 /* IP16_31_28 [4] */
6388 0, 0, 0, 0, 0, 0, 0, 0,
6389 0, 0, 0, 0, 0, 0, 0, 0,
6390 /* IP16_27_24 [4] */
6391 0, 0, 0, 0, 0, 0, 0, 0,
6392 0, 0, 0, 0, 0, 0, 0, 0,
6393 /* IP16_23_20 [4] */
6394 0, 0, 0, 0, 0, 0, 0, 0,
6395 0, 0, 0, 0, 0, 0, 0, 0,
6396 /* IP16_19_16 [4] */
6397 0, 0, 0, 0, 0, 0, 0, 0,
6398 0, 0, 0, 0, 0, 0, 0, 0,
6399 /* IP16_15_12 [4] */
6400 0, 0, 0, 0, 0, 0, 0, 0,
6401 0, 0, 0, 0, 0, 0, 0, 0,
6402 /* IP16_11_10 [2] */
6403 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
6404 /* IP16_9_8 [2] */
6405 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
6406 /* IP16_7_6 [2] */
6407 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
6408 /* IP16_5_3 [3] */
6409 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
6410 FN_GLO_SS_C, FN_VI1_DATA7_C,
6411 0, 0, 0,
6412 /* IP16_2_0 [3] */
6413 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6414 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6415 0, 0, 0, }
6416 },
6417 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6418 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
6419 3, 2, 2, 2, 1, 2, 2, 2) {
6420 /* RESERVED [1] */
6421 0, 0,
6422 /* SEL_SCIF1 [2] */
6423 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
6424 /* SEL_SCIFB [2] */
6425 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
6426 /* SEL_SCIFB2 [2] */
6427 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
6428 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
6429 /* SEL_SCIFB1 [3] */
6430 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
6431 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
6432 0, 0, 0, 0,
6433 /* SEL_SCIFA1 [2] */
6434 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6435 /* SEL_SSI9 [1] */
6436 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
6437 /* SEL_SCFA [1] */
6438 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
6439 /* SEL_QSP [1] */
6440 FN_SEL_QSP_0, FN_SEL_QSP_1,
6441 /* SEL_SSI7 [1] */
6442 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
6443 /* SEL_HSCIF1 [3] */
6444 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
6445 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
6446 0, 0, 0,
6447 /* RESERVED [2] */
6448 0, 0, 0, 0,
6449 /* SEL_VI1 [2] */
6450 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6451 /* RESERVED [2] */
6452 0, 0, 0, 0,
6453 /* SEL_TMU [1] */
6454 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
6455 /* SEL_LBS [2] */
6456 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
6457 /* SEL_TSIF0 [2] */
6458 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6459 /* SEL_SOF0 [2] */
6460 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
6461 },
6462 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6463 3, 1, 1, 3, 2, 1, 1, 2, 2,
6464 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
6465 /* SEL_SCIF0 [3] */
6466 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6467 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
6468 0, 0, 0,
6469 /* RESERVED [1] */
6470 0, 0,
6471 /* SEL_SCIF [1] */
6472 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
6473 /* SEL_CAN0 [3] */
6474 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
6475 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
6476 0, 0,
6477 /* SEL_CAN1 [2] */
6478 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
6479 /* RESERVED [1] */
6480 0, 0,
6481 /* SEL_SCIFA2 [1] */
6482 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
6483 /* SEL_SCIF4 [2] */
6484 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6485 /* RESERVED [2] */
6486 0, 0, 0, 0,
6487 /* SEL_ADG [1] */
6488 FN_SEL_ADG_0, FN_SEL_ADG_1,
6489 /* SEL_FM [3] */
6490 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
6491 FN_SEL_FM_3, FN_SEL_FM_4,
6492 0, 0, 0,
6493 /* SEL_SCIFA5 [2] */
6494 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6495 /* RESERVED [1] */
6496 0, 0,
6497 /* SEL_GPS [2] */
6498 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
6499 /* SEL_SCIFA4 [2] */
6500 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6501 /* SEL_SCIFA3 [2] */
6502 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6503 /* SEL_SIM [1] */
6504 FN_SEL_SIM_0, FN_SEL_SIM_1,
6505 /* RESERVED [1] */
6506 0, 0,
6507 /* SEL_SSI8 [1] */
6508 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
6509 },
6510 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6511 2, 2, 2, 2, 2, 2, 2, 2,
6512 1, 1, 2, 2, 3, 2, 2, 2, 1) {
6513 /* SEL_HSCIF2 [2] */
6514 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6515 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
6516 /* SEL_CANCLK [2] */
6517 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
6518 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
6519 /* SEL_IIC1 [2] */
6520 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
6521 /* SEL_IIC0 [2] */
6522 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6523 /* SEL_I2C4 [2] */
6524 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
6525 /* SEL_I2C3 [2] */
6526 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
6527 /* SEL_SCIF3 [2] */
6528 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
6529 /* SEL_IEB [2] */
6530 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6531 /* SEL_MMC [1] */
6532 FN_SEL_MMC_0, FN_SEL_MMC_1,
6533 /* SEL_SCIF5 [1] */
6534 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
6535 /* RESERVED [2] */
6536 0, 0, 0, 0,
6537 /* SEL_I2C2 [2] */
6538 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
6539 /* SEL_I2C1 [3] */
6540 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
6541 FN_SEL_I2C1_4,
6542 0, 0, 0,
6543 /* SEL_I2C0 [2] */
6544 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
6545 /* RESERVED [2] */
6546 0, 0, 0, 0,
6547 /* RESERVED [2] */
6548 0, 0, 0, 0,
6549 /* RESERVED [1] */
6550 0, 0, }
6551 },
6552 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6553 3, 2, 2, 1, 1, 1, 1, 3, 2,
6554 2, 3, 1, 1, 1, 2, 2, 2, 2) {
6555 /* SEL_SOF1 [3] */
6556 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6557 FN_SEL_SOF1_4,
6558 0, 0, 0,
6559 /* SEL_HSCIF0 [2] */
6560 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6561 /* SEL_DIS [2] */
6562 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6563 /* RESERVED [1] */
6564 0, 0,
6565 /* SEL_RAD [1] */
6566 FN_SEL_RAD_0, FN_SEL_RAD_1,
6567 /* SEL_RCN [1] */
6568 FN_SEL_RCN_0, FN_SEL_RCN_1,
6569 /* SEL_RSP [1] */
6570 FN_SEL_RSP_0, FN_SEL_RSP_1,
6571 /* SEL_SCIF2 [3] */
6572 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
6573 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
6574 0, 0, 0,
6575 /* RESERVED [2] */
6576 0, 0, 0, 0,
6577 /* RESERVED [2] */
6578 0, 0, 0, 0,
6579 /* SEL_SOF2 [3] */
6580 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
6581 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
6582 0, 0, 0,
6583 /* RESERVED [1] */
6584 0, 0,
6585 /* SEL_SSI1 [1] */
6586 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
6587 /* SEL_SSI0 [1] */
6588 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
6589 /* SEL_SSP [2] */
6590 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6591 /* RESERVED [2] */
6592 0, 0, 0, 0,
6593 /* RESERVED [2] */
6594 0, 0, 0, 0,
6595 /* RESERVED [2] */
6596 0, 0, 0, 0, }
6597 },
6598 { },
6599 };
6600
r8a7791_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)6601 static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6602 {
6603 if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
6604 return -EINVAL;
6605
6606 *pocctrl = 0xe606008c;
6607
6608 return 31 - (pin & 0x1f);
6609 }
6610
6611 static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
6612 .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
6613 };
6614
6615 #ifdef CONFIG_PINCTRL_PFC_R8A7743
6616 const struct sh_pfc_soc_info r8a7743_pinmux_info = {
6617 .name = "r8a77430_pfc",
6618 .ops = &r8a7791_pinmux_ops,
6619 .unlock_reg = 0xe6060000, /* PMMR */
6620
6621 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6622
6623 .pins = pinmux_pins,
6624 .nr_pins = ARRAY_SIZE(pinmux_pins),
6625 .groups = pinmux_groups.common,
6626 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6627 .functions = pinmux_functions.common,
6628 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6629
6630 .cfg_regs = pinmux_config_regs,
6631
6632 .pinmux_data = pinmux_data,
6633 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6634 };
6635 #endif
6636
6637 #ifdef CONFIG_PINCTRL_PFC_R8A7791
6638 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
6639 .name = "r8a77910_pfc",
6640 .ops = &r8a7791_pinmux_ops,
6641 .unlock_reg = 0xe6060000, /* PMMR */
6642
6643 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6644
6645 .pins = pinmux_pins,
6646 .nr_pins = ARRAY_SIZE(pinmux_pins),
6647 .groups = pinmux_groups.common,
6648 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6649 ARRAY_SIZE(pinmux_groups.r8a779x),
6650 .functions = pinmux_functions.common,
6651 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6652 ARRAY_SIZE(pinmux_functions.r8a779x),
6653
6654 .cfg_regs = pinmux_config_regs,
6655
6656 .pinmux_data = pinmux_data,
6657 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6658 };
6659 #endif
6660
6661 #ifdef CONFIG_PINCTRL_PFC_R8A7793
6662 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
6663 .name = "r8a77930_pfc",
6664 .ops = &r8a7791_pinmux_ops,
6665 .unlock_reg = 0xe6060000, /* PMMR */
6666
6667 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6668
6669 .pins = pinmux_pins,
6670 .nr_pins = ARRAY_SIZE(pinmux_pins),
6671 .groups = pinmux_groups.common,
6672 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6673 ARRAY_SIZE(pinmux_groups.r8a779x),
6674 .functions = pinmux_functions.common,
6675 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6676 ARRAY_SIZE(pinmux_functions.r8a779x),
6677
6678 .cfg_regs = pinmux_config_regs,
6679
6680 .pinmux_data = pinmux_data,
6681 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6682 };
6683 #endif
6684
