1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * R8A77470 processor support - PFC hardware block. 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8 #include <linux/kernel.h> 9 10 #include "sh_pfc.h" 11 12 #define CPU_ALL_PORT(fn, sfx) \ 13 PORT_GP_23(0, fn, sfx), \ 14 PORT_GP_23(1, fn, sfx), \ 15 PORT_GP_32(2, fn, sfx), \ 16 PORT_GP_17(3, fn, sfx), \ 17 PORT_GP_1(3, 27, fn, sfx), \ 18 PORT_GP_1(3, 28, fn, sfx), \ 19 PORT_GP_1(3, 29, fn, sfx), \ 20 PORT_GP_26(4, fn, sfx), \ 21 PORT_GP_32(5, fn, sfx) 22 23 enum { 24 PINMUX_RESERVED = 0, 25 26 PINMUX_DATA_BEGIN, 27 GP_ALL(DATA), 28 PINMUX_DATA_END, 29 30 PINMUX_FUNCTION_BEGIN, 31 GP_ALL(FN), 32 33 /* GPSR0 */ 34 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, FN_CLKOUT, 35 FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8, FN_IP0_15_12, FN_IP0_19_16, 36 FN_IP0_23_20, FN_IP0_27_24, FN_IP0_31_28, FN_MMC0_CLK_SDHI1_CLK, 37 FN_MMC0_CMD_SDHI1_CMD, FN_MMC0_D0_SDHI1_D0, FN_MMC0_D1_SDHI1_D1, 38 FN_MMC0_D2_SDHI1_D2, FN_MMC0_D3_SDHI1_D3, FN_IP1_3_0, 39 FN_IP1_7_4, FN_MMC0_D6, FN_MMC0_D7, 40 41 /* GPSR1 */ 42 FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20, FN_IP1_27_24, 43 FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12, 44 FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24, FN_IP2_31_28, FN_IP3_3_0, 45 FN_IP3_7_4, FN_IP3_11_8, FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20, 46 FN_IP3_27_24, FN_IP3_31_28, FN_IP4_3_0, 47 48 /* GPSR2 */ 49 FN_IP4_7_4, FN_IP4_11_8, FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20, 50 FN_IP4_27_24, FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8, 51 FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24, FN_IP5_31_28, 52 FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8, FN_IP6_15_12, FN_IP6_19_16, 53 FN_IP6_23_20, FN_IP6_27_24, FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4, 54 FN_IP7_11_8, FN_IP7_15_12, FN_IP7_19_16, FN_IP7_23_20, FN_IP7_27_24, 55 FN_IP7_31_28, FN_IP8_3_0, 56 57 /* GPSR3 */ 58 FN_IP8_7_4, FN_IP8_11_8, FN_IP8_15_12, FN_IP8_19_16, FN_IP8_23_20, 59 FN_IP8_27_24, FN_IP8_31_28, FN_IP9_3_0, FN_IP9_7_4, FN_IP9_11_8, 60 FN_IP9_15_12, FN_IP9_19_16, FN_IP9_23_20, FN_IP9_27_24, FN_IP9_31_28, 61 FN_IP10_3_0, FN_IP10_7_4, FN_IP10_11_8, FN_IP10_15_12, FN_IP10_19_16, 62 63 /* GPSR4 */ 64 FN_IP10_23_20, FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4, 65 FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20, 66 FN_IP11_27_24, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4, FN_IP12_11_8, 67 FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20, FN_IP12_27_24, 68 FN_IP12_31_28, FN_IP13_3_0, FN_IP13_7_4, FN_IP13_11_8, FN_IP13_15_12, 69 FN_IP13_19_16, FN_IP13_23_20, FN_IP13_27_24, 70 71 /* GPSR5 */ 72 FN_IP13_31_28, FN_IP14_3_0, FN_IP14_7_4, FN_IP14_11_8, FN_IP14_15_12, 73 FN_IP14_19_16, FN_IP14_23_20, FN_IP14_27_24, FN_IP14_31_28, 74 FN_IP15_3_0, FN_IP15_7_4, FN_IP15_11_8, FN_IP15_15_12, FN_IP15_19_16, 75 FN_IP15_23_20, FN_IP15_27_24, FN_IP15_31_28, FN_IP16_3_0, FN_IP16_7_4, 76 FN_IP16_11_8, FN_IP16_15_12, FN_IP16_19_16, FN_IP16_23_20, 77 FN_IP16_27_24, FN_IP16_31_28, FN_IP17_3_0, FN_IP17_7_4, FN_IP17_11_8, 78 FN_IP17_15_12, FN_IP17_19_16, FN_IP17_23_20, FN_IP17_27_24, 79 80 /* IPSR0 */ 81 FN_SD0_CLK, FN_SSI_SCK1_C, FN_RX3_C, 82 FN_SD0_CMD, FN_SSI_WS1_C, FN_TX3_C, 83 FN_SD0_DAT0, FN_SSI_SDATA1_C, FN_RX4_E, 84 FN_SD0_DAT1, FN_SSI_SCK0129_B, FN_TX4_E, 85 FN_SD0_DAT2, FN_SSI_WS0129_B, FN_RX5_E, 86 FN_SD0_DAT3, FN_SSI_SDATA0_B, FN_TX5_E, 87 FN_SD0_CD, FN_CAN0_RX_A, 88 FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 89 90 /* IPSR1 */ 91 FN_MMC0_D4, FN_SD1_CD, 92 FN_MMC0_D5, FN_SD1_WP, 93 FN_D0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 94 FN_D1, FN_SDA3_B, FN_TX5_B, FN_MSIOF2_TXD_C, FN_SSI_WS5_B, 95 FN_D2, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 96 FN_D3, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, FN_MSIOF2_SYNC_C, 97 FN_D4, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 98 FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 99 100 /* IPSR2 */ 101 FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 102 FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, 103 FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 104 FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 105 FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 106 FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 107 FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, FN_CAN_CLK_C, 108 FN_D13, FN_MSIOF2_SYNC_A, FN_RX4_C, 109 110 /* IPSR3 */ 111 FN_D14, FN_MSIOF2_SS1, FN_TX4_C, FN_CAN1_RX_B, FN_AVB_AVTP_CAPTURE_A, 112 FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, FN_CAN1_TX_B, FN_IRQ2, FN_AVB_AVTP_MATCH_A, 113 FN_QSPI0_SPCLK, FN_WE0_N, 114 FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 115 FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 116 FN_QSPI0_IO2, FN_CS0_N, 117 FN_QSPI0_IO3, FN_RD_N, 118 FN_QSPI0_SSL, FN_WE1_N, 119 120 /* IPSR4 */ 121 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 122 FN_DU0_DR0, FN_RX5_C, FN_SCL2_D, FN_A0, 123 FN_DU0_DR1, FN_TX5_C, FN_SDA2_D, FN_A1, 124 FN_DU0_DR2, FN_RX0_D, FN_SCL0_E, FN_A2, 125 FN_DU0_DR3, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, FN_A3, 126 FN_DU0_DR4, FN_RX1_D, FN_A4, 127 FN_DU0_DR5, FN_TX1_D, FN_PWM1_B, FN_A5, 128 FN_DU0_DR6, FN_RX2_C, FN_A6, 129 130 /* IPSR5 */ 131 FN_DU0_DR7, FN_TX2_C, FN_PWM2_B, FN_A7, 132 FN_DU0_DG0, FN_RX3_B, FN_SCL3_D, FN_A8, 133 FN_DU0_DG1, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, FN_A9, 134 FN_DU0_DG2, FN_RX4_D, FN_A10, 135 FN_DU0_DG3, FN_TX4_D, FN_PWM4_B, FN_A11, 136 FN_DU0_DG4, FN_HRX0_A, FN_A12, 137 FN_DU0_DG5, FN_HTX0_A, FN_PWM5_B, FN_A13, 138 FN_DU0_DG6, FN_HRX1_C, FN_A14, 139 140 /* IPSR6 */ 141 FN_DU0_DG7, FN_HTX1_C, FN_PWM6_B, FN_A15, 142 FN_DU0_DB0, FN_SCL4_D, FN_CAN0_RX_C, FN_A16, 143 FN_DU0_DB1, FN_SDA4_D, FN_CAN0_TX_C, FN_A17, 144 FN_DU0_DB2, FN_HCTS0_N, FN_A18, 145 FN_DU0_DB3, FN_HRTS0_N, FN_A19, 146 FN_DU0_DB4, FN_HCTS1_N_C, FN_A20, 147 FN_DU0_DB5, FN_HRTS1_N_C, FN_A21, 148 FN_DU0_DB6, FN_A22, 149 150 /* IPSR7 */ 151 FN_DU0_DB7, FN_A23, 152 FN_DU0_DOTCLKIN, FN_A24, 153 FN_DU0_DOTCLKOUT0, FN_A25, 154 FN_DU0_DOTCLKOUT1, FN_MSIOF2_RXD_B, FN_CS1_N_A26, 155 FN_DU0_EXHSYNC_DU0_HSYNC, FN_MSIOF2_TXD_B, FN_DREQ0_N, 156 FN_DU0_EXVSYNC_DU0_VSYNC, FN_MSIOF2_SYNC_B, FN_DACK0, 157 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_MSIOF2_SCK_B, FN_DRACK0, 158 FN_DU0_DISP, FN_CAN1_RX_C, 159 160 /* IPSR8 */ 161 FN_DU0_CDE, FN_CAN1_TX_C, 162 FN_VI1_CLK, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 163 FN_VI1_DATA0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 164 FN_VI1_DATA1, FN_AVB_RXD0, FN_ETH_RXD0, 165 FN_VI1_DATA2, FN_AVB_RXD1, FN_ETH_RXD1, 166 FN_VI1_DATA3, FN_AVB_RXD2, FN_ETH_MDIO, 167 FN_VI1_DATA4, FN_AVB_RXD3, FN_ETH_RX_ER, 168 FN_VI1_DATA5, FN_AVB_RXD4, FN_ETH_LINK, 169 170 /* IPSR9 */ 171 FN_VI1_DATA6, FN_AVB_RXD5, FN_ETH_TXD1, 172 FN_VI1_DATA7, FN_AVB_RXD6, FN_ETH_TX_EN, 173 FN_VI1_CLKENB, FN_SCL3_A, FN_AVB_RXD7, FN_ETH_MAGIC, 174 FN_VI1_FIELD, FN_SDA3_A, FN_AVB_RX_ER, FN_ETH_TXD0, 175 FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, FN_AVB_GTXREFCLK, FN_ETH_MDC, 176 FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_CLK, 177 FN_VI1_DATA8, FN_SCL2_B, FN_AVB_TX_EN, 178 FN_VI1_DATA9, FN_SDA2_B, FN_AVB_TXD0, 179 180 /* IPSR10 */ 181 FN_VI1_DATA10, FN_CAN0_RX_B, FN_AVB_TXD1, 182 FN_VI1_DATA11, FN_CAN0_TX_B, FN_AVB_TXD2, 183 FN_AVB_TXD3, FN_AUDIO_CLKA_B, FN_SSI_SCK1_D, FN_RX5_F, FN_MSIOF0_RXD_B, 184 FN_AVB_TXD4, FN_AUDIO_CLKB_B, FN_SSI_WS1_D, FN_TX5_F, FN_MSIOF0_TXD_B, 185 FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, FN_SSI_SDATA1_D, FN_MSIOF0_SCK_B, 186 FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6, FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 187 FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, FN_CAN1_TX_D, FN_DVC_MUTE, 188 FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, FN_SSI_SCK6_B, FN_VI0_G0, 189 190 /* IPSR11 */ 191 FN_SDA1_A, FN_TX4_A, FN_DU1_DR1, FN_SSI_WS6_B, FN_VI0_G1, 192 FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2, 193 FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3, 194 FN_MSIOF0_SCK_A, FN_IRQ0, FN_DU1_DR4, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4, 195 FN_MSIOF0_SYNC_A, FN_PWM1_A, FN_DU1_DR5, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 196 FN_MSIOF0_SS1_A, FN_DU1_DR6, FN_QSPI1_IO3, FN_SSI_SDATA8_B, 197 FN_MSIOF0_SS2_A, FN_DU1_DR7, FN_QSPI1_SSL, 198 FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 199 200 /* IPSR12 */ 201 FN_HTX1_A, FN_SDA4_A, FN_DU1_DG1, FN_TX0_A, 202 FN_HCTS1_N_A, FN_PWM2_A, FN_DU1_DG2, FN_REMOCON_B, 203 FN_HRTS1_N_A, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 204 FN_SD2_CLK, FN_HSCK1, FN_DU1_DG4, FN_SSI_SCK1_B, 205 FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, FN_SSI_SCK2_B, FN_PWM3_A, 206 FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, FN_SSI_SDATA1_B, 207 FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B, 208 FN_SD2_DAT2, FN_RX2_A, FN_DU1_DB0, FN_SSI_SDATA2_B, 209 210 /* IPSR13 */ 211 FN_SD2_DAT3, FN_TX2_A, FN_DU1_DB1, FN_SSI_WS9_B, 212 FN_SD2_CD, FN_SCIF2_SCK_A, FN_DU1_DB2, FN_SSI_SCK9_B, 213 FN_SD2_WP, FN_SCIF3_SCK, FN_DU1_DB3, FN_SSI_SDATA9_B, 214 FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 215 FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 216 FN_SCL2_A, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, FN_SSI_SCK4_B, 217 FN_SDA2_A, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, 218 FN_SSI_SCK5_A, FN_DU1_DOTCLKOUT1, 219 220 /* IPSR14 */ 221 FN_SSI_WS5_A, FN_SCL3_C, FN_DU1_DOTCLKIN, 222 FN_SSI_SDATA5_A, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 223 FN_SSI_SCK6_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 224 FN_SSI_WS6_A, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 225 FN_SSI_SDATA6_A, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 226 FN_SSI_SCK78_A, FN_SDA4_E, FN_DU1_DISP, 227 FN_SSI_WS78_A, FN_SCL4_E, FN_DU1_CDE, 228 FN_SSI_SDATA7_A, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_VI0_G5, 229 230 /* IPSR15 */ 231 FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, FN_VI0_G6, 232 FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, FN_VI0_G7, 233 FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, FN_VI0_R0, 234 FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, FN_DACK1, FN_VI0_R1, 235 FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, FN_CAN1_RX_A, FN_DREQ1_N, FN_VI0_R2, 236 FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, FN_CAN1_TX_A, FN_DREQ2_N, FN_VI0_R3, 237 FN_SSI_SCK4_A, FN_AVB_MAGIC, FN_VI0_R4, 238 FN_SSI_WS4_A, FN_AVB_PHY_INT, FN_VI0_R5, 239 240 /* IPSR16 */ 241 FN_SSI_SDATA4_A, FN_AVB_CRS, FN_VI0_R6, 242 FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 243 FN_SSI_SDATA8_A, FN_RX1_B, FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 244 FN_SSI_WS1_A, FN_TX1_B, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 245 FN_SSI_SDATA1_A, FN_HRX1_B, FN_VI0_DATA1_VI0_B1, 246 FN_SSI_SCK2_A, FN_HTX1_B, FN_AVB_TXD7, FN_VI0_DATA2_VI0_B2, 247 FN_SSI_WS2_A, FN_HCTS1_N_B, FN_AVB_TX_ER, FN_VI0_DATA3_VI0_B3, 248 FN_SSI_SDATA2_A, FN_HRTS1_N_B, FN_VI0_DATA4_VI0_B4, 249 250 /* IPSR17 */ 251 FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, FN_EX_WAIT1, FN_VI0_DATA5_VI0_B5, 252 FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, FN_VI0_DATA6_VI0_B6, 253 FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, FN_VI0_DATA7_VI0_B7, 254 FN_AUDIO_CLKA_A, FN_SCL0_B, FN_VI0_CLKENB, 255 FN_AUDIO_CLKB_A, FN_SDA0_B, FN_VI0_FIELD, 256 FN_AUDIO_CLKC_A, FN_SCL4_B, FN_VI0_HSYNC_N, 257 FN_AUDIO_CLKOUT_A, FN_SDA4_B, FN_VI0_VSYNC_N, 258 259 /* MOD_SEL0 */ 260 FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3, 261 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, 262 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 263 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 264 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, FN_SEL_I2C04_4, 265 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, FN_SEL_I2C03_4, 266 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, 267 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, 268 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4, 269 FN_SEL_AVB_0, FN_SEL_AVB_1, 270 271 /* MOD_SEL1 */ 272 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 273 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 274 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, FN_SEL_SCIF4_4, 275 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 276 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 277 FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1, 278 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 279 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 280 FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 281 FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, 282 FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1, 283 FN_SEL_RCN_0, FN_SEL_RCN_1, 284 FN_SEL_TMU2_0, FN_SEL_TMU2_1, 285 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 286 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 287 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, 288 289 /* MOD_SEL2 */ 290 FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 291 FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 292 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 293 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 294 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 295 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 296 FN_SEL_SSI5_0, FN_SEL_SSI5_1, 297 FN_SEL_SSI4_0, FN_SEL_SSI4_1, 298 FN_SEL_SSI2_0, FN_SEL_SSI2_1, 299 FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3, 300 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 301 PINMUX_FUNCTION_END, 302 303 PINMUX_MARK_BEGIN, 304 305 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, 306 CLKOUT_MARK, MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK, 307 MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, 308 MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D6_MARK, 309 MMC0_D7_MARK, 310 311 /* IPSR0 */ 312 SD0_CLK_MARK, SSI_SCK1_C_MARK, RX3_C_MARK, 313 SD0_CMD_MARK, SSI_WS1_C_MARK, TX3_C_MARK, 314 SD0_DAT0_MARK, SSI_SDATA1_C_MARK, RX4_E_MARK, 315 SD0_DAT1_MARK, SSI_SCK0129_B_MARK, TX4_E_MARK, 316 SD0_DAT2_MARK, SSI_WS0129_B_MARK, RX5_E_MARK, 317 SD0_DAT3_MARK, SSI_SDATA0_B_MARK, TX5_E_MARK, 318 SD0_CD_MARK, CAN0_RX_A_MARK, 319 SD0_WP_MARK, IRQ7_MARK, CAN0_TX_A_MARK, 320 321 /* IPSR1 */ 322 MMC0_D4_MARK, SD1_CD_MARK, 323 MMC0_D5_MARK, SD1_WP_MARK, 324 D0_MARK, SCL3_B_MARK, RX5_B_MARK, IRQ4_MARK, MSIOF2_RXD_C_MARK, SSI_SDATA5_B_MARK, 325 D1_MARK, SDA3_B_MARK, TX5_B_MARK, MSIOF2_TXD_C_MARK, SSI_WS5_B_MARK, 326 D2_MARK, RX4_B_MARK, SCL0_D_MARK, PWM1_C_MARK, MSIOF2_SCK_C_MARK, SSI_SCK5_B_MARK, 327 D3_MARK, TX4_B_MARK, SDA0_D_MARK, PWM0_A_MARK, MSIOF2_SYNC_C_MARK, 328 D4_MARK, IRQ3_MARK, TCLK1_A_MARK, PWM6_C_MARK, 329 D5_MARK, HRX2_MARK, SCL1_B_MARK, PWM2_C_MARK, TCLK2_B_MARK, 330 331 /* IPSR2 */ 332 D6_MARK, HTX2_MARK, SDA1_B_MARK, PWM4_C_MARK, 333 D7_MARK, HSCK2_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK, 334 D8_MARK, HCTS2_N_MARK, RX1_C_MARK, SCL1_D_MARK, PWM3_C_MARK, 335 D9_MARK, HRTS2_N_MARK, TX1_C_MARK, SDA1_D_MARK, 336 D10_MARK, MSIOF2_RXD_A_MARK, HRX0_B_MARK, 337 D11_MARK, MSIOF2_TXD_A_MARK, HTX0_B_MARK, 338 D12_MARK, MSIOF2_SCK_A_MARK, HSCK0_MARK, CAN_CLK_C_MARK, 339 D13_MARK, MSIOF2_SYNC_A_MARK, RX4_C_MARK, 340 341 /* IPSR3 */ 342 D14_MARK, MSIOF2_SS1_MARK, TX4_C_MARK, CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_A_MARK, 343 D15_MARK, MSIOF2_SS2_MARK, PWM4_A_MARK, CAN1_TX_B_MARK, IRQ2_MARK, AVB_AVTP_MATCH_A_MARK, 344 QSPI0_SPCLK_MARK, WE0_N_MARK, 345 QSPI0_MOSI_QSPI0_IO0_MARK, BS_N_MARK, 346 QSPI0_MISO_QSPI0_IO1_MARK, RD_WR_N_MARK, 347 QSPI0_IO2_MARK, CS0_N_MARK, 348 QSPI0_IO3_MARK, RD_N_MARK, 349 QSPI0_SSL_MARK, WE1_N_MARK, 350 351 /* IPSR4 */ 352 EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_A_MARK, 353 DU0_DR0_MARK, RX5_C_MARK, SCL2_D_MARK, A0_MARK, 354 DU0_DR1_MARK, TX5_C_MARK, SDA2_D_MARK, A1_MARK, 355 DU0_DR2_MARK, RX0_D_MARK, SCL0_E_MARK, A2_MARK, 356 DU0_DR3_MARK, TX0_D_MARK, SDA0_E_MARK, PWM0_B_MARK, A3_MARK, 357 DU0_DR4_MARK, RX1_D_MARK, A4_MARK, 358 DU0_DR5_MARK, TX1_D_MARK, PWM1_B_MARK, A5_MARK, 359 DU0_DR6_MARK, RX2_C_MARK, A6_MARK, 360 361 /* IPSR5 */ 362 DU0_DR7_MARK, TX2_C_MARK, PWM2_B_MARK, A7_MARK, 363 DU0_DG0_MARK, RX3_B_MARK, SCL3_D_MARK, A8_MARK, 364 DU0_DG1_MARK, TX3_B_MARK, SDA3_D_MARK, PWM3_B_MARK, A9_MARK, 365 DU0_DG2_MARK, RX4_D_MARK, A10_MARK, 366 DU0_DG3_MARK, TX4_D_MARK, PWM4_B_MARK, A11_MARK, 367 DU0_DG4_MARK, HRX0_A_MARK, A12_MARK, 368 DU0_DG5_MARK, HTX0_A_MARK, PWM5_B_MARK, A13_MARK, 369 DU0_DG6_MARK, HRX1_C_MARK, A14_MARK, 370 371 /* IPSR6 */ 372 DU0_DG7_MARK, HTX1_C_MARK, PWM6_B_MARK, A15_MARK, 373 DU0_DB0_MARK, SCL4_D_MARK, CAN0_RX_C_MARK, A16_MARK, 374 DU0_DB1_MARK, SDA4_D_MARK, CAN0_TX_C_MARK, A17_MARK, 375 DU0_DB2_MARK, HCTS0_N_MARK, A18_MARK, 376 DU0_DB3_MARK, HRTS0_N_MARK, A19_MARK, 377 DU0_DB4_MARK, HCTS1_N_C_MARK, A20_MARK, 378 DU0_DB5_MARK, HRTS1_N_C_MARK, A21_MARK, 379 DU0_DB6_MARK, A22_MARK, 380 381 /* IPSR7 */ 382 DU0_DB7_MARK, A23_MARK, 383 DU0_DOTCLKIN_MARK, A24_MARK, 384 DU0_DOTCLKOUT0_MARK, A25_MARK, 385 DU0_DOTCLKOUT1_MARK, MSIOF2_RXD_B_MARK, CS1_N_A26_MARK, 386 DU0_EXHSYNC_DU0_HSYNC_MARK, MSIOF2_TXD_B_MARK, DREQ0_N_MARK, 387 DU0_EXVSYNC_DU0_VSYNC_MARK, MSIOF2_SYNC_B_MARK, DACK0_MARK, 388 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, MSIOF2_SCK_B_MARK, DRACK0_MARK, 389 DU0_DISP_MARK, CAN1_RX_C_MARK, 390 391 /* IPSR8 */ 392 DU0_CDE_MARK, CAN1_TX_C_MARK, 393 VI1_CLK_MARK, AVB_RX_CLK_MARK, ETH_REF_CLK_MARK, 394 VI1_DATA0_MARK, AVB_RX_DV_MARK, ETH_CRS_DV_MARK, 395 VI1_DATA1_MARK, AVB_RXD0_MARK, ETH_RXD0_MARK, 396 VI1_DATA2_MARK, AVB_RXD1_MARK, ETH_RXD1_MARK, 397 VI1_DATA3_MARK, AVB_RXD2_MARK, ETH_MDIO_MARK, 398 VI1_DATA4_MARK, AVB_RXD3_MARK, ETH_RX_ER_MARK, 399 VI1_DATA5_MARK, AVB_RXD4_MARK, ETH_LINK_MARK, 400 401 /* IPSR9 */ 402 VI1_DATA6_MARK, AVB_RXD5_MARK, ETH_TXD1_MARK, 403 VI1_DATA7_MARK, AVB_RXD6_MARK, ETH_TX_EN_MARK, 404 VI1_CLKENB_MARK, SCL3_A_MARK, AVB_RXD7_MARK, ETH_MAGIC_MARK, 405 VI1_FIELD_MARK, SDA3_A_MARK, AVB_RX_ER_MARK, ETH_TXD0_MARK, 406 VI1_HSYNC_N_MARK, RX0_B_MARK, SCL0_C_MARK, AVB_GTXREFCLK_MARK, ETH_MDC_MARK, 407 VI1_VSYNC_N_MARK, TX0_B_MARK, SDA0_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_CLK_MARK, 408 VI1_DATA8_MARK, SCL2_B_MARK, AVB_TX_EN_MARK, 409 VI1_DATA9_MARK, SDA2_B_MARK, AVB_TXD0_MARK, 410 411 /* IPSR10 */ 412 VI1_DATA10_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, 413 VI1_DATA11_MARK, CAN0_TX_B_MARK, AVB_TXD2_MARK, 414 AVB_TXD3_MARK, AUDIO_CLKA_B_MARK, SSI_SCK1_D_MARK, RX5_F_MARK, MSIOF0_RXD_B_MARK, 415 AVB_TXD4_MARK, AUDIO_CLKB_B_MARK, SSI_WS1_D_MARK, TX5_F_MARK, MSIOF0_TXD_B_MARK, 416 AVB_TXD5_MARK, SCIF_CLK_B_MARK, AUDIO_CLKC_B_MARK, SSI_SDATA1_D_MARK, MSIOF0_SCK_B_MARK, 417 SCL0_A_MARK, RX0_C_MARK, PWM5_A_MARK, TCLK1_B_MARK, AVB_TXD6_MARK, CAN1_RX_D_MARK, MSIOF0_SYNC_B_MARK, 418 SDA0_A_MARK, TX0_C_MARK, IRQ5_MARK, CAN_CLK_A_MARK, AVB_GTX_CLK_MARK, CAN1_TX_D_MARK, DVC_MUTE_MARK, 419 SCL1_A_MARK, RX4_A_MARK, PWM5_D_MARK, DU1_DR0_MARK, SSI_SCK6_B_MARK, VI0_G0_MARK, 420 421 /* IPSR11 */ 422 SDA1_A_MARK, TX4_A_MARK, DU1_DR1_MARK, SSI_WS6_B_MARK, VI0_G1_MARK, 423 MSIOF0_RXD_A_MARK, RX5_A_MARK, SCL2_C_MARK, DU1_DR2_MARK, QSPI1_MOSI_QSPI1_IO0_MARK, SSI_SDATA6_B_MARK, VI0_G2_MARK, 424 MSIOF0_TXD_A_MARK, TX5_A_MARK, SDA2_C_MARK, DU1_DR3_MARK, QSPI1_MISO_QSPI1_IO1_MARK, SSI_WS78_B_MARK, VI0_G3_MARK, 425 MSIOF0_SCK_A_MARK, IRQ0_MARK, DU1_DR4_MARK, QSPI1_SPCLK_MARK, SSI_SCK78_B_MARK, VI0_G4_MARK, 426 MSIOF0_SYNC_A_MARK, PWM1_A_MARK, DU1_DR5_MARK, QSPI1_IO2_MARK, SSI_SDATA7_B_MARK, 427 MSIOF0_SS1_A_MARK, DU1_DR6_MARK, QSPI1_IO3_MARK, SSI_SDATA8_B_MARK, 428 MSIOF0_SS2_A_MARK, DU1_DR7_MARK, QSPI1_SSL_MARK, 429 HRX1_A_MARK, SCL4_A_MARK, PWM6_A_MARK, DU1_DG0_MARK, RX0_A_MARK, 430 431 /* IPSR12 */ 432 HTX1_A_MARK, SDA4_A_MARK, DU1_DG1_MARK, TX0_A_MARK, 433 HCTS1_N_A_MARK, PWM2_A_MARK, DU1_DG2_MARK, REMOCON_B_MARK, 434 HRTS1_N_A_MARK, DU1_DG3_MARK, SSI_WS1_B_MARK, IRQ1_MARK, 435 SD2_CLK_MARK, HSCK1_MARK, DU1_DG4_MARK, SSI_SCK1_B_MARK, 436 SD2_CMD_MARK, SCIF1_SCK_A_MARK, TCLK2_A_MARK, DU1_DG5_MARK, SSI_SCK2_B_MARK, PWM3_A_MARK, 437 SD2_DAT0_MARK, RX1_A_MARK, SCL1_E_MARK, DU1_DG6_MARK, SSI_SDATA1_B_MARK, 438 SD2_DAT1_MARK, TX1_A_MARK, SDA1_E_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK, 439 SD2_DAT2_MARK, RX2_A_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK, 440 441 /* IPSR13 */ 442 SD2_DAT3_MARK, TX2_A_MARK, DU1_DB1_MARK, SSI_WS9_B_MARK, 443 SD2_CD_MARK, SCIF2_SCK_A_MARK, DU1_DB2_MARK, SSI_SCK9_B_MARK, 444 SD2_WP_MARK, SCIF3_SCK_MARK, DU1_DB3_MARK, SSI_SDATA9_B_MARK, 445 RX3_A_MARK, SCL1_C_MARK, MSIOF1_RXD_B_MARK, DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SDATA4_B_MARK, 446 TX3_A_MARK, SDA1_C_MARK, MSIOF1_TXD_B_MARK, DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, 447 SCL2_A_MARK, MSIOF1_SCK_B_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, SSI_SCK4_B_MARK, 448 SDA2_A_MARK, MSIOF1_SYNC_B_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, 449 SSI_SCK5_A_MARK, DU1_DOTCLKOUT1_MARK, 450 451 /* IPSR14 */ 452 SSI_WS5_A_MARK, SCL3_C_MARK, DU1_DOTCLKIN_MARK, 453 SSI_SDATA5_A_MARK, SDA3_C_MARK, DU1_DOTCLKOUT0_MARK, 454 SSI_SCK6_A_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, 455 SSI_WS6_A_MARK, SCL4_C_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, 456 SSI_SDATA6_A_MARK, SDA4_C_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, 457 SSI_SCK78_A_MARK, SDA4_E_MARK, DU1_DISP_MARK, 458 SSI_WS78_A_MARK, SCL4_E_MARK, DU1_CDE_MARK, 459 SSI_SDATA7_A_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, VI0_G5_MARK, 460 461 /* IPSR15 */ 462 SSI_SCK0129_A_MARK, MSIOF1_RXD_A_MARK, RX5_D_MARK, VI0_G6_MARK, 463 SSI_WS0129_A_MARK, MSIOF1_TXD_A_MARK, TX5_D_MARK, VI0_G7_MARK, 464 SSI_SDATA0_A_MARK, MSIOF1_SYNC_A_MARK, PWM0_C_MARK, VI0_R0_MARK, 465 SSI_SCK34_MARK, MSIOF1_SCK_A_MARK, AVB_MDC_MARK, DACK1_MARK, VI0_R1_MARK, 466 SSI_WS34_MARK, MSIOF1_SS1_A_MARK, AVB_MDIO_MARK, CAN1_RX_A_MARK, DREQ1_N_MARK, VI0_R2_MARK, 467 SSI_SDATA3_MARK, MSIOF1_SS2_A_MARK, AVB_LINK_MARK, CAN1_TX_A_MARK, DREQ2_N_MARK, VI0_R3_MARK, 468 SSI_SCK4_A_MARK, AVB_MAGIC_MARK, VI0_R4_MARK, 469 SSI_WS4_A_MARK, AVB_PHY_INT_MARK, VI0_R5_MARK, 470 471 /* IPSR16 */ 472 SSI_SDATA4_A_MARK, AVB_CRS_MARK, VI0_R6_MARK, 473 SSI_SCK1_A_MARK, SCIF1_SCK_B_MARK, PWM1_D_MARK, IRQ9_MARK, REMOCON_A_MARK, DACK2_MARK, VI0_CLK_MARK, AVB_COL_MARK, 474 SSI_SDATA8_A_MARK, RX1_B_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_B_MARK, VI0_R7_MARK, 475 SSI_WS1_A_MARK, TX1_B_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_B_MARK, VI0_DATA0_VI0_B0_MARK, 476 SSI_SDATA1_A_MARK, HRX1_B_MARK, VI0_DATA1_VI0_B1_MARK, 477 SSI_SCK2_A_MARK, HTX1_B_MARK, AVB_TXD7_MARK, VI0_DATA2_VI0_B2_MARK, 478 SSI_WS2_A_MARK, HCTS1_N_B_MARK, AVB_TX_ER_MARK, VI0_DATA3_VI0_B3_MARK, 479 SSI_SDATA2_A_MARK, HRTS1_N_B_MARK, VI0_DATA4_VI0_B4_MARK, 480 481 /* IPSR17 */ 482 SSI_SCK9_A_MARK, RX2_B_MARK, SCL3_E_MARK, EX_WAIT1_MARK, VI0_DATA5_VI0_B5_MARK, 483 SSI_WS9_A_MARK, TX2_B_MARK, SDA3_E_MARK, VI0_DATA6_VI0_B6_MARK, 484 SSI_SDATA9_A_MARK, SCIF2_SCK_B_MARK, PWM2_D_MARK, VI0_DATA7_VI0_B7_MARK, 485 AUDIO_CLKA_A_MARK, SCL0_B_MARK, VI0_CLKENB_MARK, 486 AUDIO_CLKB_A_MARK, SDA0_B_MARK, VI0_FIELD_MARK, 487 AUDIO_CLKC_A_MARK, SCL4_B_MARK, VI0_HSYNC_N_MARK, 488 AUDIO_CLKOUT_A_MARK, SDA4_B_MARK, VI0_VSYNC_N_MARK, 489 490 PINMUX_MARK_END, 491 }; 492 493 static const u16 pinmux_data[] = { 494 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 495 496 PINMUX_SINGLE(USB0_PWEN), 497 PINMUX_SINGLE(USB0_OVC), 498 PINMUX_SINGLE(USB1_PWEN), 499 PINMUX_SINGLE(USB1_OVC), 500 PINMUX_SINGLE(CLKOUT), 501 PINMUX_SINGLE(MMC0_CLK_SDHI1_CLK), 502 PINMUX_SINGLE(MMC0_CMD_SDHI1_CMD), 503 PINMUX_SINGLE(MMC0_D0_SDHI1_D0), 504 PINMUX_SINGLE(MMC0_D1_SDHI1_D1), 505 PINMUX_SINGLE(MMC0_D2_SDHI1_D2), 506 PINMUX_SINGLE(MMC0_D3_SDHI1_D3), 507 PINMUX_SINGLE(MMC0_D6), 508 PINMUX_SINGLE(MMC0_D7), 509 510 /* IPSR0 */ 511 PINMUX_IPSR_GPSR(IP0_3_0, SD0_CLK), 512 PINMUX_IPSR_MSEL(IP0_3_0, SSI_SCK1_C, SEL_SSI1_2), 513 PINMUX_IPSR_MSEL(IP0_3_0, RX3_C, SEL_SCIF3_2), 514 PINMUX_IPSR_GPSR(IP0_7_4, SD0_CMD), 515 PINMUX_IPSR_MSEL(IP0_7_4, SSI_WS1_C, SEL_SSI1_2), 516 PINMUX_IPSR_MSEL(IP0_7_4, TX3_C, SEL_SCIF3_2), 517 PINMUX_IPSR_GPSR(IP0_11_8, SD0_DAT0), 518 PINMUX_IPSR_MSEL(IP0_11_8, SSI_SDATA1_C, SEL_SSI1_2), 519 PINMUX_IPSR_MSEL(IP0_11_8, RX4_E, SEL_SCIF4_4), 520 PINMUX_IPSR_GPSR(IP0_15_12, SD0_DAT1), 521 PINMUX_IPSR_MSEL(IP0_15_12, SSI_SCK0129_B, SEL_SSI0_1), 522 PINMUX_IPSR_MSEL(IP0_15_12, TX4_E, SEL_SCIF4_4), 523 PINMUX_IPSR_GPSR(IP0_19_16, SD0_DAT2), 524 PINMUX_IPSR_MSEL(IP0_19_16, SSI_WS0129_B, SEL_SSI0_1), 525 PINMUX_IPSR_MSEL(IP0_19_16, RX5_E, SEL_SCIF5_4), 526 PINMUX_IPSR_GPSR(IP0_23_20, SD0_DAT3), 527 PINMUX_IPSR_MSEL(IP0_23_20, SSI_SDATA0_B, SEL_SSI0_1), 528 PINMUX_IPSR_MSEL(IP0_23_20, TX5_E, SEL_SCIF5_4), 529 PINMUX_IPSR_GPSR(IP0_27_24, SD0_CD), 530 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_RX_A, SEL_CAN0_0), 531 PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP), 532 PINMUX_IPSR_GPSR(IP0_31_28, IRQ7), 533 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0), 534 535 /* IPSR1 */ 536 PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4), 537 PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD), 538 PINMUX_IPSR_GPSR(IP1_7_4, MMC0_D5), 539 PINMUX_IPSR_GPSR(IP1_7_4, SD1_WP), 540 PINMUX_IPSR_GPSR(IP1_11_8, D0), 541 PINMUX_IPSR_MSEL(IP1_11_8, SCL3_B, SEL_I2C03_1), 542 PINMUX_IPSR_MSEL(IP1_11_8, RX5_B, SEL_SCIF5_1), 543 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4), 544 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF2_RXD_C, SEL_MSIOF2_2), 545 PINMUX_IPSR_MSEL(IP1_11_8, SSI_SDATA5_B, SEL_SSI5_1), 546 PINMUX_IPSR_GPSR(IP1_15_12, D1), 547 PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1), 548 PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1), 549 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2), 550 PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1), 551 PINMUX_IPSR_GPSR(IP1_19_16, D2), 552 PINMUX_IPSR_MSEL(IP1_19_16, RX4_B, SEL_SCIF4_1), 553 PINMUX_IPSR_MSEL(IP1_19_16, SCL0_D, SEL_I2C00_3), 554 PINMUX_IPSR_GPSR(IP1_19_16, PWM1_C), 555 PINMUX_IPSR_MSEL(IP1_19_16, MSIOF2_SCK_C, SEL_MSIOF2_2), 556 PINMUX_IPSR_MSEL(IP1_19_16, SSI_SCK5_B, SEL_SSI5_1), 557 PINMUX_IPSR_GPSR(IP1_23_20, D3), 558 PINMUX_IPSR_MSEL(IP1_23_20, TX4_B, SEL_SCIF4_1), 559 PINMUX_IPSR_MSEL(IP1_23_20, SDA0_D, SEL_I2C00_3), 560 PINMUX_IPSR_GPSR(IP1_23_20, PWM0_A), 561 PINMUX_IPSR_MSEL(IP1_23_20, MSIOF2_SYNC_C, SEL_MSIOF2_2), 562 PINMUX_IPSR_GPSR(IP1_27_24, D4), 563 PINMUX_IPSR_GPSR(IP1_27_24, IRQ3), 564 PINMUX_IPSR_MSEL(IP1_27_24, TCLK1_A, SEL_TMU1_0), 565 PINMUX_IPSR_GPSR(IP1_27_24, PWM6_C), 566 PINMUX_IPSR_GPSR(IP1_31_28, D5), 567 PINMUX_IPSR_GPSR(IP1_31_28, HRX2), 568 PINMUX_IPSR_MSEL(IP1_31_28, SCL1_B, SEL_I2C01_1), 569 PINMUX_IPSR_GPSR(IP1_31_28, PWM2_C), 570 PINMUX_IPSR_MSEL(IP1_31_28, TCLK2_B, SEL_TMU2_1), 571 572 /* IPSR2 */ 573 PINMUX_IPSR_GPSR(IP2_3_0, D6), 574 PINMUX_IPSR_GPSR(IP2_3_0, HTX2), 575 PINMUX_IPSR_MSEL(IP2_3_0, SDA1_B, SEL_I2C01_1), 576 PINMUX_IPSR_GPSR(IP2_3_0, PWM4_C), 577 PINMUX_IPSR_GPSR(IP2_7_4, D7), 578 PINMUX_IPSR_GPSR(IP2_7_4, HSCK2), 579 PINMUX_IPSR_MSEL(IP2_7_4, SCIF1_SCK_C, SEL_SCIF1_2), 580 PINMUX_IPSR_GPSR(IP2_7_4, IRQ6), 581 PINMUX_IPSR_GPSR(IP2_7_4, PWM5_C), 582 PINMUX_IPSR_GPSR(IP2_11_8, D8), 583 PINMUX_IPSR_GPSR(IP2_11_8, HCTS2_N), 584 PINMUX_IPSR_MSEL(IP2_11_8, RX1_C, SEL_SCIF1_2), 585 PINMUX_IPSR_MSEL(IP2_11_8, SCL1_D, SEL_I2C01_3), 586 PINMUX_IPSR_GPSR(IP2_11_8, PWM3_C), 587 PINMUX_IPSR_GPSR(IP2_15_12, D9), 588 PINMUX_IPSR_GPSR(IP2_15_12, HRTS2_N), 589 PINMUX_IPSR_MSEL(IP2_15_12, TX1_C, SEL_SCIF1_2), 590 PINMUX_IPSR_MSEL(IP2_15_12, SDA1_D, SEL_I2C01_3), 591 PINMUX_IPSR_GPSR(IP2_19_16, D10), 592 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF2_RXD_A, SEL_MSIOF2_0), 593 PINMUX_IPSR_MSEL(IP2_19_16, HRX0_B, SEL_HSCIF0_1), 594 PINMUX_IPSR_GPSR(IP2_23_20, D11), 595 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_TXD_A, SEL_MSIOF2_0), 596 PINMUX_IPSR_MSEL(IP2_23_20, HTX0_B, SEL_HSCIF0_1), 597 PINMUX_IPSR_GPSR(IP2_27_24, D12), 598 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SCK_A, SEL_MSIOF2_0), 599 PINMUX_IPSR_GPSR(IP2_27_24, HSCK0), 600 PINMUX_IPSR_MSEL(IP2_27_24, CAN_CLK_C, SEL_CANCLK_2), 601 PINMUX_IPSR_GPSR(IP2_31_28, D13), 602 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0), 603 PINMUX_IPSR_MSEL(IP2_31_28, RX4_C, SEL_SCIF4_2), 604 605 /* IPSR3 */ 606 PINMUX_IPSR_GPSR(IP3_3_0, D14), 607 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SS1), 608 PINMUX_IPSR_MSEL(IP3_3_0, TX4_C, SEL_SCIF4_2), 609 PINMUX_IPSR_MSEL(IP3_3_0, CAN1_RX_B, SEL_CAN1_1), 610 PINMUX_IPSR_MSEL(IP3_3_0, AVB_AVTP_CAPTURE_A, SEL_AVB_0), 611 PINMUX_IPSR_GPSR(IP3_7_4, D15), 612 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2), 613 PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A), 614 PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1), 615 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2), 616 PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0), 617 PINMUX_IPSR_GPSR(IP3_11_8, QSPI0_SPCLK), 618 PINMUX_IPSR_GPSR(IP3_11_8, WE0_N), 619 PINMUX_IPSR_GPSR(IP3_15_12, QSPI0_MOSI_QSPI0_IO0), 620 PINMUX_IPSR_GPSR(IP3_15_12, BS_N), 621 PINMUX_IPSR_GPSR(IP3_19_16, QSPI0_MISO_QSPI0_IO1), 622 PINMUX_IPSR_GPSR(IP3_19_16, RD_WR_N), 623 PINMUX_IPSR_GPSR(IP3_23_20, QSPI0_IO2), 624 PINMUX_IPSR_GPSR(IP3_23_20, CS0_N), 625 PINMUX_IPSR_GPSR(IP3_27_24, QSPI0_IO3), 626 PINMUX_IPSR_GPSR(IP3_27_24, RD_N), 627 PINMUX_IPSR_GPSR(IP3_31_28, QSPI0_SSL), 628 PINMUX_IPSR_GPSR(IP3_31_28, WE1_N), 629 630 /* IPSR4 */ 631 PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0), 632 PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1), 633 PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0), 634 PINMUX_IPSR_GPSR(IP4_7_4, DU0_DR0), 635 PINMUX_IPSR_MSEL(IP4_7_4, RX5_C, SEL_SCIF5_2), 636 PINMUX_IPSR_MSEL(IP4_7_4, SCL2_D, SEL_I2C02_3), 637 PINMUX_IPSR_GPSR(IP4_7_4, A0), 638 PINMUX_IPSR_GPSR(IP4_11_8, DU0_DR1), 639 PINMUX_IPSR_MSEL(IP4_11_8, TX5_C, SEL_SCIF5_2), 640 PINMUX_IPSR_MSEL(IP4_11_8, SDA2_D, SEL_I2C02_3), 641 PINMUX_IPSR_GPSR(IP4_11_8, A1), 642 PINMUX_IPSR_GPSR(IP4_15_12, DU0_DR2), 643 PINMUX_IPSR_MSEL(IP4_15_12, RX0_D, SEL_SCIF0_3), 644 PINMUX_IPSR_MSEL(IP4_15_12, SCL0_E, SEL_I2C00_4), 645 PINMUX_IPSR_GPSR(IP4_15_12, A2), 646 PINMUX_IPSR_GPSR(IP4_19_16, DU0_DR3), 647 PINMUX_IPSR_MSEL(IP4_19_16, TX0_D, SEL_SCIF0_3), 648 PINMUX_IPSR_MSEL(IP4_19_16, SDA0_E, SEL_I2C00_4), 649 PINMUX_IPSR_GPSR(IP4_19_16, PWM0_B), 650 PINMUX_IPSR_GPSR(IP4_19_16, A3), 651 PINMUX_IPSR_GPSR(IP4_23_20, DU0_DR4), 652 PINMUX_IPSR_MSEL(IP4_23_20, RX1_D, SEL_SCIF1_3), 653 PINMUX_IPSR_GPSR(IP4_23_20, A4), 654 PINMUX_IPSR_GPSR(IP4_27_24, DU0_DR5), 655 PINMUX_IPSR_MSEL(IP4_27_24, TX1_D, SEL_SCIF1_3), 656 PINMUX_IPSR_GPSR(IP4_27_24, PWM1_B), 657 PINMUX_IPSR_GPSR(IP4_27_24, A5), 658 PINMUX_IPSR_GPSR(IP4_31_28, DU0_DR6), 659 PINMUX_IPSR_MSEL(IP4_31_28, RX2_C, SEL_SCIF2_2), 660 PINMUX_IPSR_GPSR(IP4_31_28, A6), 661 662 /* IPSR5 */ 663 PINMUX_IPSR_GPSR(IP5_3_0, DU0_DR7), 664 PINMUX_IPSR_MSEL(IP5_3_0, TX2_C, SEL_SCIF2_2), 665 PINMUX_IPSR_GPSR(IP5_3_0, PWM2_B), 666 PINMUX_IPSR_GPSR(IP5_3_0, A7), 667 PINMUX_IPSR_GPSR(IP5_7_4, DU0_DG0), 668 PINMUX_IPSR_MSEL(IP5_7_4, RX3_B, SEL_SCIF3_1), 669 PINMUX_IPSR_MSEL(IP5_7_4, SCL3_D, SEL_I2C03_3), 670 PINMUX_IPSR_GPSR(IP5_7_4, A8), 671 PINMUX_IPSR_GPSR(IP5_11_8, DU0_DG1), 672 PINMUX_IPSR_MSEL(IP5_11_8, TX3_B, SEL_SCIF3_1), 673 PINMUX_IPSR_MSEL(IP5_11_8, SDA3_D, SEL_I2C03_3), 674 PINMUX_IPSR_GPSR(IP5_11_8, PWM3_B), 675 PINMUX_IPSR_GPSR(IP5_11_8, A9), 676 PINMUX_IPSR_GPSR(IP5_15_12, DU0_DG2), 677 PINMUX_IPSR_MSEL(IP5_15_12, RX4_D, SEL_SCIF4_3), 678 PINMUX_IPSR_GPSR(IP5_15_12, A10), 679 PINMUX_IPSR_GPSR(IP5_19_16, DU0_DG3), 680 PINMUX_IPSR_MSEL(IP5_19_16, TX4_D, SEL_SCIF4_3), 681 PINMUX_IPSR_GPSR(IP5_19_16, PWM4_B), 682 PINMUX_IPSR_GPSR(IP5_19_16, A11), 683 PINMUX_IPSR_GPSR(IP5_23_20, DU0_DG4), 684 PINMUX_IPSR_MSEL(IP5_23_20, HRX0_A, SEL_HSCIF0_0), 685 PINMUX_IPSR_GPSR(IP5_23_20, A12), 686 PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5), 687 PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0), 688 PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B), 689 PINMUX_IPSR_GPSR(IP5_27_24, A13), 690 PINMUX_IPSR_GPSR(IP5_31_28, DU0_DG6), 691 PINMUX_IPSR_MSEL(IP5_31_28, HRX1_C, SEL_HSCIF1_2), 692 PINMUX_IPSR_GPSR(IP5_31_28, A14), 693 694 /* IPSR6 */ 695 PINMUX_IPSR_GPSR(IP6_3_0, DU0_DG7), 696 PINMUX_IPSR_MSEL(IP6_3_0, HTX1_C, SEL_HSCIF1_2), 697 PINMUX_IPSR_GPSR(IP6_3_0, PWM6_B), 698 PINMUX_IPSR_GPSR(IP6_3_0, A15), 699 PINMUX_IPSR_GPSR(IP6_7_4, DU0_DB0), 700 PINMUX_IPSR_MSEL(IP6_7_4, SCL4_D, SEL_I2C04_3), 701 PINMUX_IPSR_MSEL(IP6_7_4, CAN0_RX_C, SEL_CAN0_2), 702 PINMUX_IPSR_GPSR(IP6_7_4, A16), 703 PINMUX_IPSR_GPSR(IP6_11_8, DU0_DB1), 704 PINMUX_IPSR_MSEL(IP6_11_8, SDA4_D, SEL_I2C04_3), 705 PINMUX_IPSR_MSEL(IP6_11_8, CAN0_TX_C, SEL_CAN0_2), 706 PINMUX_IPSR_GPSR(IP6_11_8, A17), 707 PINMUX_IPSR_GPSR(IP6_15_12, DU0_DB2), 708 PINMUX_IPSR_GPSR(IP6_15_12, HCTS0_N), 709 PINMUX_IPSR_GPSR(IP6_15_12, A18), 710 PINMUX_IPSR_GPSR(IP6_19_16, DU0_DB3), 711 PINMUX_IPSR_GPSR(IP6_19_16, HRTS0_N), 712 PINMUX_IPSR_GPSR(IP6_19_16, A19), 713 PINMUX_IPSR_GPSR(IP6_23_20, DU0_DB4), 714 PINMUX_IPSR_MSEL(IP6_23_20, HCTS1_N_C, SEL_HSCIF1_2), 715 PINMUX_IPSR_GPSR(IP6_23_20, A20), 716 PINMUX_IPSR_GPSR(IP6_27_24, DU0_DB5), 717 PINMUX_IPSR_MSEL(IP6_27_24, HRTS1_N_C, SEL_HSCIF1_2), 718 PINMUX_IPSR_GPSR(IP6_27_24, A21), 719 PINMUX_IPSR_GPSR(IP6_31_28, DU0_DB6), 720 PINMUX_IPSR_GPSR(IP6_31_28, A22), 721 722 /* IPSR7 */ 723 PINMUX_IPSR_GPSR(IP7_3_0, DU0_DB7), 724 PINMUX_IPSR_GPSR(IP7_3_0, A23), 725 PINMUX_IPSR_GPSR(IP7_7_4, DU0_DOTCLKIN), 726 PINMUX_IPSR_GPSR(IP7_7_4, A24), 727 PINMUX_IPSR_GPSR(IP7_11_8, DU0_DOTCLKOUT0), 728 PINMUX_IPSR_GPSR(IP7_11_8, A25), 729 PINMUX_IPSR_GPSR(IP7_15_12, DU0_DOTCLKOUT1), 730 PINMUX_IPSR_MSEL(IP7_15_12, MSIOF2_RXD_B, SEL_MSIOF2_1), 731 PINMUX_IPSR_GPSR(IP7_15_12, CS1_N_A26), 732 PINMUX_IPSR_GPSR(IP7_19_16, DU0_EXHSYNC_DU0_HSYNC), 733 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF2_TXD_B, SEL_MSIOF2_1), 734 PINMUX_IPSR_GPSR(IP7_19_16, DREQ0_N), 735 PINMUX_IPSR_GPSR(IP7_23_20, DU0_EXVSYNC_DU0_VSYNC), 736 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF2_SYNC_B, SEL_MSIOF2_1), 737 PINMUX_IPSR_GPSR(IP7_23_20, DACK0), 738 PINMUX_IPSR_GPSR(IP7_27_24, DU0_EXODDF_DU0_ODDF_DISP_CDE), 739 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF2_SCK_B, SEL_MSIOF2_1), 740 PINMUX_IPSR_GPSR(IP7_27_24, DRACK0), 741 PINMUX_IPSR_GPSR(IP7_31_28, DU0_DISP), 742 PINMUX_IPSR_MSEL(IP7_31_28, CAN1_RX_C, SEL_CAN1_2), 743 744 /* IPSR8 */ 745 PINMUX_IPSR_GPSR(IP8_3_0, DU0_CDE), 746 PINMUX_IPSR_MSEL(IP8_3_0, CAN1_TX_C, SEL_CAN1_2), 747 PINMUX_IPSR_GPSR(IP8_7_4, VI1_CLK), 748 PINMUX_IPSR_GPSR(IP8_7_4, AVB_RX_CLK), 749 PINMUX_IPSR_GPSR(IP8_7_4, ETH_REF_CLK), 750 PINMUX_IPSR_GPSR(IP8_11_8, VI1_DATA0), 751 PINMUX_IPSR_GPSR(IP8_11_8, AVB_RX_DV), 752 PINMUX_IPSR_GPSR(IP8_11_8, ETH_CRS_DV), 753 PINMUX_IPSR_GPSR(IP8_15_12, VI1_DATA1), 754 PINMUX_IPSR_GPSR(IP8_15_12, AVB_RXD0), 755 PINMUX_IPSR_GPSR(IP8_15_12, ETH_RXD0), 756 PINMUX_IPSR_GPSR(IP8_19_16, VI1_DATA2), 757 PINMUX_IPSR_GPSR(IP8_19_16, AVB_RXD1), 758 PINMUX_IPSR_GPSR(IP8_19_16, ETH_RXD1), 759 PINMUX_IPSR_GPSR(IP8_23_20, VI1_DATA3), 760 PINMUX_IPSR_GPSR(IP8_23_20, AVB_RXD2), 761 PINMUX_IPSR_GPSR(IP8_23_20, ETH_MDIO), 762 PINMUX_IPSR_GPSR(IP8_27_24, VI1_DATA4), 763 PINMUX_IPSR_GPSR(IP8_27_24, AVB_RXD3), 764 PINMUX_IPSR_GPSR(IP8_27_24, ETH_RX_ER), 765 PINMUX_IPSR_GPSR(IP8_31_28, VI1_DATA5), 766 PINMUX_IPSR_GPSR(IP8_31_28, AVB_RXD4), 767 PINMUX_IPSR_GPSR(IP8_31_28, ETH_LINK), 768 769 /* IPSR9 */ 770 PINMUX_IPSR_GPSR(IP9_3_0, VI1_DATA6), 771 PINMUX_IPSR_GPSR(IP9_3_0, AVB_RXD5), 772 PINMUX_IPSR_GPSR(IP9_3_0, ETH_TXD1), 773 PINMUX_IPSR_GPSR(IP9_7_4, VI1_DATA7), 774 PINMUX_IPSR_GPSR(IP9_7_4, AVB_RXD6), 775 PINMUX_IPSR_GPSR(IP9_7_4, ETH_TX_EN), 776 PINMUX_IPSR_GPSR(IP9_11_8, VI1_CLKENB), 777 PINMUX_IPSR_MSEL(IP9_11_8, SCL3_A, SEL_I2C03_0), 778 PINMUX_IPSR_GPSR(IP9_11_8, AVB_RXD7), 779 PINMUX_IPSR_GPSR(IP9_11_8, ETH_MAGIC), 780 PINMUX_IPSR_GPSR(IP9_15_12, VI1_FIELD), 781 PINMUX_IPSR_MSEL(IP9_15_12, SDA3_A, SEL_I2C03_0), 782 PINMUX_IPSR_GPSR(IP9_15_12, AVB_RX_ER), 783 PINMUX_IPSR_GPSR(IP9_15_12, ETH_TXD0), 784 PINMUX_IPSR_GPSR(IP9_19_16, VI1_HSYNC_N), 785 PINMUX_IPSR_MSEL(IP9_19_16, RX0_B, SEL_SCIF0_1), 786 PINMUX_IPSR_MSEL(IP9_19_16, SCL0_C, SEL_I2C00_2), 787 PINMUX_IPSR_GPSR(IP9_19_16, AVB_GTXREFCLK), 788 PINMUX_IPSR_GPSR(IP9_19_16, ETH_MDC), 789 PINMUX_IPSR_GPSR(IP9_23_20, VI1_VSYNC_N), 790 PINMUX_IPSR_MSEL(IP9_23_20, TX0_B, SEL_SCIF0_1), 791 PINMUX_IPSR_MSEL(IP9_23_20, SDA0_C, SEL_I2C00_2), 792 PINMUX_IPSR_GPSR(IP9_23_20, AUDIO_CLKOUT_B), 793 PINMUX_IPSR_GPSR(IP9_23_20, AVB_TX_CLK), 794 PINMUX_IPSR_GPSR(IP9_27_24, VI1_DATA8), 795 PINMUX_IPSR_MSEL(IP9_27_24, SCL2_B, SEL_I2C02_1), 796 PINMUX_IPSR_GPSR(IP9_27_24, AVB_TX_EN), 797 PINMUX_IPSR_GPSR(IP9_31_28, VI1_DATA9), 798 PINMUX_IPSR_MSEL(IP9_31_28, SDA2_B, SEL_I2C02_1), 799 PINMUX_IPSR_GPSR(IP9_31_28, AVB_TXD0), 800 801 /* IPSR10 */ 802 PINMUX_IPSR_GPSR(IP10_3_0, VI1_DATA10), 803 PINMUX_IPSR_MSEL(IP10_3_0, CAN0_RX_B, SEL_CAN0_1), 804 PINMUX_IPSR_GPSR(IP10_3_0, AVB_TXD1), 805 PINMUX_IPSR_GPSR(IP10_7_4, VI1_DATA11), 806 PINMUX_IPSR_MSEL(IP10_7_4, CAN0_TX_B, SEL_CAN0_1), 807 PINMUX_IPSR_GPSR(IP10_7_4, AVB_TXD2), 808 PINMUX_IPSR_GPSR(IP10_11_8, AVB_TXD3), 809 PINMUX_IPSR_MSEL(IP10_11_8, AUDIO_CLKA_B, SEL_ADGA_1), 810 PINMUX_IPSR_MSEL(IP10_11_8, SSI_SCK1_D, SEL_SSI1_3), 811 PINMUX_IPSR_MSEL(IP10_11_8, RX5_F, SEL_SCIF5_5), 812 PINMUX_IPSR_MSEL(IP10_11_8, MSIOF0_RXD_B, SEL_MSIOF0_1), 813 PINMUX_IPSR_GPSR(IP10_15_12, AVB_TXD4), 814 PINMUX_IPSR_MSEL(IP10_15_12, AUDIO_CLKB_B, SEL_ADGB_1), 815 PINMUX_IPSR_MSEL(IP10_15_12, SSI_WS1_D, SEL_SSI1_3), 816 PINMUX_IPSR_MSEL(IP10_15_12, TX5_F, SEL_SCIF5_5), 817 PINMUX_IPSR_MSEL(IP10_15_12, MSIOF0_TXD_B, SEL_MSIOF0_1), 818 PINMUX_IPSR_GPSR(IP10_19_16, AVB_TXD5), 819 PINMUX_IPSR_MSEL(IP10_19_16, SCIF_CLK_B, SEL_SCIFCLK_1), 820 PINMUX_IPSR_MSEL(IP10_19_16, AUDIO_CLKC_B, SEL_ADGC_1), 821 PINMUX_IPSR_MSEL(IP10_19_16, SSI_SDATA1_D, SEL_SSI1_3), 822 PINMUX_IPSR_MSEL(IP10_19_16, MSIOF0_SCK_B, SEL_MSIOF0_1), 823 PINMUX_IPSR_MSEL(IP10_23_20, SCL0_A, SEL_I2C00_0), 824 PINMUX_IPSR_MSEL(IP10_23_20, RX0_C, SEL_SCIF0_2), 825 PINMUX_IPSR_GPSR(IP10_23_20, PWM5_A), 826 PINMUX_IPSR_MSEL(IP10_23_20, TCLK1_B, SEL_TMU1_1), 827 PINMUX_IPSR_GPSR(IP10_23_20, AVB_TXD6), 828 PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_D, SEL_CAN1_3), 829 PINMUX_IPSR_MSEL(IP10_23_20, MSIOF0_SYNC_B, SEL_MSIOF0_1), 830 PINMUX_IPSR_MSEL(IP10_27_24, SDA0_A, SEL_I2C00_0), 831 PINMUX_IPSR_MSEL(IP10_27_24, TX0_C, SEL_SCIF0_2), 832 PINMUX_IPSR_GPSR(IP10_27_24, IRQ5), 833 PINMUX_IPSR_MSEL(IP10_27_24, CAN_CLK_A, SEL_CANCLK_0), 834 PINMUX_IPSR_GPSR(IP10_27_24, AVB_GTX_CLK), 835 PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_D, SEL_CAN1_3), 836 PINMUX_IPSR_GPSR(IP10_27_24, DVC_MUTE), 837 PINMUX_IPSR_MSEL(IP10_31_28, SCL1_A, SEL_I2C01_0), 838 PINMUX_IPSR_MSEL(IP10_31_28, RX4_A, SEL_SCIF4_0), 839 PINMUX_IPSR_GPSR(IP10_31_28, PWM5_D), 840 PINMUX_IPSR_GPSR(IP10_31_28, DU1_DR0), 841 PINMUX_IPSR_MSEL(IP10_31_28, SSI_SCK6_B, SEL_SSI6_1), 842 PINMUX_IPSR_GPSR(IP10_31_28, VI0_G0), 843 844 /* IPSR11 */ 845 PINMUX_IPSR_MSEL(IP11_3_0, SDA1_A, SEL_I2C01_0), 846 PINMUX_IPSR_MSEL(IP11_3_0, TX4_A, SEL_SCIF4_0), 847 PINMUX_IPSR_GPSR(IP11_3_0, DU1_DR1), 848 PINMUX_IPSR_MSEL(IP11_3_0, SSI_WS6_B, SEL_SSI6_1), 849 PINMUX_IPSR_GPSR(IP11_3_0, VI0_G1), 850 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF0_RXD_A, SEL_MSIOF0_0), 851 PINMUX_IPSR_MSEL(IP11_7_4, RX5_A, SEL_SCIF5_0), 852 PINMUX_IPSR_MSEL(IP11_7_4, SCL2_C, SEL_I2C02_2), 853 PINMUX_IPSR_GPSR(IP11_7_4, DU1_DR2), 854 PINMUX_IPSR_GPSR(IP11_7_4, QSPI1_MOSI_QSPI1_IO0), 855 PINMUX_IPSR_MSEL(IP11_7_4, SSI_SDATA6_B, SEL_SSI6_1), 856 PINMUX_IPSR_GPSR(IP11_7_4, VI0_G2), 857 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF0_TXD_A, SEL_MSIOF0_0), 858 PINMUX_IPSR_MSEL(IP11_11_8, TX5_A, SEL_SCIF5_0), 859 PINMUX_IPSR_MSEL(IP11_11_8, SDA2_C, SEL_I2C02_2), 860 PINMUX_IPSR_GPSR(IP11_11_8, DU1_DR3), 861 PINMUX_IPSR_GPSR(IP11_11_8, QSPI1_MISO_QSPI1_IO1), 862 PINMUX_IPSR_MSEL(IP11_11_8, SSI_WS78_B, SEL_SSI7_1), 863 PINMUX_IPSR_GPSR(IP11_11_8, VI0_G3), 864 PINMUX_IPSR_MSEL(IP11_15_12, MSIOF0_SCK_A, SEL_MSIOF0_0), 865 PINMUX_IPSR_GPSR(IP11_15_12, IRQ0), 866 PINMUX_IPSR_GPSR(IP11_15_12, DU1_DR4), 867 PINMUX_IPSR_GPSR(IP11_15_12, QSPI1_SPCLK), 868 PINMUX_IPSR_MSEL(IP11_15_12, SSI_SCK78_B, SEL_SSI7_1), 869 PINMUX_IPSR_GPSR(IP11_15_12, VI0_G4), 870 PINMUX_IPSR_MSEL(IP11_19_16, MSIOF0_SYNC_A, SEL_MSIOF0_0), 871 PINMUX_IPSR_GPSR(IP11_19_16, PWM1_A), 872 PINMUX_IPSR_GPSR(IP11_19_16, DU1_DR5), 873 PINMUX_IPSR_GPSR(IP11_19_16, QSPI1_IO2), 874 PINMUX_IPSR_MSEL(IP11_19_16, SSI_SDATA7_B, SEL_SSI7_1), 875 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF0_SS1_A, SEL_MSIOF0_0), 876 PINMUX_IPSR_GPSR(IP11_23_20, DU1_DR6), 877 PINMUX_IPSR_GPSR(IP11_23_20, QSPI1_IO3), 878 PINMUX_IPSR_MSEL(IP11_23_20, SSI_SDATA8_B, SEL_SSI8_1), 879 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF0_SS2_A, SEL_MSIOF0_0), 880 PINMUX_IPSR_GPSR(IP11_27_24, DU1_DR7), 881 PINMUX_IPSR_GPSR(IP11_27_24, QSPI1_SSL), 882 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_A, SEL_HSCIF1_0), 883 PINMUX_IPSR_MSEL(IP11_31_28, SCL4_A, SEL_I2C04_0), 884 PINMUX_IPSR_GPSR(IP11_31_28, PWM6_A), 885 PINMUX_IPSR_GPSR(IP11_31_28, DU1_DG0), 886 PINMUX_IPSR_MSEL(IP11_31_28, RX0_A, SEL_SCIF0_0), 887 888 /* IPSR12 */ 889 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_A, SEL_HSCIF1_0), 890 PINMUX_IPSR_MSEL(IP12_3_0, SDA4_A, SEL_I2C04_0), 891 PINMUX_IPSR_GPSR(IP12_3_0, DU1_DG1), 892 PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0), 893 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_A, SEL_HSCIF1_0), 894 PINMUX_IPSR_GPSR(IP12_7_4, PWM2_A), 895 PINMUX_IPSR_GPSR(IP12_7_4, DU1_DG2), 896 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_B, SEL_RCN_1), 897 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_A, SEL_HSCIF1_0), 898 PINMUX_IPSR_GPSR(IP12_11_8, DU1_DG3), 899 PINMUX_IPSR_MSEL(IP12_11_8, SSI_WS1_B, SEL_SSI1_1), 900 PINMUX_IPSR_GPSR(IP12_11_8, IRQ1), 901 PINMUX_IPSR_GPSR(IP12_15_12, SD2_CLK), 902 PINMUX_IPSR_GPSR(IP12_15_12, HSCK1), 903 PINMUX_IPSR_GPSR(IP12_15_12, DU1_DG4), 904 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SCK1_B, SEL_SSI1_1), 905 PINMUX_IPSR_GPSR(IP12_19_16, SD2_CMD), 906 PINMUX_IPSR_MSEL(IP12_19_16, SCIF1_SCK_A, SEL_SCIF1_0), 907 PINMUX_IPSR_MSEL(IP12_19_16, TCLK2_A, SEL_TMU2_0), 908 PINMUX_IPSR_GPSR(IP12_19_16, DU1_DG5), 909 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SCK2_B, SEL_SSI2_1), 910 PINMUX_IPSR_GPSR(IP12_19_16, PWM3_A), 911 PINMUX_IPSR_GPSR(IP12_23_20, SD2_DAT0), 912 PINMUX_IPSR_MSEL(IP12_23_20, RX1_A, SEL_SCIF1_0), 913 PINMUX_IPSR_MSEL(IP12_23_20, SCL1_E, SEL_I2C01_4), 914 PINMUX_IPSR_GPSR(IP12_23_20, DU1_DG6), 915 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SDATA1_B, SEL_SSI1_1), 916 PINMUX_IPSR_GPSR(IP12_27_24, SD2_DAT1), 917 PINMUX_IPSR_MSEL(IP12_27_24, TX1_A, SEL_SCIF1_0), 918 PINMUX_IPSR_MSEL(IP12_27_24, SDA1_E, SEL_I2C01_4), 919 PINMUX_IPSR_GPSR(IP12_27_24, DU1_DG7), 920 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS2_B, SEL_SSI2_1), 921 PINMUX_IPSR_GPSR(IP12_31_28, SD2_DAT2), 922 PINMUX_IPSR_MSEL(IP12_31_28, RX2_A, SEL_SCIF2_0), 923 PINMUX_IPSR_GPSR(IP12_31_28, DU1_DB0), 924 PINMUX_IPSR_MSEL(IP12_31_28, SSI_SDATA2_B, SEL_SSI2_1), 925 926 /* IPSR13 */ 927 PINMUX_IPSR_GPSR(IP13_3_0, SD2_DAT3), 928 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0), 929 PINMUX_IPSR_GPSR(IP13_3_0, DU1_DB1), 930 PINMUX_IPSR_MSEL(IP13_3_0, SSI_WS9_B, SEL_SSI9_1), 931 PINMUX_IPSR_GPSR(IP13_7_4, SD2_CD), 932 PINMUX_IPSR_MSEL(IP13_7_4, SCIF2_SCK_A, SEL_SCIF2_CLK_0), 933 PINMUX_IPSR_GPSR(IP13_7_4, DU1_DB2), 934 PINMUX_IPSR_MSEL(IP13_7_4, SSI_SCK9_B, SEL_SSI9_1), 935 PINMUX_IPSR_GPSR(IP13_11_8, SD2_WP), 936 PINMUX_IPSR_GPSR(IP13_11_8, SCIF3_SCK), 937 PINMUX_IPSR_GPSR(IP13_11_8, DU1_DB3), 938 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA9_B, SEL_SSI9_1), 939 PINMUX_IPSR_MSEL(IP13_15_12, RX3_A, SEL_SCIF3_0), 940 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_C, SEL_I2C01_2), 941 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_B, SEL_MSIOF1_1), 942 PINMUX_IPSR_GPSR(IP13_15_12, DU1_DB4), 943 PINMUX_IPSR_MSEL(IP13_15_12, AUDIO_CLKA_C, SEL_ADGA_2), 944 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA4_B, SEL_SSI4_1), 945 PINMUX_IPSR_MSEL(IP13_19_16, TX3_A, SEL_SCIF3_0), 946 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_C, SEL_I2C01_2), 947 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_B, SEL_MSIOF1_1), 948 PINMUX_IPSR_GPSR(IP13_19_16, DU1_DB5), 949 PINMUX_IPSR_MSEL(IP13_19_16, AUDIO_CLKB_C, SEL_ADGB_2), 950 PINMUX_IPSR_MSEL(IP13_19_16, SSI_WS4_B, SEL_SSI4_1), 951 PINMUX_IPSR_MSEL(IP13_23_20, SCL2_A, SEL_I2C02_0), 952 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SCK_B, SEL_MSIOF1_1), 953 PINMUX_IPSR_GPSR(IP13_23_20, DU1_DB6), 954 PINMUX_IPSR_MSEL(IP13_23_20, AUDIO_CLKC_C, SEL_ADGC_2), 955 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK4_B, SEL_SSI4_1), 956 PINMUX_IPSR_MSEL(IP13_27_24, SDA2_A, SEL_I2C02_0), 957 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SYNC_B, SEL_MSIOF1_1), 958 PINMUX_IPSR_GPSR(IP13_27_24, DU1_DB7), 959 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT_C), 960 PINMUX_IPSR_MSEL(IP13_31_28, SSI_SCK5_A, SEL_SSI5_0), 961 PINMUX_IPSR_GPSR(IP13_31_28, DU1_DOTCLKOUT1), 962 963 /* IPSR14 */ 964 PINMUX_IPSR_MSEL(IP14_3_0, SSI_WS5_A, SEL_SSI5_0), 965 PINMUX_IPSR_MSEL(IP14_3_0, SCL3_C, SEL_I2C03_2), 966 PINMUX_IPSR_GPSR(IP14_3_0, DU1_DOTCLKIN), 967 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA5_A, SEL_SSI5_0), 968 PINMUX_IPSR_MSEL(IP14_7_4, SDA3_C, SEL_I2C03_2), 969 PINMUX_IPSR_GPSR(IP14_7_4, DU1_DOTCLKOUT0), 970 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK6_A, SEL_SSI6_0), 971 PINMUX_IPSR_GPSR(IP14_11_8, DU1_EXODDF_DU1_ODDF_DISP_CDE), 972 PINMUX_IPSR_MSEL(IP14_15_12, SSI_WS6_A, SEL_SSI6_0), 973 PINMUX_IPSR_MSEL(IP14_15_12, SCL4_C, SEL_I2C04_2), 974 PINMUX_IPSR_GPSR(IP14_15_12, DU1_EXHSYNC_DU1_HSYNC), 975 PINMUX_IPSR_MSEL(IP14_19_16, SSI_SDATA6_A, SEL_SSI6_0), 976 PINMUX_IPSR_MSEL(IP14_19_16, SDA4_C, SEL_I2C04_2), 977 PINMUX_IPSR_GPSR(IP14_19_16, DU1_EXVSYNC_DU1_VSYNC), 978 PINMUX_IPSR_MSEL(IP14_23_20, SSI_SCK78_A, SEL_SSI7_0), 979 PINMUX_IPSR_MSEL(IP14_23_20, SDA4_E, SEL_I2C04_4), 980 PINMUX_IPSR_GPSR(IP14_23_20, DU1_DISP), 981 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS78_A, SEL_SSI7_0), 982 PINMUX_IPSR_MSEL(IP14_27_24, SCL4_E, SEL_I2C04_4), 983 PINMUX_IPSR_GPSR(IP14_27_24, DU1_CDE), 984 PINMUX_IPSR_MSEL(IP14_31_28, SSI_SDATA7_A, SEL_SSI7_0), 985 PINMUX_IPSR_GPSR(IP14_31_28, IRQ8), 986 PINMUX_IPSR_MSEL(IP14_31_28, AUDIO_CLKA_D, SEL_ADGA_3), 987 PINMUX_IPSR_MSEL(IP14_31_28, CAN_CLK_D, SEL_CANCLK_3), 988 PINMUX_IPSR_GPSR(IP14_31_28, VI0_G5), 989 990 /* IPSR15 */ 991 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SCK0129_A, SEL_SSI0_0), 992 PINMUX_IPSR_MSEL(IP15_3_0, MSIOF1_RXD_A, SEL_MSIOF1_0), 993 PINMUX_IPSR_MSEL(IP15_3_0, RX5_D, SEL_SCIF5_3), 994 PINMUX_IPSR_GPSR(IP15_3_0, VI0_G6), 995 PINMUX_IPSR_MSEL(IP15_7_4, SSI_WS0129_A, SEL_SSI0_0), 996 PINMUX_IPSR_MSEL(IP15_7_4, MSIOF1_TXD_A, SEL_MSIOF1_0), 997 PINMUX_IPSR_MSEL(IP15_7_4, TX5_D, SEL_SCIF5_3), 998 PINMUX_IPSR_GPSR(IP15_7_4, VI0_G7), 999 PINMUX_IPSR_MSEL(IP15_11_8, SSI_SDATA0_A, SEL_SSI0_0), 1000 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SYNC_A, SEL_MSIOF1_0), 1001 PINMUX_IPSR_GPSR(IP15_11_8, PWM0_C), 1002 PINMUX_IPSR_GPSR(IP15_11_8, VI0_R0), 1003 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK34), 1004 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_A, SEL_MSIOF1_0), 1005 PINMUX_IPSR_GPSR(IP15_15_12, AVB_MDC), 1006 PINMUX_IPSR_GPSR(IP15_15_12, DACK1), 1007 PINMUX_IPSR_GPSR(IP15_15_12, VI0_R1), 1008 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS34), 1009 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SS1_A, SEL_MSIOF1_0), 1010 PINMUX_IPSR_GPSR(IP15_19_16, AVB_MDIO), 1011 PINMUX_IPSR_MSEL(IP15_19_16, CAN1_RX_A, SEL_CAN1_0), 1012 PINMUX_IPSR_GPSR(IP15_19_16, DREQ1_N), 1013 PINMUX_IPSR_GPSR(IP15_19_16, VI0_R2), 1014 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA3), 1015 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SS2_A, SEL_MSIOF1_0), 1016 PINMUX_IPSR_GPSR(IP15_23_20, AVB_LINK), 1017 PINMUX_IPSR_MSEL(IP15_23_20, CAN1_TX_A, SEL_CAN1_0), 1018 PINMUX_IPSR_GPSR(IP15_23_20, DREQ2_N), 1019 PINMUX_IPSR_GPSR(IP15_23_20, VI0_R3), 1020 PINMUX_IPSR_MSEL(IP15_27_24, SSI_SCK4_A, SEL_SSI4_0), 1021 PINMUX_IPSR_GPSR(IP15_27_24, AVB_MAGIC), 1022 PINMUX_IPSR_GPSR(IP15_27_24, VI0_R4), 1023 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS4_A, SEL_SSI4_0), 1024 PINMUX_IPSR_GPSR(IP15_31_28, AVB_PHY_INT), 1025 PINMUX_IPSR_GPSR(IP15_31_28, VI0_R5), 1026 1027 /* IPSR16 */ 1028 PINMUX_IPSR_MSEL(IP16_3_0, SSI_SDATA4_A, SEL_SSI4_0), 1029 PINMUX_IPSR_GPSR(IP16_3_0, AVB_CRS), 1030 PINMUX_IPSR_GPSR(IP16_3_0, VI0_R6), 1031 PINMUX_IPSR_MSEL(IP16_7_4, SSI_SCK1_A, SEL_SSI1_0), 1032 PINMUX_IPSR_MSEL(IP16_7_4, SCIF1_SCK_B, SEL_SCIF1_1), 1033 PINMUX_IPSR_GPSR(IP16_7_4, PWM1_D), 1034 PINMUX_IPSR_GPSR(IP16_7_4, IRQ9), 1035 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_RCN_0), 1036 PINMUX_IPSR_GPSR(IP16_7_4, DACK2), 1037 PINMUX_IPSR_GPSR(IP16_7_4, VI0_CLK), 1038 PINMUX_IPSR_GPSR(IP16_7_4, AVB_COL), 1039 PINMUX_IPSR_MSEL(IP16_11_8, SSI_SDATA8_A, SEL_SSI8_0), 1040 PINMUX_IPSR_MSEL(IP16_11_8, RX1_B, SEL_SCIF1_1), 1041 PINMUX_IPSR_MSEL(IP16_11_8, CAN0_RX_D, SEL_CAN0_3), 1042 PINMUX_IPSR_MSEL(IP16_11_8, AVB_AVTP_CAPTURE_B, SEL_AVB_1), 1043 PINMUX_IPSR_GPSR(IP16_11_8, VI0_R7), 1044 PINMUX_IPSR_MSEL(IP16_15_12, SSI_WS1_A, SEL_SSI1_0), 1045 PINMUX_IPSR_MSEL(IP16_15_12, TX1_B, SEL_SCIF1_1), 1046 PINMUX_IPSR_MSEL(IP16_15_12, CAN0_TX_D, SEL_CAN0_3), 1047 PINMUX_IPSR_MSEL(IP16_15_12, AVB_AVTP_MATCH_B, SEL_AVB_1), 1048 PINMUX_IPSR_GPSR(IP16_15_12, VI0_DATA0_VI0_B0), 1049 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SDATA1_A, SEL_SSI1_0), 1050 PINMUX_IPSR_MSEL(IP16_19_16, HRX1_B, SEL_HSCIF1_1), 1051 PINMUX_IPSR_GPSR(IP16_19_16, VI0_DATA1_VI0_B1), 1052 PINMUX_IPSR_MSEL(IP16_23_20, SSI_SCK2_A, SEL_SSI2_0), 1053 PINMUX_IPSR_MSEL(IP16_23_20, HTX1_B, SEL_HSCIF1_1), 1054 PINMUX_IPSR_GPSR(IP16_23_20, AVB_TXD7), 1055 PINMUX_IPSR_GPSR(IP16_23_20, VI0_DATA2_VI0_B2), 1056 PINMUX_IPSR_MSEL(IP16_27_24, SSI_WS2_A, SEL_SSI2_0), 1057 PINMUX_IPSR_MSEL(IP16_27_24, HCTS1_N_B, SEL_HSCIF1_1), 1058 PINMUX_IPSR_GPSR(IP16_27_24, AVB_TX_ER), 1059 PINMUX_IPSR_GPSR(IP16_27_24, VI0_DATA3_VI0_B3), 1060 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA2_A, SEL_SSI2_0), 1061 PINMUX_IPSR_MSEL(IP16_31_28, HRTS1_N_B, SEL_HSCIF1_1), 1062 PINMUX_IPSR_GPSR(IP16_31_28, VI0_DATA4_VI0_B4), 1063 1064 /* IPSR17 */ 1065 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_A, SEL_SSI9_0), 1066 PINMUX_IPSR_MSEL(IP17_3_0, RX2_B, SEL_SCIF2_1), 1067 PINMUX_IPSR_MSEL(IP17_3_0, SCL3_E, SEL_I2C03_4), 1068 PINMUX_IPSR_GPSR(IP17_3_0, EX_WAIT1), 1069 PINMUX_IPSR_GPSR(IP17_3_0, VI0_DATA5_VI0_B5), 1070 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_A, SEL_SSI9_0), 1071 PINMUX_IPSR_MSEL(IP17_7_4, TX2_B, SEL_SCIF2_1), 1072 PINMUX_IPSR_MSEL(IP17_7_4, SDA3_E, SEL_I2C03_4), 1073 PINMUX_IPSR_GPSR(IP17_7_4, VI0_DATA6_VI0_B6), 1074 PINMUX_IPSR_MSEL(IP17_11_8, SSI_SDATA9_A, SEL_SSI9_0), 1075 PINMUX_IPSR_GPSR(IP17_11_8, SCIF2_SCK_B), 1076 PINMUX_IPSR_GPSR(IP17_11_8, PWM2_D), 1077 PINMUX_IPSR_GPSR(IP17_11_8, VI0_DATA7_VI0_B7), 1078 PINMUX_IPSR_MSEL(IP17_15_12, AUDIO_CLKA_A, SEL_ADGA_0), 1079 PINMUX_IPSR_MSEL(IP17_15_12, SCL0_B, SEL_I2C00_1), 1080 PINMUX_IPSR_GPSR(IP17_15_12, VI0_CLKENB), 1081 PINMUX_IPSR_MSEL(IP17_19_16, AUDIO_CLKB_A, SEL_ADGB_0), 1082 PINMUX_IPSR_MSEL(IP17_19_16, SDA0_B, SEL_I2C00_1), 1083 PINMUX_IPSR_GPSR(IP17_19_16, VI0_FIELD), 1084 PINMUX_IPSR_MSEL(IP17_23_20, AUDIO_CLKC_A, SEL_ADGC_0), 1085 PINMUX_IPSR_MSEL(IP17_23_20, SCL4_B, SEL_I2C04_1), 1086 PINMUX_IPSR_GPSR(IP17_23_20, VI0_HSYNC_N), 1087 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_A), 1088 PINMUX_IPSR_MSEL(IP17_27_24, SDA4_B, SEL_I2C04_1), 1089 PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N), 1090 }; 1091 1092 static const struct sh_pfc_pin pinmux_pins[] = { 1093 PINMUX_GPIO_GP_ALL(), 1094 }; 1095 1096 /* - MMC -------------------------------------------------------------------- */ 1097 static const unsigned int mmc_data1_pins[] = { 1098 /* D0 */ 1099 RCAR_GP_PIN(0, 15), 1100 }; 1101 static const unsigned int mmc_data1_mux[] = { 1102 MMC0_D0_SDHI1_D0_MARK, 1103 }; 1104 static const unsigned int mmc_data4_pins[] = { 1105 /* D[0:3] */ 1106 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), 1107 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18), 1108 }; 1109 static const unsigned int mmc_data4_mux[] = { 1110 MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, 1111 MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, 1112 }; 1113 static const unsigned int mmc_data8_pins[] = { 1114 /* D[0:3] */ 1115 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16), 1116 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18), 1117 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), 1118 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22), 1119 }; 1120 static const unsigned int mmc_data8_mux[] = { 1121 MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK, 1122 MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, 1123 MMC0_D4_MARK, MMC0_D5_MARK, 1124 MMC0_D6_MARK, MMC0_D7_MARK, 1125 }; 1126 static const unsigned int mmc_ctrl_pins[] = { 1127 /* CLK, CMD */ 1128 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), 1129 }; 1130 static const unsigned int mmc_ctrl_mux[] = { 1131 MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK, 1132 }; 1133 /* - SCIF0 ------------------------------------------------------------------ */ 1134 static const unsigned int scif0_data_a_pins[] = { 1135 /* RX, TX */ 1136 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), 1137 }; 1138 static const unsigned int scif0_data_a_mux[] = { 1139 RX0_A_MARK, TX0_A_MARK, 1140 }; 1141 static const unsigned int scif0_data_b_pins[] = { 1142 /* RX, TX */ 1143 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), 1144 }; 1145 static const unsigned int scif0_data_b_mux[] = { 1146 RX0_B_MARK, TX0_B_MARK, 1147 }; 1148 static const unsigned int scif0_data_c_pins[] = { 1149 /* RX, TX */ 1150 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), 1151 }; 1152 static const unsigned int scif0_data_c_mux[] = { 1153 RX0_C_MARK, TX0_C_MARK, 1154 }; 1155 static const unsigned int scif0_data_d_pins[] = { 1156 /* RX, TX */ 1157 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 1158 }; 1159 static const unsigned int scif0_data_d_mux[] = { 1160 RX0_D_MARK, TX0_D_MARK, 1161 }; 1162 /* - SCIF1 ------------------------------------------------------------------ */ 1163 static const unsigned int scif1_data_a_pins[] = { 1164 /* RX, TX */ 1165 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), 1166 }; 1167 static const unsigned int scif1_data_a_mux[] = { 1168 RX1_A_MARK, TX1_A_MARK, 1169 }; 1170 static const unsigned int scif1_clk_a_pins[] = { 1171 /* SCK */ 1172 RCAR_GP_PIN(4, 15), 1173 }; 1174 static const unsigned int scif1_clk_a_mux[] = { 1175 SCIF1_SCK_A_MARK, 1176 }; 1177 static const unsigned int scif1_data_b_pins[] = { 1178 /* RX, TX */ 1179 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20), 1180 }; 1181 static const unsigned int scif1_data_b_mux[] = { 1182 RX1_B_MARK, TX1_B_MARK, 1183 }; 1184 static const unsigned int scif1_clk_b_pins[] = { 1185 /* SCK */ 1186 RCAR_GP_PIN(5, 18), 1187 }; 1188 static const unsigned int scif1_clk_b_mux[] = { 1189 SCIF1_SCK_B_MARK, 1190 }; 1191 static const unsigned int scif1_data_c_pins[] = { 1192 /* RX, TX */ 1193 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9), 1194 }; 1195 static const unsigned int scif1_data_c_mux[] = { 1196 RX1_C_MARK, TX1_C_MARK, 1197 }; 1198 static const unsigned int scif1_clk_c_pins[] = { 1199 /* SCK */ 1200 RCAR_GP_PIN(1, 7), 1201 }; 1202 static const unsigned int scif1_clk_c_mux[] = { 1203 SCIF1_SCK_C_MARK, 1204 }; 1205 static const unsigned int scif1_data_d_pins[] = { 1206 /* RX, TX */ 1207 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), 1208 }; 1209 static const unsigned int scif1_data_d_mux[] = { 1210 RX1_D_MARK, TX1_D_MARK, 1211 }; 1212 /* - SCIF2 ------------------------------------------------------------------ */ 1213 static const unsigned int scif2_data_a_pins[] = { 1214 /* RX, TX */ 1215 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19), 1216 }; 1217 static const unsigned int scif2_data_a_mux[] = { 1218 RX2_A_MARK, TX2_A_MARK, 1219 }; 1220 static const unsigned int scif2_clk_a_pins[] = { 1221 /* SCK */ 1222 RCAR_GP_PIN(4, 20), 1223 }; 1224 static const unsigned int scif2_clk_a_mux[] = { 1225 SCIF2_SCK_A_MARK, 1226 }; 1227 static const unsigned int scif2_data_b_pins[] = { 1228 /* RX, TX */ 1229 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), 1230 }; 1231 static const unsigned int scif2_data_b_mux[] = { 1232 RX2_B_MARK, TX2_B_MARK, 1233 }; 1234 static const unsigned int scif2_clk_b_pins[] = { 1235 /* SCK */ 1236 RCAR_GP_PIN(5, 27), 1237 }; 1238 static const unsigned int scif2_clk_b_mux[] = { 1239 SCIF2_SCK_B_MARK, 1240 }; 1241 static const unsigned int scif2_data_c_pins[] = { 1242 /* RX, TX */ 1243 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), 1244 }; 1245 static const unsigned int scif2_data_c_mux[] = { 1246 RX2_C_MARK, TX2_C_MARK, 1247 }; 1248 /* - SCIF3 ------------------------------------------------------------------ */ 1249 static const unsigned int scif3_data_a_pins[] = { 1250 /* RX, TX */ 1251 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), 1252 }; 1253 static const unsigned int scif3_data_a_mux[] = { 1254 RX3_A_MARK, TX3_A_MARK, 1255 }; 1256 static const unsigned int scif3_clk_pins[] = { 1257 /* SCK */ 1258 RCAR_GP_PIN(4, 21), 1259 }; 1260 static const unsigned int scif3_clk_mux[] = { 1261 SCIF3_SCK_MARK, 1262 }; 1263 static const unsigned int scif3_data_b_pins[] = { 1264 /* RX, TX */ 1265 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), 1266 }; 1267 static const unsigned int scif3_data_b_mux[] = { 1268 RX3_B_MARK, TX3_B_MARK, 1269 }; 1270 static const unsigned int scif3_data_c_pins[] = { 1271 /* RX, TX */ 1272 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 1273 }; 1274 static const unsigned int scif3_data_c_mux[] = { 1275 RX3_C_MARK, TX3_C_MARK, 1276 }; 1277 /* - SCIF4 ------------------------------------------------------------------ */ 1278 static const unsigned int scif4_data_a_pins[] = { 1279 /* RX, TX */ 1280 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3), 1281 }; 1282 static const unsigned int scif4_data_a_mux[] = { 1283 RX4_A_MARK, TX4_A_MARK, 1284 }; 1285 static const unsigned int scif4_data_b_pins[] = { 1286 /* RX, TX */ 1287 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), 1288 }; 1289 static const unsigned int scif4_data_b_mux[] = { 1290 RX4_B_MARK, TX4_B_MARK, 1291 }; 1292 static const unsigned int scif4_data_c_pins[] = { 1293 /* RX, TX */ 1294 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14), 1295 }; 1296 static const unsigned int scif4_data_c_mux[] = { 1297 RX4_C_MARK, TX4_C_MARK, 1298 }; 1299 static const unsigned int scif4_data_d_pins[] = { 1300 /* RX, TX */ 1301 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), 1302 }; 1303 static const unsigned int scif4_data_d_mux[] = { 1304 RX4_D_MARK, TX4_D_MARK, 1305 }; 1306 static const unsigned int scif4_data_e_pins[] = { 1307 /* RX, TX */ 1308 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), 1309 }; 1310 static const unsigned int scif4_data_e_mux[] = { 1311 RX4_E_MARK, TX4_E_MARK, 1312 }; 1313 /* - SCIF5 ------------------------------------------------------------------ */ 1314 static const unsigned int scif5_data_a_pins[] = { 1315 /* RX, TX */ 1316 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), 1317 }; 1318 static const unsigned int scif5_data_a_mux[] = { 1319 RX5_A_MARK, TX5_A_MARK, 1320 }; 1321 static const unsigned int scif5_data_b_pins[] = { 1322 /* RX, TX */ 1323 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1), 1324 }; 1325 static const unsigned int scif5_data_b_mux[] = { 1326 RX5_B_MARK, TX5_B_MARK, 1327 }; 1328 static const unsigned int scif5_data_c_pins[] = { 1329 /* RX, TX */ 1330 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), 1331 }; 1332 static const unsigned int scif5_data_c_mux[] = { 1333 RX5_C_MARK, TX5_C_MARK, 1334 }; 1335 static const unsigned int scif5_data_d_pins[] = { 1336 /* RX, TX */ 1337 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), 1338 }; 1339 static const unsigned int scif5_data_d_mux[] = { 1340 RX5_D_MARK, TX5_D_MARK, 1341 }; 1342 static const unsigned int scif5_data_e_pins[] = { 1343 /* RX, TX */ 1344 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 1345 }; 1346 static const unsigned int scif5_data_e_mux[] = { 1347 RX5_E_MARK, TX5_E_MARK, 1348 }; 1349 static const unsigned int scif5_data_f_pins[] = { 1350 /* RX, TX */ 1351 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), 1352 }; 1353 static const unsigned int scif5_data_f_mux[] = { 1354 RX5_F_MARK, TX5_F_MARK, 1355 }; 1356 /* - SCIF Clock ------------------------------------------------------------- */ 1357 static const unsigned int scif_clk_a_pins[] = { 1358 /* SCIF_CLK */ 1359 RCAR_GP_PIN(1, 22), 1360 }; 1361 static const unsigned int scif_clk_a_mux[] = { 1362 SCIF_CLK_A_MARK, 1363 }; 1364 static const unsigned int scif_clk_b_pins[] = { 1365 /* SCIF_CLK */ 1366 RCAR_GP_PIN(3, 29), 1367 }; 1368 static const unsigned int scif_clk_b_mux[] = { 1369 SCIF_CLK_B_MARK, 1370 }; 1371 1372 static const struct sh_pfc_pin_group pinmux_groups[] = { 1373 SH_PFC_PIN_GROUP(mmc_data1), 1374 SH_PFC_PIN_GROUP(mmc_data4), 1375 SH_PFC_PIN_GROUP(mmc_data8), 1376 SH_PFC_PIN_GROUP(mmc_ctrl), 1377 SH_PFC_PIN_GROUP(scif0_data_a), 1378 SH_PFC_PIN_GROUP(scif0_data_b), 1379 SH_PFC_PIN_GROUP(scif0_data_c), 1380 SH_PFC_PIN_GROUP(scif0_data_d), 1381 SH_PFC_PIN_GROUP(scif1_data_a), 1382 SH_PFC_PIN_GROUP(scif1_clk_a), 1383 SH_PFC_PIN_GROUP(scif1_data_b), 1384 SH_PFC_PIN_GROUP(scif1_clk_b), 1385 SH_PFC_PIN_GROUP(scif1_data_c), 1386 SH_PFC_PIN_GROUP(scif1_clk_c), 1387 SH_PFC_PIN_GROUP(scif1_data_d), 1388 SH_PFC_PIN_GROUP(scif2_data_a), 1389 SH_PFC_PIN_GROUP(scif2_clk_a), 1390 SH_PFC_PIN_GROUP(scif2_data_b), 1391 SH_PFC_PIN_GROUP(scif2_clk_b), 1392 SH_PFC_PIN_GROUP(scif2_data_c), 1393 SH_PFC_PIN_GROUP(scif3_data_a), 1394 SH_PFC_PIN_GROUP(scif3_clk), 1395 SH_PFC_PIN_GROUP(scif3_data_b), 1396 SH_PFC_PIN_GROUP(scif3_data_c), 1397 SH_PFC_PIN_GROUP(scif4_data_a), 1398 SH_PFC_PIN_GROUP(scif4_data_b), 1399 SH_PFC_PIN_GROUP(scif4_data_c), 1400 SH_PFC_PIN_GROUP(scif4_data_d), 1401 SH_PFC_PIN_GROUP(scif4_data_e), 1402 SH_PFC_PIN_GROUP(scif5_data_a), 1403 SH_PFC_PIN_GROUP(scif5_data_b), 1404 SH_PFC_PIN_GROUP(scif5_data_c), 1405 SH_PFC_PIN_GROUP(scif5_data_d), 1406 SH_PFC_PIN_GROUP(scif5_data_e), 1407 SH_PFC_PIN_GROUP(scif5_data_f), 1408 SH_PFC_PIN_GROUP(scif_clk_a), 1409 SH_PFC_PIN_GROUP(scif_clk_b), 1410 }; 1411 1412 static const char * const mmc_groups[] = { 1413 "mmc_data1", 1414 "mmc_data4", 1415 "mmc_data8", 1416 "mmc_ctrl", 1417 }; 1418 1419 static const char * const scif0_groups[] = { 1420 "scif0_data_a", 1421 "scif0_data_b", 1422 "scif0_data_c", 1423 "scif0_data_d", 1424 }; 1425 1426 static const char * const scif1_groups[] = { 1427 "scif1_data_a", 1428 "scif1_clk_a", 1429 "scif1_data_b", 1430 "scif1_clk_b", 1431 "scif1_data_c", 1432 "scif1_clk_c", 1433 "scif1_data_d", 1434 }; 1435 1436 static const char * const scif2_groups[] = { 1437 "scif2_data_a", 1438 "scif2_clk_a", 1439 "scif2_data_b", 1440 "scif2_clk_b", 1441 "scif2_data_c", 1442 }; 1443 1444 static const char * const scif3_groups[] = { 1445 "scif3_data_a", 1446 "scif3_clk", 1447 "scif3_data_b", 1448 "scif3_data_c", 1449 }; 1450 1451 static const char * const scif4_groups[] = { 1452 "scif4_data_a", 1453 "scif4_data_b", 1454 "scif4_data_c", 1455 "scif4_data_d", 1456 "scif4_data_e", 1457 }; 1458 1459 static const char * const scif5_groups[] = { 1460 "scif5_data_a", 1461 "scif5_data_b", 1462 "scif5_data_c", 1463 "scif5_data_d", 1464 "scif5_data_e", 1465 "scif5_data_f", 1466 }; 1467 1468 static const char * const scif_clk_groups[] = { 1469 "scif_clk_a", 1470 "scif_clk_b", 1471 }; 1472 1473 static const struct sh_pfc_function pinmux_functions[] = { 1474 SH_PFC_FUNCTION(mmc), 1475 SH_PFC_FUNCTION(scif0), 1476 SH_PFC_FUNCTION(scif1), 1477 SH_PFC_FUNCTION(scif2), 1478 SH_PFC_FUNCTION(scif3), 1479 SH_PFC_FUNCTION(scif4), 1480 SH_PFC_FUNCTION(scif5), 1481 SH_PFC_FUNCTION(scif_clk), 1482 }; 1483 1484 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1485 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 1486 0, 0, 1487 0, 0, 1488 0, 0, 1489 0, 0, 1490 0, 0, 1491 0, 0, 1492 0, 0, 1493 0, 0, 1494 0, 0, 1495 GP_0_22_FN, FN_MMC0_D7, 1496 GP_0_21_FN, FN_MMC0_D6, 1497 GP_0_20_FN, FN_IP1_7_4, 1498 GP_0_19_FN, FN_IP1_3_0, 1499 GP_0_18_FN, FN_MMC0_D3_SDHI1_D3, 1500 GP_0_17_FN, FN_MMC0_D2_SDHI1_D2, 1501 GP_0_16_FN, FN_MMC0_D1_SDHI1_D1, 1502 GP_0_15_FN, FN_MMC0_D0_SDHI1_D0, 1503 GP_0_14_FN, FN_MMC0_CMD_SDHI1_CMD, 1504 GP_0_13_FN, FN_MMC0_CLK_SDHI1_CLK, 1505 GP_0_12_FN, FN_IP0_31_28, 1506 GP_0_11_FN, FN_IP0_27_24, 1507 GP_0_10_FN, FN_IP0_23_20, 1508 GP_0_9_FN, FN_IP0_19_16, 1509 GP_0_8_FN, FN_IP0_15_12, 1510 GP_0_7_FN, FN_IP0_11_8, 1511 GP_0_6_FN, FN_IP0_7_4, 1512 GP_0_5_FN, FN_IP0_3_0, 1513 GP_0_4_FN, FN_CLKOUT, 1514 GP_0_3_FN, FN_USB1_OVC, 1515 GP_0_2_FN, FN_USB1_PWEN, 1516 GP_0_1_FN, FN_USB0_OVC, 1517 GP_0_0_FN, FN_USB0_PWEN, } 1518 }, 1519 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { 1520 0, 0, 1521 0, 0, 1522 0, 0, 1523 0, 0, 1524 0, 0, 1525 0, 0, 1526 0, 0, 1527 0, 0, 1528 0, 0, 1529 GP_1_22_FN, FN_IP4_3_0, 1530 GP_1_21_FN, FN_IP3_31_28, 1531 GP_1_20_FN, FN_IP3_27_24, 1532 GP_1_19_FN, FN_IP3_23_20, 1533 GP_1_18_FN, FN_IP3_19_16, 1534 GP_1_17_FN, FN_IP3_15_12, 1535 GP_1_16_FN, FN_IP3_11_8, 1536 GP_1_15_FN, FN_IP3_7_4, 1537 GP_1_14_FN, FN_IP3_3_0, 1538 GP_1_13_FN, FN_IP2_31_28, 1539 GP_1_12_FN, FN_IP2_27_24, 1540 GP_1_11_FN, FN_IP2_23_20, 1541 GP_1_10_FN, FN_IP2_19_16, 1542 GP_1_9_FN, FN_IP2_15_12, 1543 GP_1_8_FN, FN_IP2_11_8, 1544 GP_1_7_FN, FN_IP2_7_4, 1545 GP_1_6_FN, FN_IP2_3_0, 1546 GP_1_5_FN, FN_IP1_31_28, 1547 GP_1_4_FN, FN_IP1_27_24, 1548 GP_1_3_FN, FN_IP1_23_20, 1549 GP_1_2_FN, FN_IP1_19_16, 1550 GP_1_1_FN, FN_IP1_15_12, 1551 GP_1_0_FN, FN_IP1_11_8, } 1552 }, 1553 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { 1554 GP_2_31_FN, FN_IP8_3_0, 1555 GP_2_30_FN, FN_IP7_31_28, 1556 GP_2_29_FN, FN_IP7_27_24, 1557 GP_2_28_FN, FN_IP7_23_20, 1558 GP_2_27_FN, FN_IP7_19_16, 1559 GP_2_26_FN, FN_IP7_15_12, 1560 GP_2_25_FN, FN_IP7_11_8, 1561 GP_2_24_FN, FN_IP7_7_4, 1562 GP_2_23_FN, FN_IP7_3_0, 1563 GP_2_22_FN, FN_IP6_31_28, 1564 GP_2_21_FN, FN_IP6_27_24, 1565 GP_2_20_FN, FN_IP6_23_20, 1566 GP_2_19_FN, FN_IP6_19_16, 1567 GP_2_18_FN, FN_IP6_15_12, 1568 GP_2_17_FN, FN_IP6_11_8, 1569 GP_2_16_FN, FN_IP6_7_4, 1570 GP_2_15_FN, FN_IP6_3_0, 1571 GP_2_14_FN, FN_IP5_31_28, 1572 GP_2_13_FN, FN_IP5_27_24, 1573 GP_2_12_FN, FN_IP5_23_20, 1574 GP_2_11_FN, FN_IP5_19_16, 1575 GP_2_10_FN, FN_IP5_15_12, 1576 GP_2_9_FN, FN_IP5_11_8, 1577 GP_2_8_FN, FN_IP5_7_4, 1578 GP_2_7_FN, FN_IP5_3_0, 1579 GP_2_6_FN, FN_IP4_31_28, 1580 GP_2_5_FN, FN_IP4_27_24, 1581 GP_2_4_FN, FN_IP4_23_20, 1582 GP_2_3_FN, FN_IP4_19_16, 1583 GP_2_2_FN, FN_IP4_15_12, 1584 GP_2_1_FN, FN_IP4_11_8, 1585 GP_2_0_FN, FN_IP4_7_4, } 1586 }, 1587 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { 1588 0, 0, 1589 0, 0, 1590 GP_3_29_FN, FN_IP10_19_16, 1591 GP_3_28_FN, FN_IP10_15_12, 1592 GP_3_27_FN, FN_IP10_11_8, 1593 0, 0, 1594 0, 0, 1595 0, 0, 1596 0, 0, 1597 0, 0, 1598 0, 0, 1599 0, 0, 1600 0, 0, 1601 0, 0, 1602 0, 0, 1603 GP_3_16_FN, FN_IP10_7_4, 1604 GP_3_15_FN, FN_IP10_3_0, 1605 GP_3_14_FN, FN_IP9_31_28, 1606 GP_3_13_FN, FN_IP9_27_24, 1607 GP_3_12_FN, FN_IP9_23_20, 1608 GP_3_11_FN, FN_IP9_19_16, 1609 GP_3_10_FN, FN_IP9_15_12, 1610 GP_3_9_FN, FN_IP9_11_8, 1611 GP_3_8_FN, FN_IP9_7_4, 1612 GP_3_7_FN, FN_IP9_3_0, 1613 GP_3_6_FN, FN_IP8_31_28, 1614 GP_3_5_FN, FN_IP8_27_24, 1615 GP_3_4_FN, FN_IP8_23_20, 1616 GP_3_3_FN, FN_IP8_19_16, 1617 GP_3_2_FN, FN_IP8_15_12, 1618 GP_3_1_FN, FN_IP8_11_8, 1619 GP_3_0_FN, FN_IP8_7_4, } 1620 }, 1621 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { 1622 0, 0, 1623 0, 0, 1624 0, 0, 1625 0, 0, 1626 0, 0, 1627 0, 0, 1628 GP_4_25_FN, FN_IP13_27_24, 1629 GP_4_24_FN, FN_IP13_23_20, 1630 GP_4_23_FN, FN_IP13_19_16, 1631 GP_4_22_FN, FN_IP13_15_12, 1632 GP_4_21_FN, FN_IP13_11_8, 1633 GP_4_20_FN, FN_IP13_7_4, 1634 GP_4_19_FN, FN_IP13_3_0, 1635 GP_4_18_FN, FN_IP12_31_28, 1636 GP_4_17_FN, FN_IP12_27_24, 1637 GP_4_16_FN, FN_IP12_23_20, 1638 GP_4_15_FN, FN_IP12_19_16, 1639 GP_4_14_FN, FN_IP12_15_12, 1640 GP_4_13_FN, FN_IP12_11_8, 1641 GP_4_12_FN, FN_IP12_7_4, 1642 GP_4_11_FN, FN_IP12_3_0, 1643 GP_4_10_FN, FN_IP11_31_28, 1644 GP_4_9_FN, FN_IP11_27_24, 1645 GP_4_8_FN, FN_IP11_23_20, 1646 GP_4_7_FN, FN_IP11_19_16, 1647 GP_4_6_FN, FN_IP11_15_12, 1648 GP_4_5_FN, FN_IP11_11_8, 1649 GP_4_4_FN, FN_IP11_7_4, 1650 GP_4_3_FN, FN_IP11_3_0, 1651 GP_4_2_FN, FN_IP10_31_28, 1652 GP_4_1_FN, FN_IP10_27_24, 1653 GP_4_0_FN, FN_IP10_23_20, } 1654 }, 1655 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { 1656 GP_5_31_FN, FN_IP17_27_24, 1657 GP_5_30_FN, FN_IP17_23_20, 1658 GP_5_29_FN, FN_IP17_19_16, 1659 GP_5_28_FN, FN_IP17_15_12, 1660 GP_5_27_FN, FN_IP17_11_8, 1661 GP_5_26_FN, FN_IP17_7_4, 1662 GP_5_25_FN, FN_IP17_3_0, 1663 GP_5_24_FN, FN_IP16_31_28, 1664 GP_5_23_FN, FN_IP16_27_24, 1665 GP_5_22_FN, FN_IP16_23_20, 1666 GP_5_21_FN, FN_IP16_19_16, 1667 GP_5_20_FN, FN_IP16_15_12, 1668 GP_5_19_FN, FN_IP16_11_8, 1669 GP_5_18_FN, FN_IP16_7_4, 1670 GP_5_17_FN, FN_IP16_3_0, 1671 GP_5_16_FN, FN_IP15_31_28, 1672 GP_5_15_FN, FN_IP15_27_24, 1673 GP_5_14_FN, FN_IP15_23_20, 1674 GP_5_13_FN, FN_IP15_19_16, 1675 GP_5_12_FN, FN_IP15_15_12, 1676 GP_5_11_FN, FN_IP15_11_8, 1677 GP_5_10_FN, FN_IP15_7_4, 1678 GP_5_9_FN, FN_IP15_3_0, 1679 GP_5_8_FN, FN_IP14_31_28, 1680 GP_5_7_FN, FN_IP14_27_24, 1681 GP_5_6_FN, FN_IP14_23_20, 1682 GP_5_5_FN, FN_IP14_19_16, 1683 GP_5_4_FN, FN_IP14_15_12, 1684 GP_5_3_FN, FN_IP14_11_8, 1685 GP_5_2_FN, FN_IP14_7_4, 1686 GP_5_1_FN, FN_IP14_3_0, 1687 GP_5_0_FN, FN_IP13_31_28, } 1688 }, 1689 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32, 1690 4, 4, 4, 4, 4, 4, 4, 4) { 1691 /* IP0_31_28 [4] */ 1692 FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0, 1693 0, 0, 0, 0, 0, 0, 0, 0, 1694 /* IP0_27_24 [4] */ 1695 FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0, 1696 0, 0, 0, 0, 0, 0, 0, 0, 1697 /* IP0_23_20 [4] */ 1698 FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0, 1699 0, 0, 0, 0, 0, 0, 0, 0, 1700 /* IP0_19_16 [4] */ 1701 FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0, 1702 0, 0, 0, 0, 0, 0, 0, 0, 1703 /* IP0_15_12 [4] */ 1704 FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0, 1705 0, 0, 0, 0, 0, 0, 0, 0, 1706 /* IP0_11_8 [4] */ 1707 FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0, 1708 0, 0, 0, 0, 0, 0, 0, 0, 1709 /* IP0_7_4 [4] */ 1710 FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0, 1711 0, 0, 0, 0, 0, 0, 0, 0, 1712 /* IP0_3_0 [4] */ 1713 FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0, 1714 0, 0, 0, 0, 0, 0, 0, 0, } 1715 }, 1716 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32, 1717 4, 4, 4, 4, 4, 4, 4, 4) { 1718 /* IP1_31_28 [4] */ 1719 FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0, 1720 0, 0, 0, 0, 0, 0, 0, 0, 1721 /* IP1_27_24 [4] */ 1722 FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0, 1723 0, 0, 0, 0, 0, 0, 0, 0, 1724 /* IP1_23_20 [4] */ 1725 FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, 1726 FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1727 /* IP1_19_16 [4] */ 1728 FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, 1729 FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1730 /* IP1_15_12 [4] */ 1731 FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C, 1732 FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1733 /* IP1_11_8 [4] */ 1734 FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, 1735 FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1736 /* IP1_7_4 [4] */ 1737 FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0, 1738 0, 0, 0, 0, 0, 0, 0, 0, 1739 /* IP1_3_0 [4] */ 1740 FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0, 1741 0, 0, 0, 0, 0, 0, 0, 0, } 1742 }, 1743 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32, 1744 4, 4, 4, 4, 4, 4, 4, 4) { 1745 /* IP2_31_28 [4] */ 1746 FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0, 1747 0, 0, 0, 0, 0, 0, 0, 1748 /* IP2_27_24 [4] */ 1749 FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C, 1750 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1751 /* IP2_23_20 [4] */ 1752 FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0, 1753 0, 0, 0, 0, 0, 0, 0, 1754 /* IP2_19_16 [4] */ 1755 FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0, 1756 0, 0, 0, 0, 0, 0, 0, 1757 /* IP2_15_12 [4] */ 1758 FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0, 1759 0, 0, 0, 0, 0, 0, 0, 0, 0, 1760 /* IP2_11_8 [4] */ 1761 FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0, 1762 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1763 /* IP2_7_4 [4] */ 1764 FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, 1765 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1766 /* IP2_3_0 [4] */ 1767 FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0, 1768 0, 0, 0, 0, 0, 0, 0, 0, } 1769 }, 1770 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32, 1771 4, 4, 4, 4, 4, 4, 4, 4) { 1772 /* IP3_31_28 [4] */ 1773 FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1774 0, 0, 1775 /* IP3_27_24 [4] */ 1776 FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1777 0, 0, 1778 /* IP3_23_20 [4] */ 1779 FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1780 0, 0, 1781 /* IP3_19_16 [4] */ 1782 FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1783 0, 0, 0, 0, 1784 /* IP3_15_12 [4] */ 1785 FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1786 0, 0, 0, 1787 /* IP3_11_8 [4] */ 1788 FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1789 0, 0, 1790 /* IP3_7_4 [4] */ 1791 FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2, 1792 FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1793 /* IP3_3_0 [4] */ 1794 FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B, 1795 0, FN_AVB_AVTP_CAPTURE_A, 1796 0, 0, 0, 0, 0, 0, 0, 0, 0, } 1797 }, 1798 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32, 1799 4, 4, 4, 4, 4, 4, 4, 4) { 1800 /* IP4_31_28 [4] */ 1801 FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0, 1802 0, 0, 0, 0, 0, 0, 0, 0, 1803 /* IP4_27_24 [4] */ 1804 FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0, 1805 0, 0, 0, 0, 0, 0, 0, 0, 1806 /* IP4_23_20 [4] */ 1807 FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0, 1808 0, 0, 0, 0, 0, 1809 /* IP4_19_16 [4] */ 1810 FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0, 1811 FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1812 /* IP4_15_12 [4] */ 1813 FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0, 1814 0, 0, 0, 0, 0, 0, 0, 0, 1815 /* IP4_11_8 [4] */ 1816 FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0, 1817 0, 0, 0, 0, 0, 0, 0, 0, 1818 /* IP4_7_4 [4] */ 1819 FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0, 1820 0, 0, 0, 0, 0, 0, 0, 0, 1821 /* IP4_3_0 [4] */ 1822 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0, 1823 0, 0, 0, 0, 0, 0, 0, 0, 0, } 1824 }, 1825 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32, 1826 4, 4, 4, 4, 4, 4, 4, 4) { 1827 /* IP5_31_28 [4] */ 1828 FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0, 1829 0, 0, 0, 0, 0, 0, 1830 /* IP5_27_24 [4] */ 1831 FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13, 1832 0, 0, 0, 0, 0, 0, 0, 0, 0, 1833 /* IP5_23_20 [4] */ 1834 FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0, 1835 0, 0, 0, 0, 0, 0, 1836 /* IP5_19_16 [4] */ 1837 FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0, 1838 0, 0, 0, 0, 0, 0, 0, 0, 1839 /* IP5_15_12 [4] */ 1840 FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0, 1841 0, 0, 0, 0, 0, 0, 1842 /* IP5_11_8 [4] */ 1843 FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0, 1844 FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1845 /* IP5_7_4 [4] */ 1846 FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0, 1847 0, 0, 0, 0, 0, 0, 0, 0, 1848 /* IP5_3_0 [4] */ 1849 FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0, 1850 0, 0, 0, 0, 0, 0, 0, 0, } 1851 }, 1852 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32, 1853 4, 4, 4, 4, 4, 4, 4, 4) { 1854 /* IP6_31_28 [4] */ 1855 FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0, 1856 0, 0, 0, 0, 0, 0, 0, 1857 /* IP6_27_24 [4] */ 1858 FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0, 1859 FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1860 /* IP6_23_20 [4] */ 1861 FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0, 1862 FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1863 /* IP6_19_16 [4] */ 1864 FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0, 1865 0, 0, 0, 0, 0, 0, 1866 /* IP6_15_12 [4] */ 1867 FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0, 1868 0, 0, 0, 0, 0, 0, 1869 /* IP6_11_8 [4] */ 1870 FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17, 1871 0, 0, 0, 0, 0, 0, 0, 0, 0, 1872 /* IP6_7_4 [4] */ 1873 FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16, 1874 0, 0, 0, 0, 0, 0, 0, 0, 0, 1875 /* IP6_3_0 [4] */ 1876 FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15, 1877 0, 0, 0, 0, 0, 0, 0, 0, 0, } 1878 }, 1879 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32, 1880 4, 4, 4, 4, 4, 4, 4, 4) { 1881 /* IP7_31_28 [4] */ 1882 FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0, 1883 0, 0, 0, 0, 0, 1884 /* IP7_27_24 [4] */ 1885 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B, 1886 0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1887 /* IP7_23_20 [4] */ 1888 FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0, 1889 0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1890 /* IP7_19_16 [4] */ 1891 FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0, 1892 0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1893 /* IP7_15_12 [4] */ 1894 FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0, 1895 FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1896 /* IP7_11_8 [4] */ 1897 FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0, 1898 0, 0, 0, 0, 0, 1899 /* IP7_7_4 [4] */ 1900 FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0, 1901 0, 0, 0, 0, 0, 0, 1902 /* IP7_3_0 [4] */ 1903 FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0, 1904 0, 0, 0, 0, 0, 0, 0, } 1905 }, 1906 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32, 1907 4, 4, 4, 4, 4, 4, 4, 4) { 1908 /* IP8_31_28 [4] */ 1909 FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0, 1910 0, 0, 0, 0, 0, 0, 1911 /* IP8_27_24 [4] */ 1912 FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0, 1913 0, 0, 0, 0, 0, 0, 1914 /* IP8_23_20 [4] */ 1915 FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0, 1916 0, 0, 0, 0, 0, 0, 1917 /* IP8_19_16 [4] */ 1918 FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0, 1919 0, 0, 0, 0, 0, 0, 1920 /* IP8_15_12 [4] */ 1921 FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0, 1922 0, 0, 0, 0, 0, 0, 1923 /* IP8_11_8 [4] */ 1924 FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0, 1925 0, 0, 0, 0, 0, 0, 0, 1926 /* IP8_7_4 [4] */ 1927 FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0, 1928 0, 0, 0, 0, 0, 0, 0, 1929 /* IP8_3_0 [4] */ 1930 FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0, 1931 0, 0, 0, 0, } 1932 }, 1933 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32, 1934 4, 4, 4, 4, 4, 4, 4, 4) { 1935 /* IP9_31_28 [4] */ 1936 FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0, 1937 0, 0, 0, 0, 0, 1938 /* IP9_27_24 [4] */ 1939 FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0, 1940 0, 0, 0, 0, 0, 1941 /* IP9_23_20 [4] */ 1942 FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, 1943 FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1944 /* IP9_19_16 [4] */ 1945 FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK, 1946 FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1947 /* IP9_15_12 [4] */ 1948 FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0, 1949 0, 0, 0, 0, 0, 0, 0, 0, 0, 1950 /* IP9_11_8 [4] */ 1951 FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0, 1952 0, 0, 0, 0, 0, 0, 0, 0, 0, 1953 /* IP9_7_4 [4] */ 1954 FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0, 1955 0, 0, 0, 0, 0, 0, 1956 /* IP9_3_0 [4] */ 1957 FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0, 1958 0, 0, 0, 0, 0, 0, } 1959 }, 1960 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32, 1961 4, 4, 4, 4, 4, 4, 4, 4) { 1962 /* IP10_31_28 [4] */ 1963 FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0, 1964 FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0, 1965 /* IP10_27_24 [4] */ 1966 FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, 1967 FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1968 /* IP10_23_20 [4] */ 1969 FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6, 1970 FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1971 /* IP10_19_16 [4] */ 1972 FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0, 1973 FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0, 1974 0, 0, 1975 /* IP10_15_12 [4] */ 1976 FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F, 1977 FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1978 /* IP10_11_8 [4] */ 1979 FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F, 1980 FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1981 /* IP10_7_4 [4] */ 1982 FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0, 1983 0, 0, 0, 0, 0, 0, 0, 1984 /* IP10_3_0 [4] */ 1985 FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0, 1986 0, 0, 0, 0, 0, 0, 0, } 1987 }, 1988 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32, 1989 4, 4, 4, 4, 4, 4, 4, 4) { 1990 /* IP11_31_28 [4] */ 1991 FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0, 1992 0, 0, 0, 0, 0, 0, 0, 0, 0, 1993 /* IP11_27_24 [4] */ 1994 FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0, 1995 FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1996 /* IP11_23_20 [4] */ 1997 FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0, 1998 FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1999 /* IP11_19_16 [4] */ 2000 FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5, 2001 0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0, 2002 0, 0, 0, 0, 2003 /* IP11_15_12 [4] */ 2004 FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4, 2005 0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4, 2006 0, 0, 0, 0, 0, 0, 0, 0, 2007 /* IP11_11_8 [4] */ 2008 FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0, 2009 FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3, 2010 0, 0, 0, 0, 0, 0, 0, 0, 2011 /* IP11_7_4 [4] */ 2012 FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0, 2013 FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2, 2014 0, 0, 0, 0, 0, 0, 0, 0, 2015 /* IP11_3_0 [4] */ 2016 FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B, 2017 FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, } 2018 }, 2019 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32, 2020 4, 4, 4, 4, 4, 4, 4, 4) { 2021 /* IP12_31_28 [4] */ 2022 FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0, 2023 0, 0, 0, 0, 0, 0, 0, 0, 0, 2024 /* IP12_27_24 [4] */ 2025 FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B, 2026 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2027 /* IP12_23_20 [4] */ 2028 FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, 2029 FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2030 /* IP12_19_16 [4] */ 2031 FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, 2032 FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2033 /* IP12_15_12 [4] */ 2034 FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0, 2035 0, 0, 0, 0, 0, 0, 0, 0, 2036 /* IP12_11_8 [4] */ 2037 FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0, 2038 0, 0, 0, 0, 0, 0, 0, 0, 2039 /* IP12_7_4 [4] */ 2040 FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B, 2041 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2042 /* IP12_3_0 [4] */ 2043 FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0, 2044 0, 0, 0, 0, 0, 0, } 2045 }, 2046 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32, 2047 4, 4, 4, 4, 4, 4, 4, 4) { 2048 /* IP13_31_28 [4] */ 2049 FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0, 2050 0, 0, 0, 0, 0, 2051 /* IP13_27_24 [4] */ 2052 FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, 2053 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2054 /* IP13_23_20 [4] */ 2055 FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, 2056 FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2057 /* IP13_19_16 [4] */ 2058 FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, 2059 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2060 /* IP13_15_12 [4] */ 2061 FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, 2062 FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0, 2063 0, 0, 2064 /* IP13_11_8 [4] */ 2065 FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0, 2066 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2067 /* IP13_7_4 [4] */ 2068 FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0, 2069 0, 0, 0, 0, 0, 0, 0, 0, 0, 2070 /* IP13_3_0 [4] */ 2071 FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0, 2072 0, 0, 0, 0, 0, 0, 0, 0, } 2073 }, 2074 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32, 2075 4, 4, 4, 4, 4, 4, 4, 4) { 2076 /* IP14_31_28 [4] */ 2077 FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, 2078 FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2079 /* IP14_27_24 [4] */ 2080 FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0, 2081 0, 0, 0, 0, 0, 2082 /* IP14_23_20 [4] */ 2083 FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0, 2084 0, 0, 0, 0, 0, 0, 2085 /* IP14_19_16 [4] */ 2086 FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 2087 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2088 /* IP14_15_12 [4] */ 2089 FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0, 2090 0, 0, 0, 0, 0, 0, 0, 0, 0, 2091 /* IP14_11_8 [4] */ 2092 FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 2093 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2094 /* IP14_7_4 [4] */ 2095 FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0, 2096 0, 0, 0, 0, 0, 0, 0, 0, 0, 2097 /* IP14_3_0 [4] */ 2098 FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0, 2099 0, 0, 0, 0, 0, 0, } 2100 }, 2101 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32, 2102 4, 4, 4, 4, 4, 4, 4, 4) { 2103 /* IP15_31_28 [4] */ 2104 FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0, 2105 0, 0, 0, 0, 0, 0, 2106 /* IP15_27_24 [4] */ 2107 FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0, 2108 0, 0, 0, 0, 0, 0, 2109 /* IP15_23_20 [4] */ 2110 FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A, 2111 FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2112 /* IP15_19_16 [4] */ 2113 FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A, 2114 FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2115 /* IP15_15_12 [4] */ 2116 FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1, 2117 FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2118 /* IP15_11_8 [4] */ 2119 FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0, 2120 FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2121 /* IP15_7_4 [4] */ 2122 FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0, 2123 FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2124 /* IP15_3_0 [4] */ 2125 FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0, 2126 FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, } 2127 }, 2128 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32, 2129 4, 4, 4, 4, 4, 4, 4, 4) { 2130 /* IP16_31_28 [4] */ 2131 FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0, 2132 FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2133 /* IP16_27_24 [4] */ 2134 FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER, 2135 FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2136 /* IP16_23_20 [4] */ 2137 FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7, 2138 FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2139 /* IP16_19_16 [4] */ 2140 FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1, 2141 0, 0, 0, 0, 0, 0, 0, 0, 0, 2142 /* IP16_15_12 [4] */ 2143 FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D, 2144 FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0, 2145 0, 0, 0, 2146 /* IP16_11_8 [4] */ 2147 FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D, 2148 FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2149 /* IP16_7_4 [4] */ 2150 FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, 2151 FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0, 2152 /* IP16_3_0 [4] */ 2153 FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0, 2154 0, 0, 0, 0, 0, 0, } 2155 }, 2156 { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32, 2157 4, 4, 4, 4, 4, 4, 4, 4) { 2158 /* IP17_31_28 [4] */ 2159 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2160 /* IP17_27_24 [4] */ 2161 FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0, 2162 FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2163 /* IP17_23_20 [4] */ 2164 FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0, 2165 FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2166 /* IP17_19_16 [4] */ 2167 FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0, 2168 FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2169 /* IP17_15_12 [4] */ 2170 FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0, 2171 FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2172 /* IP17_11_8 [4] */ 2173 FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0, 2174 FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2175 /* IP17_7_4 [4] */ 2176 FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0, 2177 FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2178 /* IP17_3_0 [4] */ 2179 FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1, 2180 FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, } 2181 }, 2182 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32, 2183 1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1, 3, 3, 2184 1, 2, 3, 3, 1) { 2185 /* RESERVED [1] */ 2186 0, 0, 2187 /* RESERVED [1] */ 2188 0, 0, 2189 /* RESERVED [1] */ 2190 0, 0, 2191 /* RESERVED [1] */ 2192 0, 0, 2193 /* RESERVED [1] */ 2194 0, 0, 2195 /* SEL_ADGA [2] */ 2196 FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3, 2197 /* RESERVED [1] */ 2198 0, 0, 2199 /* RESERVED [1] */ 2200 0, 0, 2201 /* SEL_CANCLK [2] */ 2202 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 2203 FN_SEL_CANCLK_3, 2204 /* SEL_CAN1 [2] */ 2205 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, 2206 /* SEL_CAN0 [2] */ 2207 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, 2208 /* RESERVED [1] */ 2209 0, 0, 2210 /* SEL_I2C04 [3] */ 2211 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, 2212 FN_SEL_I2C04_4, 0, 0, 0, 2213 /* SEL_I2C03 [3] */ 2214 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, 2215 FN_SEL_I2C03_4, 0, 0, 0, 2216 /* RESERVED [1] */ 2217 0, 0, 2218 /* SEL_I2C02 [2] */ 2219 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, 2220 /* SEL_I2C01 [3] */ 2221 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, 2222 FN_SEL_I2C01_4, 0, 0, 0, 2223 /* SEL_I2C00 [3] */ 2224 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, 2225 FN_SEL_I2C00_4, 0, 0, 0, 2226 /* SEL_AVB [1] */ 2227 FN_SEL_AVB_0, FN_SEL_AVB_1, } 2228 }, 2229 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32, 2230 1, 3, 3, 2, 2, 1, 2, 2, 2231 2, 1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 1) { 2232 /* SEL_SCIFCLK [1] */ 2233 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, 2234 /* SEL_SCIF5 [3] */ 2235 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, 2236 FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0, 2237 /* SEL_SCIF4 [3] */ 2238 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, 2239 FN_SEL_SCIF4_4, 0, 0, 0, 2240 /* SEL_SCIF3 [2] */ 2241 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0, 2242 /* SEL_SCIF2 [2] */ 2243 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0, 2244 /* SEL_SCIF2_CLK [1] */ 2245 FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1, 2246 /* SEL_SCIF1 [2] */ 2247 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 2248 /* SEL_SCIF0 [2] */ 2249 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, 2250 /* SEL_MSIOF2 [2] */ 2251 FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0, 2252 /* RESERVED [1] */ 2253 0, 0, 2254 /* SEL_MSIOF1 [1] */ 2255 FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1, 2256 /* RESERVED [1] */ 2257 0, 0, 2258 /* SEL_MSIOF0 [1] */ 2259 FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1, 2260 /* SEL_RCN [1] */ 2261 FN_SEL_RCN_0, FN_SEL_RCN_1, 2262 /* RESERVED [2] */ 2263 0, 0, 0, 0, 2264 /* SEL_TMU2 [1] */ 2265 FN_SEL_TMU2_0, FN_SEL_TMU2_1, 2266 /* SEL_TMU1 [1] */ 2267 FN_SEL_TMU1_0, FN_SEL_TMU1_1, 2268 /* RESERVED [2] */ 2269 0, 0, 0, 0, 2270 /* SEL_HSCIF1 [2] */ 2271 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0, 2272 /* SEL_HSCIF0 [1] */ 2273 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,} 2274 }, 2275 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32, 2276 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2277 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) { 2278 /* RESERVED [1] */ 2279 0, 0, 2280 /* RESERVED [1] */ 2281 0, 0, 2282 /* RESERVED [1] */ 2283 0, 0, 2284 /* RESERVED [1] */ 2285 0, 0, 2286 /* RESERVED [1] */ 2287 0, 0, 2288 /* RESERVED [1] */ 2289 0, 0, 2290 /* RESERVED [1] */ 2291 0, 0, 2292 /* RESERVED [1] */ 2293 0, 0, 2294 /* RESERVED [1] */ 2295 0, 0, 2296 /* RESERVED [1] */ 2297 0, 0, 2298 /* SEL_ADGB [2] */ 2299 FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0, 2300 /* SEL_ADGC [2] */ 2301 FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0, 2302 /* SEL_SSI9 [2] */ 2303 FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0, 2304 /* SEL_SSI8 [2] */ 2305 FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0, 2306 /* SEL_SSI7 [2] */ 2307 FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0, 2308 /* SEL_SSI6 [2] */ 2309 FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0, 2310 /* SEL_SSI5 [2] */ 2311 FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0, 2312 /* SEL_SSI4 [2] */ 2313 FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0, 2314 /* SEL_SSI2 [2] */ 2315 FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0, 2316 /* SEL_SSI1 [2] */ 2317 FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3, 2318 /* SEL_SSI0 [2] */ 2319 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, } 2320 }, 2321 { }, 2322 }; 2323 2324 #ifdef CONFIG_PINCTRL_PFC_R8A77470 2325 const struct sh_pfc_soc_info r8a77470_pinmux_info = { 2326 .name = "r8a77470_pfc", 2327 .unlock_reg = 0xe6060000, /* PMMR */ 2328 2329 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2330 2331 .pins = pinmux_pins, 2332 .nr_pins = ARRAY_SIZE(pinmux_pins), 2333 .groups = pinmux_groups, 2334 .nr_groups = ARRAY_SIZE(pinmux_groups), 2335 .functions = pinmux_functions, 2336 .nr_functions = ARRAY_SIZE(pinmux_functions), 2337 2338 .cfg_regs = pinmux_config_regs, 2339 2340 .pinmux_data = pinmux_data, 2341 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 2342 }; 2343 #endif 2344
