1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * linux/sound/soc/pxa/mmp-sspa.h 4 * 5 * Copyright (C) 2011 Marvell International Ltd. 6 */ 7 #ifndef _MMP_SSPA_H 8 #define _MMP_SSPA_H 9 10 /* 11 * SSPA Registers 12 */ 13 #define SSPA_RXD (0x00) 14 #define SSPA_RXID (0x04) 15 #define SSPA_RXCTL (0x08) 16 #define SSPA_RXSP (0x0c) 17 #define SSPA_RXFIFO_UL (0x10) 18 #define SSPA_RXINT_MASK (0x14) 19 #define SSPA_RXC (0x18) 20 #define SSPA_RXFIFO_NOFS (0x1c) 21 #define SSPA_RXFIFO_SIZE (0x20) 22 23 #define SSPA_TXD (0x80) 24 #define SSPA_TXID (0x84) 25 #define SSPA_TXCTL (0x88) 26 #define SSPA_TXSP (0x8c) 27 #define SSPA_TXFIFO_LL (0x90) 28 #define SSPA_TXINT_MASK (0x94) 29 #define SSPA_TXC (0x98) 30 #define SSPA_TXFIFO_NOFS (0x9c) 31 #define SSPA_TXFIFO_SIZE (0xa0) 32 33 /* SSPA Control Register */ 34 #define SSPA_CTL_XPH (1 << 31) /* Read Phase */ 35 #define SSPA_CTL_XFIG (1 << 15) /* Transmit Zeros when FIFO Empty */ 36 #define SSPA_CTL_JST (1 << 3) /* Audio Sample Justification */ 37 #define SSPA_CTL_XFRLEN2_MASK (7 << 24) 38 #define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */ 39 #define SSPA_CTL_XWDLEN2_MASK (7 << 21) 40 #define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */ 41 #define SSPA_CTL_XDATDLY(x) ((x) << 19) /* Tansmit Data Delay */ 42 #define SSPA_CTL_XSSZ2_MASK (7 << 16) 43 #define SSPA_CTL_XSSZ2(x) ((x) << 16) /* Transmit Sample Audio Size */ 44 #define SSPA_CTL_XFRLEN1_MASK (7 << 8) 45 #define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */ 46 #define SSPA_CTL_XWDLEN1_MASK (7 << 5) 47 #define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */ 48 #define SSPA_CTL_XSSZ1_MASK (7 << 0) 49 #define SSPA_CTL_XSSZ1(x) ((x) << 0) /* XSSZ1 */ 50 51 #define SSPA_CTL_8_BITS (0x0) /* Sample Size */ 52 #define SSPA_CTL_12_BITS (0x1) 53 #define SSPA_CTL_16_BITS (0x2) 54 #define SSPA_CTL_20_BITS (0x3) 55 #define SSPA_CTL_24_BITS (0x4) 56 #define SSPA_CTL_32_BITS (0x5) 57 58 /* SSPA Serial Port Register */ 59 #define SSPA_SP_WEN (1 << 31) /* Write Configuration Enable */ 60 #define SSPA_SP_MSL (1 << 18) /* Master Slave Configuration */ 61 #define SSPA_SP_CLKP (1 << 17) /* CLKP Polarity Clock Edge Select */ 62 #define SSPA_SP_FSP (1 << 16) /* FSP Polarity Clock Edge Select */ 63 #define SSPA_SP_FFLUSH (1 << 2) /* FIFO Flush */ 64 #define SSPA_SP_S_RST (1 << 1) /* Active High Reset Signal */ 65 #define SSPA_SP_S_EN (1 << 0) /* Serial Clock Domain Enable */ 66 #define SSPA_SP_FWID(x) ((x) << 20) /* Frame-Sync Width */ 67 #define SSPA_TXSP_FPER(x) ((x) << 4) /* Frame-Sync Active */ 68 69 /* sspa clock sources */ 70 #define MMP_SSPA_CLK_PLL 0 71 #define MMP_SSPA_CLK_VCXO 1 72 #define MMP_SSPA_CLK_AUDIO 3 73 74 /* sspa pll id */ 75 #define MMP_SYSCLK 0 76 #define MMP_SSPA_CLK 1 77 78 #endif /* _MMP_SSPA_H */ 79
