1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_QP_H
34 #define MLX5_QP_H
35
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
38
39 #define MLX5_INVALID_LKEY 0x100
40 /* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */
41 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 8)
42 #define MLX5_DIF_SIZE 8
43 #define MLX5_STRIDE_BLOCK_OP 0x400
44 #define MLX5_CPY_GRD_MASK 0xc0
45 #define MLX5_CPY_APP_MASK 0x30
46 #define MLX5_CPY_REF_MASK 0x0f
47 #define MLX5_BSF_INC_REFTAG (1 << 6)
48 #define MLX5_BSF_INL_VALID (1 << 15)
49 #define MLX5_BSF_REFRESH_DIF (1 << 14)
50 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
51 #define MLX5_BSF_APPTAG_ESCAPE 0x1
52 #define MLX5_BSF_APPREF_ESCAPE 0x2
53
54 enum mlx5_qp_optpar {
55 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
56 MLX5_QP_OPTPAR_RRE = 1 << 1,
57 MLX5_QP_OPTPAR_RAE = 1 << 2,
58 MLX5_QP_OPTPAR_RWE = 1 << 3,
59 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
60 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
61 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
62 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
63 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
64 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
65 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
66 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
67 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
68 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
69 MLX5_QP_OPTPAR_LAG_TX_AFF = 1 << 15,
70 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
71 MLX5_QP_OPTPAR_SRQN = 1 << 18,
72 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
73 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
74 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
75 MLX5_QP_OPTPAR_COUNTER_SET_ID = 1 << 25,
76 };
77
78 enum mlx5_qp_state {
79 MLX5_QP_STATE_RST = 0,
80 MLX5_QP_STATE_INIT = 1,
81 MLX5_QP_STATE_RTR = 2,
82 MLX5_QP_STATE_RTS = 3,
83 MLX5_QP_STATE_SQER = 4,
84 MLX5_QP_STATE_SQD = 5,
85 MLX5_QP_STATE_ERR = 6,
86 MLX5_QP_STATE_SQ_DRAINING = 7,
87 MLX5_QP_STATE_SUSPENDED = 9,
88 MLX5_QP_NUM_STATE,
89 MLX5_QP_STATE,
90 MLX5_QP_STATE_BAD,
91 };
92
93 enum {
94 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
95 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
96 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
97 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
98 };
99
100 enum {
101 MLX5_QP_ST_RC = 0x0,
102 MLX5_QP_ST_UC = 0x1,
103 MLX5_QP_ST_UD = 0x2,
104 MLX5_QP_ST_XRC = 0x3,
105 MLX5_QP_ST_MLX = 0x4,
106 MLX5_QP_ST_DCI = 0x5,
107 MLX5_QP_ST_DCT = 0x6,
108 MLX5_QP_ST_QP0 = 0x7,
109 MLX5_QP_ST_QP1 = 0x8,
110 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
111 MLX5_QP_ST_RAW_IPV6 = 0xa,
112 MLX5_QP_ST_SNIFFER = 0xb,
113 MLX5_QP_ST_SYNC_UMR = 0xe,
114 MLX5_QP_ST_PTP_1588 = 0xd,
115 MLX5_QP_ST_REG_UMR = 0xc,
116 MLX5_QP_ST_MAX
117 };
118
119 enum {
120 MLX5_QP_PM_MIGRATED = 0x3,
121 MLX5_QP_PM_ARMED = 0x0,
122 MLX5_QP_PM_REARM = 0x1
123 };
124
125 enum {
126 MLX5_NON_ZERO_RQ = 0x0,
127 MLX5_SRQ_RQ = 0x1,
128 MLX5_CRQ_RQ = 0x2,
129 MLX5_ZERO_LEN_RQ = 0x3
130 };
131
132 /* TODO REM */
133 enum {
134 /* params1 */
135 MLX5_QP_BIT_SRE = 1 << 15,
136 MLX5_QP_BIT_SWE = 1 << 14,
137 MLX5_QP_BIT_SAE = 1 << 13,
138 /* params2 */
139 MLX5_QP_BIT_RRE = 1 << 15,
140 MLX5_QP_BIT_RWE = 1 << 14,
141 MLX5_QP_BIT_RAE = 1 << 13,
142 MLX5_QP_BIT_RIC = 1 << 4,
143 MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2,
144 MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1,
145 MLX5_QP_BIT_CC_MASTER = 1 << 0
146 };
147
148 enum {
149 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
150 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
151 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
152 };
153
154 enum {
155 MLX5_SEND_WQE_DS = 16,
156 MLX5_SEND_WQE_BB = 64,
157 };
158
159 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
160
161 enum {
162 MLX5_SEND_WQE_MAX_WQEBBS = 16,
163 };
164
165 enum {
166 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
167 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
168 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
169 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
170 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
171 };
172
173 enum {
174 MLX5_FENCE_MODE_NONE = 0 << 5,
175 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
176 MLX5_FENCE_MODE_FENCE = 2 << 5,
177 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
178 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
179 };
180
181 enum {
182 MLX5_RCV_DBR = 0,
183 MLX5_SND_DBR = 1,
184 };
185
186 enum {
187 MLX5_FLAGS_INLINE = 1<<7,
188 MLX5_FLAGS_CHECK_FREE = 1<<5,
189 };
190
191 struct mlx5_wqe_fmr_seg {
192 __be32 flags;
193 __be32 mem_key;
194 __be64 buf_list;
195 __be64 start_addr;
196 __be64 reg_len;
197 __be32 offset;
198 __be32 page_size;
199 u32 reserved[2];
200 };
201
202 struct mlx5_wqe_ctrl_seg {
203 __be32 opmod_idx_opcode;
204 __be32 qpn_ds;
205 u8 signature;
206 u8 rsvd[2];
207 u8 fm_ce_se;
208 union {
209 __be32 general_id;
210 __be32 imm;
211 __be32 umr_mkey;
212 __be32 tis_tir_num;
213 };
214 };
215
216 #define MLX5_WQE_CTRL_DS_MASK 0x3f
217 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
218 #define MLX5_WQE_CTRL_QPN_SHIFT 8
219 #define MLX5_WQE_DS_UNITS 16
220 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff
221 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
222 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
223
224 enum {
225 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
226 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
227 MLX5_ETH_WQE_L3_CSUM = 1 << 6,
228 MLX5_ETH_WQE_L4_CSUM = 1 << 7,
229 };
230
231 enum {
232 MLX5_ETH_WQE_SVLAN = 1 << 0,
233 MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC = 1 << 26,
234 MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC = 1 << 27,
235 MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC = 3 << 26,
236 MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC = 1 << 28,
237 MLX5_ETH_WQE_INSERT_TRAILER = 1 << 30,
238 MLX5_ETH_WQE_INSERT_VLAN = 1 << 15,
239 };
240
241 enum {
242 MLX5_ETH_WQE_SWP_INNER_L3_IPV6 = 1 << 0,
243 MLX5_ETH_WQE_SWP_INNER_L4_UDP = 1 << 1,
244 MLX5_ETH_WQE_SWP_OUTER_L3_IPV6 = 1 << 4,
245 MLX5_ETH_WQE_SWP_OUTER_L4_UDP = 1 << 5,
246 };
247
248 enum {
249 MLX5_ETH_WQE_FT_META_IPSEC = BIT(0),
250 };
251
252 struct mlx5_wqe_eth_seg {
253 u8 swp_outer_l4_offset;
254 u8 swp_outer_l3_offset;
255 u8 swp_inner_l4_offset;
256 u8 swp_inner_l3_offset;
257 u8 cs_flags;
258 u8 swp_flags;
259 __be16 mss;
260 __be32 flow_table_metadata;
261 union {
262 struct {
263 __be16 sz;
264 u8 start[2];
265 } inline_hdr;
266 struct {
267 __be16 type;
268 __be16 vlan_tci;
269 } insert;
270 __be32 trailer;
271 };
272 };
273
274 struct mlx5_wqe_xrc_seg {
275 __be32 xrc_srqn;
276 u8 rsvd[12];
277 };
278
279 struct mlx5_wqe_masked_atomic_seg {
280 __be64 swap_add;
281 __be64 compare;
282 __be64 swap_add_mask;
283 __be64 compare_mask;
284 };
285
286 struct mlx5_base_av {
287 union {
288 struct {
289 __be32 qkey;
290 __be32 reserved;
291 } qkey;
292 __be64 dc_key;
293 } key;
294 __be32 dqp_dct;
295 u8 stat_rate_sl;
296 u8 fl_mlid;
297 union {
298 __be16 rlid;
299 __be16 udp_sport;
300 };
301 };
302
303 struct mlx5_av {
304 union {
305 struct {
306 __be32 qkey;
307 __be32 reserved;
308 } qkey;
309 __be64 dc_key;
310 } key;
311 __be32 dqp_dct;
312 u8 stat_rate_sl;
313 u8 fl_mlid;
314 union {
315 __be16 rlid;
316 __be16 udp_sport;
317 };
318 u8 reserved0[4];
319 u8 rmac[6];
320 u8 tclass;
321 u8 hop_limit;
322 __be32 grh_gid_fl;
323 u8 rgid[16];
324 };
325
326 struct mlx5_ib_ah {
327 struct ib_ah ibah;
328 struct mlx5_av av;
329 u8 xmit_port;
330 };
331
to_mah(struct ib_ah * ibah)332 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
333 {
334 return container_of(ibah, struct mlx5_ib_ah, ibah);
335 }
336
337 struct mlx5_wqe_datagram_seg {
338 struct mlx5_av av;
339 };
340
341 struct mlx5_wqe_raddr_seg {
342 __be64 raddr;
343 __be32 rkey;
344 u32 reserved;
345 };
346
347 struct mlx5_wqe_atomic_seg {
348 __be64 swap_add;
349 __be64 compare;
350 };
351
352 struct mlx5_wqe_data_seg {
353 __be32 byte_count;
354 __be32 lkey;
355 __be64 addr;
356 };
357
358 struct mlx5_wqe_umr_ctrl_seg {
359 u8 flags;
360 u8 rsvd0[3];
361 __be16 xlt_octowords;
362 union {
363 __be16 xlt_offset;
364 __be16 bsf_octowords;
365 };
366 __be64 mkey_mask;
367 __be32 xlt_offset_47_16;
368 u8 rsvd1[28];
369 };
370
371 struct mlx5_seg_set_psv {
372 __be32 psv_num;
373 __be16 syndrome;
374 __be16 status;
375 __be32 transient_sig;
376 __be32 ref_tag;
377 };
378
379 struct mlx5_seg_get_psv {
380 u8 rsvd[19];
381 u8 num_psv;
382 __be32 l_key;
383 __be64 va;
384 __be32 psv_index[4];
385 };
386
387 struct mlx5_seg_check_psv {
388 u8 rsvd0[2];
389 __be16 err_coalescing_op;
390 u8 rsvd1[2];
391 __be16 xport_err_op;
392 u8 rsvd2[2];
393 __be16 xport_err_mask;
394 u8 rsvd3[7];
395 u8 num_psv;
396 __be32 l_key;
397 __be64 va;
398 __be32 psv_index[4];
399 };
400
401 struct mlx5_rwqe_sig {
402 u8 rsvd0[4];
403 u8 signature;
404 u8 rsvd1[11];
405 };
406
407 struct mlx5_wqe_signature_seg {
408 u8 rsvd0[4];
409 u8 signature;
410 u8 rsvd1[11];
411 };
412
413 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
414
415 struct mlx5_wqe_inline_seg {
416 __be32 byte_count;
417 __be32 data[];
418 };
419
420 enum mlx5_sig_type {
421 MLX5_DIF_CRC = 0x1,
422 MLX5_DIF_IPCS = 0x2,
423 };
424
425 struct mlx5_bsf_inl {
426 __be16 vld_refresh;
427 __be16 dif_apptag;
428 __be32 dif_reftag;
429 u8 sig_type;
430 u8 rp_inv_seed;
431 u8 rsvd[3];
432 u8 dif_inc_ref_guard_check;
433 __be16 dif_app_bitmask_check;
434 };
435
436 struct mlx5_bsf {
437 struct mlx5_bsf_basic {
438 u8 bsf_size_sbs;
439 u8 check_byte_mask;
440 union {
441 u8 copy_byte_mask;
442 u8 bs_selector;
443 u8 rsvd_wflags;
444 } wire;
445 union {
446 u8 bs_selector;
447 u8 rsvd_mflags;
448 } mem;
449 __be32 raw_data_size;
450 __be32 w_bfs_psv;
451 __be32 m_bfs_psv;
452 } basic;
453 struct mlx5_bsf_ext {
454 __be32 t_init_gen_pro_size;
455 __be32 rsvd_epi_size;
456 __be32 w_tfs_psv;
457 __be32 m_tfs_psv;
458 } ext;
459 struct mlx5_bsf_inl w_inl;
460 struct mlx5_bsf_inl m_inl;
461 };
462
463 struct mlx5_mtt {
464 __be64 ptag;
465 };
466
467 struct mlx5_klm {
468 __be32 bcount;
469 __be32 key;
470 __be64 va;
471 };
472
473 struct mlx5_stride_block_entry {
474 __be16 stride;
475 __be16 bcount;
476 __be32 key;
477 __be64 va;
478 };
479
480 struct mlx5_stride_block_ctrl_seg {
481 __be32 bcount_per_cycle;
482 __be32 op;
483 __be32 repeat_count;
484 u16 rsvd;
485 __be16 num_entries;
486 };
487
488 struct mlx5_core_qp {
489 struct mlx5_core_rsc_common common; /* must be first */
490 void (*event) (struct mlx5_core_qp *, int);
491 int qpn;
492 struct mlx5_rsc_debug *dbg;
493 int pid;
494 u16 uid;
495 };
496
497 struct mlx5_core_dct {
498 struct mlx5_core_qp mqp;
499 struct completion drained;
500 };
501
502 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
503 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
504
mlx5_qp_type_str(int type)505 static inline const char *mlx5_qp_type_str(int type)
506 {
507 switch (type) {
508 case MLX5_QP_ST_RC: return "RC";
509 case MLX5_QP_ST_UC: return "C";
510 case MLX5_QP_ST_UD: return "UD";
511 case MLX5_QP_ST_XRC: return "XRC";
512 case MLX5_QP_ST_MLX: return "MLX";
513 case MLX5_QP_ST_QP0: return "QP0";
514 case MLX5_QP_ST_QP1: return "QP1";
515 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
516 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
517 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
518 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
519 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
520 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
521 default: return "Invalid transport type";
522 }
523 }
524
mlx5_qp_state_str(int state)525 static inline const char *mlx5_qp_state_str(int state)
526 {
527 switch (state) {
528 case MLX5_QP_STATE_RST:
529 return "RST";
530 case MLX5_QP_STATE_INIT:
531 return "INIT";
532 case MLX5_QP_STATE_RTR:
533 return "RTR";
534 case MLX5_QP_STATE_RTS:
535 return "RTS";
536 case MLX5_QP_STATE_SQER:
537 return "SQER";
538 case MLX5_QP_STATE_SQD:
539 return "SQD";
540 case MLX5_QP_STATE_ERR:
541 return "ERR";
542 case MLX5_QP_STATE_SQ_DRAINING:
543 return "SQ_DRAINING";
544 case MLX5_QP_STATE_SUSPENDED:
545 return "SUSPENDED";
546 default: return "Invalid QP state";
547 }
548 }
549
mlx5_get_qp_default_ts(struct mlx5_core_dev * dev)550 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
551 {
552 return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
553 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING :
554 MLX5_TIMESTAMP_FORMAT_DEFAULT;
555 }
556
557 #endif /* MLX5_QP_H */
558
