1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DEVICE_H
34 #define MLX5_DEVICE_H
35
36 #include <linux/types.h>
37 #include <rdma/ib_verbs.h>
38 #include <linux/mlx5/mlx5_ifc.h>
39 #include <linux/bitfield.h>
40
41 #if defined(__LITTLE_ENDIAN)
42 #define MLX5_SET_HOST_ENDIANNESS 0
43 #elif defined(__BIG_ENDIAN)
44 #define MLX5_SET_HOST_ENDIANNESS 0x80
45 #else
46 #error Host endianness not defined
47 #endif
48
49 /* helper macros */
50 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
51 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
52 #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
53 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
54 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
55 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
56 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
57 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
58 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
59 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
60 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
61 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
62 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
63
64 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
65 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
66 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
67 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
68 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
69 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
70 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
71 #define MLX5_ADDR_OF(typ, p, fld) ((void *)((uint8_t *)(p) + MLX5_BYTE_OFF(typ, fld)))
72
73 /* insert a value to a struct */
74 #define MLX5_SET(typ, p, fld, v) do { \
75 u32 _v = v; \
76 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
77 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
78 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
79 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
80 << __mlx5_dw_bit_off(typ, fld))); \
81 } while (0)
82
83 #define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
84 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
85 MLX5_SET(typ, p, fld[idx], v); \
86 } while (0)
87
88 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
89 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
90 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
91 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
92 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
93 << __mlx5_dw_bit_off(typ, fld))); \
94 } while (0)
95
96 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
97 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
98 __mlx5_mask(typ, fld))
99
100 #define MLX5_GET_PR(typ, p, fld) ({ \
101 u32 ___t = MLX5_GET(typ, p, fld); \
102 pr_debug(#fld " = 0x%x\n", ___t); \
103 ___t; \
104 })
105
106 #define __MLX5_SET64(typ, p, fld, v) do { \
107 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
108 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
109 } while (0)
110
111 #define MLX5_SET64(typ, p, fld, v) do { \
112 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
113 __MLX5_SET64(typ, p, fld, v); \
114 } while (0)
115
116 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
117 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
118 __MLX5_SET64(typ, p, fld[idx], v); \
119 } while (0)
120
121 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
122
123 #define MLX5_GET64_PR(typ, p, fld) ({ \
124 u64 ___t = MLX5_GET64(typ, p, fld); \
125 pr_debug(#fld " = 0x%llx\n", ___t); \
126 ___t; \
127 })
128
129 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
130 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
131 __mlx5_mask16(typ, fld))
132
133 #define MLX5_SET16(typ, p, fld, v) do { \
134 u16 _v = v; \
135 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
136 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
137 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
138 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
139 << __mlx5_16_bit_off(typ, fld))); \
140 } while (0)
141
142 /* Big endian getters */
143 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
144 __mlx5_64_off(typ, fld)))
145
146 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
147 type_t tmp; \
148 switch (sizeof(tmp)) { \
149 case sizeof(u8): \
150 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
151 break; \
152 case sizeof(u16): \
153 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
154 break; \
155 case sizeof(u32): \
156 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
157 break; \
158 case sizeof(u64): \
159 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
160 break; \
161 } \
162 tmp; \
163 })
164
165 enum mlx5_inline_modes {
166 MLX5_INLINE_MODE_NONE,
167 MLX5_INLINE_MODE_L2,
168 MLX5_INLINE_MODE_IP,
169 MLX5_INLINE_MODE_TCP_UDP,
170 };
171
172 enum {
173 MLX5_MAX_COMMANDS = 32,
174 MLX5_CMD_DATA_BLOCK_SIZE = 512,
175 MLX5_PCI_CMD_XPORT = 7,
176 MLX5_MKEY_BSF_OCTO_SIZE = 4,
177 MLX5_MAX_PSVS = 4,
178 };
179
180 enum {
181 MLX5_EXTENDED_UD_AV = 0x80000000,
182 };
183
184 enum {
185 MLX5_CQ_STATE_ARMED = 9,
186 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
187 MLX5_CQ_STATE_FIRED = 0xa,
188 };
189
190 enum {
191 MLX5_STAT_RATE_OFFSET = 5,
192 };
193
194 enum {
195 MLX5_INLINE_SEG = 0x80000000,
196 };
197
198 enum {
199 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
200 };
201
202 enum {
203 MLX5_MIN_PKEY_TABLE_SIZE = 128,
204 MLX5_MAX_LOG_PKEY_TABLE = 5,
205 };
206
207 enum {
208 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
209 };
210
211 enum {
212 MLX5_PFAULT_SUBTYPE_WQE = 0,
213 MLX5_PFAULT_SUBTYPE_RDMA = 1,
214 };
215
216 enum wqe_page_fault_type {
217 MLX5_WQE_PF_TYPE_RMP = 0,
218 MLX5_WQE_PF_TYPE_REQ_SEND_OR_WRITE = 1,
219 MLX5_WQE_PF_TYPE_RESP = 2,
220 MLX5_WQE_PF_TYPE_REQ_READ_OR_ATOMIC = 3,
221 };
222
223 enum {
224 MLX5_PERM_LOCAL_READ = 1 << 2,
225 MLX5_PERM_LOCAL_WRITE = 1 << 3,
226 MLX5_PERM_REMOTE_READ = 1 << 4,
227 MLX5_PERM_REMOTE_WRITE = 1 << 5,
228 MLX5_PERM_ATOMIC = 1 << 6,
229 MLX5_PERM_UMR_EN = 1 << 7,
230 };
231
232 enum {
233 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
234 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
235 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
236 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
237 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
238 };
239
240 enum {
241 MLX5_EN_RD = (u64)1,
242 MLX5_EN_WR = (u64)2
243 };
244
245 enum {
246 MLX5_ADAPTER_PAGE_SHIFT = 12,
247 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
248 };
249
250 enum {
251 MLX5_BFREGS_PER_UAR = 4,
252 MLX5_MAX_UARS = 1 << 8,
253 MLX5_NON_FP_BFREGS_PER_UAR = 2,
254 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
255 MLX5_NON_FP_BFREGS_PER_UAR,
256 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
257 MLX5_NON_FP_BFREGS_PER_UAR,
258 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
259 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
260 MLX5_MIN_DYN_BFREGS = 512,
261 MLX5_MAX_DYN_BFREGS = 1024,
262 };
263
264 enum {
265 MLX5_MKEY_MASK_LEN = 1ull << 0,
266 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
267 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
268 MLX5_MKEY_MASK_PD = 1ull << 7,
269 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
270 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
271 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
272 MLX5_MKEY_MASK_KEY = 1ull << 13,
273 MLX5_MKEY_MASK_QPN = 1ull << 14,
274 MLX5_MKEY_MASK_LR = 1ull << 17,
275 MLX5_MKEY_MASK_LW = 1ull << 18,
276 MLX5_MKEY_MASK_RR = 1ull << 19,
277 MLX5_MKEY_MASK_RW = 1ull << 20,
278 MLX5_MKEY_MASK_A = 1ull << 21,
279 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
280 MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE = 1ull << 25,
281 MLX5_MKEY_MASK_FREE = 1ull << 29,
282 MLX5_MKEY_MASK_RELAXED_ORDERING_READ = 1ull << 47,
283 };
284
285 enum {
286 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
287
288 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
289 MLX5_UMR_CHECK_FREE = (2 << 5),
290
291 MLX5_UMR_INLINE = (1 << 7),
292 };
293
294 #define MLX5_UMR_FLEX_ALIGNMENT 0x40
295 #define MLX5_UMR_MTT_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_mtt))
296 #define MLX5_UMR_KLM_NUM_ENTRIES_ALIGNMENT (MLX5_UMR_FLEX_ALIGNMENT / sizeof(struct mlx5_klm))
297
298 #define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
299
300 enum {
301 MLX5_EVENT_QUEUE_TYPE_QP = 0,
302 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
303 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
304 MLX5_EVENT_QUEUE_TYPE_DCT = 6,
305 };
306
307 /* mlx5 components can subscribe to any one of these events via
308 * mlx5_eq_notifier_register API.
309 */
310 enum mlx5_event {
311 /* Special value to subscribe to any event */
312 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0,
313 /* HW events enum start: comp events are not subscribable */
314 MLX5_EVENT_TYPE_COMP = 0x0,
315 /* HW Async events enum start: subscribable events */
316 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
317 MLX5_EVENT_TYPE_COMM_EST = 0x02,
318 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
319 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
320 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
321
322 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
323 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
324 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
325 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
326 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
327 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
328 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
329
330 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
331 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
332 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
333 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
334 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
335 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18,
336 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
337 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
338 MLX5_EVENT_TYPE_MONITOR_COUNTER = 0x24,
339 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
340
341 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
342 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
343
344 MLX5_EVENT_TYPE_CMD = 0x0a,
345 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
346
347 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
348 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
349
350 MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED = 0xe,
351 MLX5_EVENT_TYPE_VHCA_STATE_CHANGE = 0xf,
352
353 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
354 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
355
356 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
357 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
358
359 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
360
361 MLX5_EVENT_TYPE_MAX = 0x100,
362 };
363
364 enum mlx5_driver_event {
365 MLX5_DRIVER_EVENT_TYPE_TRAP = 0,
366 MLX5_DRIVER_EVENT_UPLINK_NETDEV,
367 MLX5_DRIVER_EVENT_MACSEC_SA_ADDED,
368 MLX5_DRIVER_EVENT_MACSEC_SA_DELETED,
369 };
370
371 enum {
372 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
373 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
374 MLX5_TRACER_SUBTYPE_STRINGS_DB_UPDATE = 0x2,
375 };
376
377 enum {
378 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
379 MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
380 MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT = 0x7,
381 MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8,
382 };
383
384 enum {
385 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
386 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
387 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
388 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
389 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
390 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
391 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
392 };
393
394 enum {
395 MLX5_ROCE_VERSION_1 = 0,
396 MLX5_ROCE_VERSION_2 = 2,
397 };
398
399 enum {
400 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
401 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
402 };
403
404 enum {
405 MLX5_ROCE_L3_TYPE_IPV4 = 0,
406 MLX5_ROCE_L3_TYPE_IPV6 = 1,
407 };
408
409 enum {
410 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
411 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
412 };
413
414 enum {
415 MLX5_OPCODE_NOP = 0x00,
416 MLX5_OPCODE_SEND_INVAL = 0x01,
417 MLX5_OPCODE_RDMA_WRITE = 0x08,
418 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
419 MLX5_OPCODE_SEND = 0x0a,
420 MLX5_OPCODE_SEND_IMM = 0x0b,
421 MLX5_OPCODE_LSO = 0x0e,
422 MLX5_OPCODE_RDMA_READ = 0x10,
423 MLX5_OPCODE_ATOMIC_CS = 0x11,
424 MLX5_OPCODE_ATOMIC_FA = 0x12,
425 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
426 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
427 MLX5_OPCODE_BIND_MW = 0x18,
428 MLX5_OPCODE_CONFIG_CMD = 0x1f,
429 MLX5_OPCODE_ENHANCED_MPSW = 0x29,
430
431 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
432 MLX5_RECV_OPCODE_SEND = 0x01,
433 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
434 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
435
436 MLX5_CQE_OPCODE_ERROR = 0x1e,
437 MLX5_CQE_OPCODE_RESIZE = 0x16,
438
439 MLX5_OPCODE_SET_PSV = 0x20,
440 MLX5_OPCODE_GET_PSV = 0x21,
441 MLX5_OPCODE_CHECK_PSV = 0x22,
442 MLX5_OPCODE_DUMP = 0x23,
443 MLX5_OPCODE_RGET_PSV = 0x26,
444 MLX5_OPCODE_RCHECK_PSV = 0x27,
445
446 MLX5_OPCODE_UMR = 0x25,
447
448 MLX5_OPCODE_FLOW_TBL_ACCESS = 0x2c,
449
450 MLX5_OPCODE_ACCESS_ASO = 0x2d,
451 };
452
453 enum {
454 MLX5_OPC_MOD_TLS_TIS_STATIC_PARAMS = 0x1,
455 MLX5_OPC_MOD_TLS_TIR_STATIC_PARAMS = 0x2,
456 };
457
458 enum {
459 MLX5_OPC_MOD_TLS_TIS_PROGRESS_PARAMS = 0x1,
460 MLX5_OPC_MOD_TLS_TIR_PROGRESS_PARAMS = 0x2,
461 };
462
463 struct mlx5_wqe_tls_static_params_seg {
464 u8 ctx[MLX5_ST_SZ_BYTES(tls_static_params)];
465 };
466
467 struct mlx5_wqe_tls_progress_params_seg {
468 __be32 tis_tir_num;
469 u8 ctx[MLX5_ST_SZ_BYTES(tls_progress_params)];
470 };
471
472 enum {
473 MLX5_SET_PORT_RESET_QKEY = 0,
474 MLX5_SET_PORT_GUID0 = 16,
475 MLX5_SET_PORT_NODE_GUID = 17,
476 MLX5_SET_PORT_SYS_GUID = 18,
477 MLX5_SET_PORT_GID_TABLE = 19,
478 MLX5_SET_PORT_PKEY_TABLE = 20,
479 };
480
481 enum {
482 MLX5_BW_NO_LIMIT = 0,
483 MLX5_100_MBPS_UNIT = 3,
484 MLX5_GBPS_UNIT = 4,
485 };
486
487 enum {
488 MLX5_MAX_PAGE_SHIFT = 31
489 };
490
491 enum {
492 /*
493 * Max wqe size for rdma read is 512 bytes, so this
494 * limits our max_sge_rd as the wqe needs to fit:
495 * - ctrl segment (16 bytes)
496 * - rdma segment (16 bytes)
497 * - scatter elements (16 bytes each)
498 */
499 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
500 };
501
502 enum mlx5_odp_transport_cap_bits {
503 MLX5_ODP_SUPPORT_SEND = 1 << 31,
504 MLX5_ODP_SUPPORT_RECV = 1 << 30,
505 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
506 MLX5_ODP_SUPPORT_READ = 1 << 28,
507 };
508
509 struct mlx5_odp_caps {
510 char reserved[0x10];
511 struct {
512 __be32 rc_odp_caps;
513 __be32 uc_odp_caps;
514 __be32 ud_odp_caps;
515 } per_transport_caps;
516 char reserved2[0xe4];
517 };
518
519 struct mlx5_cmd_layout {
520 u8 type;
521 u8 rsvd0[3];
522 __be32 inlen;
523 __be64 in_ptr;
524 __be32 in[4];
525 __be32 out[4];
526 __be64 out_ptr;
527 __be32 outlen;
528 u8 token;
529 u8 sig;
530 u8 rsvd1;
531 u8 status_own;
532 };
533
534 enum mlx5_rfr_severity_bit_offsets {
535 MLX5_RFR_BIT_OFFSET = 0x7,
536 };
537
538 struct health_buffer {
539 __be32 assert_var[6];
540 __be32 rsvd0[2];
541 __be32 assert_exit_ptr;
542 __be32 assert_callra;
543 __be32 rsvd1[1];
544 __be32 time;
545 __be32 fw_ver;
546 __be32 hw_id;
547 u8 rfr_severity;
548 u8 rsvd2[3];
549 u8 irisc_index;
550 u8 synd;
551 __be16 ext_synd;
552 };
553
554 enum mlx5_initializing_bit_offsets {
555 MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
556 };
557
558 enum mlx5_cmd_addr_l_sz_offset {
559 MLX5_NIC_IFC_OFFSET = 8,
560 };
561
562 struct mlx5_init_seg {
563 __be32 fw_rev;
564 __be32 cmdif_rev_fw_sub;
565 __be32 rsvd0[2];
566 __be32 cmdq_addr_h;
567 __be32 cmdq_addr_l_sz;
568 __be32 cmd_dbell;
569 __be32 rsvd1[120];
570 __be32 initializing;
571 struct health_buffer health;
572 __be32 rsvd2[878];
573 __be32 cmd_exec_to;
574 __be32 cmd_q_init_to;
575 __be32 internal_timer_h;
576 __be32 internal_timer_l;
577 __be32 rsvd3[2];
578 __be32 health_counter;
579 __be32 rsvd4[11];
580 __be32 real_time_h;
581 __be32 real_time_l;
582 __be32 rsvd5[1006];
583 __be64 ieee1588_clk;
584 __be32 ieee1588_clk_type;
585 __be32 clr_intx;
586 };
587
588 struct mlx5_eqe_comp {
589 __be32 reserved[6];
590 __be32 cqn;
591 };
592
593 struct mlx5_eqe_qp_srq {
594 __be32 reserved1[5];
595 u8 type;
596 u8 reserved2[3];
597 __be32 qp_srq_n;
598 };
599
600 struct mlx5_eqe_cq_err {
601 __be32 cqn;
602 u8 reserved1[7];
603 u8 syndrome;
604 };
605
606 struct mlx5_eqe_xrq_err {
607 __be32 reserved1[5];
608 __be32 type_xrqn;
609 __be32 reserved2;
610 };
611
612 struct mlx5_eqe_port_state {
613 u8 reserved0[8];
614 u8 port;
615 };
616
617 struct mlx5_eqe_gpio {
618 __be32 reserved0[2];
619 __be64 gpio_event;
620 };
621
622 struct mlx5_eqe_congestion {
623 u8 type;
624 u8 rsvd0;
625 u8 congestion_level;
626 };
627
628 struct mlx5_eqe_stall_vl {
629 u8 rsvd0[3];
630 u8 port_vl;
631 };
632
633 struct mlx5_eqe_cmd {
634 __be32 vector;
635 __be32 rsvd[6];
636 };
637
638 struct mlx5_eqe_page_req {
639 __be16 ec_function;
640 __be16 func_id;
641 __be32 num_pages;
642 __be32 rsvd1[5];
643 };
644
645 struct mlx5_eqe_page_fault {
646 __be32 bytes_committed;
647 union {
648 struct {
649 u16 reserved1;
650 __be16 wqe_index;
651 u16 reserved2;
652 __be16 packet_length;
653 __be32 token;
654 u8 reserved4[8];
655 __be32 pftype_wq;
656 } __packed wqe;
657 struct {
658 __be32 r_key;
659 u16 reserved1;
660 __be16 packet_length;
661 __be32 rdma_op_len;
662 __be64 rdma_va;
663 __be32 pftype_token;
664 } __packed rdma;
665 } __packed;
666 } __packed;
667
668 struct mlx5_eqe_vport_change {
669 u8 rsvd0[2];
670 __be16 vport_num;
671 __be32 rsvd1[6];
672 } __packed;
673
674 struct mlx5_eqe_port_module {
675 u8 reserved_at_0[1];
676 u8 module;
677 u8 reserved_at_2[1];
678 u8 module_status;
679 u8 reserved_at_4[2];
680 u8 error_type;
681 } __packed;
682
683 struct mlx5_eqe_pps {
684 u8 rsvd0[3];
685 u8 pin;
686 u8 rsvd1[4];
687 union {
688 struct {
689 __be32 time_sec;
690 __be32 time_nsec;
691 };
692 struct {
693 __be64 time_stamp;
694 };
695 };
696 u8 rsvd2[12];
697 } __packed;
698
699 struct mlx5_eqe_dct {
700 __be32 reserved[6];
701 __be32 dctn;
702 };
703
704 struct mlx5_eqe_temp_warning {
705 __be64 sensor_warning_msb;
706 __be64 sensor_warning_lsb;
707 } __packed;
708
709 struct mlx5_eqe_obj_change {
710 u8 rsvd0[2];
711 __be16 obj_type;
712 __be32 obj_id;
713 } __packed;
714
715 #define SYNC_RST_STATE_MASK 0xf
716
717 enum sync_rst_state_type {
718 MLX5_SYNC_RST_STATE_RESET_REQUEST = 0x0,
719 MLX5_SYNC_RST_STATE_RESET_NOW = 0x1,
720 MLX5_SYNC_RST_STATE_RESET_ABORT = 0x2,
721 MLX5_SYNC_RST_STATE_RESET_UNLOAD = 0x3,
722 };
723
724 struct mlx5_eqe_sync_fw_update {
725 u8 reserved_at_0[3];
726 u8 sync_rst_state;
727 };
728
729 struct mlx5_eqe_vhca_state {
730 __be16 ec_function;
731 __be16 function_id;
732 } __packed;
733
734 union ev_data {
735 __be32 raw[7];
736 struct mlx5_eqe_cmd cmd;
737 struct mlx5_eqe_comp comp;
738 struct mlx5_eqe_qp_srq qp_srq;
739 struct mlx5_eqe_cq_err cq_err;
740 struct mlx5_eqe_port_state port;
741 struct mlx5_eqe_gpio gpio;
742 struct mlx5_eqe_congestion cong;
743 struct mlx5_eqe_stall_vl stall_vl;
744 struct mlx5_eqe_page_req req_pages;
745 struct mlx5_eqe_page_fault page_fault;
746 struct mlx5_eqe_vport_change vport_change;
747 struct mlx5_eqe_port_module port_module;
748 struct mlx5_eqe_pps pps;
749 struct mlx5_eqe_dct dct;
750 struct mlx5_eqe_temp_warning temp_warning;
751 struct mlx5_eqe_xrq_err xrq_err;
752 struct mlx5_eqe_sync_fw_update sync_fw_update;
753 struct mlx5_eqe_vhca_state vhca_state;
754 struct mlx5_eqe_obj_change obj_change;
755 } __packed;
756
757 struct mlx5_eqe {
758 u8 rsvd0;
759 u8 type;
760 u8 rsvd1;
761 u8 sub_type;
762 __be32 rsvd2[7];
763 union ev_data data;
764 __be16 rsvd3;
765 u8 signature;
766 u8 owner;
767 } __packed;
768
769 struct mlx5_cmd_prot_block {
770 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
771 u8 rsvd0[48];
772 __be64 next;
773 __be32 block_num;
774 u8 rsvd1;
775 u8 token;
776 u8 ctrl_sig;
777 u8 sig;
778 };
779
780 enum {
781 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
782 };
783
784 struct mlx5_err_cqe {
785 u8 rsvd0[32];
786 __be32 srqn;
787 u8 rsvd1[18];
788 u8 vendor_err_synd;
789 u8 syndrome;
790 __be32 s_wqe_opcode_qpn;
791 __be16 wqe_counter;
792 u8 signature;
793 u8 op_own;
794 };
795
796 struct mlx5_cqe64 {
797 u8 tls_outer_l3_tunneled;
798 u8 rsvd0;
799 __be16 wqe_id;
800 union {
801 struct {
802 u8 tcppsh_abort_dupack;
803 u8 min_ttl;
804 __be16 tcp_win;
805 __be32 ack_seq_num;
806 } lro;
807 struct {
808 u8 reserved0:1;
809 u8 match:1;
810 u8 flush:1;
811 u8 reserved3:5;
812 u8 header_size;
813 __be16 header_entry_index;
814 __be32 data_offset;
815 } shampo;
816 };
817 __be32 rss_hash_result;
818 u8 rss_hash_type;
819 u8 ml_path;
820 u8 rsvd20[2];
821 __be16 check_sum;
822 __be16 slid;
823 __be32 flags_rqpn;
824 u8 hds_ip_ext;
825 u8 l4_l3_hdr_type;
826 __be16 vlan_info;
827 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
828 union {
829 __be32 immediate;
830 __be32 inval_rkey;
831 __be32 pkey;
832 __be32 ft_metadata;
833 };
834 u8 rsvd40[4];
835 __be32 byte_cnt;
836 __be32 timestamp_h;
837 __be32 timestamp_l;
838 __be32 sop_drop_qpn;
839 __be16 wqe_counter;
840 union {
841 u8 signature;
842 u8 validity_iteration_count;
843 };
844 u8 op_own;
845 };
846
847 struct mlx5_mini_cqe8 {
848 union {
849 __be32 rx_hash_result;
850 struct {
851 __be16 checksum;
852 __be16 stridx;
853 };
854 struct {
855 __be16 wqe_counter;
856 u8 s_wqe_opcode;
857 u8 reserved;
858 } s_wqe_info;
859 };
860 __be32 byte_cnt;
861 };
862
863 enum {
864 MLX5_NO_INLINE_DATA,
865 MLX5_INLINE_DATA32_SEG,
866 MLX5_INLINE_DATA64_SEG,
867 MLX5_COMPRESSED,
868 };
869
870 enum {
871 MLX5_CQE_FORMAT_CSUM = 0x1,
872 MLX5_CQE_FORMAT_CSUM_STRIDX = 0x3,
873 };
874
875 enum {
876 MLX5_CQE_COMPRESS_LAYOUT_BASIC = 0,
877 MLX5_CQE_COMPRESS_LAYOUT_ENHANCED = 1,
878 };
879
880 #define MLX5_MINI_CQE_ARRAY_SIZE 8
881
mlx5_get_cqe_format(struct mlx5_cqe64 * cqe)882 static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
883 {
884 return (cqe->op_own >> 2) & 0x3;
885 }
886
get_cqe_opcode(struct mlx5_cqe64 * cqe)887 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
888 {
889 return cqe->op_own >> 4;
890 }
891
get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 * cqe)892 static inline u8 get_cqe_enhanced_num_mini_cqes(struct mlx5_cqe64 *cqe)
893 {
894 /* num_of_mini_cqes is zero based */
895 return get_cqe_opcode(cqe) + 1;
896 }
897
get_cqe_lro_tcppsh(struct mlx5_cqe64 * cqe)898 static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
899 {
900 return (cqe->lro.tcppsh_abort_dupack >> 6) & 1;
901 }
902
get_cqe_l4_hdr_type(struct mlx5_cqe64 * cqe)903 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
904 {
905 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
906 }
907
cqe_is_tunneled(struct mlx5_cqe64 * cqe)908 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
909 {
910 return cqe->tls_outer_l3_tunneled & 0x1;
911 }
912
get_cqe_tls_offload(struct mlx5_cqe64 * cqe)913 static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe)
914 {
915 return (cqe->tls_outer_l3_tunneled >> 3) & 0x3;
916 }
917
cqe_has_vlan(struct mlx5_cqe64 * cqe)918 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
919 {
920 return cqe->l4_l3_hdr_type & 0x1;
921 }
922
get_cqe_ts(struct mlx5_cqe64 * cqe)923 static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
924 {
925 u32 hi, lo;
926
927 hi = be32_to_cpu(cqe->timestamp_h);
928 lo = be32_to_cpu(cqe->timestamp_l);
929
930 return (u64)lo | ((u64)hi << 32);
931 }
932
get_cqe_flow_tag(struct mlx5_cqe64 * cqe)933 static inline u16 get_cqe_flow_tag(struct mlx5_cqe64 *cqe)
934 {
935 return be32_to_cpu(cqe->sop_drop_qpn) & 0xFFF;
936 }
937
938 #define MLX5_MPWQE_LOG_NUM_STRIDES_EXT_BASE 3
939 #define MLX5_MPWQE_LOG_NUM_STRIDES_BASE 9
940 #define MLX5_MPWQE_LOG_NUM_STRIDES_MAX 16
941 #define MLX5_MPWQE_LOG_STRIDE_SZ_BASE 6
942 #define MLX5_MPWQE_LOG_STRIDE_SZ_MAX 13
943
944 struct mpwrq_cqe_bc {
945 __be16 filler_consumed_strides;
946 __be16 byte_cnt;
947 };
948
mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 * cqe)949 static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
950 {
951 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
952
953 return be16_to_cpu(bc->byte_cnt);
954 }
955
mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc * bc)956 static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
957 {
958 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
959 }
960
mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 * cqe)961 static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
962 {
963 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
964
965 return mpwrq_get_cqe_bc_consumed_strides(bc);
966 }
967
mpwrq_is_filler_cqe(struct mlx5_cqe64 * cqe)968 static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
969 {
970 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
971
972 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
973 }
974
mpwrq_get_cqe_stride_index(struct mlx5_cqe64 * cqe)975 static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
976 {
977 return be16_to_cpu(cqe->wqe_counter);
978 }
979
980 enum {
981 CQE_L4_HDR_TYPE_NONE = 0x0,
982 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
983 CQE_L4_HDR_TYPE_UDP = 0x2,
984 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
985 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
986 };
987
988 enum {
989 CQE_RSS_HTYPE_IP = GENMASK(3, 2),
990 /* cqe->rss_hash_type[3:2] - IP destination selected for hash
991 * (00 = none, 01 = IPv4, 10 = IPv6, 11 = Reserved)
992 */
993 CQE_RSS_IP_NONE = 0x0,
994 CQE_RSS_IPV4 = 0x1,
995 CQE_RSS_IPV6 = 0x2,
996 CQE_RSS_RESERVED = 0x3,
997
998 CQE_RSS_HTYPE_L4 = GENMASK(7, 6),
999 /* cqe->rss_hash_type[7:6] - L4 destination selected for hash
1000 * (00 = none, 01 = TCP. 10 = UDP, 11 = IPSEC.SPI
1001 */
1002 CQE_RSS_L4_NONE = 0x0,
1003 CQE_RSS_L4_TCP = 0x1,
1004 CQE_RSS_L4_UDP = 0x2,
1005 CQE_RSS_L4_IPSEC = 0x3,
1006 };
1007
1008 enum {
1009 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
1010 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
1011 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
1012 };
1013
1014 enum {
1015 CQE_L2_OK = 1 << 0,
1016 CQE_L3_OK = 1 << 1,
1017 CQE_L4_OK = 1 << 2,
1018 };
1019
1020 enum {
1021 CQE_TLS_OFFLOAD_NOT_DECRYPTED = 0x0,
1022 CQE_TLS_OFFLOAD_DECRYPTED = 0x1,
1023 CQE_TLS_OFFLOAD_RESYNC = 0x2,
1024 CQE_TLS_OFFLOAD_ERROR = 0x3,
1025 };
1026
1027 struct mlx5_sig_err_cqe {
1028 u8 rsvd0[16];
1029 __be32 expected_trans_sig;
1030 __be32 actual_trans_sig;
1031 __be32 expected_reftag;
1032 __be32 actual_reftag;
1033 __be16 syndrome;
1034 u8 rsvd22[2];
1035 __be32 mkey;
1036 __be64 err_offset;
1037 u8 rsvd30[8];
1038 __be32 qpn;
1039 u8 rsvd38[2];
1040 u8 signature;
1041 u8 op_own;
1042 };
1043
1044 struct mlx5_wqe_srq_next_seg {
1045 u8 rsvd0[2];
1046 __be16 next_wqe_index;
1047 u8 signature;
1048 u8 rsvd1[11];
1049 };
1050
1051 union mlx5_ext_cqe {
1052 struct ib_grh grh;
1053 u8 inl[64];
1054 };
1055
1056 struct mlx5_cqe128 {
1057 union mlx5_ext_cqe inl_grh;
1058 struct mlx5_cqe64 cqe64;
1059 };
1060
1061 enum {
1062 MLX5_MKEY_STATUS_FREE = 1 << 6,
1063 };
1064
1065 enum {
1066 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
1067 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
1068 MLX5_MKEY_BSF_EN = 1 << 30,
1069 };
1070
1071 struct mlx5_mkey_seg {
1072 /* This is a two bit field occupying bits 31-30.
1073 * bit 31 is always 0,
1074 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have translation
1075 */
1076 u8 status;
1077 u8 pcie_control;
1078 u8 flags;
1079 u8 version;
1080 __be32 qpn_mkey7_0;
1081 u8 rsvd1[4];
1082 __be32 flags_pd;
1083 __be64 start_addr;
1084 __be64 len;
1085 __be32 bsfs_octo_size;
1086 u8 rsvd2[16];
1087 __be32 xlt_oct_size;
1088 u8 rsvd3[3];
1089 u8 log2_page_size;
1090 u8 rsvd4[4];
1091 };
1092
1093 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1094
1095 enum {
1096 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1097 };
1098
1099 enum {
1100 VPORT_STATE_DOWN = 0x0,
1101 VPORT_STATE_UP = 0x1,
1102 };
1103
1104 enum {
1105 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0,
1106 MLX5_VPORT_ADMIN_STATE_UP = 0x1,
1107 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2,
1108 };
1109
1110 enum {
1111 MLX5_VPORT_CVLAN_INSERT_WHEN_NO_CVLAN = 0x1,
1112 MLX5_VPORT_CVLAN_INSERT_ALWAYS = 0x3,
1113 };
1114
1115 enum {
1116 MLX5_L3_PROT_TYPE_IPV4 = 0,
1117 MLX5_L3_PROT_TYPE_IPV6 = 1,
1118 };
1119
1120 enum {
1121 MLX5_L4_PROT_TYPE_TCP = 0,
1122 MLX5_L4_PROT_TYPE_UDP = 1,
1123 };
1124
1125 enum {
1126 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1127 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1128 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1129 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1130 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1131 };
1132
1133 enum {
1134 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1135 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1136 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1137 MLX5_MATCH_MISC_PARAMETERS_2 = 1 << 3,
1138 MLX5_MATCH_MISC_PARAMETERS_3 = 1 << 4,
1139 MLX5_MATCH_MISC_PARAMETERS_4 = 1 << 5,
1140 MLX5_MATCH_MISC_PARAMETERS_5 = 1 << 6,
1141 };
1142
1143 enum {
1144 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1145 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1146 };
1147
1148 enum {
1149 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1150 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1151 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1152 };
1153
1154 enum mlx5_list_type {
1155 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
1156 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
1157 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
1158 };
1159
1160 enum {
1161 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1162 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1163 };
1164
1165 enum mlx5_wol_mode {
1166 MLX5_WOL_DISABLE = 0,
1167 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1168 MLX5_WOL_MAGIC = 1 << 2,
1169 MLX5_WOL_ARP = 1 << 3,
1170 MLX5_WOL_BROADCAST = 1 << 4,
1171 MLX5_WOL_MULTICAST = 1 << 5,
1172 MLX5_WOL_UNICAST = 1 << 6,
1173 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1174 };
1175
1176 enum mlx5_mpls_supported_fields {
1177 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1178 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1,
1179 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1180 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
1181 };
1182
1183 enum mlx5_flex_parser_protos {
1184 MLX5_FLEX_PROTO_GENEVE = 1 << 3,
1185 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
1186 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
1187 MLX5_FLEX_PROTO_ICMP = 1 << 8,
1188 MLX5_FLEX_PROTO_ICMPV6 = 1 << 9,
1189 };
1190
1191 /* MLX5 DEV CAPs */
1192
1193 /* TODO: EAT.ME */
1194 enum mlx5_cap_mode {
1195 HCA_CAP_OPMOD_GET_MAX = 0,
1196 HCA_CAP_OPMOD_GET_CUR = 1,
1197 };
1198
1199 /* Any new cap addition must update mlx5_hca_caps_alloc() to allocate
1200 * capability memory.
1201 */
1202 enum mlx5_cap_type {
1203 MLX5_CAP_GENERAL = 0,
1204 MLX5_CAP_ETHERNET_OFFLOADS,
1205 MLX5_CAP_ODP,
1206 MLX5_CAP_ATOMIC,
1207 MLX5_CAP_ROCE,
1208 MLX5_CAP_IPOIB_OFFLOADS,
1209 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1210 MLX5_CAP_FLOW_TABLE,
1211 MLX5_CAP_ESWITCH_FLOW_TABLE,
1212 MLX5_CAP_ESWITCH,
1213 MLX5_CAP_QOS = 0xc,
1214 MLX5_CAP_DEBUG,
1215 MLX5_CAP_RESERVED_14,
1216 MLX5_CAP_DEV_MEM,
1217 MLX5_CAP_RESERVED_16,
1218 MLX5_CAP_TLS,
1219 MLX5_CAP_VDPA_EMULATION = 0x13,
1220 MLX5_CAP_DEV_EVENT = 0x14,
1221 MLX5_CAP_IPSEC,
1222 MLX5_CAP_CRYPTO = 0x1a,
1223 MLX5_CAP_MACSEC = 0x1f,
1224 MLX5_CAP_GENERAL_2 = 0x20,
1225 MLX5_CAP_PORT_SELECTION = 0x25,
1226 MLX5_CAP_ADV_VIRTUALIZATION = 0x26,
1227 /* NUM OF CAP Types */
1228 MLX5_CAP_NUM
1229 };
1230
1231 enum mlx5_pcam_reg_groups {
1232 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1233 };
1234
1235 enum mlx5_pcam_feature_groups {
1236 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1237 };
1238
1239 enum mlx5_mcam_reg_groups {
1240 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1241 MLX5_MCAM_REGS_0x9100_0x917F = 0x2,
1242 MLX5_MCAM_REGS_NUM = 0x3,
1243 };
1244
1245 enum mlx5_mcam_feature_groups {
1246 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1247 };
1248
1249 enum mlx5_qcam_reg_groups {
1250 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1251 };
1252
1253 enum mlx5_qcam_feature_groups {
1254 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1255 };
1256
1257 /* GET Dev Caps macros */
1258 #define MLX5_CAP_GEN(mdev, cap) \
1259 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1260
1261 #define MLX5_CAP_GEN_64(mdev, cap) \
1262 MLX5_GET64(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->cur, cap)
1263
1264 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1265 MLX5_GET(cmd_hca_cap, mdev->caps.hca[MLX5_CAP_GENERAL]->max, cap)
1266
1267 #define MLX5_CAP_GEN_2(mdev, cap) \
1268 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1269
1270 #define MLX5_CAP_GEN_2_64(mdev, cap) \
1271 MLX5_GET64(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->cur, cap)
1272
1273 #define MLX5_CAP_GEN_2_MAX(mdev, cap) \
1274 MLX5_GET(cmd_hca_cap_2, mdev->caps.hca[MLX5_CAP_GENERAL_2]->max, cap)
1275
1276 #define MLX5_CAP_ETH(mdev, cap) \
1277 MLX5_GET(per_protocol_networking_offload_caps,\
1278 mdev->caps.hca[MLX5_CAP_ETHERNET_OFFLOADS]->cur, cap)
1279
1280 #define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1281 MLX5_GET(per_protocol_networking_offload_caps,\
1282 mdev->caps.hca[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS]->cur, cap)
1283
1284 #define MLX5_CAP_ROCE(mdev, cap) \
1285 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->cur, cap)
1286
1287 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1288 MLX5_GET(roce_cap, mdev->caps.hca[MLX5_CAP_ROCE]->max, cap)
1289
1290 #define MLX5_CAP_ATOMIC(mdev, cap) \
1291 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->cur, cap)
1292
1293 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1294 MLX5_GET(atomic_caps, mdev->caps.hca[MLX5_CAP_ATOMIC]->max, cap)
1295
1296 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1297 MLX5_GET(flow_table_nic_cap, mdev->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1298
1299 #define MLX5_CAP64_FLOWTABLE(mdev, cap) \
1300 MLX5_GET64(flow_table_nic_cap, (mdev)->caps.hca[MLX5_CAP_FLOW_TABLE]->cur, cap)
1301
1302 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1303 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1304
1305 #define MLX5_CAP_FLOWTABLE_NIC_TX(mdev, cap) \
1306 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit.cap)
1307
1308 #define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1309 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1310
1311 #define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1312 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1313
1314 #define MLX5_CAP_FLOWTABLE_RDMA_RX(mdev, cap) \
1315 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_rdma.cap)
1316
1317 #define MLX5_CAP_FLOWTABLE_RDMA_TX(mdev, cap) \
1318 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_rdma.cap)
1319
1320 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1321 MLX5_GET(flow_table_eswitch_cap, \
1322 mdev->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1323
1324 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1325 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1326
1327 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1328 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1329
1330 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1331 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1332
1333 #define MLX5_CAP_ESW_FT_FIELD_SUPPORT_2(mdev, cap) \
1334 MLX5_CAP_ESW_FLOWTABLE(mdev, ft_field_support_2_esw_fdb.cap)
1335
1336 #define MLX5_CAP_ESW(mdev, cap) \
1337 MLX5_GET(e_switch_cap, \
1338 mdev->caps.hca[MLX5_CAP_ESWITCH]->cur, cap)
1339
1340 #define MLX5_CAP64_ESW_FLOWTABLE(mdev, cap) \
1341 MLX5_GET64(flow_table_eswitch_cap, \
1342 (mdev)->caps.hca[MLX5_CAP_ESWITCH_FLOW_TABLE]->cur, cap)
1343
1344 #define MLX5_CAP_PORT_SELECTION(mdev, cap) \
1345 MLX5_GET(port_selection_cap, \
1346 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->cur, cap)
1347
1348 #define MLX5_CAP_PORT_SELECTION_MAX(mdev, cap) \
1349 MLX5_GET(port_selection_cap, \
1350 mdev->caps.hca[MLX5_CAP_PORT_SELECTION]->max, cap)
1351
1352 #define MLX5_CAP_ADV_VIRTUALIZATION(mdev, cap) \
1353 MLX5_GET(adv_virtualization_cap, \
1354 mdev->caps.hca[MLX5_CAP_ADV_VIRTUALIZATION]->cur, cap)
1355
1356 #define MLX5_CAP_FLOWTABLE_PORT_SELECTION(mdev, cap) \
1357 MLX5_CAP_PORT_SELECTION(mdev, flow_table_properties_port_selection.cap)
1358
1359 #define MLX5_CAP_ODP(mdev, cap)\
1360 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->cur, cap)
1361
1362 #define MLX5_CAP_ODP_MAX(mdev, cap)\
1363 MLX5_GET(odp_cap, mdev->caps.hca[MLX5_CAP_ODP]->max, cap)
1364
1365 #define MLX5_CAP_QOS(mdev, cap)\
1366 MLX5_GET(qos_cap, mdev->caps.hca[MLX5_CAP_QOS]->cur, cap)
1367
1368 #define MLX5_CAP_DEBUG(mdev, cap)\
1369 MLX5_GET(debug_cap, mdev->caps.hca[MLX5_CAP_DEBUG]->cur, cap)
1370
1371 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1372 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1373
1374 #define MLX5_CAP_PCAM_REG(mdev, reg) \
1375 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1376
1377 #define MLX5_CAP_MCAM_REG(mdev, reg) \
1378 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_FIRST_128], \
1379 mng_access_reg_cap_mask.access_regs.reg)
1380
1381 #define MLX5_CAP_MCAM_REG2(mdev, reg) \
1382 MLX5_GET(mcam_reg, (mdev)->caps.mcam[MLX5_MCAM_REGS_0x9100_0x917F], \
1383 mng_access_reg_cap_mask.access_regs2.reg)
1384
1385 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1386 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1387
1388 #define MLX5_CAP_QCAM_REG(mdev, fld) \
1389 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1390
1391 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1392 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1393
1394 #define MLX5_CAP_FPGA(mdev, cap) \
1395 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1396
1397 #define MLX5_CAP64_FPGA(mdev, cap) \
1398 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1399
1400 #define MLX5_CAP_DEV_MEM(mdev, cap)\
1401 MLX5_GET(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1402
1403 #define MLX5_CAP64_DEV_MEM(mdev, cap)\
1404 MLX5_GET64(device_mem_cap, mdev->caps.hca[MLX5_CAP_DEV_MEM]->cur, cap)
1405
1406 #define MLX5_CAP_TLS(mdev, cap) \
1407 MLX5_GET(tls_cap, (mdev)->caps.hca[MLX5_CAP_TLS]->cur, cap)
1408
1409 #define MLX5_CAP_DEV_EVENT(mdev, cap)\
1410 MLX5_ADDR_OF(device_event_cap, (mdev)->caps.hca[MLX5_CAP_DEV_EVENT]->cur, cap)
1411
1412 #define MLX5_CAP_DEV_VDPA_EMULATION(mdev, cap)\
1413 MLX5_GET(virtio_emulation_cap, \
1414 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1415
1416 #define MLX5_CAP64_DEV_VDPA_EMULATION(mdev, cap)\
1417 MLX5_GET64(virtio_emulation_cap, \
1418 (mdev)->caps.hca[MLX5_CAP_VDPA_EMULATION]->cur, cap)
1419
1420 #define MLX5_CAP_IPSEC(mdev, cap)\
1421 MLX5_GET(ipsec_cap, (mdev)->caps.hca[MLX5_CAP_IPSEC]->cur, cap)
1422
1423 #define MLX5_CAP_CRYPTO(mdev, cap)\
1424 MLX5_GET(crypto_cap, (mdev)->caps.hca[MLX5_CAP_CRYPTO]->cur, cap)
1425
1426 #define MLX5_CAP_MACSEC(mdev, cap)\
1427 MLX5_GET(macsec_cap, (mdev)->caps.hca[MLX5_CAP_MACSEC]->cur, cap)
1428
1429 enum {
1430 MLX5_CMD_STAT_OK = 0x0,
1431 MLX5_CMD_STAT_INT_ERR = 0x1,
1432 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1433 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1434 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1435 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1436 MLX5_CMD_STAT_RES_BUSY = 0x6,
1437 MLX5_CMD_STAT_LIM_ERR = 0x8,
1438 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1439 MLX5_CMD_STAT_IX_ERR = 0xa,
1440 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1441 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1442 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1443 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1444 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1445 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1446 };
1447
1448 enum {
1449 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1450 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1451 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1452 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1453 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1454 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1455 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1456 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1457 MLX5_PER_TRAFFIC_CLASS_CONGESTION_GROUP = 0x13,
1458 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1459 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1460 };
1461
1462 enum {
1463 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1464 };
1465
mlx5_to_sw_pkey_sz(int pkey_sz)1466 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1467 {
1468 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1469 return 0;
1470 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1471 }
1472
1473 #define MLX5_RDMA_RX_NUM_COUNTERS_PRIOS 2
1474 #define MLX5_RDMA_TX_NUM_COUNTERS_PRIOS 1
1475 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1476 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1477 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1478 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1479 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1480 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1481
1482 #endif /* MLX5_DEVICE_H */
1483
