1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31 */
32 #ifndef MLX5_IFC_H
33 #define MLX5_IFC_H
34 
35 #include "mlx5_ifc_fpga.h"
36 
37 enum {
38 	MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
39 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
40 	MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
41 	MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
42 	MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
43 	MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
44 	MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
45 	MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
46 	MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
47 	MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
48 	MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
49 	MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
50 	MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
51 	MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
52 	MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
53 	MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
54 	MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
55 	MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
56 	MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 	MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 	MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
59 	MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
60 	MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
61 	MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
62 	MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
63 	MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
64 };
65 
66 enum {
67 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
68 	MLX5_SET_HCA_CAP_OP_MOD_ETHERNET_OFFLOADS     = 0x1,
69 	MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
70 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
71 	MLX5_SET_HCA_CAP_OP_MOD_ROCE                  = 0x4,
72 	MLX5_SET_HCA_CAP_OP_MOD_IPSEC                 = 0x15,
73 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE2       = 0x20,
74 	MLX5_SET_HCA_CAP_OP_MOD_PORT_SELECTION        = 0x25,
75 };
76 
77 enum {
78 	MLX5_SHARED_RESOURCE_UID = 0xffff,
79 };
80 
81 enum {
82 	MLX5_OBJ_TYPE_SW_ICM = 0x0008,
83 	MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT  = 0x23,
84 };
85 
86 enum {
87 	MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
88 	MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
89 	MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
90 	MLX5_GENERAL_OBJ_TYPES_CAP_HEADER_MODIFY_ARGUMENT =
91 		(1ULL << MLX5_OBJ_TYPE_HEADER_MODIFY_ARGUMENT),
92 	MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39),
93 };
94 
95 enum {
96 	MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
97 	MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d,
98 	MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
99 	MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018,
100 	MLX5_OBJ_TYPE_PAGE_TRACK = 0x46,
101 	MLX5_OBJ_TYPE_MKEY = 0xff01,
102 	MLX5_OBJ_TYPE_QP = 0xff02,
103 	MLX5_OBJ_TYPE_PSV = 0xff03,
104 	MLX5_OBJ_TYPE_RMP = 0xff04,
105 	MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
106 	MLX5_OBJ_TYPE_RQ = 0xff06,
107 	MLX5_OBJ_TYPE_SQ = 0xff07,
108 	MLX5_OBJ_TYPE_TIR = 0xff08,
109 	MLX5_OBJ_TYPE_TIS = 0xff09,
110 	MLX5_OBJ_TYPE_DCT = 0xff0a,
111 	MLX5_OBJ_TYPE_XRQ = 0xff0b,
112 	MLX5_OBJ_TYPE_RQT = 0xff0e,
113 	MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
114 	MLX5_OBJ_TYPE_CQ = 0xff10,
115 };
116 
117 enum {
118 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
119 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
120 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
121 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
122 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
123 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
124 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
125 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
126 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
127 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
128 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
129 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
130 	MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
131 	MLX5_CMD_OP_ALLOC_SF                      = 0x113,
132 	MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
133 	MLX5_CMD_OP_SUSPEND_VHCA                  = 0x115,
134 	MLX5_CMD_OP_RESUME_VHCA                   = 0x116,
135 	MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE    = 0x117,
136 	MLX5_CMD_OP_SAVE_VHCA_STATE               = 0x118,
137 	MLX5_CMD_OP_LOAD_VHCA_STATE               = 0x119,
138 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
139 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
140 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
141 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
142 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
143 	MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
144 	MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
145 	MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
146 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
147 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
148 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
149 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
150 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
151 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
152 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
153 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
154 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
155 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
156 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
157 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
158 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
159 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
160 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
161 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
162 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
163 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
164 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
165 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
166 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
167 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
168 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
169 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
170 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
171 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
172 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
173 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
174 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
175 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
176 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
177 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
178 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
179 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
180 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
181 	MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
182 	MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
183 	MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
184 	MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
185 	MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
186 	MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
187 	MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
188 	MLX5_CMD_OP_RELEASE_XRQ_ERROR             = 0x729,
189 	MLX5_CMD_OP_MODIFY_XRQ                    = 0x72a,
190 	MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
191 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
192 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
193 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
194 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
195 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
196 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
197 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
198 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
199 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
200 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
201 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
202 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
203 	MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
204 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
205 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
206 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
207 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
208 	MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
209 	MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
210 	MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
211 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
212 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
213 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
214 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
215 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
216 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
217 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
218 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
219 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
220 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
221 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
222 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
223 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
224 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
225 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
226 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
227 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
228 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
229 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
230 	MLX5_CMD_OP_NOP                           = 0x80d,
231 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
232 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
233 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
234 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
235 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
236 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
237 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
238 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
239 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
240 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
241 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
242 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
243 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
244 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
245 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
246 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
247 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
248 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
249 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
250 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
251 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
252 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
253 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
254 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
255 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
256 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
257 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
258 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
259 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
260 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
261 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
262 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
263 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
264 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
265 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
266 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
267 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
268 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
269 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
270 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
271 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
272 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
273 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
274 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
275 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
276 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
277 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
278 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT		  = 0x92f,
279 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
280 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
281 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
282 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
283 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
284 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
285 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
286 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
287 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
288 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
289 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
290 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
291 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
292 	MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
293 	MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
294 	MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
295 	MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
296 	MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
297 	MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
298 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
299 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
300 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
301 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
302 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
303 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
304 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
305 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
306 	MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
307 	MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
308 	MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
309 	MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
310 	MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
311 	MLX5_CMD_OP_SYNC_STEERING                 = 0xb00,
312 	MLX5_CMD_OP_QUERY_VHCA_STATE              = 0xb0d,
313 	MLX5_CMD_OP_MODIFY_VHCA_STATE             = 0xb0e,
314 	MLX5_CMD_OP_SYNC_CRYPTO                   = 0xb12,
315 	MLX5_CMD_OP_MAX
316 };
317 
318 /* Valid range for general commands that don't work over an object */
319 enum {
320 	MLX5_CMD_OP_GENERAL_START = 0xb00,
321 	MLX5_CMD_OP_GENERAL_END = 0xd00,
322 };
323 
324 enum {
325 	MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
326 	MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1),
327 };
328 
329 enum {
330 	MLX5_CMD_OP_MOD_UPDATE_HEADER_MODIFY_ARGUMENT = 0x1,
331 };
332 
333 struct mlx5_ifc_flow_table_fields_supported_bits {
334 	u8         outer_dmac[0x1];
335 	u8         outer_smac[0x1];
336 	u8         outer_ether_type[0x1];
337 	u8         outer_ip_version[0x1];
338 	u8         outer_first_prio[0x1];
339 	u8         outer_first_cfi[0x1];
340 	u8         outer_first_vid[0x1];
341 	u8         outer_ipv4_ttl[0x1];
342 	u8         outer_second_prio[0x1];
343 	u8         outer_second_cfi[0x1];
344 	u8         outer_second_vid[0x1];
345 	u8         reserved_at_b[0x1];
346 	u8         outer_sip[0x1];
347 	u8         outer_dip[0x1];
348 	u8         outer_frag[0x1];
349 	u8         outer_ip_protocol[0x1];
350 	u8         outer_ip_ecn[0x1];
351 	u8         outer_ip_dscp[0x1];
352 	u8         outer_udp_sport[0x1];
353 	u8         outer_udp_dport[0x1];
354 	u8         outer_tcp_sport[0x1];
355 	u8         outer_tcp_dport[0x1];
356 	u8         outer_tcp_flags[0x1];
357 	u8         outer_gre_protocol[0x1];
358 	u8         outer_gre_key[0x1];
359 	u8         outer_vxlan_vni[0x1];
360 	u8         outer_geneve_vni[0x1];
361 	u8         outer_geneve_oam[0x1];
362 	u8         outer_geneve_protocol_type[0x1];
363 	u8         outer_geneve_opt_len[0x1];
364 	u8         source_vhca_port[0x1];
365 	u8         source_eswitch_port[0x1];
366 
367 	u8         inner_dmac[0x1];
368 	u8         inner_smac[0x1];
369 	u8         inner_ether_type[0x1];
370 	u8         inner_ip_version[0x1];
371 	u8         inner_first_prio[0x1];
372 	u8         inner_first_cfi[0x1];
373 	u8         inner_first_vid[0x1];
374 	u8         reserved_at_27[0x1];
375 	u8         inner_second_prio[0x1];
376 	u8         inner_second_cfi[0x1];
377 	u8         inner_second_vid[0x1];
378 	u8         reserved_at_2b[0x1];
379 	u8         inner_sip[0x1];
380 	u8         inner_dip[0x1];
381 	u8         inner_frag[0x1];
382 	u8         inner_ip_protocol[0x1];
383 	u8         inner_ip_ecn[0x1];
384 	u8         inner_ip_dscp[0x1];
385 	u8         inner_udp_sport[0x1];
386 	u8         inner_udp_dport[0x1];
387 	u8         inner_tcp_sport[0x1];
388 	u8         inner_tcp_dport[0x1];
389 	u8         inner_tcp_flags[0x1];
390 	u8         reserved_at_37[0x9];
391 
392 	u8         geneve_tlv_option_0_data[0x1];
393 	u8         geneve_tlv_option_0_exist[0x1];
394 	u8         reserved_at_42[0x3];
395 	u8         outer_first_mpls_over_udp[0x4];
396 	u8         outer_first_mpls_over_gre[0x4];
397 	u8         inner_first_mpls[0x4];
398 	u8         outer_first_mpls[0x4];
399 	u8         reserved_at_55[0x2];
400 	u8	   outer_esp_spi[0x1];
401 	u8         reserved_at_58[0x2];
402 	u8         bth_dst_qp[0x1];
403 	u8         reserved_at_5b[0x5];
404 
405 	u8         reserved_at_60[0x18];
406 	u8         metadata_reg_c_7[0x1];
407 	u8         metadata_reg_c_6[0x1];
408 	u8         metadata_reg_c_5[0x1];
409 	u8         metadata_reg_c_4[0x1];
410 	u8         metadata_reg_c_3[0x1];
411 	u8         metadata_reg_c_2[0x1];
412 	u8         metadata_reg_c_1[0x1];
413 	u8         metadata_reg_c_0[0x1];
414 };
415 
416 /* Table 2170 - Flow Table Fields Supported 2 Format */
417 struct mlx5_ifc_flow_table_fields_supported_2_bits {
418 	u8         reserved_at_0[0xe];
419 	u8         bth_opcode[0x1];
420 	u8         reserved_at_f[0x1];
421 	u8         tunnel_header_0_1[0x1];
422 	u8         reserved_at_11[0xf];
423 
424 	u8         reserved_at_20[0x60];
425 };
426 
427 struct mlx5_ifc_flow_table_prop_layout_bits {
428 	u8         ft_support[0x1];
429 	u8         reserved_at_1[0x1];
430 	u8         flow_counter[0x1];
431 	u8	   flow_modify_en[0x1];
432 	u8         modify_root[0x1];
433 	u8         identified_miss_table_mode[0x1];
434 	u8         flow_table_modify[0x1];
435 	u8         reformat[0x1];
436 	u8         decap[0x1];
437 	u8         reserved_at_9[0x1];
438 	u8         pop_vlan[0x1];
439 	u8         push_vlan[0x1];
440 	u8         reserved_at_c[0x1];
441 	u8         pop_vlan_2[0x1];
442 	u8         push_vlan_2[0x1];
443 	u8	   reformat_and_vlan_action[0x1];
444 	u8	   reserved_at_10[0x1];
445 	u8         sw_owner[0x1];
446 	u8	   reformat_l3_tunnel_to_l2[0x1];
447 	u8	   reformat_l2_to_l3_tunnel[0x1];
448 	u8	   reformat_and_modify_action[0x1];
449 	u8	   ignore_flow_level[0x1];
450 	u8         reserved_at_16[0x1];
451 	u8	   table_miss_action_domain[0x1];
452 	u8         termination_table[0x1];
453 	u8         reformat_and_fwd_to_table[0x1];
454 	u8         reserved_at_1a[0x2];
455 	u8         ipsec_encrypt[0x1];
456 	u8         ipsec_decrypt[0x1];
457 	u8         sw_owner_v2[0x1];
458 	u8         reserved_at_1f[0x1];
459 
460 	u8         termination_table_raw_traffic[0x1];
461 	u8         reserved_at_21[0x1];
462 	u8         log_max_ft_size[0x6];
463 	u8         log_max_modify_header_context[0x8];
464 	u8         max_modify_header_actions[0x8];
465 	u8         max_ft_level[0x8];
466 
467 	u8         reformat_add_esp_trasport[0x1];
468 	u8         reformat_l2_to_l3_esp_tunnel[0x1];
469 	u8         reformat_add_esp_transport_over_udp[0x1];
470 	u8         reformat_del_esp_trasport[0x1];
471 	u8         reformat_l3_esp_tunnel_to_l2[0x1];
472 	u8         reformat_del_esp_transport_over_udp[0x1];
473 	u8         execute_aso[0x1];
474 	u8         reserved_at_47[0x19];
475 
476 	u8         reserved_at_60[0x2];
477 	u8         reformat_insert[0x1];
478 	u8         reformat_remove[0x1];
479 	u8         macsec_encrypt[0x1];
480 	u8         macsec_decrypt[0x1];
481 	u8         reserved_at_66[0x2];
482 	u8         reformat_add_macsec[0x1];
483 	u8         reformat_remove_macsec[0x1];
484 	u8         reserved_at_6a[0xe];
485 	u8         log_max_ft_num[0x8];
486 
487 	u8         reserved_at_80[0x10];
488 	u8         log_max_flow_counter[0x8];
489 	u8         log_max_destination[0x8];
490 
491 	u8         reserved_at_a0[0x18];
492 	u8         log_max_flow[0x8];
493 
494 	u8         reserved_at_c0[0x40];
495 
496 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
497 
498 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
499 };
500 
501 struct mlx5_ifc_odp_per_transport_service_cap_bits {
502 	u8         send[0x1];
503 	u8         receive[0x1];
504 	u8         write[0x1];
505 	u8         read[0x1];
506 	u8         atomic[0x1];
507 	u8         srq_receive[0x1];
508 	u8         reserved_at_6[0x1a];
509 };
510 
511 struct mlx5_ifc_ipv4_layout_bits {
512 	u8         reserved_at_0[0x60];
513 
514 	u8         ipv4[0x20];
515 };
516 
517 struct mlx5_ifc_ipv6_layout_bits {
518 	u8         ipv6[16][0x8];
519 };
520 
521 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
522 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
523 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
524 	u8         reserved_at_0[0x80];
525 };
526 
527 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
528 	u8         smac_47_16[0x20];
529 
530 	u8         smac_15_0[0x10];
531 	u8         ethertype[0x10];
532 
533 	u8         dmac_47_16[0x20];
534 
535 	u8         dmac_15_0[0x10];
536 	u8         first_prio[0x3];
537 	u8         first_cfi[0x1];
538 	u8         first_vid[0xc];
539 
540 	u8         ip_protocol[0x8];
541 	u8         ip_dscp[0x6];
542 	u8         ip_ecn[0x2];
543 	u8         cvlan_tag[0x1];
544 	u8         svlan_tag[0x1];
545 	u8         frag[0x1];
546 	u8         ip_version[0x4];
547 	u8         tcp_flags[0x9];
548 
549 	u8         tcp_sport[0x10];
550 	u8         tcp_dport[0x10];
551 
552 	u8         reserved_at_c0[0x10];
553 	u8         ipv4_ihl[0x4];
554 	u8         reserved_at_c4[0x4];
555 
556 	u8         ttl_hoplimit[0x8];
557 
558 	u8         udp_sport[0x10];
559 	u8         udp_dport[0x10];
560 
561 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
562 
563 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
564 };
565 
566 struct mlx5_ifc_nvgre_key_bits {
567 	u8 hi[0x18];
568 	u8 lo[0x8];
569 };
570 
571 union mlx5_ifc_gre_key_bits {
572 	struct mlx5_ifc_nvgre_key_bits nvgre;
573 	u8 key[0x20];
574 };
575 
576 struct mlx5_ifc_fte_match_set_misc_bits {
577 	u8         gre_c_present[0x1];
578 	u8         reserved_at_1[0x1];
579 	u8         gre_k_present[0x1];
580 	u8         gre_s_present[0x1];
581 	u8         source_vhca_port[0x4];
582 	u8         source_sqn[0x18];
583 
584 	u8         source_eswitch_owner_vhca_id[0x10];
585 	u8         source_port[0x10];
586 
587 	u8         outer_second_prio[0x3];
588 	u8         outer_second_cfi[0x1];
589 	u8         outer_second_vid[0xc];
590 	u8         inner_second_prio[0x3];
591 	u8         inner_second_cfi[0x1];
592 	u8         inner_second_vid[0xc];
593 
594 	u8         outer_second_cvlan_tag[0x1];
595 	u8         inner_second_cvlan_tag[0x1];
596 	u8         outer_second_svlan_tag[0x1];
597 	u8         inner_second_svlan_tag[0x1];
598 	u8         reserved_at_64[0xc];
599 	u8         gre_protocol[0x10];
600 
601 	union mlx5_ifc_gre_key_bits gre_key;
602 
603 	u8         vxlan_vni[0x18];
604 	u8         bth_opcode[0x8];
605 
606 	u8         geneve_vni[0x18];
607 	u8         reserved_at_d8[0x6];
608 	u8         geneve_tlv_option_0_exist[0x1];
609 	u8         geneve_oam[0x1];
610 
611 	u8         reserved_at_e0[0xc];
612 	u8         outer_ipv6_flow_label[0x14];
613 
614 	u8         reserved_at_100[0xc];
615 	u8         inner_ipv6_flow_label[0x14];
616 
617 	u8         reserved_at_120[0xa];
618 	u8         geneve_opt_len[0x6];
619 	u8         geneve_protocol_type[0x10];
620 
621 	u8         reserved_at_140[0x8];
622 	u8         bth_dst_qp[0x18];
623 	u8	   reserved_at_160[0x20];
624 	u8	   outer_esp_spi[0x20];
625 	u8         reserved_at_1a0[0x60];
626 };
627 
628 struct mlx5_ifc_fte_match_mpls_bits {
629 	u8         mpls_label[0x14];
630 	u8         mpls_exp[0x3];
631 	u8         mpls_s_bos[0x1];
632 	u8         mpls_ttl[0x8];
633 };
634 
635 struct mlx5_ifc_fte_match_set_misc2_bits {
636 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
637 
638 	struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
639 
640 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
641 
642 	struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
643 
644 	u8         metadata_reg_c_7[0x20];
645 
646 	u8         metadata_reg_c_6[0x20];
647 
648 	u8         metadata_reg_c_5[0x20];
649 
650 	u8         metadata_reg_c_4[0x20];
651 
652 	u8         metadata_reg_c_3[0x20];
653 
654 	u8         metadata_reg_c_2[0x20];
655 
656 	u8         metadata_reg_c_1[0x20];
657 
658 	u8         metadata_reg_c_0[0x20];
659 
660 	u8         metadata_reg_a[0x20];
661 
662 	u8         reserved_at_1a0[0x8];
663 
664 	u8         macsec_syndrome[0x8];
665 	u8         ipsec_syndrome[0x8];
666 	u8         reserved_at_1b8[0x8];
667 
668 	u8         reserved_at_1c0[0x40];
669 };
670 
671 struct mlx5_ifc_fte_match_set_misc3_bits {
672 	u8         inner_tcp_seq_num[0x20];
673 
674 	u8         outer_tcp_seq_num[0x20];
675 
676 	u8         inner_tcp_ack_num[0x20];
677 
678 	u8         outer_tcp_ack_num[0x20];
679 
680 	u8	   reserved_at_80[0x8];
681 	u8         outer_vxlan_gpe_vni[0x18];
682 
683 	u8         outer_vxlan_gpe_next_protocol[0x8];
684 	u8         outer_vxlan_gpe_flags[0x8];
685 	u8	   reserved_at_b0[0x10];
686 
687 	u8	   icmp_header_data[0x20];
688 
689 	u8	   icmpv6_header_data[0x20];
690 
691 	u8	   icmp_type[0x8];
692 	u8	   icmp_code[0x8];
693 	u8	   icmpv6_type[0x8];
694 	u8	   icmpv6_code[0x8];
695 
696 	u8         geneve_tlv_option_0_data[0x20];
697 
698 	u8	   gtpu_teid[0x20];
699 
700 	u8	   gtpu_msg_type[0x8];
701 	u8	   gtpu_msg_flags[0x8];
702 	u8	   reserved_at_170[0x10];
703 
704 	u8	   gtpu_dw_2[0x20];
705 
706 	u8	   gtpu_first_ext_dw_0[0x20];
707 
708 	u8	   gtpu_dw_0[0x20];
709 
710 	u8	   reserved_at_1e0[0x20];
711 };
712 
713 struct mlx5_ifc_fte_match_set_misc4_bits {
714 	u8         prog_sample_field_value_0[0x20];
715 
716 	u8         prog_sample_field_id_0[0x20];
717 
718 	u8         prog_sample_field_value_1[0x20];
719 
720 	u8         prog_sample_field_id_1[0x20];
721 
722 	u8         prog_sample_field_value_2[0x20];
723 
724 	u8         prog_sample_field_id_2[0x20];
725 
726 	u8         prog_sample_field_value_3[0x20];
727 
728 	u8         prog_sample_field_id_3[0x20];
729 
730 	u8         reserved_at_100[0x100];
731 };
732 
733 struct mlx5_ifc_fte_match_set_misc5_bits {
734 	u8         macsec_tag_0[0x20];
735 
736 	u8         macsec_tag_1[0x20];
737 
738 	u8         macsec_tag_2[0x20];
739 
740 	u8         macsec_tag_3[0x20];
741 
742 	u8         tunnel_header_0[0x20];
743 
744 	u8         tunnel_header_1[0x20];
745 
746 	u8         tunnel_header_2[0x20];
747 
748 	u8         tunnel_header_3[0x20];
749 
750 	u8         reserved_at_100[0x100];
751 };
752 
753 struct mlx5_ifc_cmd_pas_bits {
754 	u8         pa_h[0x20];
755 
756 	u8         pa_l[0x14];
757 	u8         reserved_at_34[0xc];
758 };
759 
760 struct mlx5_ifc_uint64_bits {
761 	u8         hi[0x20];
762 
763 	u8         lo[0x20];
764 };
765 
766 enum {
767 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
768 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
769 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
770 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
771 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
772 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
773 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
774 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
775 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
776 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
777 };
778 
779 struct mlx5_ifc_ads_bits {
780 	u8         fl[0x1];
781 	u8         free_ar[0x1];
782 	u8         reserved_at_2[0xe];
783 	u8         pkey_index[0x10];
784 
785 	u8         reserved_at_20[0x8];
786 	u8         grh[0x1];
787 	u8         mlid[0x7];
788 	u8         rlid[0x10];
789 
790 	u8         ack_timeout[0x5];
791 	u8         reserved_at_45[0x3];
792 	u8         src_addr_index[0x8];
793 	u8         reserved_at_50[0x4];
794 	u8         stat_rate[0x4];
795 	u8         hop_limit[0x8];
796 
797 	u8         reserved_at_60[0x4];
798 	u8         tclass[0x8];
799 	u8         flow_label[0x14];
800 
801 	u8         rgid_rip[16][0x8];
802 
803 	u8         reserved_at_100[0x4];
804 	u8         f_dscp[0x1];
805 	u8         f_ecn[0x1];
806 	u8         reserved_at_106[0x1];
807 	u8         f_eth_prio[0x1];
808 	u8         ecn[0x2];
809 	u8         dscp[0x6];
810 	u8         udp_sport[0x10];
811 
812 	u8         dei_cfi[0x1];
813 	u8         eth_prio[0x3];
814 	u8         sl[0x4];
815 	u8         vhca_port_num[0x8];
816 	u8         rmac_47_32[0x10];
817 
818 	u8         rmac_31_0[0x20];
819 };
820 
821 struct mlx5_ifc_flow_table_nic_cap_bits {
822 	u8         nic_rx_multi_path_tirs[0x1];
823 	u8         nic_rx_multi_path_tirs_fts[0x1];
824 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
825 	u8	   reserved_at_3[0x4];
826 	u8	   sw_owner_reformat_supported[0x1];
827 	u8	   reserved_at_8[0x18];
828 
829 	u8	   encap_general_header[0x1];
830 	u8	   reserved_at_21[0xa];
831 	u8	   log_max_packet_reformat_context[0x5];
832 	u8	   reserved_at_30[0x6];
833 	u8	   max_encap_header_size[0xa];
834 	u8	   reserved_at_40[0x1c0];
835 
836 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
837 
838 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
839 
840 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
841 
842 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
843 
844 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
845 
846 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
847 
848 	u8         reserved_at_e00[0x700];
849 
850 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma;
851 
852 	u8         reserved_at_1580[0x280];
853 
854 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma;
855 
856 	u8         reserved_at_1880[0x780];
857 
858 	u8         sw_steering_nic_rx_action_drop_icm_address[0x40];
859 
860 	u8         sw_steering_nic_tx_action_drop_icm_address[0x40];
861 
862 	u8         sw_steering_nic_tx_action_allow_icm_address[0x40];
863 
864 	u8         reserved_at_20c0[0x5f40];
865 };
866 
867 struct mlx5_ifc_port_selection_cap_bits {
868 	u8         reserved_at_0[0x10];
869 	u8         port_select_flow_table[0x1];
870 	u8         reserved_at_11[0x1];
871 	u8         port_select_flow_table_bypass[0x1];
872 	u8         reserved_at_13[0xd];
873 
874 	u8         reserved_at_20[0x1e0];
875 
876 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection;
877 
878 	u8         reserved_at_400[0x7c00];
879 };
880 
881 enum {
882 	MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
883 	MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
884 	MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
885 	MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
886 	MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
887 	MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
888 	MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
889 	MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
890 };
891 
892 struct mlx5_ifc_flow_table_eswitch_cap_bits {
893 	u8      fdb_to_vport_reg_c_id[0x8];
894 	u8      reserved_at_8[0x5];
895 	u8      fdb_uplink_hairpin[0x1];
896 	u8      fdb_multi_path_any_table_limit_regc[0x1];
897 	u8      reserved_at_f[0x3];
898 	u8      fdb_multi_path_any_table[0x1];
899 	u8      reserved_at_13[0x2];
900 	u8      fdb_modify_header_fwd_to_table[0x1];
901 	u8      fdb_ipv4_ttl_modify[0x1];
902 	u8      flow_source[0x1];
903 	u8      reserved_at_18[0x2];
904 	u8      multi_fdb_encap[0x1];
905 	u8      egress_acl_forward_to_vport[0x1];
906 	u8      fdb_multi_path_to_table[0x1];
907 	u8      reserved_at_1d[0x3];
908 
909 	u8      reserved_at_20[0x1e0];
910 
911 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
912 
913 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
914 
915 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
916 
917 	u8      reserved_at_800[0xC00];
918 
919 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_esw_fdb;
920 
921 	struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_bitmask_support_2_esw_fdb;
922 
923 	u8      reserved_at_1500[0x300];
924 
925 	u8      sw_steering_fdb_action_drop_icm_address_rx[0x40];
926 
927 	u8      sw_steering_fdb_action_drop_icm_address_tx[0x40];
928 
929 	u8      sw_steering_uplink_icm_address_rx[0x40];
930 
931 	u8      sw_steering_uplink_icm_address_tx[0x40];
932 
933 	u8      reserved_at_1900[0x6700];
934 };
935 
936 enum {
937 	MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
938 	MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
939 };
940 
941 struct mlx5_ifc_e_switch_cap_bits {
942 	u8         vport_svlan_strip[0x1];
943 	u8         vport_cvlan_strip[0x1];
944 	u8         vport_svlan_insert[0x1];
945 	u8         vport_cvlan_insert_if_not_exist[0x1];
946 	u8         vport_cvlan_insert_overwrite[0x1];
947 	u8         reserved_at_5[0x1];
948 	u8         vport_cvlan_insert_always[0x1];
949 	u8         esw_shared_ingress_acl[0x1];
950 	u8         esw_uplink_ingress_acl[0x1];
951 	u8         root_ft_on_other_esw[0x1];
952 	u8         reserved_at_a[0xf];
953 	u8         esw_functions_changed[0x1];
954 	u8         reserved_at_1a[0x1];
955 	u8         ecpf_vport_exists[0x1];
956 	u8         counter_eswitch_affinity[0x1];
957 	u8         merged_eswitch[0x1];
958 	u8         nic_vport_node_guid_modify[0x1];
959 	u8         nic_vport_port_guid_modify[0x1];
960 
961 	u8         vxlan_encap_decap[0x1];
962 	u8         nvgre_encap_decap[0x1];
963 	u8         reserved_at_22[0x1];
964 	u8         log_max_fdb_encap_uplink[0x5];
965 	u8         reserved_at_21[0x3];
966 	u8         log_max_packet_reformat_context[0x5];
967 	u8         reserved_2b[0x6];
968 	u8         max_encap_header_size[0xa];
969 
970 	u8         reserved_at_40[0xb];
971 	u8         log_max_esw_sf[0x5];
972 	u8         esw_sf_base_id[0x10];
973 
974 	u8         reserved_at_60[0x7a0];
975 
976 };
977 
978 struct mlx5_ifc_qos_cap_bits {
979 	u8         packet_pacing[0x1];
980 	u8         esw_scheduling[0x1];
981 	u8         esw_bw_share[0x1];
982 	u8         esw_rate_limit[0x1];
983 	u8         reserved_at_4[0x1];
984 	u8         packet_pacing_burst_bound[0x1];
985 	u8         packet_pacing_typical_size[0x1];
986 	u8         reserved_at_7[0x1];
987 	u8         nic_sq_scheduling[0x1];
988 	u8         nic_bw_share[0x1];
989 	u8         nic_rate_limit[0x1];
990 	u8         packet_pacing_uid[0x1];
991 	u8         log_esw_max_sched_depth[0x4];
992 	u8         reserved_at_10[0x10];
993 
994 	u8         reserved_at_20[0xb];
995 	u8         log_max_qos_nic_queue_group[0x5];
996 	u8         reserved_at_30[0x10];
997 
998 	u8         packet_pacing_max_rate[0x20];
999 
1000 	u8         packet_pacing_min_rate[0x20];
1001 
1002 	u8         reserved_at_80[0x10];
1003 	u8         packet_pacing_rate_table_size[0x10];
1004 
1005 	u8         esw_element_type[0x10];
1006 	u8         esw_tsar_type[0x10];
1007 
1008 	u8         reserved_at_c0[0x10];
1009 	u8         max_qos_para_vport[0x10];
1010 
1011 	u8         max_tsar_bw_share[0x20];
1012 
1013 	u8         reserved_at_100[0x20];
1014 
1015 	u8         reserved_at_120[0x3];
1016 	u8         log_meter_aso_granularity[0x5];
1017 	u8         reserved_at_128[0x3];
1018 	u8         log_meter_aso_max_alloc[0x5];
1019 	u8         reserved_at_130[0x3];
1020 	u8         log_max_num_meter_aso[0x5];
1021 	u8         reserved_at_138[0x8];
1022 
1023 	u8         reserved_at_140[0x6c0];
1024 };
1025 
1026 struct mlx5_ifc_debug_cap_bits {
1027 	u8         core_dump_general[0x1];
1028 	u8         core_dump_qp[0x1];
1029 	u8         reserved_at_2[0x7];
1030 	u8         resource_dump[0x1];
1031 	u8         reserved_at_a[0x16];
1032 
1033 	u8         reserved_at_20[0x2];
1034 	u8         stall_detect[0x1];
1035 	u8         reserved_at_23[0x1d];
1036 
1037 	u8         reserved_at_40[0x7c0];
1038 };
1039 
1040 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1041 	u8         csum_cap[0x1];
1042 	u8         vlan_cap[0x1];
1043 	u8         lro_cap[0x1];
1044 	u8         lro_psh_flag[0x1];
1045 	u8         lro_time_stamp[0x1];
1046 	u8         reserved_at_5[0x2];
1047 	u8         wqe_vlan_insert[0x1];
1048 	u8         self_lb_en_modifiable[0x1];
1049 	u8         reserved_at_9[0x2];
1050 	u8         max_lso_cap[0x5];
1051 	u8         multi_pkt_send_wqe[0x2];
1052 	u8	   wqe_inline_mode[0x2];
1053 	u8         rss_ind_tbl_cap[0x4];
1054 	u8         reg_umr_sq[0x1];
1055 	u8         scatter_fcs[0x1];
1056 	u8         enhanced_multi_pkt_send_wqe[0x1];
1057 	u8         tunnel_lso_const_out_ip_id[0x1];
1058 	u8         tunnel_lro_gre[0x1];
1059 	u8         tunnel_lro_vxlan[0x1];
1060 	u8         tunnel_stateless_gre[0x1];
1061 	u8         tunnel_stateless_vxlan[0x1];
1062 
1063 	u8         swp[0x1];
1064 	u8         swp_csum[0x1];
1065 	u8         swp_lso[0x1];
1066 	u8         cqe_checksum_full[0x1];
1067 	u8         tunnel_stateless_geneve_tx[0x1];
1068 	u8         tunnel_stateless_mpls_over_udp[0x1];
1069 	u8         tunnel_stateless_mpls_over_gre[0x1];
1070 	u8         tunnel_stateless_vxlan_gpe[0x1];
1071 	u8         tunnel_stateless_ipv4_over_vxlan[0x1];
1072 	u8         tunnel_stateless_ip_over_ip[0x1];
1073 	u8         insert_trailer[0x1];
1074 	u8         reserved_at_2b[0x1];
1075 	u8         tunnel_stateless_ip_over_ip_rx[0x1];
1076 	u8         tunnel_stateless_ip_over_ip_tx[0x1];
1077 	u8         reserved_at_2e[0x2];
1078 	u8         max_vxlan_udp_ports[0x8];
1079 	u8         reserved_at_38[0x6];
1080 	u8         max_geneve_opt_len[0x1];
1081 	u8         tunnel_stateless_geneve_rx[0x1];
1082 
1083 	u8         reserved_at_40[0x10];
1084 	u8         lro_min_mss_size[0x10];
1085 
1086 	u8         reserved_at_60[0x120];
1087 
1088 	u8         lro_timer_supported_periods[4][0x20];
1089 
1090 	u8         reserved_at_200[0x600];
1091 };
1092 
1093 enum {
1094 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING               = 0x0,
1095 	MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME                  = 0x1,
1096 	MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1097 };
1098 
1099 struct mlx5_ifc_roce_cap_bits {
1100 	u8         roce_apm[0x1];
1101 	u8         reserved_at_1[0x3];
1102 	u8         sw_r_roce_src_udp_port[0x1];
1103 	u8         fl_rc_qp_when_roce_disabled[0x1];
1104 	u8         fl_rc_qp_when_roce_enabled[0x1];
1105 	u8         reserved_at_7[0x1];
1106 	u8	   qp_ooo_transmit_default[0x1];
1107 	u8         reserved_at_9[0x15];
1108 	u8	   qp_ts_format[0x2];
1109 
1110 	u8         reserved_at_20[0x60];
1111 
1112 	u8         reserved_at_80[0xc];
1113 	u8         l3_type[0x4];
1114 	u8         reserved_at_90[0x8];
1115 	u8         roce_version[0x8];
1116 
1117 	u8         reserved_at_a0[0x10];
1118 	u8         r_roce_dest_udp_port[0x10];
1119 
1120 	u8         r_roce_max_src_udp_port[0x10];
1121 	u8         r_roce_min_src_udp_port[0x10];
1122 
1123 	u8         reserved_at_e0[0x10];
1124 	u8         roce_address_table_size[0x10];
1125 
1126 	u8         reserved_at_100[0x700];
1127 };
1128 
1129 struct mlx5_ifc_sync_steering_in_bits {
1130 	u8         opcode[0x10];
1131 	u8         uid[0x10];
1132 
1133 	u8         reserved_at_20[0x10];
1134 	u8         op_mod[0x10];
1135 
1136 	u8         reserved_at_40[0xc0];
1137 };
1138 
1139 struct mlx5_ifc_sync_steering_out_bits {
1140 	u8         status[0x8];
1141 	u8         reserved_at_8[0x18];
1142 
1143 	u8         syndrome[0x20];
1144 
1145 	u8         reserved_at_40[0x40];
1146 };
1147 
1148 struct mlx5_ifc_sync_crypto_in_bits {
1149 	u8         opcode[0x10];
1150 	u8         uid[0x10];
1151 
1152 	u8         reserved_at_20[0x10];
1153 	u8         op_mod[0x10];
1154 
1155 	u8         reserved_at_40[0x20];
1156 
1157 	u8         reserved_at_60[0x10];
1158 	u8         crypto_type[0x10];
1159 
1160 	u8         reserved_at_80[0x80];
1161 };
1162 
1163 struct mlx5_ifc_sync_crypto_out_bits {
1164 	u8         status[0x8];
1165 	u8         reserved_at_8[0x18];
1166 
1167 	u8         syndrome[0x20];
1168 
1169 	u8         reserved_at_40[0x40];
1170 };
1171 
1172 struct mlx5_ifc_device_mem_cap_bits {
1173 	u8         memic[0x1];
1174 	u8         reserved_at_1[0x1f];
1175 
1176 	u8         reserved_at_20[0xb];
1177 	u8         log_min_memic_alloc_size[0x5];
1178 	u8         reserved_at_30[0x8];
1179 	u8	   log_max_memic_addr_alignment[0x8];
1180 
1181 	u8         memic_bar_start_addr[0x40];
1182 
1183 	u8         memic_bar_size[0x20];
1184 
1185 	u8         max_memic_size[0x20];
1186 
1187 	u8         steering_sw_icm_start_address[0x40];
1188 
1189 	u8         reserved_at_100[0x8];
1190 	u8         log_header_modify_sw_icm_size[0x8];
1191 	u8         reserved_at_110[0x2];
1192 	u8         log_sw_icm_alloc_granularity[0x6];
1193 	u8         log_steering_sw_icm_size[0x8];
1194 
1195 	u8         reserved_at_120[0x18];
1196 	u8         log_header_modify_pattern_sw_icm_size[0x8];
1197 
1198 	u8         header_modify_sw_icm_start_address[0x40];
1199 
1200 	u8         reserved_at_180[0x40];
1201 
1202 	u8         header_modify_pattern_sw_icm_start_address[0x40];
1203 
1204 	u8         memic_operations[0x20];
1205 
1206 	u8         reserved_at_220[0x5e0];
1207 };
1208 
1209 struct mlx5_ifc_device_event_cap_bits {
1210 	u8         user_affiliated_events[4][0x40];
1211 
1212 	u8         user_unaffiliated_events[4][0x40];
1213 };
1214 
1215 struct mlx5_ifc_virtio_emulation_cap_bits {
1216 	u8         desc_tunnel_offload_type[0x1];
1217 	u8         eth_frame_offload_type[0x1];
1218 	u8         virtio_version_1_0[0x1];
1219 	u8         device_features_bits_mask[0xd];
1220 	u8         event_mode[0x8];
1221 	u8         virtio_queue_type[0x8];
1222 
1223 	u8         max_tunnel_desc[0x10];
1224 	u8         reserved_at_30[0x3];
1225 	u8         log_doorbell_stride[0x5];
1226 	u8         reserved_at_38[0x3];
1227 	u8         log_doorbell_bar_size[0x5];
1228 
1229 	u8         doorbell_bar_offset[0x40];
1230 
1231 	u8         max_emulated_devices[0x8];
1232 	u8         max_num_virtio_queues[0x18];
1233 
1234 	u8         reserved_at_a0[0x60];
1235 
1236 	u8         umem_1_buffer_param_a[0x20];
1237 
1238 	u8         umem_1_buffer_param_b[0x20];
1239 
1240 	u8         umem_2_buffer_param_a[0x20];
1241 
1242 	u8         umem_2_buffer_param_b[0x20];
1243 
1244 	u8         umem_3_buffer_param_a[0x20];
1245 
1246 	u8         umem_3_buffer_param_b[0x20];
1247 
1248 	u8         reserved_at_1c0[0x640];
1249 };
1250 
1251 enum {
1252 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
1253 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
1254 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
1255 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
1256 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
1257 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
1258 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
1259 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
1260 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
1261 };
1262 
1263 enum {
1264 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
1265 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
1266 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
1267 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
1268 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
1269 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
1270 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
1271 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
1272 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
1273 };
1274 
1275 struct mlx5_ifc_atomic_caps_bits {
1276 	u8         reserved_at_0[0x40];
1277 
1278 	u8         atomic_req_8B_endianness_mode[0x2];
1279 	u8         reserved_at_42[0x4];
1280 	u8         supported_atomic_req_8B_endianness_mode_1[0x1];
1281 
1282 	u8         reserved_at_47[0x19];
1283 
1284 	u8         reserved_at_60[0x20];
1285 
1286 	u8         reserved_at_80[0x10];
1287 	u8         atomic_operations[0x10];
1288 
1289 	u8         reserved_at_a0[0x10];
1290 	u8         atomic_size_qp[0x10];
1291 
1292 	u8         reserved_at_c0[0x10];
1293 	u8         atomic_size_dc[0x10];
1294 
1295 	u8         reserved_at_e0[0x720];
1296 };
1297 
1298 struct mlx5_ifc_odp_cap_bits {
1299 	u8         reserved_at_0[0x40];
1300 
1301 	u8         sig[0x1];
1302 	u8         reserved_at_41[0x1f];
1303 
1304 	u8         reserved_at_60[0x20];
1305 
1306 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1307 
1308 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1309 
1310 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1311 
1312 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1313 
1314 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1315 
1316 	u8         reserved_at_120[0x6E0];
1317 };
1318 
1319 struct mlx5_ifc_tls_cap_bits {
1320 	u8         tls_1_2_aes_gcm_128[0x1];
1321 	u8         tls_1_3_aes_gcm_128[0x1];
1322 	u8         tls_1_2_aes_gcm_256[0x1];
1323 	u8         tls_1_3_aes_gcm_256[0x1];
1324 	u8         reserved_at_4[0x1c];
1325 
1326 	u8         reserved_at_20[0x7e0];
1327 };
1328 
1329 struct mlx5_ifc_ipsec_cap_bits {
1330 	u8         ipsec_full_offload[0x1];
1331 	u8         ipsec_crypto_offload[0x1];
1332 	u8         ipsec_esn[0x1];
1333 	u8         ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1334 	u8         ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1335 	u8         ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1336 	u8         ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1337 	u8         reserved_at_7[0x4];
1338 	u8         log_max_ipsec_offload[0x5];
1339 	u8         reserved_at_10[0x10];
1340 
1341 	u8         min_log_ipsec_full_replay_window[0x8];
1342 	u8         max_log_ipsec_full_replay_window[0x8];
1343 	u8         reserved_at_30[0x7d0];
1344 };
1345 
1346 struct mlx5_ifc_macsec_cap_bits {
1347 	u8    macsec_epn[0x1];
1348 	u8    reserved_at_1[0x2];
1349 	u8    macsec_crypto_esp_aes_gcm_256_encrypt[0x1];
1350 	u8    macsec_crypto_esp_aes_gcm_128_encrypt[0x1];
1351 	u8    macsec_crypto_esp_aes_gcm_256_decrypt[0x1];
1352 	u8    macsec_crypto_esp_aes_gcm_128_decrypt[0x1];
1353 	u8    reserved_at_7[0x4];
1354 	u8    log_max_macsec_offload[0x5];
1355 	u8    reserved_at_10[0x10];
1356 
1357 	u8    min_log_macsec_full_replay_window[0x8];
1358 	u8    max_log_macsec_full_replay_window[0x8];
1359 	u8    reserved_at_30[0x10];
1360 
1361 	u8    reserved_at_40[0x7c0];
1362 };
1363 
1364 enum {
1365 	MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
1366 	MLX5_WQ_TYPE_CYCLIC       = 0x1,
1367 	MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1368 	MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1369 };
1370 
1371 enum {
1372 	MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
1373 	MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
1374 };
1375 
1376 enum {
1377 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1378 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1379 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1380 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1381 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1382 };
1383 
1384 enum {
1385 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1386 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1387 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1388 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1389 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1390 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1391 };
1392 
1393 enum {
1394 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1395 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1396 };
1397 
1398 enum {
1399 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1400 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1401 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1402 };
1403 
1404 enum {
1405 	MLX5_CAP_PORT_TYPE_IB  = 0x0,
1406 	MLX5_CAP_PORT_TYPE_ETH = 0x1,
1407 };
1408 
1409 enum {
1410 	MLX5_CAP_UMR_FENCE_STRONG	= 0x0,
1411 	MLX5_CAP_UMR_FENCE_SMALL	= 0x1,
1412 	MLX5_CAP_UMR_FENCE_NONE		= 0x2,
1413 };
1414 
1415 enum {
1416 	MLX5_FLEX_PARSER_GENEVE_ENABLED		= 1 << 3,
1417 	MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED	= 1 << 4,
1418 	MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED	= 1 << 5,
1419 	MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED	= 1 << 7,
1420 	MLX5_FLEX_PARSER_ICMP_V4_ENABLED	= 1 << 8,
1421 	MLX5_FLEX_PARSER_ICMP_V6_ENABLED	= 1 << 9,
1422 	MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10,
1423 	MLX5_FLEX_PARSER_GTPU_ENABLED		= 1 << 11,
1424 	MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED	= 1 << 16,
1425 	MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17,
1426 	MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED	= 1 << 18,
1427 	MLX5_FLEX_PARSER_GTPU_TEID_ENABLED	= 1 << 19,
1428 };
1429 
1430 enum {
1431 	MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1432 	MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1433 };
1434 
1435 #define MLX5_FC_BULK_SIZE_FACTOR 128
1436 
1437 enum mlx5_fc_bulk_alloc_bitmask {
1438 	MLX5_FC_BULK_128   = (1 << 0),
1439 	MLX5_FC_BULK_256   = (1 << 1),
1440 	MLX5_FC_BULK_512   = (1 << 2),
1441 	MLX5_FC_BULK_1024  = (1 << 3),
1442 	MLX5_FC_BULK_2048  = (1 << 4),
1443 	MLX5_FC_BULK_4096  = (1 << 5),
1444 	MLX5_FC_BULK_8192  = (1 << 6),
1445 	MLX5_FC_BULK_16384 = (1 << 7),
1446 };
1447 
1448 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1449 
1450 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63
1451 
1452 enum {
1453 	MLX5_STEERING_FORMAT_CONNECTX_5   = 0,
1454 	MLX5_STEERING_FORMAT_CONNECTX_6DX = 1,
1455 	MLX5_STEERING_FORMAT_CONNECTX_7   = 2,
1456 };
1457 
1458 struct mlx5_ifc_cmd_hca_cap_bits {
1459 	u8         reserved_at_0[0x10];
1460 	u8         shared_object_to_user_object_allowed[0x1];
1461 	u8         reserved_at_13[0xe];
1462 	u8         vhca_resource_manager[0x1];
1463 
1464 	u8         hca_cap_2[0x1];
1465 	u8         create_lag_when_not_master_up[0x1];
1466 	u8         dtor[0x1];
1467 	u8         event_on_vhca_state_teardown_request[0x1];
1468 	u8         event_on_vhca_state_in_use[0x1];
1469 	u8         event_on_vhca_state_active[0x1];
1470 	u8         event_on_vhca_state_allocated[0x1];
1471 	u8         event_on_vhca_state_invalid[0x1];
1472 	u8         reserved_at_28[0x8];
1473 	u8         vhca_id[0x10];
1474 
1475 	u8         reserved_at_40[0x40];
1476 
1477 	u8         log_max_srq_sz[0x8];
1478 	u8         log_max_qp_sz[0x8];
1479 	u8         event_cap[0x1];
1480 	u8         reserved_at_91[0x2];
1481 	u8         isolate_vl_tc_new[0x1];
1482 	u8         reserved_at_94[0x4];
1483 	u8         prio_tag_required[0x1];
1484 	u8         reserved_at_99[0x2];
1485 	u8         log_max_qp[0x5];
1486 
1487 	u8         reserved_at_a0[0x3];
1488 	u8	   ece_support[0x1];
1489 	u8	   reserved_at_a4[0x5];
1490 	u8         reg_c_preserve[0x1];
1491 	u8         reserved_at_aa[0x1];
1492 	u8         log_max_srq[0x5];
1493 	u8         reserved_at_b0[0x1];
1494 	u8         uplink_follow[0x1];
1495 	u8         ts_cqe_to_dest_cqn[0x1];
1496 	u8         reserved_at_b3[0x6];
1497 	u8         go_back_n[0x1];
1498 	u8         shampo[0x1];
1499 	u8         reserved_at_bb[0x5];
1500 
1501 	u8         max_sgl_for_optimized_performance[0x8];
1502 	u8         log_max_cq_sz[0x8];
1503 	u8         relaxed_ordering_write_umr[0x1];
1504 	u8         relaxed_ordering_read_umr[0x1];
1505 	u8         reserved_at_d2[0x7];
1506 	u8         virtio_net_device_emualtion_manager[0x1];
1507 	u8         virtio_blk_device_emualtion_manager[0x1];
1508 	u8         log_max_cq[0x5];
1509 
1510 	u8         log_max_eq_sz[0x8];
1511 	u8         relaxed_ordering_write[0x1];
1512 	u8         relaxed_ordering_read_pci_enabled[0x1];
1513 	u8         log_max_mkey[0x6];
1514 	u8         reserved_at_f0[0x6];
1515 	u8	   terminate_scatter_list_mkey[0x1];
1516 	u8	   repeated_mkey[0x1];
1517 	u8         dump_fill_mkey[0x1];
1518 	u8         reserved_at_f9[0x2];
1519 	u8         fast_teardown[0x1];
1520 	u8         log_max_eq[0x4];
1521 
1522 	u8         max_indirection[0x8];
1523 	u8         fixed_buffer_size[0x1];
1524 	u8         log_max_mrw_sz[0x7];
1525 	u8         force_teardown[0x1];
1526 	u8         reserved_at_111[0x1];
1527 	u8         log_max_bsf_list_size[0x6];
1528 	u8         umr_extended_translation_offset[0x1];
1529 	u8         null_mkey[0x1];
1530 	u8         log_max_klm_list_size[0x6];
1531 
1532 	u8         reserved_at_120[0x2];
1533 	u8	   qpc_extension[0x1];
1534 	u8	   reserved_at_123[0x7];
1535 	u8         log_max_ra_req_dc[0x6];
1536 	u8         reserved_at_130[0x2];
1537 	u8         eth_wqe_too_small[0x1];
1538 	u8         reserved_at_133[0x6];
1539 	u8         vnic_env_cq_overrun[0x1];
1540 	u8         log_max_ra_res_dc[0x6];
1541 
1542 	u8         reserved_at_140[0x5];
1543 	u8         release_all_pages[0x1];
1544 	u8         must_not_use[0x1];
1545 	u8         reserved_at_147[0x2];
1546 	u8         roce_accl[0x1];
1547 	u8         log_max_ra_req_qp[0x6];
1548 	u8         reserved_at_150[0xa];
1549 	u8         log_max_ra_res_qp[0x6];
1550 
1551 	u8         end_pad[0x1];
1552 	u8         cc_query_allowed[0x1];
1553 	u8         cc_modify_allowed[0x1];
1554 	u8         start_pad[0x1];
1555 	u8         cache_line_128byte[0x1];
1556 	u8         reserved_at_165[0x4];
1557 	u8         rts2rts_qp_counters_set_id[0x1];
1558 	u8         reserved_at_16a[0x2];
1559 	u8         vnic_env_int_rq_oob[0x1];
1560 	u8         sbcam_reg[0x1];
1561 	u8         reserved_at_16e[0x1];
1562 	u8         qcam_reg[0x1];
1563 	u8         gid_table_size[0x10];
1564 
1565 	u8         out_of_seq_cnt[0x1];
1566 	u8         vport_counters[0x1];
1567 	u8         retransmission_q_counters[0x1];
1568 	u8         debug[0x1];
1569 	u8         modify_rq_counter_set_id[0x1];
1570 	u8         rq_delay_drop[0x1];
1571 	u8         max_qp_cnt[0xa];
1572 	u8         pkey_table_size[0x10];
1573 
1574 	u8         vport_group_manager[0x1];
1575 	u8         vhca_group_manager[0x1];
1576 	u8         ib_virt[0x1];
1577 	u8         eth_virt[0x1];
1578 	u8         vnic_env_queue_counters[0x1];
1579 	u8         ets[0x1];
1580 	u8         nic_flow_table[0x1];
1581 	u8         eswitch_manager[0x1];
1582 	u8         device_memory[0x1];
1583 	u8         mcam_reg[0x1];
1584 	u8         pcam_reg[0x1];
1585 	u8         local_ca_ack_delay[0x5];
1586 	u8         port_module_event[0x1];
1587 	u8         enhanced_error_q_counters[0x1];
1588 	u8         ports_check[0x1];
1589 	u8         reserved_at_1b3[0x1];
1590 	u8         disable_link_up[0x1];
1591 	u8         beacon_led[0x1];
1592 	u8         port_type[0x2];
1593 	u8         num_ports[0x8];
1594 
1595 	u8         reserved_at_1c0[0x1];
1596 	u8         pps[0x1];
1597 	u8         pps_modify[0x1];
1598 	u8         log_max_msg[0x5];
1599 	u8         reserved_at_1c8[0x4];
1600 	u8         max_tc[0x4];
1601 	u8         temp_warn_event[0x1];
1602 	u8         dcbx[0x1];
1603 	u8         general_notification_event[0x1];
1604 	u8         reserved_at_1d3[0x2];
1605 	u8         fpga[0x1];
1606 	u8         rol_s[0x1];
1607 	u8         rol_g[0x1];
1608 	u8         reserved_at_1d8[0x1];
1609 	u8         wol_s[0x1];
1610 	u8         wol_g[0x1];
1611 	u8         wol_a[0x1];
1612 	u8         wol_b[0x1];
1613 	u8         wol_m[0x1];
1614 	u8         wol_u[0x1];
1615 	u8         wol_p[0x1];
1616 
1617 	u8         stat_rate_support[0x10];
1618 	u8         reserved_at_1f0[0x1];
1619 	u8         pci_sync_for_fw_update_event[0x1];
1620 	u8         reserved_at_1f2[0x6];
1621 	u8         init2_lag_tx_port_affinity[0x1];
1622 	u8         reserved_at_1fa[0x3];
1623 	u8         cqe_version[0x4];
1624 
1625 	u8         compact_address_vector[0x1];
1626 	u8         striding_rq[0x1];
1627 	u8         reserved_at_202[0x1];
1628 	u8         ipoib_enhanced_offloads[0x1];
1629 	u8         ipoib_basic_offloads[0x1];
1630 	u8         reserved_at_205[0x1];
1631 	u8         repeated_block_disabled[0x1];
1632 	u8         umr_modify_entity_size_disabled[0x1];
1633 	u8         umr_modify_atomic_disabled[0x1];
1634 	u8         umr_indirect_mkey_disabled[0x1];
1635 	u8         umr_fence[0x2];
1636 	u8         dc_req_scat_data_cqe[0x1];
1637 	u8         reserved_at_20d[0x2];
1638 	u8         drain_sigerr[0x1];
1639 	u8         cmdif_checksum[0x2];
1640 	u8         sigerr_cqe[0x1];
1641 	u8         reserved_at_213[0x1];
1642 	u8         wq_signature[0x1];
1643 	u8         sctr_data_cqe[0x1];
1644 	u8         reserved_at_216[0x1];
1645 	u8         sho[0x1];
1646 	u8         tph[0x1];
1647 	u8         rf[0x1];
1648 	u8         dct[0x1];
1649 	u8         qos[0x1];
1650 	u8         eth_net_offloads[0x1];
1651 	u8         roce[0x1];
1652 	u8         atomic[0x1];
1653 	u8         reserved_at_21f[0x1];
1654 
1655 	u8         cq_oi[0x1];
1656 	u8         cq_resize[0x1];
1657 	u8         cq_moderation[0x1];
1658 	u8         reserved_at_223[0x3];
1659 	u8         cq_eq_remap[0x1];
1660 	u8         pg[0x1];
1661 	u8         block_lb_mc[0x1];
1662 	u8         reserved_at_229[0x1];
1663 	u8         scqe_break_moderation[0x1];
1664 	u8         cq_period_start_from_cqe[0x1];
1665 	u8         cd[0x1];
1666 	u8         reserved_at_22d[0x1];
1667 	u8         apm[0x1];
1668 	u8         vector_calc[0x1];
1669 	u8         umr_ptr_rlky[0x1];
1670 	u8	   imaicl[0x1];
1671 	u8	   qp_packet_based[0x1];
1672 	u8         reserved_at_233[0x3];
1673 	u8         qkv[0x1];
1674 	u8         pkv[0x1];
1675 	u8         set_deth_sqpn[0x1];
1676 	u8         reserved_at_239[0x3];
1677 	u8         xrc[0x1];
1678 	u8         ud[0x1];
1679 	u8         uc[0x1];
1680 	u8         rc[0x1];
1681 
1682 	u8         uar_4k[0x1];
1683 	u8         reserved_at_241[0x7];
1684 	u8         fl_rc_qp_when_roce_disabled[0x1];
1685 	u8         regexp_params[0x1];
1686 	u8         uar_sz[0x6];
1687 	u8         port_selection_cap[0x1];
1688 	u8         reserved_at_251[0x1];
1689 	u8         umem_uid_0[0x1];
1690 	u8         reserved_at_253[0x5];
1691 	u8         log_pg_sz[0x8];
1692 
1693 	u8         bf[0x1];
1694 	u8         driver_version[0x1];
1695 	u8         pad_tx_eth_packet[0x1];
1696 	u8         reserved_at_263[0x3];
1697 	u8         mkey_by_name[0x1];
1698 	u8         reserved_at_267[0x4];
1699 
1700 	u8         log_bf_reg_size[0x5];
1701 
1702 	u8         reserved_at_270[0x3];
1703 	u8	   qp_error_syndrome[0x1];
1704 	u8	   reserved_at_274[0x2];
1705 	u8         lag_dct[0x2];
1706 	u8         lag_tx_port_affinity[0x1];
1707 	u8         lag_native_fdb_selection[0x1];
1708 	u8         reserved_at_27a[0x1];
1709 	u8         lag_master[0x1];
1710 	u8         num_lag_ports[0x4];
1711 
1712 	u8         reserved_at_280[0x10];
1713 	u8         max_wqe_sz_sq[0x10];
1714 
1715 	u8         reserved_at_2a0[0x10];
1716 	u8         max_wqe_sz_rq[0x10];
1717 
1718 	u8         max_flow_counter_31_16[0x10];
1719 	u8         max_wqe_sz_sq_dc[0x10];
1720 
1721 	u8         reserved_at_2e0[0x7];
1722 	u8         max_qp_mcg[0x19];
1723 
1724 	u8         reserved_at_300[0x10];
1725 	u8         flow_counter_bulk_alloc[0x8];
1726 	u8         log_max_mcg[0x8];
1727 
1728 	u8         reserved_at_320[0x3];
1729 	u8         log_max_transport_domain[0x5];
1730 	u8         reserved_at_328[0x2];
1731 	u8	   relaxed_ordering_read[0x1];
1732 	u8         log_max_pd[0x5];
1733 	u8         reserved_at_330[0x6];
1734 	u8         pci_sync_for_fw_update_with_driver_unload[0x1];
1735 	u8         vnic_env_cnt_steering_fail[0x1];
1736 	u8         vport_counter_local_loopback[0x1];
1737 	u8         q_counter_aggregation[0x1];
1738 	u8         q_counter_other_vport[0x1];
1739 	u8         log_max_xrcd[0x5];
1740 
1741 	u8         nic_receive_steering_discard[0x1];
1742 	u8         receive_discard_vport_down[0x1];
1743 	u8         transmit_discard_vport_down[0x1];
1744 	u8         eq_overrun_count[0x1];
1745 	u8         reserved_at_344[0x1];
1746 	u8         invalid_command_count[0x1];
1747 	u8         quota_exceeded_count[0x1];
1748 	u8         reserved_at_347[0x1];
1749 	u8         log_max_flow_counter_bulk[0x8];
1750 	u8         max_flow_counter_15_0[0x10];
1751 
1752 
1753 	u8         reserved_at_360[0x3];
1754 	u8         log_max_rq[0x5];
1755 	u8         reserved_at_368[0x3];
1756 	u8         log_max_sq[0x5];
1757 	u8         reserved_at_370[0x3];
1758 	u8         log_max_tir[0x5];
1759 	u8         reserved_at_378[0x3];
1760 	u8         log_max_tis[0x5];
1761 
1762 	u8         basic_cyclic_rcv_wqe[0x1];
1763 	u8         reserved_at_381[0x2];
1764 	u8         log_max_rmp[0x5];
1765 	u8         reserved_at_388[0x3];
1766 	u8         log_max_rqt[0x5];
1767 	u8         reserved_at_390[0x3];
1768 	u8         log_max_rqt_size[0x5];
1769 	u8         reserved_at_398[0x3];
1770 	u8         log_max_tis_per_sq[0x5];
1771 
1772 	u8         ext_stride_num_range[0x1];
1773 	u8         roce_rw_supported[0x1];
1774 	u8         log_max_current_uc_list_wr_supported[0x1];
1775 	u8         log_max_stride_sz_rq[0x5];
1776 	u8         reserved_at_3a8[0x3];
1777 	u8         log_min_stride_sz_rq[0x5];
1778 	u8         reserved_at_3b0[0x3];
1779 	u8         log_max_stride_sz_sq[0x5];
1780 	u8         reserved_at_3b8[0x3];
1781 	u8         log_min_stride_sz_sq[0x5];
1782 
1783 	u8         hairpin[0x1];
1784 	u8         reserved_at_3c1[0x2];
1785 	u8         log_max_hairpin_queues[0x5];
1786 	u8         reserved_at_3c8[0x3];
1787 	u8         log_max_hairpin_wq_data_sz[0x5];
1788 	u8         reserved_at_3d0[0x3];
1789 	u8         log_max_hairpin_num_packets[0x5];
1790 	u8         reserved_at_3d8[0x3];
1791 	u8         log_max_wq_sz[0x5];
1792 
1793 	u8         nic_vport_change_event[0x1];
1794 	u8         disable_local_lb_uc[0x1];
1795 	u8         disable_local_lb_mc[0x1];
1796 	u8         log_min_hairpin_wq_data_sz[0x5];
1797 	u8         reserved_at_3e8[0x2];
1798 	u8         vhca_state[0x1];
1799 	u8         log_max_vlan_list[0x5];
1800 	u8         reserved_at_3f0[0x3];
1801 	u8         log_max_current_mc_list[0x5];
1802 	u8         reserved_at_3f8[0x3];
1803 	u8         log_max_current_uc_list[0x5];
1804 
1805 	u8         general_obj_types[0x40];
1806 
1807 	u8         sq_ts_format[0x2];
1808 	u8         rq_ts_format[0x2];
1809 	u8         steering_format_version[0x4];
1810 	u8         create_qp_start_hint[0x18];
1811 
1812 	u8         reserved_at_460[0x1];
1813 	u8         ats[0x1];
1814 	u8         reserved_at_462[0x1];
1815 	u8         log_max_uctx[0x5];
1816 	u8         reserved_at_468[0x1];
1817 	u8         crypto[0x1];
1818 	u8         ipsec_offload[0x1];
1819 	u8         log_max_umem[0x5];
1820 	u8         max_num_eqs[0x10];
1821 
1822 	u8         reserved_at_480[0x1];
1823 	u8         tls_tx[0x1];
1824 	u8         tls_rx[0x1];
1825 	u8         log_max_l2_table[0x5];
1826 	u8         reserved_at_488[0x8];
1827 	u8         log_uar_page_sz[0x10];
1828 
1829 	u8         reserved_at_4a0[0x20];
1830 	u8         device_frequency_mhz[0x20];
1831 	u8         device_frequency_khz[0x20];
1832 
1833 	u8         reserved_at_500[0x20];
1834 	u8	   num_of_uars_per_page[0x20];
1835 
1836 	u8         flex_parser_protocols[0x20];
1837 
1838 	u8         max_geneve_tlv_options[0x8];
1839 	u8         reserved_at_568[0x3];
1840 	u8         max_geneve_tlv_option_data_len[0x5];
1841 	u8         reserved_at_570[0x9];
1842 	u8         adv_virtualization[0x1];
1843 	u8         reserved_at_57a[0x6];
1844 
1845 	u8	   reserved_at_580[0xb];
1846 	u8	   log_max_dci_stream_channels[0x5];
1847 	u8	   reserved_at_590[0x3];
1848 	u8	   log_max_dci_errored_streams[0x5];
1849 	u8	   reserved_at_598[0x8];
1850 
1851 	u8         reserved_at_5a0[0x10];
1852 	u8         enhanced_cqe_compression[0x1];
1853 	u8         reserved_at_5b1[0x2];
1854 	u8         log_max_dek[0x5];
1855 	u8         reserved_at_5b8[0x4];
1856 	u8         mini_cqe_resp_stride_index[0x1];
1857 	u8         cqe_128_always[0x1];
1858 	u8         cqe_compression_128[0x1];
1859 	u8         cqe_compression[0x1];
1860 
1861 	u8         cqe_compression_timeout[0x10];
1862 	u8         cqe_compression_max_num[0x10];
1863 
1864 	u8         reserved_at_5e0[0x8];
1865 	u8         flex_parser_id_gtpu_dw_0[0x4];
1866 	u8         reserved_at_5ec[0x4];
1867 	u8         tag_matching[0x1];
1868 	u8         rndv_offload_rc[0x1];
1869 	u8         rndv_offload_dc[0x1];
1870 	u8         log_tag_matching_list_sz[0x5];
1871 	u8         reserved_at_5f8[0x3];
1872 	u8         log_max_xrq[0x5];
1873 
1874 	u8	   affiliate_nic_vport_criteria[0x8];
1875 	u8	   native_port_num[0x8];
1876 	u8	   num_vhca_ports[0x8];
1877 	u8         flex_parser_id_gtpu_teid[0x4];
1878 	u8         reserved_at_61c[0x2];
1879 	u8	   sw_owner_id[0x1];
1880 	u8         reserved_at_61f[0x1];
1881 
1882 	u8         max_num_of_monitor_counters[0x10];
1883 	u8         num_ppcnt_monitor_counters[0x10];
1884 
1885 	u8         max_num_sf[0x10];
1886 	u8         num_q_monitor_counters[0x10];
1887 
1888 	u8         reserved_at_660[0x20];
1889 
1890 	u8         sf[0x1];
1891 	u8         sf_set_partition[0x1];
1892 	u8         reserved_at_682[0x1];
1893 	u8         log_max_sf[0x5];
1894 	u8         apu[0x1];
1895 	u8         reserved_at_689[0x4];
1896 	u8         migration[0x1];
1897 	u8         reserved_at_68e[0x2];
1898 	u8         log_min_sf_size[0x8];
1899 	u8         max_num_sf_partitions[0x8];
1900 
1901 	u8         uctx_cap[0x20];
1902 
1903 	u8         reserved_at_6c0[0x4];
1904 	u8         flex_parser_id_geneve_tlv_option_0[0x4];
1905 	u8         flex_parser_id_icmp_dw1[0x4];
1906 	u8         flex_parser_id_icmp_dw0[0x4];
1907 	u8         flex_parser_id_icmpv6_dw1[0x4];
1908 	u8         flex_parser_id_icmpv6_dw0[0x4];
1909 	u8         flex_parser_id_outer_first_mpls_over_gre[0x4];
1910 	u8         flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1911 
1912 	u8         max_num_match_definer[0x10];
1913 	u8	   sf_base_id[0x10];
1914 
1915 	u8         flex_parser_id_gtpu_dw_2[0x4];
1916 	u8         flex_parser_id_gtpu_first_ext_dw_0[0x4];
1917 	u8	   num_total_dynamic_vf_msix[0x18];
1918 	u8	   reserved_at_720[0x14];
1919 	u8	   dynamic_msix_table_size[0xc];
1920 	u8	   reserved_at_740[0xc];
1921 	u8	   min_dynamic_vf_msix_table_size[0x4];
1922 	u8	   reserved_at_750[0x4];
1923 	u8	   max_dynamic_vf_msix_table_size[0xc];
1924 
1925 	u8         reserved_at_760[0x3];
1926 	u8         log_max_num_header_modify_argument[0x5];
1927 	u8         reserved_at_768[0x4];
1928 	u8         log_header_modify_argument_granularity[0x4];
1929 	u8         reserved_at_770[0x3];
1930 	u8         log_header_modify_argument_max_alloc[0x5];
1931 	u8         reserved_at_778[0x8];
1932 
1933 	u8	   vhca_tunnel_commands[0x40];
1934 	u8         match_definer_format_supported[0x40];
1935 };
1936 
1937 struct mlx5_ifc_cmd_hca_cap_2_bits {
1938 	u8	   reserved_at_0[0x80];
1939 
1940 	u8         migratable[0x1];
1941 	u8         reserved_at_81[0x1f];
1942 
1943 	u8	   max_reformat_insert_size[0x8];
1944 	u8	   max_reformat_insert_offset[0x8];
1945 	u8	   max_reformat_remove_size[0x8];
1946 	u8	   max_reformat_remove_offset[0x8];
1947 
1948 	u8	   reserved_at_c0[0x8];
1949 	u8	   migration_multi_load[0x1];
1950 	u8	   migration_tracking_state[0x1];
1951 	u8	   reserved_at_ca[0x16];
1952 
1953 	u8	   reserved_at_e0[0xc0];
1954 
1955 	u8	   flow_table_type_2_type[0x8];
1956 	u8	   reserved_at_1a8[0x3];
1957 	u8	   log_min_mkey_entity_size[0x5];
1958 	u8	   reserved_at_1b0[0x10];
1959 
1960 	u8	   reserved_at_1c0[0x60];
1961 
1962 	u8	   reserved_at_220[0x1];
1963 	u8	   sw_vhca_id_valid[0x1];
1964 	u8	   sw_vhca_id[0xe];
1965 	u8	   reserved_at_230[0x10];
1966 
1967 	u8	   reserved_at_240[0xb];
1968 	u8	   ts_cqe_metadata_size2wqe_counter[0x5];
1969 	u8	   reserved_at_250[0x10];
1970 
1971 	u8	   reserved_at_260[0x120];
1972 	u8	   reserved_at_380[0x10];
1973 	u8	   ec_vf_vport_base[0x10];
1974 	u8	   reserved_at_3a0[0x460];
1975 };
1976 
1977 enum mlx5_ifc_flow_destination_type {
1978 	MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1979 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1980 	MLX5_IFC_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1981 	MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1982 	MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK       = 0x8,
1983 	MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE   = 0xA,
1984 };
1985 
1986 enum mlx5_flow_table_miss_action {
1987 	MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1988 	MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1989 	MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1990 };
1991 
1992 struct mlx5_ifc_dest_format_struct_bits {
1993 	u8         destination_type[0x8];
1994 	u8         destination_id[0x18];
1995 
1996 	u8         destination_eswitch_owner_vhca_id_valid[0x1];
1997 	u8         packet_reformat[0x1];
1998 	u8         reserved_at_22[0x6];
1999 	u8         destination_table_type[0x8];
2000 	u8         destination_eswitch_owner_vhca_id[0x10];
2001 };
2002 
2003 struct mlx5_ifc_flow_counter_list_bits {
2004 	u8         flow_counter_id[0x20];
2005 
2006 	u8         reserved_at_20[0x20];
2007 };
2008 
2009 struct mlx5_ifc_extended_dest_format_bits {
2010 	struct mlx5_ifc_dest_format_struct_bits destination_entry;
2011 
2012 	u8         packet_reformat_id[0x20];
2013 
2014 	u8         reserved_at_60[0x20];
2015 };
2016 
2017 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
2018 	struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
2019 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
2020 };
2021 
2022 struct mlx5_ifc_fte_match_param_bits {
2023 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
2024 
2025 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
2026 
2027 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
2028 
2029 	struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
2030 
2031 	struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
2032 
2033 	struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
2034 
2035 	struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
2036 
2037 	u8         reserved_at_e00[0x200];
2038 };
2039 
2040 enum {
2041 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2042 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2043 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2044 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2045 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2046 };
2047 
2048 struct mlx5_ifc_rx_hash_field_select_bits {
2049 	u8         l3_prot_type[0x1];
2050 	u8         l4_prot_type[0x1];
2051 	u8         selected_fields[0x1e];
2052 };
2053 
2054 enum {
2055 	MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
2056 	MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
2057 };
2058 
2059 enum {
2060 	MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
2061 	MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
2062 };
2063 
2064 struct mlx5_ifc_wq_bits {
2065 	u8         wq_type[0x4];
2066 	u8         wq_signature[0x1];
2067 	u8         end_padding_mode[0x2];
2068 	u8         cd_slave[0x1];
2069 	u8         reserved_at_8[0x18];
2070 
2071 	u8         hds_skip_first_sge[0x1];
2072 	u8         log2_hds_buf_size[0x3];
2073 	u8         reserved_at_24[0x7];
2074 	u8         page_offset[0x5];
2075 	u8         lwm[0x10];
2076 
2077 	u8         reserved_at_40[0x8];
2078 	u8         pd[0x18];
2079 
2080 	u8         reserved_at_60[0x8];
2081 	u8         uar_page[0x18];
2082 
2083 	u8         dbr_addr[0x40];
2084 
2085 	u8         hw_counter[0x20];
2086 
2087 	u8         sw_counter[0x20];
2088 
2089 	u8         reserved_at_100[0xc];
2090 	u8         log_wq_stride[0x4];
2091 	u8         reserved_at_110[0x3];
2092 	u8         log_wq_pg_sz[0x5];
2093 	u8         reserved_at_118[0x3];
2094 	u8         log_wq_sz[0x5];
2095 
2096 	u8         dbr_umem_valid[0x1];
2097 	u8         wq_umem_valid[0x1];
2098 	u8         reserved_at_122[0x1];
2099 	u8         log_hairpin_num_packets[0x5];
2100 	u8         reserved_at_128[0x3];
2101 	u8         log_hairpin_data_sz[0x5];
2102 
2103 	u8         reserved_at_130[0x4];
2104 	u8         log_wqe_num_of_strides[0x4];
2105 	u8         two_byte_shift_en[0x1];
2106 	u8         reserved_at_139[0x4];
2107 	u8         log_wqe_stride_size[0x3];
2108 
2109 	u8         reserved_at_140[0x80];
2110 
2111 	u8         headers_mkey[0x20];
2112 
2113 	u8         shampo_enable[0x1];
2114 	u8         reserved_at_1e1[0x4];
2115 	u8         log_reservation_size[0x3];
2116 	u8         reserved_at_1e8[0x5];
2117 	u8         log_max_num_of_packets_per_reservation[0x3];
2118 	u8         reserved_at_1f0[0x6];
2119 	u8         log_headers_entry_size[0x2];
2120 	u8         reserved_at_1f8[0x4];
2121 	u8         log_headers_buffer_entry_num[0x4];
2122 
2123 	u8         reserved_at_200[0x400];
2124 
2125 	struct mlx5_ifc_cmd_pas_bits pas[];
2126 };
2127 
2128 struct mlx5_ifc_rq_num_bits {
2129 	u8         reserved_at_0[0x8];
2130 	u8         rq_num[0x18];
2131 };
2132 
2133 struct mlx5_ifc_mac_address_layout_bits {
2134 	u8         reserved_at_0[0x10];
2135 	u8         mac_addr_47_32[0x10];
2136 
2137 	u8         mac_addr_31_0[0x20];
2138 };
2139 
2140 struct mlx5_ifc_vlan_layout_bits {
2141 	u8         reserved_at_0[0x14];
2142 	u8         vlan[0x0c];
2143 
2144 	u8         reserved_at_20[0x20];
2145 };
2146 
2147 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
2148 	u8         reserved_at_0[0xa0];
2149 
2150 	u8         min_time_between_cnps[0x20];
2151 
2152 	u8         reserved_at_c0[0x12];
2153 	u8         cnp_dscp[0x6];
2154 	u8         reserved_at_d8[0x4];
2155 	u8         cnp_prio_mode[0x1];
2156 	u8         cnp_802p_prio[0x3];
2157 
2158 	u8         reserved_at_e0[0x720];
2159 };
2160 
2161 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
2162 	u8         reserved_at_0[0x60];
2163 
2164 	u8         reserved_at_60[0x4];
2165 	u8         clamp_tgt_rate[0x1];
2166 	u8         reserved_at_65[0x3];
2167 	u8         clamp_tgt_rate_after_time_inc[0x1];
2168 	u8         reserved_at_69[0x17];
2169 
2170 	u8         reserved_at_80[0x20];
2171 
2172 	u8         rpg_time_reset[0x20];
2173 
2174 	u8         rpg_byte_reset[0x20];
2175 
2176 	u8         rpg_threshold[0x20];
2177 
2178 	u8         rpg_max_rate[0x20];
2179 
2180 	u8         rpg_ai_rate[0x20];
2181 
2182 	u8         rpg_hai_rate[0x20];
2183 
2184 	u8         rpg_gd[0x20];
2185 
2186 	u8         rpg_min_dec_fac[0x20];
2187 
2188 	u8         rpg_min_rate[0x20];
2189 
2190 	u8         reserved_at_1c0[0xe0];
2191 
2192 	u8         rate_to_set_on_first_cnp[0x20];
2193 
2194 	u8         dce_tcp_g[0x20];
2195 
2196 	u8         dce_tcp_rtt[0x20];
2197 
2198 	u8         rate_reduce_monitor_period[0x20];
2199 
2200 	u8         reserved_at_320[0x20];
2201 
2202 	u8         initial_alpha_value[0x20];
2203 
2204 	u8         reserved_at_360[0x4a0];
2205 };
2206 
2207 struct mlx5_ifc_cong_control_r_roce_general_bits {
2208 	u8         reserved_at_0[0x80];
2209 
2210 	u8         reserved_at_80[0x10];
2211 	u8         rtt_resp_dscp_valid[0x1];
2212 	u8         reserved_at_91[0x9];
2213 	u8         rtt_resp_dscp[0x6];
2214 
2215 	u8         reserved_at_a0[0x760];
2216 };
2217 
2218 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
2219 	u8         reserved_at_0[0x80];
2220 
2221 	u8         rppp_max_rps[0x20];
2222 
2223 	u8         rpg_time_reset[0x20];
2224 
2225 	u8         rpg_byte_reset[0x20];
2226 
2227 	u8         rpg_threshold[0x20];
2228 
2229 	u8         rpg_max_rate[0x20];
2230 
2231 	u8         rpg_ai_rate[0x20];
2232 
2233 	u8         rpg_hai_rate[0x20];
2234 
2235 	u8         rpg_gd[0x20];
2236 
2237 	u8         rpg_min_dec_fac[0x20];
2238 
2239 	u8         rpg_min_rate[0x20];
2240 
2241 	u8         reserved_at_1c0[0x640];
2242 };
2243 
2244 enum {
2245 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
2246 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
2247 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
2248 };
2249 
2250 struct mlx5_ifc_resize_field_select_bits {
2251 	u8         resize_field_select[0x20];
2252 };
2253 
2254 struct mlx5_ifc_resource_dump_bits {
2255 	u8         more_dump[0x1];
2256 	u8         inline_dump[0x1];
2257 	u8         reserved_at_2[0xa];
2258 	u8         seq_num[0x4];
2259 	u8         segment_type[0x10];
2260 
2261 	u8         reserved_at_20[0x10];
2262 	u8         vhca_id[0x10];
2263 
2264 	u8         index1[0x20];
2265 
2266 	u8         index2[0x20];
2267 
2268 	u8         num_of_obj1[0x10];
2269 	u8         num_of_obj2[0x10];
2270 
2271 	u8         reserved_at_a0[0x20];
2272 
2273 	u8         device_opaque[0x40];
2274 
2275 	u8         mkey[0x20];
2276 
2277 	u8         size[0x20];
2278 
2279 	u8         address[0x40];
2280 
2281 	u8         inline_data[52][0x20];
2282 };
2283 
2284 struct mlx5_ifc_resource_dump_menu_record_bits {
2285 	u8         reserved_at_0[0x4];
2286 	u8         num_of_obj2_supports_active[0x1];
2287 	u8         num_of_obj2_supports_all[0x1];
2288 	u8         must_have_num_of_obj2[0x1];
2289 	u8         support_num_of_obj2[0x1];
2290 	u8         num_of_obj1_supports_active[0x1];
2291 	u8         num_of_obj1_supports_all[0x1];
2292 	u8         must_have_num_of_obj1[0x1];
2293 	u8         support_num_of_obj1[0x1];
2294 	u8         must_have_index2[0x1];
2295 	u8         support_index2[0x1];
2296 	u8         must_have_index1[0x1];
2297 	u8         support_index1[0x1];
2298 	u8         segment_type[0x10];
2299 
2300 	u8         segment_name[4][0x20];
2301 
2302 	u8         index1_name[4][0x20];
2303 
2304 	u8         index2_name[4][0x20];
2305 };
2306 
2307 struct mlx5_ifc_resource_dump_segment_header_bits {
2308 	u8         length_dw[0x10];
2309 	u8         segment_type[0x10];
2310 };
2311 
2312 struct mlx5_ifc_resource_dump_command_segment_bits {
2313 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2314 
2315 	u8         segment_called[0x10];
2316 	u8         vhca_id[0x10];
2317 
2318 	u8         index1[0x20];
2319 
2320 	u8         index2[0x20];
2321 
2322 	u8         num_of_obj1[0x10];
2323 	u8         num_of_obj2[0x10];
2324 };
2325 
2326 struct mlx5_ifc_resource_dump_error_segment_bits {
2327 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2328 
2329 	u8         reserved_at_20[0x10];
2330 	u8         syndrome_id[0x10];
2331 
2332 	u8         reserved_at_40[0x40];
2333 
2334 	u8         error[8][0x20];
2335 };
2336 
2337 struct mlx5_ifc_resource_dump_info_segment_bits {
2338 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2339 
2340 	u8         reserved_at_20[0x18];
2341 	u8         dump_version[0x8];
2342 
2343 	u8         hw_version[0x20];
2344 
2345 	u8         fw_version[0x20];
2346 };
2347 
2348 struct mlx5_ifc_resource_dump_menu_segment_bits {
2349 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2350 
2351 	u8         reserved_at_20[0x10];
2352 	u8         num_of_records[0x10];
2353 
2354 	struct mlx5_ifc_resource_dump_menu_record_bits record[];
2355 };
2356 
2357 struct mlx5_ifc_resource_dump_resource_segment_bits {
2358 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2359 
2360 	u8         reserved_at_20[0x20];
2361 
2362 	u8         index1[0x20];
2363 
2364 	u8         index2[0x20];
2365 
2366 	u8         payload[][0x20];
2367 };
2368 
2369 struct mlx5_ifc_resource_dump_terminate_segment_bits {
2370 	struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
2371 };
2372 
2373 struct mlx5_ifc_menu_resource_dump_response_bits {
2374 	struct mlx5_ifc_resource_dump_info_segment_bits info;
2375 	struct mlx5_ifc_resource_dump_command_segment_bits cmd;
2376 	struct mlx5_ifc_resource_dump_menu_segment_bits menu;
2377 	struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
2378 };
2379 
2380 enum {
2381 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
2382 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
2383 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
2384 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
2385 };
2386 
2387 struct mlx5_ifc_modify_field_select_bits {
2388 	u8         modify_field_select[0x20];
2389 };
2390 
2391 struct mlx5_ifc_field_select_r_roce_np_bits {
2392 	u8         field_select_r_roce_np[0x20];
2393 };
2394 
2395 struct mlx5_ifc_field_select_r_roce_rp_bits {
2396 	u8         field_select_r_roce_rp[0x20];
2397 };
2398 
2399 enum {
2400 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
2401 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
2402 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
2403 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
2404 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
2405 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
2406 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
2407 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
2408 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
2409 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
2410 };
2411 
2412 struct mlx5_ifc_field_select_802_1qau_rp_bits {
2413 	u8         field_select_8021qaurp[0x20];
2414 };
2415 
2416 struct mlx5_ifc_phys_layer_cntrs_bits {
2417 	u8         time_since_last_clear_high[0x20];
2418 
2419 	u8         time_since_last_clear_low[0x20];
2420 
2421 	u8         symbol_errors_high[0x20];
2422 
2423 	u8         symbol_errors_low[0x20];
2424 
2425 	u8         sync_headers_errors_high[0x20];
2426 
2427 	u8         sync_headers_errors_low[0x20];
2428 
2429 	u8         edpl_bip_errors_lane0_high[0x20];
2430 
2431 	u8         edpl_bip_errors_lane0_low[0x20];
2432 
2433 	u8         edpl_bip_errors_lane1_high[0x20];
2434 
2435 	u8         edpl_bip_errors_lane1_low[0x20];
2436 
2437 	u8         edpl_bip_errors_lane2_high[0x20];
2438 
2439 	u8         edpl_bip_errors_lane2_low[0x20];
2440 
2441 	u8         edpl_bip_errors_lane3_high[0x20];
2442 
2443 	u8         edpl_bip_errors_lane3_low[0x20];
2444 
2445 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
2446 
2447 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
2448 
2449 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
2450 
2451 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
2452 
2453 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
2454 
2455 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
2456 
2457 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
2458 
2459 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
2460 
2461 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
2462 
2463 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
2464 
2465 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
2466 
2467 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
2468 
2469 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
2470 
2471 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
2472 
2473 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
2474 
2475 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
2476 
2477 	u8         rs_fec_corrected_blocks_high[0x20];
2478 
2479 	u8         rs_fec_corrected_blocks_low[0x20];
2480 
2481 	u8         rs_fec_uncorrectable_blocks_high[0x20];
2482 
2483 	u8         rs_fec_uncorrectable_blocks_low[0x20];
2484 
2485 	u8         rs_fec_no_errors_blocks_high[0x20];
2486 
2487 	u8         rs_fec_no_errors_blocks_low[0x20];
2488 
2489 	u8         rs_fec_single_error_blocks_high[0x20];
2490 
2491 	u8         rs_fec_single_error_blocks_low[0x20];
2492 
2493 	u8         rs_fec_corrected_symbols_total_high[0x20];
2494 
2495 	u8         rs_fec_corrected_symbols_total_low[0x20];
2496 
2497 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
2498 
2499 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
2500 
2501 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
2502 
2503 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
2504 
2505 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
2506 
2507 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
2508 
2509 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
2510 
2511 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
2512 
2513 	u8         link_down_events[0x20];
2514 
2515 	u8         successful_recovery_events[0x20];
2516 
2517 	u8         reserved_at_640[0x180];
2518 };
2519 
2520 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2521 	u8         time_since_last_clear_high[0x20];
2522 
2523 	u8         time_since_last_clear_low[0x20];
2524 
2525 	u8         phy_received_bits_high[0x20];
2526 
2527 	u8         phy_received_bits_low[0x20];
2528 
2529 	u8         phy_symbol_errors_high[0x20];
2530 
2531 	u8         phy_symbol_errors_low[0x20];
2532 
2533 	u8         phy_corrected_bits_high[0x20];
2534 
2535 	u8         phy_corrected_bits_low[0x20];
2536 
2537 	u8         phy_corrected_bits_lane0_high[0x20];
2538 
2539 	u8         phy_corrected_bits_lane0_low[0x20];
2540 
2541 	u8         phy_corrected_bits_lane1_high[0x20];
2542 
2543 	u8         phy_corrected_bits_lane1_low[0x20];
2544 
2545 	u8         phy_corrected_bits_lane2_high[0x20];
2546 
2547 	u8         phy_corrected_bits_lane2_low[0x20];
2548 
2549 	u8         phy_corrected_bits_lane3_high[0x20];
2550 
2551 	u8         phy_corrected_bits_lane3_low[0x20];
2552 
2553 	u8         reserved_at_200[0x5c0];
2554 };
2555 
2556 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2557 	u8	   symbol_error_counter[0x10];
2558 
2559 	u8         link_error_recovery_counter[0x8];
2560 
2561 	u8         link_downed_counter[0x8];
2562 
2563 	u8         port_rcv_errors[0x10];
2564 
2565 	u8         port_rcv_remote_physical_errors[0x10];
2566 
2567 	u8         port_rcv_switch_relay_errors[0x10];
2568 
2569 	u8         port_xmit_discards[0x10];
2570 
2571 	u8         port_xmit_constraint_errors[0x8];
2572 
2573 	u8         port_rcv_constraint_errors[0x8];
2574 
2575 	u8         reserved_at_70[0x8];
2576 
2577 	u8         link_overrun_errors[0x8];
2578 
2579 	u8	   reserved_at_80[0x10];
2580 
2581 	u8         vl_15_dropped[0x10];
2582 
2583 	u8	   reserved_at_a0[0x80];
2584 
2585 	u8         port_xmit_wait[0x20];
2586 };
2587 
2588 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2589 	u8         transmit_queue_high[0x20];
2590 
2591 	u8         transmit_queue_low[0x20];
2592 
2593 	u8         no_buffer_discard_uc_high[0x20];
2594 
2595 	u8         no_buffer_discard_uc_low[0x20];
2596 
2597 	u8         reserved_at_80[0x740];
2598 };
2599 
2600 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2601 	u8         wred_discard_high[0x20];
2602 
2603 	u8         wred_discard_low[0x20];
2604 
2605 	u8         ecn_marked_tc_high[0x20];
2606 
2607 	u8         ecn_marked_tc_low[0x20];
2608 
2609 	u8         reserved_at_80[0x740];
2610 };
2611 
2612 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2613 	u8         rx_octets_high[0x20];
2614 
2615 	u8         rx_octets_low[0x20];
2616 
2617 	u8         reserved_at_40[0xc0];
2618 
2619 	u8         rx_frames_high[0x20];
2620 
2621 	u8         rx_frames_low[0x20];
2622 
2623 	u8         tx_octets_high[0x20];
2624 
2625 	u8         tx_octets_low[0x20];
2626 
2627 	u8         reserved_at_180[0xc0];
2628 
2629 	u8         tx_frames_high[0x20];
2630 
2631 	u8         tx_frames_low[0x20];
2632 
2633 	u8         rx_pause_high[0x20];
2634 
2635 	u8         rx_pause_low[0x20];
2636 
2637 	u8         rx_pause_duration_high[0x20];
2638 
2639 	u8         rx_pause_duration_low[0x20];
2640 
2641 	u8         tx_pause_high[0x20];
2642 
2643 	u8         tx_pause_low[0x20];
2644 
2645 	u8         tx_pause_duration_high[0x20];
2646 
2647 	u8         tx_pause_duration_low[0x20];
2648 
2649 	u8         rx_pause_transition_high[0x20];
2650 
2651 	u8         rx_pause_transition_low[0x20];
2652 
2653 	u8         rx_discards_high[0x20];
2654 
2655 	u8         rx_discards_low[0x20];
2656 
2657 	u8         device_stall_minor_watermark_cnt_high[0x20];
2658 
2659 	u8         device_stall_minor_watermark_cnt_low[0x20];
2660 
2661 	u8         device_stall_critical_watermark_cnt_high[0x20];
2662 
2663 	u8         device_stall_critical_watermark_cnt_low[0x20];
2664 
2665 	u8         reserved_at_480[0x340];
2666 };
2667 
2668 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2669 	u8         port_transmit_wait_high[0x20];
2670 
2671 	u8         port_transmit_wait_low[0x20];
2672 
2673 	u8         reserved_at_40[0x100];
2674 
2675 	u8         rx_buffer_almost_full_high[0x20];
2676 
2677 	u8         rx_buffer_almost_full_low[0x20];
2678 
2679 	u8         rx_buffer_full_high[0x20];
2680 
2681 	u8         rx_buffer_full_low[0x20];
2682 
2683 	u8         rx_icrc_encapsulated_high[0x20];
2684 
2685 	u8         rx_icrc_encapsulated_low[0x20];
2686 
2687 	u8         reserved_at_200[0x5c0];
2688 };
2689 
2690 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2691 	u8         dot3stats_alignment_errors_high[0x20];
2692 
2693 	u8         dot3stats_alignment_errors_low[0x20];
2694 
2695 	u8         dot3stats_fcs_errors_high[0x20];
2696 
2697 	u8         dot3stats_fcs_errors_low[0x20];
2698 
2699 	u8         dot3stats_single_collision_frames_high[0x20];
2700 
2701 	u8         dot3stats_single_collision_frames_low[0x20];
2702 
2703 	u8         dot3stats_multiple_collision_frames_high[0x20];
2704 
2705 	u8         dot3stats_multiple_collision_frames_low[0x20];
2706 
2707 	u8         dot3stats_sqe_test_errors_high[0x20];
2708 
2709 	u8         dot3stats_sqe_test_errors_low[0x20];
2710 
2711 	u8         dot3stats_deferred_transmissions_high[0x20];
2712 
2713 	u8         dot3stats_deferred_transmissions_low[0x20];
2714 
2715 	u8         dot3stats_late_collisions_high[0x20];
2716 
2717 	u8         dot3stats_late_collisions_low[0x20];
2718 
2719 	u8         dot3stats_excessive_collisions_high[0x20];
2720 
2721 	u8         dot3stats_excessive_collisions_low[0x20];
2722 
2723 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
2724 
2725 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
2726 
2727 	u8         dot3stats_carrier_sense_errors_high[0x20];
2728 
2729 	u8         dot3stats_carrier_sense_errors_low[0x20];
2730 
2731 	u8         dot3stats_frame_too_longs_high[0x20];
2732 
2733 	u8         dot3stats_frame_too_longs_low[0x20];
2734 
2735 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
2736 
2737 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
2738 
2739 	u8         dot3stats_symbol_errors_high[0x20];
2740 
2741 	u8         dot3stats_symbol_errors_low[0x20];
2742 
2743 	u8         dot3control_in_unknown_opcodes_high[0x20];
2744 
2745 	u8         dot3control_in_unknown_opcodes_low[0x20];
2746 
2747 	u8         dot3in_pause_frames_high[0x20];
2748 
2749 	u8         dot3in_pause_frames_low[0x20];
2750 
2751 	u8         dot3out_pause_frames_high[0x20];
2752 
2753 	u8         dot3out_pause_frames_low[0x20];
2754 
2755 	u8         reserved_at_400[0x3c0];
2756 };
2757 
2758 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2759 	u8         ether_stats_drop_events_high[0x20];
2760 
2761 	u8         ether_stats_drop_events_low[0x20];
2762 
2763 	u8         ether_stats_octets_high[0x20];
2764 
2765 	u8         ether_stats_octets_low[0x20];
2766 
2767 	u8         ether_stats_pkts_high[0x20];
2768 
2769 	u8         ether_stats_pkts_low[0x20];
2770 
2771 	u8         ether_stats_broadcast_pkts_high[0x20];
2772 
2773 	u8         ether_stats_broadcast_pkts_low[0x20];
2774 
2775 	u8         ether_stats_multicast_pkts_high[0x20];
2776 
2777 	u8         ether_stats_multicast_pkts_low[0x20];
2778 
2779 	u8         ether_stats_crc_align_errors_high[0x20];
2780 
2781 	u8         ether_stats_crc_align_errors_low[0x20];
2782 
2783 	u8         ether_stats_undersize_pkts_high[0x20];
2784 
2785 	u8         ether_stats_undersize_pkts_low[0x20];
2786 
2787 	u8         ether_stats_oversize_pkts_high[0x20];
2788 
2789 	u8         ether_stats_oversize_pkts_low[0x20];
2790 
2791 	u8         ether_stats_fragments_high[0x20];
2792 
2793 	u8         ether_stats_fragments_low[0x20];
2794 
2795 	u8         ether_stats_jabbers_high[0x20];
2796 
2797 	u8         ether_stats_jabbers_low[0x20];
2798 
2799 	u8         ether_stats_collisions_high[0x20];
2800 
2801 	u8         ether_stats_collisions_low[0x20];
2802 
2803 	u8         ether_stats_pkts64octets_high[0x20];
2804 
2805 	u8         ether_stats_pkts64octets_low[0x20];
2806 
2807 	u8         ether_stats_pkts65to127octets_high[0x20];
2808 
2809 	u8         ether_stats_pkts65to127octets_low[0x20];
2810 
2811 	u8         ether_stats_pkts128to255octets_high[0x20];
2812 
2813 	u8         ether_stats_pkts128to255octets_low[0x20];
2814 
2815 	u8         ether_stats_pkts256to511octets_high[0x20];
2816 
2817 	u8         ether_stats_pkts256to511octets_low[0x20];
2818 
2819 	u8         ether_stats_pkts512to1023octets_high[0x20];
2820 
2821 	u8         ether_stats_pkts512to1023octets_low[0x20];
2822 
2823 	u8         ether_stats_pkts1024to1518octets_high[0x20];
2824 
2825 	u8         ether_stats_pkts1024to1518octets_low[0x20];
2826 
2827 	u8         ether_stats_pkts1519to2047octets_high[0x20];
2828 
2829 	u8         ether_stats_pkts1519to2047octets_low[0x20];
2830 
2831 	u8         ether_stats_pkts2048to4095octets_high[0x20];
2832 
2833 	u8         ether_stats_pkts2048to4095octets_low[0x20];
2834 
2835 	u8         ether_stats_pkts4096to8191octets_high[0x20];
2836 
2837 	u8         ether_stats_pkts4096to8191octets_low[0x20];
2838 
2839 	u8         ether_stats_pkts8192to10239octets_high[0x20];
2840 
2841 	u8         ether_stats_pkts8192to10239octets_low[0x20];
2842 
2843 	u8         reserved_at_540[0x280];
2844 };
2845 
2846 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2847 	u8         if_in_octets_high[0x20];
2848 
2849 	u8         if_in_octets_low[0x20];
2850 
2851 	u8         if_in_ucast_pkts_high[0x20];
2852 
2853 	u8         if_in_ucast_pkts_low[0x20];
2854 
2855 	u8         if_in_discards_high[0x20];
2856 
2857 	u8         if_in_discards_low[0x20];
2858 
2859 	u8         if_in_errors_high[0x20];
2860 
2861 	u8         if_in_errors_low[0x20];
2862 
2863 	u8         if_in_unknown_protos_high[0x20];
2864 
2865 	u8         if_in_unknown_protos_low[0x20];
2866 
2867 	u8         if_out_octets_high[0x20];
2868 
2869 	u8         if_out_octets_low[0x20];
2870 
2871 	u8         if_out_ucast_pkts_high[0x20];
2872 
2873 	u8         if_out_ucast_pkts_low[0x20];
2874 
2875 	u8         if_out_discards_high[0x20];
2876 
2877 	u8         if_out_discards_low[0x20];
2878 
2879 	u8         if_out_errors_high[0x20];
2880 
2881 	u8         if_out_errors_low[0x20];
2882 
2883 	u8         if_in_multicast_pkts_high[0x20];
2884 
2885 	u8         if_in_multicast_pkts_low[0x20];
2886 
2887 	u8         if_in_broadcast_pkts_high[0x20];
2888 
2889 	u8         if_in_broadcast_pkts_low[0x20];
2890 
2891 	u8         if_out_multicast_pkts_high[0x20];
2892 
2893 	u8         if_out_multicast_pkts_low[0x20];
2894 
2895 	u8         if_out_broadcast_pkts_high[0x20];
2896 
2897 	u8         if_out_broadcast_pkts_low[0x20];
2898 
2899 	u8         reserved_at_340[0x480];
2900 };
2901 
2902 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2903 	u8         a_frames_transmitted_ok_high[0x20];
2904 
2905 	u8         a_frames_transmitted_ok_low[0x20];
2906 
2907 	u8         a_frames_received_ok_high[0x20];
2908 
2909 	u8         a_frames_received_ok_low[0x20];
2910 
2911 	u8         a_frame_check_sequence_errors_high[0x20];
2912 
2913 	u8         a_frame_check_sequence_errors_low[0x20];
2914 
2915 	u8         a_alignment_errors_high[0x20];
2916 
2917 	u8         a_alignment_errors_low[0x20];
2918 
2919 	u8         a_octets_transmitted_ok_high[0x20];
2920 
2921 	u8         a_octets_transmitted_ok_low[0x20];
2922 
2923 	u8         a_octets_received_ok_high[0x20];
2924 
2925 	u8         a_octets_received_ok_low[0x20];
2926 
2927 	u8         a_multicast_frames_xmitted_ok_high[0x20];
2928 
2929 	u8         a_multicast_frames_xmitted_ok_low[0x20];
2930 
2931 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
2932 
2933 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
2934 
2935 	u8         a_multicast_frames_received_ok_high[0x20];
2936 
2937 	u8         a_multicast_frames_received_ok_low[0x20];
2938 
2939 	u8         a_broadcast_frames_received_ok_high[0x20];
2940 
2941 	u8         a_broadcast_frames_received_ok_low[0x20];
2942 
2943 	u8         a_in_range_length_errors_high[0x20];
2944 
2945 	u8         a_in_range_length_errors_low[0x20];
2946 
2947 	u8         a_out_of_range_length_field_high[0x20];
2948 
2949 	u8         a_out_of_range_length_field_low[0x20];
2950 
2951 	u8         a_frame_too_long_errors_high[0x20];
2952 
2953 	u8         a_frame_too_long_errors_low[0x20];
2954 
2955 	u8         a_symbol_error_during_carrier_high[0x20];
2956 
2957 	u8         a_symbol_error_during_carrier_low[0x20];
2958 
2959 	u8         a_mac_control_frames_transmitted_high[0x20];
2960 
2961 	u8         a_mac_control_frames_transmitted_low[0x20];
2962 
2963 	u8         a_mac_control_frames_received_high[0x20];
2964 
2965 	u8         a_mac_control_frames_received_low[0x20];
2966 
2967 	u8         a_unsupported_opcodes_received_high[0x20];
2968 
2969 	u8         a_unsupported_opcodes_received_low[0x20];
2970 
2971 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
2972 
2973 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
2974 
2975 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2976 
2977 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2978 
2979 	u8         reserved_at_4c0[0x300];
2980 };
2981 
2982 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2983 	u8         life_time_counter_high[0x20];
2984 
2985 	u8         life_time_counter_low[0x20];
2986 
2987 	u8         rx_errors[0x20];
2988 
2989 	u8         tx_errors[0x20];
2990 
2991 	u8         l0_to_recovery_eieos[0x20];
2992 
2993 	u8         l0_to_recovery_ts[0x20];
2994 
2995 	u8         l0_to_recovery_framing[0x20];
2996 
2997 	u8         l0_to_recovery_retrain[0x20];
2998 
2999 	u8         crc_error_dllp[0x20];
3000 
3001 	u8         crc_error_tlp[0x20];
3002 
3003 	u8         tx_overflow_buffer_pkt_high[0x20];
3004 
3005 	u8         tx_overflow_buffer_pkt_low[0x20];
3006 
3007 	u8         outbound_stalled_reads[0x20];
3008 
3009 	u8         outbound_stalled_writes[0x20];
3010 
3011 	u8         outbound_stalled_reads_events[0x20];
3012 
3013 	u8         outbound_stalled_writes_events[0x20];
3014 
3015 	u8         reserved_at_200[0x5c0];
3016 };
3017 
3018 struct mlx5_ifc_cmd_inter_comp_event_bits {
3019 	u8         command_completion_vector[0x20];
3020 
3021 	u8         reserved_at_20[0xc0];
3022 };
3023 
3024 struct mlx5_ifc_stall_vl_event_bits {
3025 	u8         reserved_at_0[0x18];
3026 	u8         port_num[0x1];
3027 	u8         reserved_at_19[0x3];
3028 	u8         vl[0x4];
3029 
3030 	u8         reserved_at_20[0xa0];
3031 };
3032 
3033 struct mlx5_ifc_db_bf_congestion_event_bits {
3034 	u8         event_subtype[0x8];
3035 	u8         reserved_at_8[0x8];
3036 	u8         congestion_level[0x8];
3037 	u8         reserved_at_18[0x8];
3038 
3039 	u8         reserved_at_20[0xa0];
3040 };
3041 
3042 struct mlx5_ifc_gpio_event_bits {
3043 	u8         reserved_at_0[0x60];
3044 
3045 	u8         gpio_event_hi[0x20];
3046 
3047 	u8         gpio_event_lo[0x20];
3048 
3049 	u8         reserved_at_a0[0x40];
3050 };
3051 
3052 struct mlx5_ifc_port_state_change_event_bits {
3053 	u8         reserved_at_0[0x40];
3054 
3055 	u8         port_num[0x4];
3056 	u8         reserved_at_44[0x1c];
3057 
3058 	u8         reserved_at_60[0x80];
3059 };
3060 
3061 struct mlx5_ifc_dropped_packet_logged_bits {
3062 	u8         reserved_at_0[0xe0];
3063 };
3064 
3065 struct mlx5_ifc_default_timeout_bits {
3066 	u8         to_multiplier[0x3];
3067 	u8         reserved_at_3[0x9];
3068 	u8         to_value[0x14];
3069 };
3070 
3071 struct mlx5_ifc_dtor_reg_bits {
3072 	u8         reserved_at_0[0x20];
3073 
3074 	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;
3075 
3076 	u8         reserved_at_40[0x60];
3077 
3078 	struct mlx5_ifc_default_timeout_bits health_poll_to;
3079 
3080 	struct mlx5_ifc_default_timeout_bits full_crdump_to;
3081 
3082 	struct mlx5_ifc_default_timeout_bits fw_reset_to;
3083 
3084 	struct mlx5_ifc_default_timeout_bits flush_on_err_to;
3085 
3086 	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;
3087 
3088 	struct mlx5_ifc_default_timeout_bits tear_down_to;
3089 
3090 	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;
3091 
3092 	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;
3093 
3094 	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;
3095 
3096 	struct mlx5_ifc_default_timeout_bits reset_unload_to;
3097 
3098 	u8         reserved_at_1c0[0x20];
3099 };
3100 
3101 enum {
3102 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
3103 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
3104 };
3105 
3106 struct mlx5_ifc_cq_error_bits {
3107 	u8         reserved_at_0[0x8];
3108 	u8         cqn[0x18];
3109 
3110 	u8         reserved_at_20[0x20];
3111 
3112 	u8         reserved_at_40[0x18];
3113 	u8         syndrome[0x8];
3114 
3115 	u8         reserved_at_60[0x80];
3116 };
3117 
3118 struct mlx5_ifc_rdma_page_fault_event_bits {
3119 	u8         bytes_committed[0x20];
3120 
3121 	u8         r_key[0x20];
3122 
3123 	u8         reserved_at_40[0x10];
3124 	u8         packet_len[0x10];
3125 
3126 	u8         rdma_op_len[0x20];
3127 
3128 	u8         rdma_va[0x40];
3129 
3130 	u8         reserved_at_c0[0x5];
3131 	u8         rdma[0x1];
3132 	u8         write[0x1];
3133 	u8         requestor[0x1];
3134 	u8         qp_number[0x18];
3135 };
3136 
3137 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
3138 	u8         bytes_committed[0x20];
3139 
3140 	u8         reserved_at_20[0x10];
3141 	u8         wqe_index[0x10];
3142 
3143 	u8         reserved_at_40[0x10];
3144 	u8         len[0x10];
3145 
3146 	u8         reserved_at_60[0x60];
3147 
3148 	u8         reserved_at_c0[0x5];
3149 	u8         rdma[0x1];
3150 	u8         write_read[0x1];
3151 	u8         requestor[0x1];
3152 	u8         qpn[0x18];
3153 };
3154 
3155 struct mlx5_ifc_qp_events_bits {
3156 	u8         reserved_at_0[0xa0];
3157 
3158 	u8         type[0x8];
3159 	u8         reserved_at_a8[0x18];
3160 
3161 	u8         reserved_at_c0[0x8];
3162 	u8         qpn_rqn_sqn[0x18];
3163 };
3164 
3165 struct mlx5_ifc_dct_events_bits {
3166 	u8         reserved_at_0[0xc0];
3167 
3168 	u8         reserved_at_c0[0x8];
3169 	u8         dct_number[0x18];
3170 };
3171 
3172 struct mlx5_ifc_comp_event_bits {
3173 	u8         reserved_at_0[0xc0];
3174 
3175 	u8         reserved_at_c0[0x8];
3176 	u8         cq_number[0x18];
3177 };
3178 
3179 enum {
3180 	MLX5_QPC_STATE_RST        = 0x0,
3181 	MLX5_QPC_STATE_INIT       = 0x1,
3182 	MLX5_QPC_STATE_RTR        = 0x2,
3183 	MLX5_QPC_STATE_RTS        = 0x3,
3184 	MLX5_QPC_STATE_SQER       = 0x4,
3185 	MLX5_QPC_STATE_ERR        = 0x6,
3186 	MLX5_QPC_STATE_SQD        = 0x7,
3187 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
3188 };
3189 
3190 enum {
3191 	MLX5_QPC_ST_RC            = 0x0,
3192 	MLX5_QPC_ST_UC            = 0x1,
3193 	MLX5_QPC_ST_UD            = 0x2,
3194 	MLX5_QPC_ST_XRC           = 0x3,
3195 	MLX5_QPC_ST_DCI           = 0x5,
3196 	MLX5_QPC_ST_QP0           = 0x7,
3197 	MLX5_QPC_ST_QP1           = 0x8,
3198 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
3199 	MLX5_QPC_ST_REG_UMR       = 0xc,
3200 };
3201 
3202 enum {
3203 	MLX5_QPC_PM_STATE_ARMED     = 0x0,
3204 	MLX5_QPC_PM_STATE_REARM     = 0x1,
3205 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
3206 	MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
3207 };
3208 
3209 enum {
3210 	MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
3211 };
3212 
3213 enum {
3214 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
3215 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
3216 };
3217 
3218 enum {
3219 	MLX5_QPC_MTU_256_BYTES        = 0x1,
3220 	MLX5_QPC_MTU_512_BYTES        = 0x2,
3221 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
3222 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
3223 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
3224 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
3225 };
3226 
3227 enum {
3228 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
3229 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
3230 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
3231 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
3232 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
3233 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
3234 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
3235 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
3236 };
3237 
3238 enum {
3239 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
3240 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
3241 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
3242 };
3243 
3244 enum {
3245 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
3246 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
3247 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
3248 };
3249 
3250 enum {
3251 	MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
3252 	MLX5_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
3253 	MLX5_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
3254 };
3255 
3256 struct mlx5_ifc_qpc_bits {
3257 	u8         state[0x4];
3258 	u8         lag_tx_port_affinity[0x4];
3259 	u8         st[0x8];
3260 	u8         reserved_at_10[0x2];
3261 	u8	   isolate_vl_tc[0x1];
3262 	u8         pm_state[0x2];
3263 	u8         reserved_at_15[0x1];
3264 	u8         req_e2e_credit_mode[0x2];
3265 	u8         offload_type[0x4];
3266 	u8         end_padding_mode[0x2];
3267 	u8         reserved_at_1e[0x2];
3268 
3269 	u8         wq_signature[0x1];
3270 	u8         block_lb_mc[0x1];
3271 	u8         atomic_like_write_en[0x1];
3272 	u8         latency_sensitive[0x1];
3273 	u8         reserved_at_24[0x1];
3274 	u8         drain_sigerr[0x1];
3275 	u8         reserved_at_26[0x2];
3276 	u8         pd[0x18];
3277 
3278 	u8         mtu[0x3];
3279 	u8         log_msg_max[0x5];
3280 	u8         reserved_at_48[0x1];
3281 	u8         log_rq_size[0x4];
3282 	u8         log_rq_stride[0x3];
3283 	u8         no_sq[0x1];
3284 	u8         log_sq_size[0x4];
3285 	u8         reserved_at_55[0x1];
3286 	u8	   retry_mode[0x2];
3287 	u8	   ts_format[0x2];
3288 	u8         reserved_at_5a[0x1];
3289 	u8         rlky[0x1];
3290 	u8         ulp_stateless_offload_mode[0x4];
3291 
3292 	u8         counter_set_id[0x8];
3293 	u8         uar_page[0x18];
3294 
3295 	u8         reserved_at_80[0x8];
3296 	u8         user_index[0x18];
3297 
3298 	u8         reserved_at_a0[0x3];
3299 	u8         log_page_size[0x5];
3300 	u8         remote_qpn[0x18];
3301 
3302 	struct mlx5_ifc_ads_bits primary_address_path;
3303 
3304 	struct mlx5_ifc_ads_bits secondary_address_path;
3305 
3306 	u8         log_ack_req_freq[0x4];
3307 	u8         reserved_at_384[0x4];
3308 	u8         log_sra_max[0x3];
3309 	u8         reserved_at_38b[0x2];
3310 	u8         retry_count[0x3];
3311 	u8         rnr_retry[0x3];
3312 	u8         reserved_at_393[0x1];
3313 	u8         fre[0x1];
3314 	u8         cur_rnr_retry[0x3];
3315 	u8         cur_retry_count[0x3];
3316 	u8         reserved_at_39b[0x5];
3317 
3318 	u8         reserved_at_3a0[0x20];
3319 
3320 	u8         reserved_at_3c0[0x8];
3321 	u8         next_send_psn[0x18];
3322 
3323 	u8         reserved_at_3e0[0x3];
3324 	u8	   log_num_dci_stream_channels[0x5];
3325 	u8         cqn_snd[0x18];
3326 
3327 	u8         reserved_at_400[0x3];
3328 	u8	   log_num_dci_errored_streams[0x5];
3329 	u8         deth_sqpn[0x18];
3330 
3331 	u8         reserved_at_420[0x20];
3332 
3333 	u8         reserved_at_440[0x8];
3334 	u8         last_acked_psn[0x18];
3335 
3336 	u8         reserved_at_460[0x8];
3337 	u8         ssn[0x18];
3338 
3339 	u8         reserved_at_480[0x8];
3340 	u8         log_rra_max[0x3];
3341 	u8         reserved_at_48b[0x1];
3342 	u8         atomic_mode[0x4];
3343 	u8         rre[0x1];
3344 	u8         rwe[0x1];
3345 	u8         rae[0x1];
3346 	u8         reserved_at_493[0x1];
3347 	u8         page_offset[0x6];
3348 	u8         reserved_at_49a[0x3];
3349 	u8         cd_slave_receive[0x1];
3350 	u8         cd_slave_send[0x1];
3351 	u8         cd_master[0x1];
3352 
3353 	u8         reserved_at_4a0[0x3];
3354 	u8         min_rnr_nak[0x5];
3355 	u8         next_rcv_psn[0x18];
3356 
3357 	u8         reserved_at_4c0[0x8];
3358 	u8         xrcd[0x18];
3359 
3360 	u8         reserved_at_4e0[0x8];
3361 	u8         cqn_rcv[0x18];
3362 
3363 	u8         dbr_addr[0x40];
3364 
3365 	u8         q_key[0x20];
3366 
3367 	u8         reserved_at_560[0x5];
3368 	u8         rq_type[0x3];
3369 	u8         srqn_rmpn_xrqn[0x18];
3370 
3371 	u8         reserved_at_580[0x8];
3372 	u8         rmsn[0x18];
3373 
3374 	u8         hw_sq_wqebb_counter[0x10];
3375 	u8         sw_sq_wqebb_counter[0x10];
3376 
3377 	u8         hw_rq_counter[0x20];
3378 
3379 	u8         sw_rq_counter[0x20];
3380 
3381 	u8         reserved_at_600[0x20];
3382 
3383 	u8         reserved_at_620[0xf];
3384 	u8         cgs[0x1];
3385 	u8         cs_req[0x8];
3386 	u8         cs_res[0x8];
3387 
3388 	u8         dc_access_key[0x40];
3389 
3390 	u8         reserved_at_680[0x3];
3391 	u8         dbr_umem_valid[0x1];
3392 
3393 	u8         reserved_at_684[0xbc];
3394 };
3395 
3396 struct mlx5_ifc_roce_addr_layout_bits {
3397 	u8         source_l3_address[16][0x8];
3398 
3399 	u8         reserved_at_80[0x3];
3400 	u8         vlan_valid[0x1];
3401 	u8         vlan_id[0xc];
3402 	u8         source_mac_47_32[0x10];
3403 
3404 	u8         source_mac_31_0[0x20];
3405 
3406 	u8         reserved_at_c0[0x14];
3407 	u8         roce_l3_type[0x4];
3408 	u8         roce_version[0x8];
3409 
3410 	u8         reserved_at_e0[0x20];
3411 };
3412 
3413 struct mlx5_ifc_crypto_cap_bits {
3414 	u8    reserved_at_0[0x3];
3415 	u8    synchronize_dek[0x1];
3416 	u8    int_kek_manual[0x1];
3417 	u8    int_kek_auto[0x1];
3418 	u8    reserved_at_6[0x1a];
3419 
3420 	u8    reserved_at_20[0x3];
3421 	u8    log_dek_max_alloc[0x5];
3422 	u8    reserved_at_28[0x3];
3423 	u8    log_max_num_deks[0x5];
3424 	u8    reserved_at_30[0x10];
3425 
3426 	u8    reserved_at_40[0x20];
3427 
3428 	u8    reserved_at_60[0x3];
3429 	u8    log_dek_granularity[0x5];
3430 	u8    reserved_at_68[0x3];
3431 	u8    log_max_num_int_kek[0x5];
3432 	u8    sw_wrapped_dek[0x10];
3433 
3434 	u8    reserved_at_80[0x780];
3435 };
3436 
3437 union mlx5_ifc_hca_cap_union_bits {
3438 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
3439 	struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
3440 	struct mlx5_ifc_odp_cap_bits odp_cap;
3441 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
3442 	struct mlx5_ifc_roce_cap_bits roce_cap;
3443 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
3444 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
3445 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
3446 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3447 	struct mlx5_ifc_port_selection_cap_bits port_selection_cap;
3448 	struct mlx5_ifc_qos_cap_bits qos_cap;
3449 	struct mlx5_ifc_debug_cap_bits debug_cap;
3450 	struct mlx5_ifc_fpga_cap_bits fpga_cap;
3451 	struct mlx5_ifc_tls_cap_bits tls_cap;
3452 	struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
3453 	struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap;
3454 	struct mlx5_ifc_macsec_cap_bits macsec_cap;
3455 	struct mlx5_ifc_crypto_cap_bits crypto_cap;
3456 	struct mlx5_ifc_ipsec_cap_bits ipsec_cap;
3457 	u8         reserved_at_0[0x8000];
3458 };
3459 
3460 enum {
3461 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
3462 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
3463 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
3464 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
3465 	MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
3466 	MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
3467 	MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
3468 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
3469 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
3470 	MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
3471 	MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
3472 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
3473 	MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
3474 	MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
3475 };
3476 
3477 enum {
3478 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
3479 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
3480 	MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
3481 };
3482 
3483 enum {
3484 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC   = 0x0,
3485 	MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC  = 0x1,
3486 };
3487 
3488 struct mlx5_ifc_vlan_bits {
3489 	u8         ethtype[0x10];
3490 	u8         prio[0x3];
3491 	u8         cfi[0x1];
3492 	u8         vid[0xc];
3493 };
3494 
3495 enum {
3496 	MLX5_FLOW_METER_COLOR_RED	= 0x0,
3497 	MLX5_FLOW_METER_COLOR_YELLOW	= 0x1,
3498 	MLX5_FLOW_METER_COLOR_GREEN	= 0x2,
3499 	MLX5_FLOW_METER_COLOR_UNDEFINED	= 0x3,
3500 };
3501 
3502 enum {
3503 	MLX5_EXE_ASO_FLOW_METER		= 0x2,
3504 };
3505 
3506 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits {
3507 	u8        return_reg_id[0x4];
3508 	u8        aso_type[0x4];
3509 	u8        reserved_at_8[0x14];
3510 	u8        action[0x1];
3511 	u8        init_color[0x2];
3512 	u8        meter_id[0x1];
3513 };
3514 
3515 union mlx5_ifc_exe_aso_ctrl {
3516 	struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter;
3517 };
3518 
3519 struct mlx5_ifc_execute_aso_bits {
3520 	u8        valid[0x1];
3521 	u8        reserved_at_1[0x7];
3522 	u8        aso_object_id[0x18];
3523 
3524 	union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl;
3525 };
3526 
3527 struct mlx5_ifc_flow_context_bits {
3528 	struct mlx5_ifc_vlan_bits push_vlan;
3529 
3530 	u8         group_id[0x20];
3531 
3532 	u8         reserved_at_40[0x8];
3533 	u8         flow_tag[0x18];
3534 
3535 	u8         reserved_at_60[0x10];
3536 	u8         action[0x10];
3537 
3538 	u8         extended_destination[0x1];
3539 	u8         reserved_at_81[0x1];
3540 	u8         flow_source[0x2];
3541 	u8         encrypt_decrypt_type[0x4];
3542 	u8         destination_list_size[0x18];
3543 
3544 	u8         reserved_at_a0[0x8];
3545 	u8         flow_counter_list_size[0x18];
3546 
3547 	u8         packet_reformat_id[0x20];
3548 
3549 	u8         modify_header_id[0x20];
3550 
3551 	struct mlx5_ifc_vlan_bits push_vlan_2;
3552 
3553 	u8         encrypt_decrypt_obj_id[0x20];
3554 	u8         reserved_at_140[0xc0];
3555 
3556 	struct mlx5_ifc_fte_match_param_bits match_value;
3557 
3558 	struct mlx5_ifc_execute_aso_bits execute_aso[4];
3559 
3560 	u8         reserved_at_1300[0x500];
3561 
3562 	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[];
3563 };
3564 
3565 enum {
3566 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
3567 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
3568 };
3569 
3570 struct mlx5_ifc_xrc_srqc_bits {
3571 	u8         state[0x4];
3572 	u8         log_xrc_srq_size[0x4];
3573 	u8         reserved_at_8[0x18];
3574 
3575 	u8         wq_signature[0x1];
3576 	u8         cont_srq[0x1];
3577 	u8         reserved_at_22[0x1];
3578 	u8         rlky[0x1];
3579 	u8         basic_cyclic_rcv_wqe[0x1];
3580 	u8         log_rq_stride[0x3];
3581 	u8         xrcd[0x18];
3582 
3583 	u8         page_offset[0x6];
3584 	u8         reserved_at_46[0x1];
3585 	u8         dbr_umem_valid[0x1];
3586 	u8         cqn[0x18];
3587 
3588 	u8         reserved_at_60[0x20];
3589 
3590 	u8         user_index_equal_xrc_srqn[0x1];
3591 	u8         reserved_at_81[0x1];
3592 	u8         log_page_size[0x6];
3593 	u8         user_index[0x18];
3594 
3595 	u8         reserved_at_a0[0x20];
3596 
3597 	u8         reserved_at_c0[0x8];
3598 	u8         pd[0x18];
3599 
3600 	u8         lwm[0x10];
3601 	u8         wqe_cnt[0x10];
3602 
3603 	u8         reserved_at_100[0x40];
3604 
3605 	u8         db_record_addr_h[0x20];
3606 
3607 	u8         db_record_addr_l[0x1e];
3608 	u8         reserved_at_17e[0x2];
3609 
3610 	u8         reserved_at_180[0x80];
3611 };
3612 
3613 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3614 	u8         counter_error_queues[0x20];
3615 
3616 	u8         total_error_queues[0x20];
3617 
3618 	u8         send_queue_priority_update_flow[0x20];
3619 
3620 	u8         reserved_at_60[0x20];
3621 
3622 	u8         nic_receive_steering_discard[0x40];
3623 
3624 	u8         receive_discard_vport_down[0x40];
3625 
3626 	u8         transmit_discard_vport_down[0x40];
3627 
3628 	u8         async_eq_overrun[0x20];
3629 
3630 	u8         comp_eq_overrun[0x20];
3631 
3632 	u8         reserved_at_180[0x20];
3633 
3634 	u8         invalid_command[0x20];
3635 
3636 	u8         quota_exceeded_command[0x20];
3637 
3638 	u8         internal_rq_out_of_buffer[0x20];
3639 
3640 	u8         cq_overrun[0x20];
3641 
3642 	u8         eth_wqe_too_small[0x20];
3643 
3644 	u8         reserved_at_220[0xc0];
3645 
3646 	u8         generated_pkt_steering_fail[0x40];
3647 
3648 	u8         handled_pkt_steering_fail[0x40];
3649 
3650 	u8         reserved_at_360[0xc80];
3651 };
3652 
3653 struct mlx5_ifc_traffic_counter_bits {
3654 	u8         packets[0x40];
3655 
3656 	u8         octets[0x40];
3657 };
3658 
3659 struct mlx5_ifc_tisc_bits {
3660 	u8         strict_lag_tx_port_affinity[0x1];
3661 	u8         tls_en[0x1];
3662 	u8         reserved_at_2[0x2];
3663 	u8         lag_tx_port_affinity[0x04];
3664 
3665 	u8         reserved_at_8[0x4];
3666 	u8         prio[0x4];
3667 	u8         reserved_at_10[0x10];
3668 
3669 	u8         reserved_at_20[0x100];
3670 
3671 	u8         reserved_at_120[0x8];
3672 	u8         transport_domain[0x18];
3673 
3674 	u8         reserved_at_140[0x8];
3675 	u8         underlay_qpn[0x18];
3676 
3677 	u8         reserved_at_160[0x8];
3678 	u8         pd[0x18];
3679 
3680 	u8         reserved_at_180[0x380];
3681 };
3682 
3683 enum {
3684 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
3685 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
3686 };
3687 
3688 enum {
3689 	MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO  = BIT(0),
3690 	MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO  = BIT(1),
3691 };
3692 
3693 enum {
3694 	MLX5_RX_HASH_FN_NONE           = 0x0,
3695 	MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
3696 	MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
3697 };
3698 
3699 enum {
3700 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
3701 	MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
3702 };
3703 
3704 struct mlx5_ifc_tirc_bits {
3705 	u8         reserved_at_0[0x20];
3706 
3707 	u8         disp_type[0x4];
3708 	u8         tls_en[0x1];
3709 	u8         reserved_at_25[0x1b];
3710 
3711 	u8         reserved_at_40[0x40];
3712 
3713 	u8         reserved_at_80[0x4];
3714 	u8         lro_timeout_period_usecs[0x10];
3715 	u8         packet_merge_mask[0x4];
3716 	u8         lro_max_ip_payload_size[0x8];
3717 
3718 	u8         reserved_at_a0[0x40];
3719 
3720 	u8         reserved_at_e0[0x8];
3721 	u8         inline_rqn[0x18];
3722 
3723 	u8         rx_hash_symmetric[0x1];
3724 	u8         reserved_at_101[0x1];
3725 	u8         tunneled_offload_en[0x1];
3726 	u8         reserved_at_103[0x5];
3727 	u8         indirect_table[0x18];
3728 
3729 	u8         rx_hash_fn[0x4];
3730 	u8         reserved_at_124[0x2];
3731 	u8         self_lb_block[0x2];
3732 	u8         transport_domain[0x18];
3733 
3734 	u8         rx_hash_toeplitz_key[10][0x20];
3735 
3736 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3737 
3738 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3739 
3740 	u8         reserved_at_2c0[0x4c0];
3741 };
3742 
3743 enum {
3744 	MLX5_SRQC_STATE_GOOD   = 0x0,
3745 	MLX5_SRQC_STATE_ERROR  = 0x1,
3746 };
3747 
3748 struct mlx5_ifc_srqc_bits {
3749 	u8         state[0x4];
3750 	u8         log_srq_size[0x4];
3751 	u8         reserved_at_8[0x18];
3752 
3753 	u8         wq_signature[0x1];
3754 	u8         cont_srq[0x1];
3755 	u8         reserved_at_22[0x1];
3756 	u8         rlky[0x1];
3757 	u8         reserved_at_24[0x1];
3758 	u8         log_rq_stride[0x3];
3759 	u8         xrcd[0x18];
3760 
3761 	u8         page_offset[0x6];
3762 	u8         reserved_at_46[0x2];
3763 	u8         cqn[0x18];
3764 
3765 	u8         reserved_at_60[0x20];
3766 
3767 	u8         reserved_at_80[0x2];
3768 	u8         log_page_size[0x6];
3769 	u8         reserved_at_88[0x18];
3770 
3771 	u8         reserved_at_a0[0x20];
3772 
3773 	u8         reserved_at_c0[0x8];
3774 	u8         pd[0x18];
3775 
3776 	u8         lwm[0x10];
3777 	u8         wqe_cnt[0x10];
3778 
3779 	u8         reserved_at_100[0x40];
3780 
3781 	u8         dbr_addr[0x40];
3782 
3783 	u8         reserved_at_180[0x80];
3784 };
3785 
3786 enum {
3787 	MLX5_SQC_STATE_RST  = 0x0,
3788 	MLX5_SQC_STATE_RDY  = 0x1,
3789 	MLX5_SQC_STATE_ERR  = 0x3,
3790 };
3791 
3792 struct mlx5_ifc_sqc_bits {
3793 	u8         rlky[0x1];
3794 	u8         cd_master[0x1];
3795 	u8         fre[0x1];
3796 	u8         flush_in_error_en[0x1];
3797 	u8         allow_multi_pkt_send_wqe[0x1];
3798 	u8	   min_wqe_inline_mode[0x3];
3799 	u8         state[0x4];
3800 	u8         reg_umr[0x1];
3801 	u8         allow_swp[0x1];
3802 	u8         hairpin[0x1];
3803 	u8         reserved_at_f[0xb];
3804 	u8	   ts_format[0x2];
3805 	u8	   reserved_at_1c[0x4];
3806 
3807 	u8         reserved_at_20[0x8];
3808 	u8         user_index[0x18];
3809 
3810 	u8         reserved_at_40[0x8];
3811 	u8         cqn[0x18];
3812 
3813 	u8         reserved_at_60[0x8];
3814 	u8         hairpin_peer_rq[0x18];
3815 
3816 	u8         reserved_at_80[0x10];
3817 	u8         hairpin_peer_vhca[0x10];
3818 
3819 	u8         reserved_at_a0[0x20];
3820 
3821 	u8         reserved_at_c0[0x8];
3822 	u8         ts_cqe_to_dest_cqn[0x18];
3823 
3824 	u8         reserved_at_e0[0x10];
3825 	u8         packet_pacing_rate_limit_index[0x10];
3826 	u8         tis_lst_sz[0x10];
3827 	u8         qos_queue_group_id[0x10];
3828 
3829 	u8         reserved_at_120[0x40];
3830 
3831 	u8         reserved_at_160[0x8];
3832 	u8         tis_num_0[0x18];
3833 
3834 	struct mlx5_ifc_wq_bits wq;
3835 };
3836 
3837 enum {
3838 	SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3839 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3840 	SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3841 	SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3842 	SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4,
3843 };
3844 
3845 enum {
3846 	ELEMENT_TYPE_CAP_MASK_TASR		= 1 << 0,
3847 	ELEMENT_TYPE_CAP_MASK_VPORT		= 1 << 1,
3848 	ELEMENT_TYPE_CAP_MASK_VPORT_TC		= 1 << 2,
3849 	ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC	= 1 << 3,
3850 };
3851 
3852 struct mlx5_ifc_scheduling_context_bits {
3853 	u8         element_type[0x8];
3854 	u8         reserved_at_8[0x18];
3855 
3856 	u8         element_attributes[0x20];
3857 
3858 	u8         parent_element_id[0x20];
3859 
3860 	u8         reserved_at_60[0x40];
3861 
3862 	u8         bw_share[0x20];
3863 
3864 	u8         max_average_bw[0x20];
3865 
3866 	u8         reserved_at_e0[0x120];
3867 };
3868 
3869 struct mlx5_ifc_rqtc_bits {
3870 	u8    reserved_at_0[0xa0];
3871 
3872 	u8    reserved_at_a0[0x5];
3873 	u8    list_q_type[0x3];
3874 	u8    reserved_at_a8[0x8];
3875 	u8    rqt_max_size[0x10];
3876 
3877 	u8    rq_vhca_id_format[0x1];
3878 	u8    reserved_at_c1[0xf];
3879 	u8    rqt_actual_size[0x10];
3880 
3881 	u8    reserved_at_e0[0x6a0];
3882 
3883 	struct mlx5_ifc_rq_num_bits rq_num[];
3884 };
3885 
3886 enum {
3887 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3888 	MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3889 };
3890 
3891 enum {
3892 	MLX5_RQC_STATE_RST  = 0x0,
3893 	MLX5_RQC_STATE_RDY  = 0x1,
3894 	MLX5_RQC_STATE_ERR  = 0x3,
3895 };
3896 
3897 enum {
3898 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE    = 0x0,
3899 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE  = 0x1,
3900 	MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE    = 0x2,
3901 };
3902 
3903 enum {
3904 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH    = 0x0,
3905 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED    = 0x1,
3906 	MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE  = 0x2,
3907 };
3908 
3909 struct mlx5_ifc_rqc_bits {
3910 	u8         rlky[0x1];
3911 	u8	   delay_drop_en[0x1];
3912 	u8         scatter_fcs[0x1];
3913 	u8         vsd[0x1];
3914 	u8         mem_rq_type[0x4];
3915 	u8         state[0x4];
3916 	u8         reserved_at_c[0x1];
3917 	u8         flush_in_error_en[0x1];
3918 	u8         hairpin[0x1];
3919 	u8         reserved_at_f[0xb];
3920 	u8	   ts_format[0x2];
3921 	u8	   reserved_at_1c[0x4];
3922 
3923 	u8         reserved_at_20[0x8];
3924 	u8         user_index[0x18];
3925 
3926 	u8         reserved_at_40[0x8];
3927 	u8         cqn[0x18];
3928 
3929 	u8         counter_set_id[0x8];
3930 	u8         reserved_at_68[0x18];
3931 
3932 	u8         reserved_at_80[0x8];
3933 	u8         rmpn[0x18];
3934 
3935 	u8         reserved_at_a0[0x8];
3936 	u8         hairpin_peer_sq[0x18];
3937 
3938 	u8         reserved_at_c0[0x10];
3939 	u8         hairpin_peer_vhca[0x10];
3940 
3941 	u8         reserved_at_e0[0x46];
3942 	u8         shampo_no_match_alignment_granularity[0x2];
3943 	u8         reserved_at_128[0x6];
3944 	u8         shampo_match_criteria_type[0x2];
3945 	u8         reservation_timeout[0x10];
3946 
3947 	u8         reserved_at_140[0x40];
3948 
3949 	struct mlx5_ifc_wq_bits wq;
3950 };
3951 
3952 enum {
3953 	MLX5_RMPC_STATE_RDY  = 0x1,
3954 	MLX5_RMPC_STATE_ERR  = 0x3,
3955 };
3956 
3957 struct mlx5_ifc_rmpc_bits {
3958 	u8         reserved_at_0[0x8];
3959 	u8         state[0x4];
3960 	u8         reserved_at_c[0x14];
3961 
3962 	u8         basic_cyclic_rcv_wqe[0x1];
3963 	u8         reserved_at_21[0x1f];
3964 
3965 	u8         reserved_at_40[0x140];
3966 
3967 	struct mlx5_ifc_wq_bits wq;
3968 };
3969 
3970 enum {
3971 	VHCA_ID_TYPE_HW = 0,
3972 	VHCA_ID_TYPE_SW = 1,
3973 };
3974 
3975 struct mlx5_ifc_nic_vport_context_bits {
3976 	u8         reserved_at_0[0x5];
3977 	u8         min_wqe_inline_mode[0x3];
3978 	u8         reserved_at_8[0x15];
3979 	u8         disable_mc_local_lb[0x1];
3980 	u8         disable_uc_local_lb[0x1];
3981 	u8         roce_en[0x1];
3982 
3983 	u8         arm_change_event[0x1];
3984 	u8         reserved_at_21[0x1a];
3985 	u8         event_on_mtu[0x1];
3986 	u8         event_on_promisc_change[0x1];
3987 	u8         event_on_vlan_change[0x1];
3988 	u8         event_on_mc_address_change[0x1];
3989 	u8         event_on_uc_address_change[0x1];
3990 
3991 	u8         vhca_id_type[0x1];
3992 	u8         reserved_at_41[0xb];
3993 	u8	   affiliation_criteria[0x4];
3994 	u8	   affiliated_vhca_id[0x10];
3995 
3996 	u8	   reserved_at_60[0xd0];
3997 
3998 	u8         mtu[0x10];
3999 
4000 	u8         system_image_guid[0x40];
4001 	u8         port_guid[0x40];
4002 	u8         node_guid[0x40];
4003 
4004 	u8         reserved_at_200[0x140];
4005 	u8         qkey_violation_counter[0x10];
4006 	u8         reserved_at_350[0x430];
4007 
4008 	u8         promisc_uc[0x1];
4009 	u8         promisc_mc[0x1];
4010 	u8         promisc_all[0x1];
4011 	u8         reserved_at_783[0x2];
4012 	u8         allowed_list_type[0x3];
4013 	u8         reserved_at_788[0xc];
4014 	u8         allowed_list_size[0xc];
4015 
4016 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
4017 
4018 	u8         reserved_at_7e0[0x20];
4019 
4020 	u8         current_uc_mac_address[][0x40];
4021 };
4022 
4023 enum {
4024 	MLX5_MKC_ACCESS_MODE_PA    = 0x0,
4025 	MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
4026 	MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
4027 	MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
4028 	MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
4029 	MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
4030 };
4031 
4032 struct mlx5_ifc_mkc_bits {
4033 	u8         reserved_at_0[0x1];
4034 	u8         free[0x1];
4035 	u8         reserved_at_2[0x1];
4036 	u8         access_mode_4_2[0x3];
4037 	u8         reserved_at_6[0x7];
4038 	u8         relaxed_ordering_write[0x1];
4039 	u8         reserved_at_e[0x1];
4040 	u8         small_fence_on_rdma_read_response[0x1];
4041 	u8         umr_en[0x1];
4042 	u8         a[0x1];
4043 	u8         rw[0x1];
4044 	u8         rr[0x1];
4045 	u8         lw[0x1];
4046 	u8         lr[0x1];
4047 	u8         access_mode_1_0[0x2];
4048 	u8         reserved_at_18[0x2];
4049 	u8         ma_translation_mode[0x2];
4050 	u8         reserved_at_1c[0x4];
4051 
4052 	u8         qpn[0x18];
4053 	u8         mkey_7_0[0x8];
4054 
4055 	u8         reserved_at_40[0x20];
4056 
4057 	u8         length64[0x1];
4058 	u8         bsf_en[0x1];
4059 	u8         sync_umr[0x1];
4060 	u8         reserved_at_63[0x2];
4061 	u8         expected_sigerr_count[0x1];
4062 	u8         reserved_at_66[0x1];
4063 	u8         en_rinval[0x1];
4064 	u8         pd[0x18];
4065 
4066 	u8         start_addr[0x40];
4067 
4068 	u8         len[0x40];
4069 
4070 	u8         bsf_octword_size[0x20];
4071 
4072 	u8         reserved_at_120[0x80];
4073 
4074 	u8         translations_octword_size[0x20];
4075 
4076 	u8         reserved_at_1c0[0x19];
4077 	u8         relaxed_ordering_read[0x1];
4078 	u8         reserved_at_1d9[0x1];
4079 	u8         log_page_size[0x5];
4080 
4081 	u8         reserved_at_1e0[0x20];
4082 };
4083 
4084 struct mlx5_ifc_pkey_bits {
4085 	u8         reserved_at_0[0x10];
4086 	u8         pkey[0x10];
4087 };
4088 
4089 struct mlx5_ifc_array128_auto_bits {
4090 	u8         array128_auto[16][0x8];
4091 };
4092 
4093 struct mlx5_ifc_hca_vport_context_bits {
4094 	u8         field_select[0x20];
4095 
4096 	u8         reserved_at_20[0xe0];
4097 
4098 	u8         sm_virt_aware[0x1];
4099 	u8         has_smi[0x1];
4100 	u8         has_raw[0x1];
4101 	u8         grh_required[0x1];
4102 	u8         reserved_at_104[0xc];
4103 	u8         port_physical_state[0x4];
4104 	u8         vport_state_policy[0x4];
4105 	u8         port_state[0x4];
4106 	u8         vport_state[0x4];
4107 
4108 	u8         reserved_at_120[0x20];
4109 
4110 	u8         system_image_guid[0x40];
4111 
4112 	u8         port_guid[0x40];
4113 
4114 	u8         node_guid[0x40];
4115 
4116 	u8         cap_mask1[0x20];
4117 
4118 	u8         cap_mask1_field_select[0x20];
4119 
4120 	u8         cap_mask2[0x20];
4121 
4122 	u8         cap_mask2_field_select[0x20];
4123 
4124 	u8         reserved_at_280[0x80];
4125 
4126 	u8         lid[0x10];
4127 	u8         reserved_at_310[0x4];
4128 	u8         init_type_reply[0x4];
4129 	u8         lmc[0x3];
4130 	u8         subnet_timeout[0x5];
4131 
4132 	u8         sm_lid[0x10];
4133 	u8         sm_sl[0x4];
4134 	u8         reserved_at_334[0xc];
4135 
4136 	u8         qkey_violation_counter[0x10];
4137 	u8         pkey_violation_counter[0x10];
4138 
4139 	u8         reserved_at_360[0xca0];
4140 };
4141 
4142 struct mlx5_ifc_esw_vport_context_bits {
4143 	u8         fdb_to_vport_reg_c[0x1];
4144 	u8         reserved_at_1[0x2];
4145 	u8         vport_svlan_strip[0x1];
4146 	u8         vport_cvlan_strip[0x1];
4147 	u8         vport_svlan_insert[0x1];
4148 	u8         vport_cvlan_insert[0x2];
4149 	u8         fdb_to_vport_reg_c_id[0x8];
4150 	u8         reserved_at_10[0x10];
4151 
4152 	u8         reserved_at_20[0x20];
4153 
4154 	u8         svlan_cfi[0x1];
4155 	u8         svlan_pcp[0x3];
4156 	u8         svlan_id[0xc];
4157 	u8         cvlan_cfi[0x1];
4158 	u8         cvlan_pcp[0x3];
4159 	u8         cvlan_id[0xc];
4160 
4161 	u8         reserved_at_60[0x720];
4162 
4163 	u8         sw_steering_vport_icm_address_rx[0x40];
4164 
4165 	u8         sw_steering_vport_icm_address_tx[0x40];
4166 };
4167 
4168 enum {
4169 	MLX5_EQC_STATUS_OK                = 0x0,
4170 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
4171 };
4172 
4173 enum {
4174 	MLX5_EQC_ST_ARMED  = 0x9,
4175 	MLX5_EQC_ST_FIRED  = 0xa,
4176 };
4177 
4178 struct mlx5_ifc_eqc_bits {
4179 	u8         status[0x4];
4180 	u8         reserved_at_4[0x9];
4181 	u8         ec[0x1];
4182 	u8         oi[0x1];
4183 	u8         reserved_at_f[0x5];
4184 	u8         st[0x4];
4185 	u8         reserved_at_18[0x8];
4186 
4187 	u8         reserved_at_20[0x20];
4188 
4189 	u8         reserved_at_40[0x14];
4190 	u8         page_offset[0x6];
4191 	u8         reserved_at_5a[0x6];
4192 
4193 	u8         reserved_at_60[0x3];
4194 	u8         log_eq_size[0x5];
4195 	u8         uar_page[0x18];
4196 
4197 	u8         reserved_at_80[0x20];
4198 
4199 	u8         reserved_at_a0[0x14];
4200 	u8         intr[0xc];
4201 
4202 	u8         reserved_at_c0[0x3];
4203 	u8         log_page_size[0x5];
4204 	u8         reserved_at_c8[0x18];
4205 
4206 	u8         reserved_at_e0[0x60];
4207 
4208 	u8         reserved_at_140[0x8];
4209 	u8         consumer_counter[0x18];
4210 
4211 	u8         reserved_at_160[0x8];
4212 	u8         producer_counter[0x18];
4213 
4214 	u8         reserved_at_180[0x80];
4215 };
4216 
4217 enum {
4218 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
4219 	MLX5_DCTC_STATE_DRAINING  = 0x1,
4220 	MLX5_DCTC_STATE_DRAINED   = 0x2,
4221 };
4222 
4223 enum {
4224 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
4225 	MLX5_DCTC_CS_RES_NA         = 0x1,
4226 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
4227 };
4228 
4229 enum {
4230 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
4231 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
4232 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
4233 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
4234 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
4235 };
4236 
4237 struct mlx5_ifc_dctc_bits {
4238 	u8         reserved_at_0[0x4];
4239 	u8         state[0x4];
4240 	u8         reserved_at_8[0x18];
4241 
4242 	u8         reserved_at_20[0x8];
4243 	u8         user_index[0x18];
4244 
4245 	u8         reserved_at_40[0x8];
4246 	u8         cqn[0x18];
4247 
4248 	u8         counter_set_id[0x8];
4249 	u8         atomic_mode[0x4];
4250 	u8         rre[0x1];
4251 	u8         rwe[0x1];
4252 	u8         rae[0x1];
4253 	u8         atomic_like_write_en[0x1];
4254 	u8         latency_sensitive[0x1];
4255 	u8         rlky[0x1];
4256 	u8         free_ar[0x1];
4257 	u8         reserved_at_73[0xd];
4258 
4259 	u8         reserved_at_80[0x8];
4260 	u8         cs_res[0x8];
4261 	u8         reserved_at_90[0x3];
4262 	u8         min_rnr_nak[0x5];
4263 	u8         reserved_at_98[0x8];
4264 
4265 	u8         reserved_at_a0[0x8];
4266 	u8         srqn_xrqn[0x18];
4267 
4268 	u8         reserved_at_c0[0x8];
4269 	u8         pd[0x18];
4270 
4271 	u8         tclass[0x8];
4272 	u8         reserved_at_e8[0x4];
4273 	u8         flow_label[0x14];
4274 
4275 	u8         dc_access_key[0x40];
4276 
4277 	u8         reserved_at_140[0x5];
4278 	u8         mtu[0x3];
4279 	u8         port[0x8];
4280 	u8         pkey_index[0x10];
4281 
4282 	u8         reserved_at_160[0x8];
4283 	u8         my_addr_index[0x8];
4284 	u8         reserved_at_170[0x8];
4285 	u8         hop_limit[0x8];
4286 
4287 	u8         dc_access_key_violation_count[0x20];
4288 
4289 	u8         reserved_at_1a0[0x14];
4290 	u8         dei_cfi[0x1];
4291 	u8         eth_prio[0x3];
4292 	u8         ecn[0x2];
4293 	u8         dscp[0x6];
4294 
4295 	u8         reserved_at_1c0[0x20];
4296 	u8         ece[0x20];
4297 };
4298 
4299 enum {
4300 	MLX5_CQC_STATUS_OK             = 0x0,
4301 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
4302 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
4303 };
4304 
4305 enum {
4306 	MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
4307 	MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
4308 };
4309 
4310 enum {
4311 	MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
4312 	MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
4313 	MLX5_CQC_ST_FIRED                                 = 0xa,
4314 };
4315 
4316 enum {
4317 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
4318 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
4319 	MLX5_CQ_PERIOD_NUM_MODES
4320 };
4321 
4322 struct mlx5_ifc_cqc_bits {
4323 	u8         status[0x4];
4324 	u8         reserved_at_4[0x2];
4325 	u8         dbr_umem_valid[0x1];
4326 	u8         apu_cq[0x1];
4327 	u8         cqe_sz[0x3];
4328 	u8         cc[0x1];
4329 	u8         reserved_at_c[0x1];
4330 	u8         scqe_break_moderation_en[0x1];
4331 	u8         oi[0x1];
4332 	u8         cq_period_mode[0x2];
4333 	u8         cqe_comp_en[0x1];
4334 	u8         mini_cqe_res_format[0x2];
4335 	u8         st[0x4];
4336 	u8         reserved_at_18[0x6];
4337 	u8         cqe_compression_layout[0x2];
4338 
4339 	u8         reserved_at_20[0x20];
4340 
4341 	u8         reserved_at_40[0x14];
4342 	u8         page_offset[0x6];
4343 	u8         reserved_at_5a[0x6];
4344 
4345 	u8         reserved_at_60[0x3];
4346 	u8         log_cq_size[0x5];
4347 	u8         uar_page[0x18];
4348 
4349 	u8         reserved_at_80[0x4];
4350 	u8         cq_period[0xc];
4351 	u8         cq_max_count[0x10];
4352 
4353 	u8         c_eqn_or_apu_element[0x20];
4354 
4355 	u8         reserved_at_c0[0x3];
4356 	u8         log_page_size[0x5];
4357 	u8         reserved_at_c8[0x18];
4358 
4359 	u8         reserved_at_e0[0x20];
4360 
4361 	u8         reserved_at_100[0x8];
4362 	u8         last_notified_index[0x18];
4363 
4364 	u8         reserved_at_120[0x8];
4365 	u8         last_solicit_index[0x18];
4366 
4367 	u8         reserved_at_140[0x8];
4368 	u8         consumer_counter[0x18];
4369 
4370 	u8         reserved_at_160[0x8];
4371 	u8         producer_counter[0x18];
4372 
4373 	u8         reserved_at_180[0x40];
4374 
4375 	u8         dbr_addr[0x40];
4376 };
4377 
4378 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
4379 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
4380 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
4381 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
4382 	struct mlx5_ifc_cong_control_r_roce_general_bits cong_control_r_roce_general;
4383 	u8         reserved_at_0[0x800];
4384 };
4385 
4386 struct mlx5_ifc_query_adapter_param_block_bits {
4387 	u8         reserved_at_0[0xc0];
4388 
4389 	u8         reserved_at_c0[0x8];
4390 	u8         ieee_vendor_id[0x18];
4391 
4392 	u8         reserved_at_e0[0x10];
4393 	u8         vsd_vendor_id[0x10];
4394 
4395 	u8         vsd[208][0x8];
4396 
4397 	u8         vsd_contd_psid[16][0x8];
4398 };
4399 
4400 enum {
4401 	MLX5_XRQC_STATE_GOOD   = 0x0,
4402 	MLX5_XRQC_STATE_ERROR  = 0x1,
4403 };
4404 
4405 enum {
4406 	MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
4407 	MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
4408 };
4409 
4410 enum {
4411 	MLX5_XRQC_OFFLOAD_RNDV = 0x1,
4412 };
4413 
4414 struct mlx5_ifc_tag_matching_topology_context_bits {
4415 	u8         log_matching_list_sz[0x4];
4416 	u8         reserved_at_4[0xc];
4417 	u8         append_next_index[0x10];
4418 
4419 	u8         sw_phase_cnt[0x10];
4420 	u8         hw_phase_cnt[0x10];
4421 
4422 	u8         reserved_at_40[0x40];
4423 };
4424 
4425 struct mlx5_ifc_xrqc_bits {
4426 	u8         state[0x4];
4427 	u8         rlkey[0x1];
4428 	u8         reserved_at_5[0xf];
4429 	u8         topology[0x4];
4430 	u8         reserved_at_18[0x4];
4431 	u8         offload[0x4];
4432 
4433 	u8         reserved_at_20[0x8];
4434 	u8         user_index[0x18];
4435 
4436 	u8         reserved_at_40[0x8];
4437 	u8         cqn[0x18];
4438 
4439 	u8         reserved_at_60[0xa0];
4440 
4441 	struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
4442 
4443 	u8         reserved_at_180[0x280];
4444 
4445 	struct mlx5_ifc_wq_bits wq;
4446 };
4447 
4448 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
4449 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
4450 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
4451 	u8         reserved_at_0[0x20];
4452 };
4453 
4454 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
4455 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
4456 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
4457 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
4458 	u8         reserved_at_0[0x20];
4459 };
4460 
4461 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
4462 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
4463 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
4464 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
4465 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
4466 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
4467 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
4468 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
4469 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
4470 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
4471 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
4472 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
4473 	u8         reserved_at_0[0x7c0];
4474 };
4475 
4476 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
4477 	struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
4478 	u8         reserved_at_0[0x7c0];
4479 };
4480 
4481 union mlx5_ifc_event_auto_bits {
4482 	struct mlx5_ifc_comp_event_bits comp_event;
4483 	struct mlx5_ifc_dct_events_bits dct_events;
4484 	struct mlx5_ifc_qp_events_bits qp_events;
4485 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
4486 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
4487 	struct mlx5_ifc_cq_error_bits cq_error;
4488 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
4489 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
4490 	struct mlx5_ifc_gpio_event_bits gpio_event;
4491 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
4492 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
4493 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
4494 	u8         reserved_at_0[0xe0];
4495 };
4496 
4497 struct mlx5_ifc_health_buffer_bits {
4498 	u8         reserved_at_0[0x100];
4499 
4500 	u8         assert_existptr[0x20];
4501 
4502 	u8         assert_callra[0x20];
4503 
4504 	u8         reserved_at_140[0x20];
4505 
4506 	u8         time[0x20];
4507 
4508 	u8         fw_version[0x20];
4509 
4510 	u8         hw_id[0x20];
4511 
4512 	u8         rfr[0x1];
4513 	u8         reserved_at_1c1[0x3];
4514 	u8         valid[0x1];
4515 	u8         severity[0x3];
4516 	u8         reserved_at_1c8[0x18];
4517 
4518 	u8         irisc_index[0x8];
4519 	u8         synd[0x8];
4520 	u8         ext_synd[0x10];
4521 };
4522 
4523 struct mlx5_ifc_register_loopback_control_bits {
4524 	u8         no_lb[0x1];
4525 	u8         reserved_at_1[0x7];
4526 	u8         port[0x8];
4527 	u8         reserved_at_10[0x10];
4528 
4529 	u8         reserved_at_20[0x60];
4530 };
4531 
4532 struct mlx5_ifc_vport_tc_element_bits {
4533 	u8         traffic_class[0x4];
4534 	u8         reserved_at_4[0xc];
4535 	u8         vport_number[0x10];
4536 };
4537 
4538 struct mlx5_ifc_vport_element_bits {
4539 	u8         reserved_at_0[0x10];
4540 	u8         vport_number[0x10];
4541 };
4542 
4543 enum {
4544 	TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
4545 	TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
4546 	TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
4547 };
4548 
4549 struct mlx5_ifc_tsar_element_bits {
4550 	u8         reserved_at_0[0x8];
4551 	u8         tsar_type[0x8];
4552 	u8         reserved_at_10[0x10];
4553 };
4554 
4555 enum {
4556 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
4557 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
4558 };
4559 
4560 struct mlx5_ifc_teardown_hca_out_bits {
4561 	u8         status[0x8];
4562 	u8         reserved_at_8[0x18];
4563 
4564 	u8         syndrome[0x20];
4565 
4566 	u8         reserved_at_40[0x3f];
4567 
4568 	u8         state[0x1];
4569 };
4570 
4571 enum {
4572 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
4573 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
4574 	MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
4575 };
4576 
4577 struct mlx5_ifc_teardown_hca_in_bits {
4578 	u8         opcode[0x10];
4579 	u8         reserved_at_10[0x10];
4580 
4581 	u8         reserved_at_20[0x10];
4582 	u8         op_mod[0x10];
4583 
4584 	u8         reserved_at_40[0x10];
4585 	u8         profile[0x10];
4586 
4587 	u8         reserved_at_60[0x20];
4588 };
4589 
4590 struct mlx5_ifc_sqerr2rts_qp_out_bits {
4591 	u8         status[0x8];
4592 	u8         reserved_at_8[0x18];
4593 
4594 	u8         syndrome[0x20];
4595 
4596 	u8         reserved_at_40[0x40];
4597 };
4598 
4599 struct mlx5_ifc_sqerr2rts_qp_in_bits {
4600 	u8         opcode[0x10];
4601 	u8         uid[0x10];
4602 
4603 	u8         reserved_at_20[0x10];
4604 	u8         op_mod[0x10];
4605 
4606 	u8         reserved_at_40[0x8];
4607 	u8         qpn[0x18];
4608 
4609 	u8         reserved_at_60[0x20];
4610 
4611 	u8         opt_param_mask[0x20];
4612 
4613 	u8         reserved_at_a0[0x20];
4614 
4615 	struct mlx5_ifc_qpc_bits qpc;
4616 
4617 	u8         reserved_at_800[0x80];
4618 };
4619 
4620 struct mlx5_ifc_sqd2rts_qp_out_bits {
4621 	u8         status[0x8];
4622 	u8         reserved_at_8[0x18];
4623 
4624 	u8         syndrome[0x20];
4625 
4626 	u8         reserved_at_40[0x40];
4627 };
4628 
4629 struct mlx5_ifc_sqd2rts_qp_in_bits {
4630 	u8         opcode[0x10];
4631 	u8         uid[0x10];
4632 
4633 	u8         reserved_at_20[0x10];
4634 	u8         op_mod[0x10];
4635 
4636 	u8         reserved_at_40[0x8];
4637 	u8         qpn[0x18];
4638 
4639 	u8         reserved_at_60[0x20];
4640 
4641 	u8         opt_param_mask[0x20];
4642 
4643 	u8         reserved_at_a0[0x20];
4644 
4645 	struct mlx5_ifc_qpc_bits qpc;
4646 
4647 	u8         reserved_at_800[0x80];
4648 };
4649 
4650 struct mlx5_ifc_set_roce_address_out_bits {
4651 	u8         status[0x8];
4652 	u8         reserved_at_8[0x18];
4653 
4654 	u8         syndrome[0x20];
4655 
4656 	u8         reserved_at_40[0x40];
4657 };
4658 
4659 struct mlx5_ifc_set_roce_address_in_bits {
4660 	u8         opcode[0x10];
4661 	u8         reserved_at_10[0x10];
4662 
4663 	u8         reserved_at_20[0x10];
4664 	u8         op_mod[0x10];
4665 
4666 	u8         roce_address_index[0x10];
4667 	u8         reserved_at_50[0xc];
4668 	u8	   vhca_port_num[0x4];
4669 
4670 	u8         reserved_at_60[0x20];
4671 
4672 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
4673 };
4674 
4675 struct mlx5_ifc_set_mad_demux_out_bits {
4676 	u8         status[0x8];
4677 	u8         reserved_at_8[0x18];
4678 
4679 	u8         syndrome[0x20];
4680 
4681 	u8         reserved_at_40[0x40];
4682 };
4683 
4684 enum {
4685 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
4686 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
4687 };
4688 
4689 struct mlx5_ifc_set_mad_demux_in_bits {
4690 	u8         opcode[0x10];
4691 	u8         reserved_at_10[0x10];
4692 
4693 	u8         reserved_at_20[0x10];
4694 	u8         op_mod[0x10];
4695 
4696 	u8         reserved_at_40[0x20];
4697 
4698 	u8         reserved_at_60[0x6];
4699 	u8         demux_mode[0x2];
4700 	u8         reserved_at_68[0x18];
4701 };
4702 
4703 struct mlx5_ifc_set_l2_table_entry_out_bits {
4704 	u8         status[0x8];
4705 	u8         reserved_at_8[0x18];
4706 
4707 	u8         syndrome[0x20];
4708 
4709 	u8         reserved_at_40[0x40];
4710 };
4711 
4712 struct mlx5_ifc_set_l2_table_entry_in_bits {
4713 	u8         opcode[0x10];
4714 	u8         reserved_at_10[0x10];
4715 
4716 	u8         reserved_at_20[0x10];
4717 	u8         op_mod[0x10];
4718 
4719 	u8         reserved_at_40[0x60];
4720 
4721 	u8         reserved_at_a0[0x8];
4722 	u8         table_index[0x18];
4723 
4724 	u8         reserved_at_c0[0x20];
4725 
4726 	u8         reserved_at_e0[0x13];
4727 	u8         vlan_valid[0x1];
4728 	u8         vlan[0xc];
4729 
4730 	struct mlx5_ifc_mac_address_layout_bits mac_address;
4731 
4732 	u8         reserved_at_140[0xc0];
4733 };
4734 
4735 struct mlx5_ifc_set_issi_out_bits {
4736 	u8         status[0x8];
4737 	u8         reserved_at_8[0x18];
4738 
4739 	u8         syndrome[0x20];
4740 
4741 	u8         reserved_at_40[0x40];
4742 };
4743 
4744 struct mlx5_ifc_set_issi_in_bits {
4745 	u8         opcode[0x10];
4746 	u8         reserved_at_10[0x10];
4747 
4748 	u8         reserved_at_20[0x10];
4749 	u8         op_mod[0x10];
4750 
4751 	u8         reserved_at_40[0x10];
4752 	u8         current_issi[0x10];
4753 
4754 	u8         reserved_at_60[0x20];
4755 };
4756 
4757 struct mlx5_ifc_set_hca_cap_out_bits {
4758 	u8         status[0x8];
4759 	u8         reserved_at_8[0x18];
4760 
4761 	u8         syndrome[0x20];
4762 
4763 	u8         reserved_at_40[0x40];
4764 };
4765 
4766 struct mlx5_ifc_set_hca_cap_in_bits {
4767 	u8         opcode[0x10];
4768 	u8         reserved_at_10[0x10];
4769 
4770 	u8         reserved_at_20[0x10];
4771 	u8         op_mod[0x10];
4772 
4773 	u8         other_function[0x1];
4774 	u8         ec_vf_function[0x1];
4775 	u8         reserved_at_42[0xe];
4776 	u8         function_id[0x10];
4777 
4778 	u8         reserved_at_60[0x20];
4779 
4780 	union mlx5_ifc_hca_cap_union_bits capability;
4781 };
4782 
4783 enum {
4784 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
4785 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
4786 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
4787 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3,
4788 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID    = 0x4
4789 };
4790 
4791 struct mlx5_ifc_set_fte_out_bits {
4792 	u8         status[0x8];
4793 	u8         reserved_at_8[0x18];
4794 
4795 	u8         syndrome[0x20];
4796 
4797 	u8         reserved_at_40[0x40];
4798 };
4799 
4800 struct mlx5_ifc_set_fte_in_bits {
4801 	u8         opcode[0x10];
4802 	u8         reserved_at_10[0x10];
4803 
4804 	u8         reserved_at_20[0x10];
4805 	u8         op_mod[0x10];
4806 
4807 	u8         other_vport[0x1];
4808 	u8         reserved_at_41[0xf];
4809 	u8         vport_number[0x10];
4810 
4811 	u8         reserved_at_60[0x20];
4812 
4813 	u8         table_type[0x8];
4814 	u8         reserved_at_88[0x18];
4815 
4816 	u8         reserved_at_a0[0x8];
4817 	u8         table_id[0x18];
4818 
4819 	u8         ignore_flow_level[0x1];
4820 	u8         reserved_at_c1[0x17];
4821 	u8         modify_enable_mask[0x8];
4822 
4823 	u8         reserved_at_e0[0x20];
4824 
4825 	u8         flow_index[0x20];
4826 
4827 	u8         reserved_at_120[0xe0];
4828 
4829 	struct mlx5_ifc_flow_context_bits flow_context;
4830 };
4831 
4832 struct mlx5_ifc_rts2rts_qp_out_bits {
4833 	u8         status[0x8];
4834 	u8         reserved_at_8[0x18];
4835 
4836 	u8         syndrome[0x20];
4837 
4838 	u8         reserved_at_40[0x20];
4839 	u8         ece[0x20];
4840 };
4841 
4842 struct mlx5_ifc_rts2rts_qp_in_bits {
4843 	u8         opcode[0x10];
4844 	u8         uid[0x10];
4845 
4846 	u8         reserved_at_20[0x10];
4847 	u8         op_mod[0x10];
4848 
4849 	u8         reserved_at_40[0x8];
4850 	u8         qpn[0x18];
4851 
4852 	u8         reserved_at_60[0x20];
4853 
4854 	u8         opt_param_mask[0x20];
4855 
4856 	u8         ece[0x20];
4857 
4858 	struct mlx5_ifc_qpc_bits qpc;
4859 
4860 	u8         reserved_at_800[0x80];
4861 };
4862 
4863 struct mlx5_ifc_rtr2rts_qp_out_bits {
4864 	u8         status[0x8];
4865 	u8         reserved_at_8[0x18];
4866 
4867 	u8         syndrome[0x20];
4868 
4869 	u8         reserved_at_40[0x20];
4870 	u8         ece[0x20];
4871 };
4872 
4873 struct mlx5_ifc_rtr2rts_qp_in_bits {
4874 	u8         opcode[0x10];
4875 	u8         uid[0x10];
4876 
4877 	u8         reserved_at_20[0x10];
4878 	u8         op_mod[0x10];
4879 
4880 	u8         reserved_at_40[0x8];
4881 	u8         qpn[0x18];
4882 
4883 	u8         reserved_at_60[0x20];
4884 
4885 	u8         opt_param_mask[0x20];
4886 
4887 	u8         ece[0x20];
4888 
4889 	struct mlx5_ifc_qpc_bits qpc;
4890 
4891 	u8         reserved_at_800[0x80];
4892 };
4893 
4894 struct mlx5_ifc_rst2init_qp_out_bits {
4895 	u8         status[0x8];
4896 	u8         reserved_at_8[0x18];
4897 
4898 	u8         syndrome[0x20];
4899 
4900 	u8         reserved_at_40[0x20];
4901 	u8         ece[0x20];
4902 };
4903 
4904 struct mlx5_ifc_rst2init_qp_in_bits {
4905 	u8         opcode[0x10];
4906 	u8         uid[0x10];
4907 
4908 	u8         reserved_at_20[0x10];
4909 	u8         op_mod[0x10];
4910 
4911 	u8         reserved_at_40[0x8];
4912 	u8         qpn[0x18];
4913 
4914 	u8         reserved_at_60[0x20];
4915 
4916 	u8         opt_param_mask[0x20];
4917 
4918 	u8         ece[0x20];
4919 
4920 	struct mlx5_ifc_qpc_bits qpc;
4921 
4922 	u8         reserved_at_800[0x80];
4923 };
4924 
4925 struct mlx5_ifc_query_xrq_out_bits {
4926 	u8         status[0x8];
4927 	u8         reserved_at_8[0x18];
4928 
4929 	u8         syndrome[0x20];
4930 
4931 	u8         reserved_at_40[0x40];
4932 
4933 	struct mlx5_ifc_xrqc_bits xrq_context;
4934 };
4935 
4936 struct mlx5_ifc_query_xrq_in_bits {
4937 	u8         opcode[0x10];
4938 	u8         reserved_at_10[0x10];
4939 
4940 	u8         reserved_at_20[0x10];
4941 	u8         op_mod[0x10];
4942 
4943 	u8         reserved_at_40[0x8];
4944 	u8         xrqn[0x18];
4945 
4946 	u8         reserved_at_60[0x20];
4947 };
4948 
4949 struct mlx5_ifc_query_xrc_srq_out_bits {
4950 	u8         status[0x8];
4951 	u8         reserved_at_8[0x18];
4952 
4953 	u8         syndrome[0x20];
4954 
4955 	u8         reserved_at_40[0x40];
4956 
4957 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4958 
4959 	u8         reserved_at_280[0x600];
4960 
4961 	u8         pas[][0x40];
4962 };
4963 
4964 struct mlx5_ifc_query_xrc_srq_in_bits {
4965 	u8         opcode[0x10];
4966 	u8         reserved_at_10[0x10];
4967 
4968 	u8         reserved_at_20[0x10];
4969 	u8         op_mod[0x10];
4970 
4971 	u8         reserved_at_40[0x8];
4972 	u8         xrc_srqn[0x18];
4973 
4974 	u8         reserved_at_60[0x20];
4975 };
4976 
4977 enum {
4978 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4979 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4980 };
4981 
4982 struct mlx5_ifc_query_vport_state_out_bits {
4983 	u8         status[0x8];
4984 	u8         reserved_at_8[0x18];
4985 
4986 	u8         syndrome[0x20];
4987 
4988 	u8         reserved_at_40[0x20];
4989 
4990 	u8         reserved_at_60[0x18];
4991 	u8         admin_state[0x4];
4992 	u8         state[0x4];
4993 };
4994 
4995 enum {
4996 	MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4997 	MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4998 	MLX5_VPORT_STATE_OP_MOD_UPLINK      = 0x2,
4999 };
5000 
5001 struct mlx5_ifc_arm_monitor_counter_in_bits {
5002 	u8         opcode[0x10];
5003 	u8         uid[0x10];
5004 
5005 	u8         reserved_at_20[0x10];
5006 	u8         op_mod[0x10];
5007 
5008 	u8         reserved_at_40[0x20];
5009 
5010 	u8         reserved_at_60[0x20];
5011 };
5012 
5013 struct mlx5_ifc_arm_monitor_counter_out_bits {
5014 	u8         status[0x8];
5015 	u8         reserved_at_8[0x18];
5016 
5017 	u8         syndrome[0x20];
5018 
5019 	u8         reserved_at_40[0x40];
5020 };
5021 
5022 enum {
5023 	MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
5024 	MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
5025 };
5026 
5027 enum mlx5_monitor_counter_ppcnt {
5028 	MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
5029 	MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
5030 	MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
5031 	MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
5032 	MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
5033 	MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
5034 };
5035 
5036 enum {
5037 	MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
5038 };
5039 
5040 struct mlx5_ifc_monitor_counter_output_bits {
5041 	u8         reserved_at_0[0x4];
5042 	u8         type[0x4];
5043 	u8         reserved_at_8[0x8];
5044 	u8         counter[0x10];
5045 
5046 	u8         counter_group_id[0x20];
5047 };
5048 
5049 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
5050 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
5051 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
5052 					  MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
5053 
5054 struct mlx5_ifc_set_monitor_counter_in_bits {
5055 	u8         opcode[0x10];
5056 	u8         uid[0x10];
5057 
5058 	u8         reserved_at_20[0x10];
5059 	u8         op_mod[0x10];
5060 
5061 	u8         reserved_at_40[0x10];
5062 	u8         num_of_counters[0x10];
5063 
5064 	u8         reserved_at_60[0x20];
5065 
5066 	struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
5067 };
5068 
5069 struct mlx5_ifc_set_monitor_counter_out_bits {
5070 	u8         status[0x8];
5071 	u8         reserved_at_8[0x18];
5072 
5073 	u8         syndrome[0x20];
5074 
5075 	u8         reserved_at_40[0x40];
5076 };
5077 
5078 struct mlx5_ifc_query_vport_state_in_bits {
5079 	u8         opcode[0x10];
5080 	u8         reserved_at_10[0x10];
5081 
5082 	u8         reserved_at_20[0x10];
5083 	u8         op_mod[0x10];
5084 
5085 	u8         other_vport[0x1];
5086 	u8         reserved_at_41[0xf];
5087 	u8         vport_number[0x10];
5088 
5089 	u8         reserved_at_60[0x20];
5090 };
5091 
5092 struct mlx5_ifc_query_vnic_env_out_bits {
5093 	u8         status[0x8];
5094 	u8         reserved_at_8[0x18];
5095 
5096 	u8         syndrome[0x20];
5097 
5098 	u8         reserved_at_40[0x40];
5099 
5100 	struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
5101 };
5102 
5103 enum {
5104 	MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
5105 };
5106 
5107 struct mlx5_ifc_query_vnic_env_in_bits {
5108 	u8         opcode[0x10];
5109 	u8         reserved_at_10[0x10];
5110 
5111 	u8         reserved_at_20[0x10];
5112 	u8         op_mod[0x10];
5113 
5114 	u8         other_vport[0x1];
5115 	u8         reserved_at_41[0xf];
5116 	u8         vport_number[0x10];
5117 
5118 	u8         reserved_at_60[0x20];
5119 };
5120 
5121 struct mlx5_ifc_query_vport_counter_out_bits {
5122 	u8         status[0x8];
5123 	u8         reserved_at_8[0x18];
5124 
5125 	u8         syndrome[0x20];
5126 
5127 	u8         reserved_at_40[0x40];
5128 
5129 	struct mlx5_ifc_traffic_counter_bits received_errors;
5130 
5131 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
5132 
5133 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
5134 
5135 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
5136 
5137 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
5138 
5139 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
5140 
5141 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
5142 
5143 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
5144 
5145 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
5146 
5147 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
5148 
5149 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
5150 
5151 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
5152 
5153 	struct mlx5_ifc_traffic_counter_bits local_loopback;
5154 
5155 	u8         reserved_at_700[0x980];
5156 };
5157 
5158 enum {
5159 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
5160 };
5161 
5162 struct mlx5_ifc_query_vport_counter_in_bits {
5163 	u8         opcode[0x10];
5164 	u8         reserved_at_10[0x10];
5165 
5166 	u8         reserved_at_20[0x10];
5167 	u8         op_mod[0x10];
5168 
5169 	u8         other_vport[0x1];
5170 	u8         reserved_at_41[0xb];
5171 	u8	   port_num[0x4];
5172 	u8         vport_number[0x10];
5173 
5174 	u8         reserved_at_60[0x60];
5175 
5176 	u8         clear[0x1];
5177 	u8         reserved_at_c1[0x1f];
5178 
5179 	u8         reserved_at_e0[0x20];
5180 };
5181 
5182 struct mlx5_ifc_query_tis_out_bits {
5183 	u8         status[0x8];
5184 	u8         reserved_at_8[0x18];
5185 
5186 	u8         syndrome[0x20];
5187 
5188 	u8         reserved_at_40[0x40];
5189 
5190 	struct mlx5_ifc_tisc_bits tis_context;
5191 };
5192 
5193 struct mlx5_ifc_query_tis_in_bits {
5194 	u8         opcode[0x10];
5195 	u8         reserved_at_10[0x10];
5196 
5197 	u8         reserved_at_20[0x10];
5198 	u8         op_mod[0x10];
5199 
5200 	u8         reserved_at_40[0x8];
5201 	u8         tisn[0x18];
5202 
5203 	u8         reserved_at_60[0x20];
5204 };
5205 
5206 struct mlx5_ifc_query_tir_out_bits {
5207 	u8         status[0x8];
5208 	u8         reserved_at_8[0x18];
5209 
5210 	u8         syndrome[0x20];
5211 
5212 	u8         reserved_at_40[0xc0];
5213 
5214 	struct mlx5_ifc_tirc_bits tir_context;
5215 };
5216 
5217 struct mlx5_ifc_query_tir_in_bits {
5218 	u8         opcode[0x10];
5219 	u8         reserved_at_10[0x10];
5220 
5221 	u8         reserved_at_20[0x10];
5222 	u8         op_mod[0x10];
5223 
5224 	u8         reserved_at_40[0x8];
5225 	u8         tirn[0x18];
5226 
5227 	u8         reserved_at_60[0x20];
5228 };
5229 
5230 struct mlx5_ifc_query_srq_out_bits {
5231 	u8         status[0x8];
5232 	u8         reserved_at_8[0x18];
5233 
5234 	u8         syndrome[0x20];
5235 
5236 	u8         reserved_at_40[0x40];
5237 
5238 	struct mlx5_ifc_srqc_bits srq_context_entry;
5239 
5240 	u8         reserved_at_280[0x600];
5241 
5242 	u8         pas[][0x40];
5243 };
5244 
5245 struct mlx5_ifc_query_srq_in_bits {
5246 	u8         opcode[0x10];
5247 	u8         reserved_at_10[0x10];
5248 
5249 	u8         reserved_at_20[0x10];
5250 	u8         op_mod[0x10];
5251 
5252 	u8         reserved_at_40[0x8];
5253 	u8         srqn[0x18];
5254 
5255 	u8         reserved_at_60[0x20];
5256 };
5257 
5258 struct mlx5_ifc_query_sq_out_bits {
5259 	u8         status[0x8];
5260 	u8         reserved_at_8[0x18];
5261 
5262 	u8         syndrome[0x20];
5263 
5264 	u8         reserved_at_40[0xc0];
5265 
5266 	struct mlx5_ifc_sqc_bits sq_context;
5267 };
5268 
5269 struct mlx5_ifc_query_sq_in_bits {
5270 	u8         opcode[0x10];
5271 	u8         reserved_at_10[0x10];
5272 
5273 	u8         reserved_at_20[0x10];
5274 	u8         op_mod[0x10];
5275 
5276 	u8         reserved_at_40[0x8];
5277 	u8         sqn[0x18];
5278 
5279 	u8         reserved_at_60[0x20];
5280 };
5281 
5282 struct mlx5_ifc_query_special_contexts_out_bits {
5283 	u8         status[0x8];
5284 	u8         reserved_at_8[0x18];
5285 
5286 	u8         syndrome[0x20];
5287 
5288 	u8         dump_fill_mkey[0x20];
5289 
5290 	u8         resd_lkey[0x20];
5291 
5292 	u8         null_mkey[0x20];
5293 
5294 	u8	   terminate_scatter_list_mkey[0x20];
5295 
5296 	u8	   repeated_mkey[0x20];
5297 
5298 	u8         reserved_at_a0[0x20];
5299 };
5300 
5301 struct mlx5_ifc_query_special_contexts_in_bits {
5302 	u8         opcode[0x10];
5303 	u8         reserved_at_10[0x10];
5304 
5305 	u8         reserved_at_20[0x10];
5306 	u8         op_mod[0x10];
5307 
5308 	u8         reserved_at_40[0x40];
5309 };
5310 
5311 struct mlx5_ifc_query_scheduling_element_out_bits {
5312 	u8         opcode[0x10];
5313 	u8         reserved_at_10[0x10];
5314 
5315 	u8         reserved_at_20[0x10];
5316 	u8         op_mod[0x10];
5317 
5318 	u8         reserved_at_40[0xc0];
5319 
5320 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
5321 
5322 	u8         reserved_at_300[0x100];
5323 };
5324 
5325 enum {
5326 	SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
5327 	SCHEDULING_HIERARCHY_NIC = 0x3,
5328 };
5329 
5330 struct mlx5_ifc_query_scheduling_element_in_bits {
5331 	u8         opcode[0x10];
5332 	u8         reserved_at_10[0x10];
5333 
5334 	u8         reserved_at_20[0x10];
5335 	u8         op_mod[0x10];
5336 
5337 	u8         scheduling_hierarchy[0x8];
5338 	u8         reserved_at_48[0x18];
5339 
5340 	u8         scheduling_element_id[0x20];
5341 
5342 	u8         reserved_at_80[0x180];
5343 };
5344 
5345 struct mlx5_ifc_query_rqt_out_bits {
5346 	u8         status[0x8];
5347 	u8         reserved_at_8[0x18];
5348 
5349 	u8         syndrome[0x20];
5350 
5351 	u8         reserved_at_40[0xc0];
5352 
5353 	struct mlx5_ifc_rqtc_bits rqt_context;
5354 };
5355 
5356 struct mlx5_ifc_query_rqt_in_bits {
5357 	u8         opcode[0x10];
5358 	u8         reserved_at_10[0x10];
5359 
5360 	u8         reserved_at_20[0x10];
5361 	u8         op_mod[0x10];
5362 
5363 	u8         reserved_at_40[0x8];
5364 	u8         rqtn[0x18];
5365 
5366 	u8         reserved_at_60[0x20];
5367 };
5368 
5369 struct mlx5_ifc_query_rq_out_bits {
5370 	u8         status[0x8];
5371 	u8         reserved_at_8[0x18];
5372 
5373 	u8         syndrome[0x20];
5374 
5375 	u8         reserved_at_40[0xc0];
5376 
5377 	struct mlx5_ifc_rqc_bits rq_context;
5378 };
5379 
5380 struct mlx5_ifc_query_rq_in_bits {
5381 	u8         opcode[0x10];
5382 	u8         reserved_at_10[0x10];
5383 
5384 	u8         reserved_at_20[0x10];
5385 	u8         op_mod[0x10];
5386 
5387 	u8         reserved_at_40[0x8];
5388 	u8         rqn[0x18];
5389 
5390 	u8         reserved_at_60[0x20];
5391 };
5392 
5393 struct mlx5_ifc_query_roce_address_out_bits {
5394 	u8         status[0x8];
5395 	u8         reserved_at_8[0x18];
5396 
5397 	u8         syndrome[0x20];
5398 
5399 	u8         reserved_at_40[0x40];
5400 
5401 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
5402 };
5403 
5404 struct mlx5_ifc_query_roce_address_in_bits {
5405 	u8         opcode[0x10];
5406 	u8         reserved_at_10[0x10];
5407 
5408 	u8         reserved_at_20[0x10];
5409 	u8         op_mod[0x10];
5410 
5411 	u8         roce_address_index[0x10];
5412 	u8         reserved_at_50[0xc];
5413 	u8	   vhca_port_num[0x4];
5414 
5415 	u8         reserved_at_60[0x20];
5416 };
5417 
5418 struct mlx5_ifc_query_rmp_out_bits {
5419 	u8         status[0x8];
5420 	u8         reserved_at_8[0x18];
5421 
5422 	u8         syndrome[0x20];
5423 
5424 	u8         reserved_at_40[0xc0];
5425 
5426 	struct mlx5_ifc_rmpc_bits rmp_context;
5427 };
5428 
5429 struct mlx5_ifc_query_rmp_in_bits {
5430 	u8         opcode[0x10];
5431 	u8         reserved_at_10[0x10];
5432 
5433 	u8         reserved_at_20[0x10];
5434 	u8         op_mod[0x10];
5435 
5436 	u8         reserved_at_40[0x8];
5437 	u8         rmpn[0x18];
5438 
5439 	u8         reserved_at_60[0x20];
5440 };
5441 
5442 struct mlx5_ifc_cqe_error_syndrome_bits {
5443 	u8         hw_error_syndrome[0x8];
5444 	u8         hw_syndrome_type[0x4];
5445 	u8         reserved_at_c[0x4];
5446 	u8         vendor_error_syndrome[0x8];
5447 	u8         syndrome[0x8];
5448 };
5449 
5450 struct mlx5_ifc_qp_context_extension_bits {
5451 	u8         reserved_at_0[0x60];
5452 
5453 	struct mlx5_ifc_cqe_error_syndrome_bits error_syndrome;
5454 
5455 	u8         reserved_at_80[0x580];
5456 };
5457 
5458 struct mlx5_ifc_qpc_extension_and_pas_list_in_bits {
5459 	struct mlx5_ifc_qp_context_extension_bits qpc_data_extension;
5460 
5461 	u8         pas[0][0x40];
5462 };
5463 
5464 struct mlx5_ifc_qp_pas_list_in_bits {
5465 	struct mlx5_ifc_cmd_pas_bits pas[0];
5466 };
5467 
5468 union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits {
5469 	struct mlx5_ifc_qp_pas_list_in_bits qp_pas_list;
5470 	struct mlx5_ifc_qpc_extension_and_pas_list_in_bits qpc_ext_and_pas_list;
5471 };
5472 
5473 struct mlx5_ifc_query_qp_out_bits {
5474 	u8         status[0x8];
5475 	u8         reserved_at_8[0x18];
5476 
5477 	u8         syndrome[0x20];
5478 
5479 	u8         reserved_at_40[0x40];
5480 
5481 	u8         opt_param_mask[0x20];
5482 
5483 	u8         ece[0x20];
5484 
5485 	struct mlx5_ifc_qpc_bits qpc;
5486 
5487 	u8         reserved_at_800[0x80];
5488 
5489 	union mlx5_ifc_qp_pas_or_qpc_ext_and_pas_bits qp_pas_or_qpc_ext_and_pas;
5490 };
5491 
5492 struct mlx5_ifc_query_qp_in_bits {
5493 	u8         opcode[0x10];
5494 	u8         reserved_at_10[0x10];
5495 
5496 	u8         reserved_at_20[0x10];
5497 	u8         op_mod[0x10];
5498 
5499 	u8         qpc_ext[0x1];
5500 	u8         reserved_at_41[0x7];
5501 	u8         qpn[0x18];
5502 
5503 	u8         reserved_at_60[0x20];
5504 };
5505 
5506 struct mlx5_ifc_query_q_counter_out_bits {
5507 	u8         status[0x8];
5508 	u8         reserved_at_8[0x18];
5509 
5510 	u8         syndrome[0x20];
5511 
5512 	u8         reserved_at_40[0x40];
5513 
5514 	u8         rx_write_requests[0x20];
5515 
5516 	u8         reserved_at_a0[0x20];
5517 
5518 	u8         rx_read_requests[0x20];
5519 
5520 	u8         reserved_at_e0[0x20];
5521 
5522 	u8         rx_atomic_requests[0x20];
5523 
5524 	u8         reserved_at_120[0x20];
5525 
5526 	u8         rx_dct_connect[0x20];
5527 
5528 	u8         reserved_at_160[0x20];
5529 
5530 	u8         out_of_buffer[0x20];
5531 
5532 	u8         reserved_at_1a0[0x20];
5533 
5534 	u8         out_of_sequence[0x20];
5535 
5536 	u8         reserved_at_1e0[0x20];
5537 
5538 	u8         duplicate_request[0x20];
5539 
5540 	u8         reserved_at_220[0x20];
5541 
5542 	u8         rnr_nak_retry_err[0x20];
5543 
5544 	u8         reserved_at_260[0x20];
5545 
5546 	u8         packet_seq_err[0x20];
5547 
5548 	u8         reserved_at_2a0[0x20];
5549 
5550 	u8         implied_nak_seq_err[0x20];
5551 
5552 	u8         reserved_at_2e0[0x20];
5553 
5554 	u8         local_ack_timeout_err[0x20];
5555 
5556 	u8         reserved_at_320[0xa0];
5557 
5558 	u8         resp_local_length_error[0x20];
5559 
5560 	u8         req_local_length_error[0x20];
5561 
5562 	u8         resp_local_qp_error[0x20];
5563 
5564 	u8         local_operation_error[0x20];
5565 
5566 	u8         resp_local_protection[0x20];
5567 
5568 	u8         req_local_protection[0x20];
5569 
5570 	u8         resp_cqe_error[0x20];
5571 
5572 	u8         req_cqe_error[0x20];
5573 
5574 	u8         req_mw_binding[0x20];
5575 
5576 	u8         req_bad_response[0x20];
5577 
5578 	u8         req_remote_invalid_request[0x20];
5579 
5580 	u8         resp_remote_invalid_request[0x20];
5581 
5582 	u8         req_remote_access_errors[0x20];
5583 
5584 	u8	   resp_remote_access_errors[0x20];
5585 
5586 	u8         req_remote_operation_errors[0x20];
5587 
5588 	u8         req_transport_retries_exceeded[0x20];
5589 
5590 	u8         cq_overflow[0x20];
5591 
5592 	u8         resp_cqe_flush_error[0x20];
5593 
5594 	u8         req_cqe_flush_error[0x20];
5595 
5596 	u8         reserved_at_620[0x20];
5597 
5598 	u8         roce_adp_retrans[0x20];
5599 
5600 	u8         roce_adp_retrans_to[0x20];
5601 
5602 	u8         roce_slow_restart[0x20];
5603 
5604 	u8         roce_slow_restart_cnps[0x20];
5605 
5606 	u8         roce_slow_restart_trans[0x20];
5607 
5608 	u8         reserved_at_6e0[0x120];
5609 };
5610 
5611 struct mlx5_ifc_query_q_counter_in_bits {
5612 	u8         opcode[0x10];
5613 	u8         reserved_at_10[0x10];
5614 
5615 	u8         reserved_at_20[0x10];
5616 	u8         op_mod[0x10];
5617 
5618 	u8         other_vport[0x1];
5619 	u8         reserved_at_41[0xf];
5620 	u8         vport_number[0x10];
5621 
5622 	u8         reserved_at_60[0x60];
5623 
5624 	u8         clear[0x1];
5625 	u8         aggregate[0x1];
5626 	u8         reserved_at_c2[0x1e];
5627 
5628 	u8         reserved_at_e0[0x18];
5629 	u8         counter_set_id[0x8];
5630 };
5631 
5632 struct mlx5_ifc_query_pages_out_bits {
5633 	u8         status[0x8];
5634 	u8         reserved_at_8[0x18];
5635 
5636 	u8         syndrome[0x20];
5637 
5638 	u8         embedded_cpu_function[0x1];
5639 	u8         reserved_at_41[0xf];
5640 	u8         function_id[0x10];
5641 
5642 	u8         num_pages[0x20];
5643 };
5644 
5645 enum {
5646 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
5647 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
5648 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
5649 };
5650 
5651 struct mlx5_ifc_query_pages_in_bits {
5652 	u8         opcode[0x10];
5653 	u8         reserved_at_10[0x10];
5654 
5655 	u8         reserved_at_20[0x10];
5656 	u8         op_mod[0x10];
5657 
5658 	u8         embedded_cpu_function[0x1];
5659 	u8         reserved_at_41[0xf];
5660 	u8         function_id[0x10];
5661 
5662 	u8         reserved_at_60[0x20];
5663 };
5664 
5665 struct mlx5_ifc_query_nic_vport_context_out_bits {
5666 	u8         status[0x8];
5667 	u8         reserved_at_8[0x18];
5668 
5669 	u8         syndrome[0x20];
5670 
5671 	u8         reserved_at_40[0x40];
5672 
5673 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5674 };
5675 
5676 struct mlx5_ifc_query_nic_vport_context_in_bits {
5677 	u8         opcode[0x10];
5678 	u8         reserved_at_10[0x10];
5679 
5680 	u8         reserved_at_20[0x10];
5681 	u8         op_mod[0x10];
5682 
5683 	u8         other_vport[0x1];
5684 	u8         reserved_at_41[0xf];
5685 	u8         vport_number[0x10];
5686 
5687 	u8         reserved_at_60[0x5];
5688 	u8         allowed_list_type[0x3];
5689 	u8         reserved_at_68[0x18];
5690 };
5691 
5692 struct mlx5_ifc_query_mkey_out_bits {
5693 	u8         status[0x8];
5694 	u8         reserved_at_8[0x18];
5695 
5696 	u8         syndrome[0x20];
5697 
5698 	u8         reserved_at_40[0x40];
5699 
5700 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5701 
5702 	u8         reserved_at_280[0x600];
5703 
5704 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
5705 
5706 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
5707 };
5708 
5709 struct mlx5_ifc_query_mkey_in_bits {
5710 	u8         opcode[0x10];
5711 	u8         reserved_at_10[0x10];
5712 
5713 	u8         reserved_at_20[0x10];
5714 	u8         op_mod[0x10];
5715 
5716 	u8         reserved_at_40[0x8];
5717 	u8         mkey_index[0x18];
5718 
5719 	u8         pg_access[0x1];
5720 	u8         reserved_at_61[0x1f];
5721 };
5722 
5723 struct mlx5_ifc_query_mad_demux_out_bits {
5724 	u8         status[0x8];
5725 	u8         reserved_at_8[0x18];
5726 
5727 	u8         syndrome[0x20];
5728 
5729 	u8         reserved_at_40[0x40];
5730 
5731 	u8         mad_dumux_parameters_block[0x20];
5732 };
5733 
5734 struct mlx5_ifc_query_mad_demux_in_bits {
5735 	u8         opcode[0x10];
5736 	u8         reserved_at_10[0x10];
5737 
5738 	u8         reserved_at_20[0x10];
5739 	u8         op_mod[0x10];
5740 
5741 	u8         reserved_at_40[0x40];
5742 };
5743 
5744 struct mlx5_ifc_query_l2_table_entry_out_bits {
5745 	u8         status[0x8];
5746 	u8         reserved_at_8[0x18];
5747 
5748 	u8         syndrome[0x20];
5749 
5750 	u8         reserved_at_40[0xa0];
5751 
5752 	u8         reserved_at_e0[0x13];
5753 	u8         vlan_valid[0x1];
5754 	u8         vlan[0xc];
5755 
5756 	struct mlx5_ifc_mac_address_layout_bits mac_address;
5757 
5758 	u8         reserved_at_140[0xc0];
5759 };
5760 
5761 struct mlx5_ifc_query_l2_table_entry_in_bits {
5762 	u8         opcode[0x10];
5763 	u8         reserved_at_10[0x10];
5764 
5765 	u8         reserved_at_20[0x10];
5766 	u8         op_mod[0x10];
5767 
5768 	u8         reserved_at_40[0x60];
5769 
5770 	u8         reserved_at_a0[0x8];
5771 	u8         table_index[0x18];
5772 
5773 	u8         reserved_at_c0[0x140];
5774 };
5775 
5776 struct mlx5_ifc_query_issi_out_bits {
5777 	u8         status[0x8];
5778 	u8         reserved_at_8[0x18];
5779 
5780 	u8         syndrome[0x20];
5781 
5782 	u8         reserved_at_40[0x10];
5783 	u8         current_issi[0x10];
5784 
5785 	u8         reserved_at_60[0xa0];
5786 
5787 	u8         reserved_at_100[76][0x8];
5788 	u8         supported_issi_dw0[0x20];
5789 };
5790 
5791 struct mlx5_ifc_query_issi_in_bits {
5792 	u8         opcode[0x10];
5793 	u8         reserved_at_10[0x10];
5794 
5795 	u8         reserved_at_20[0x10];
5796 	u8         op_mod[0x10];
5797 
5798 	u8         reserved_at_40[0x40];
5799 };
5800 
5801 struct mlx5_ifc_set_driver_version_out_bits {
5802 	u8         status[0x8];
5803 	u8         reserved_0[0x18];
5804 
5805 	u8         syndrome[0x20];
5806 	u8         reserved_1[0x40];
5807 };
5808 
5809 struct mlx5_ifc_set_driver_version_in_bits {
5810 	u8         opcode[0x10];
5811 	u8         reserved_0[0x10];
5812 
5813 	u8         reserved_1[0x10];
5814 	u8         op_mod[0x10];
5815 
5816 	u8         reserved_2[0x40];
5817 	u8         driver_version[64][0x8];
5818 };
5819 
5820 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5821 	u8         status[0x8];
5822 	u8         reserved_at_8[0x18];
5823 
5824 	u8         syndrome[0x20];
5825 
5826 	u8         reserved_at_40[0x40];
5827 
5828 	struct mlx5_ifc_pkey_bits pkey[];
5829 };
5830 
5831 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5832 	u8         opcode[0x10];
5833 	u8         reserved_at_10[0x10];
5834 
5835 	u8         reserved_at_20[0x10];
5836 	u8         op_mod[0x10];
5837 
5838 	u8         other_vport[0x1];
5839 	u8         reserved_at_41[0xb];
5840 	u8         port_num[0x4];
5841 	u8         vport_number[0x10];
5842 
5843 	u8         reserved_at_60[0x10];
5844 	u8         pkey_index[0x10];
5845 };
5846 
5847 enum {
5848 	MLX5_HCA_VPORT_SEL_PORT_GUID	= 1 << 0,
5849 	MLX5_HCA_VPORT_SEL_NODE_GUID	= 1 << 1,
5850 	MLX5_HCA_VPORT_SEL_STATE_POLICY	= 1 << 2,
5851 };
5852 
5853 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5854 	u8         status[0x8];
5855 	u8         reserved_at_8[0x18];
5856 
5857 	u8         syndrome[0x20];
5858 
5859 	u8         reserved_at_40[0x20];
5860 
5861 	u8         gids_num[0x10];
5862 	u8         reserved_at_70[0x10];
5863 
5864 	struct mlx5_ifc_array128_auto_bits gid[];
5865 };
5866 
5867 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5868 	u8         opcode[0x10];
5869 	u8         reserved_at_10[0x10];
5870 
5871 	u8         reserved_at_20[0x10];
5872 	u8         op_mod[0x10];
5873 
5874 	u8         other_vport[0x1];
5875 	u8         reserved_at_41[0xb];
5876 	u8         port_num[0x4];
5877 	u8         vport_number[0x10];
5878 
5879 	u8         reserved_at_60[0x10];
5880 	u8         gid_index[0x10];
5881 };
5882 
5883 struct mlx5_ifc_query_hca_vport_context_out_bits {
5884 	u8         status[0x8];
5885 	u8         reserved_at_8[0x18];
5886 
5887 	u8         syndrome[0x20];
5888 
5889 	u8         reserved_at_40[0x40];
5890 
5891 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5892 };
5893 
5894 struct mlx5_ifc_query_hca_vport_context_in_bits {
5895 	u8         opcode[0x10];
5896 	u8         reserved_at_10[0x10];
5897 
5898 	u8         reserved_at_20[0x10];
5899 	u8         op_mod[0x10];
5900 
5901 	u8         other_vport[0x1];
5902 	u8         reserved_at_41[0xb];
5903 	u8         port_num[0x4];
5904 	u8         vport_number[0x10];
5905 
5906 	u8         reserved_at_60[0x20];
5907 };
5908 
5909 struct mlx5_ifc_query_hca_cap_out_bits {
5910 	u8         status[0x8];
5911 	u8         reserved_at_8[0x18];
5912 
5913 	u8         syndrome[0x20];
5914 
5915 	u8         reserved_at_40[0x40];
5916 
5917 	union mlx5_ifc_hca_cap_union_bits capability;
5918 };
5919 
5920 struct mlx5_ifc_query_hca_cap_in_bits {
5921 	u8         opcode[0x10];
5922 	u8         reserved_at_10[0x10];
5923 
5924 	u8         reserved_at_20[0x10];
5925 	u8         op_mod[0x10];
5926 
5927 	u8         other_function[0x1];
5928 	u8         ec_vf_function[0x1];
5929 	u8         reserved_at_42[0xe];
5930 	u8         function_id[0x10];
5931 
5932 	u8         reserved_at_60[0x20];
5933 };
5934 
5935 struct mlx5_ifc_other_hca_cap_bits {
5936 	u8         roce[0x1];
5937 	u8         reserved_at_1[0x27f];
5938 };
5939 
5940 struct mlx5_ifc_query_other_hca_cap_out_bits {
5941 	u8         status[0x8];
5942 	u8         reserved_at_8[0x18];
5943 
5944 	u8         syndrome[0x20];
5945 
5946 	u8         reserved_at_40[0x40];
5947 
5948 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
5949 };
5950 
5951 struct mlx5_ifc_query_other_hca_cap_in_bits {
5952 	u8         opcode[0x10];
5953 	u8         reserved_at_10[0x10];
5954 
5955 	u8         reserved_at_20[0x10];
5956 	u8         op_mod[0x10];
5957 
5958 	u8         reserved_at_40[0x10];
5959 	u8         function_id[0x10];
5960 
5961 	u8         reserved_at_60[0x20];
5962 };
5963 
5964 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5965 	u8         status[0x8];
5966 	u8         reserved_at_8[0x18];
5967 
5968 	u8         syndrome[0x20];
5969 
5970 	u8         reserved_at_40[0x40];
5971 };
5972 
5973 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5974 	u8         opcode[0x10];
5975 	u8         reserved_at_10[0x10];
5976 
5977 	u8         reserved_at_20[0x10];
5978 	u8         op_mod[0x10];
5979 
5980 	u8         reserved_at_40[0x10];
5981 	u8         function_id[0x10];
5982 	u8         field_select[0x20];
5983 
5984 	struct     mlx5_ifc_other_hca_cap_bits other_capability;
5985 };
5986 
5987 struct mlx5_ifc_flow_table_context_bits {
5988 	u8         reformat_en[0x1];
5989 	u8         decap_en[0x1];
5990 	u8         sw_owner[0x1];
5991 	u8         termination_table[0x1];
5992 	u8         table_miss_action[0x4];
5993 	u8         level[0x8];
5994 	u8         reserved_at_10[0x8];
5995 	u8         log_size[0x8];
5996 
5997 	u8         reserved_at_20[0x8];
5998 	u8         table_miss_id[0x18];
5999 
6000 	u8         reserved_at_40[0x8];
6001 	u8         lag_master_next_table_id[0x18];
6002 
6003 	u8         reserved_at_60[0x60];
6004 
6005 	u8         sw_owner_icm_root_1[0x40];
6006 
6007 	u8         sw_owner_icm_root_0[0x40];
6008 
6009 };
6010 
6011 struct mlx5_ifc_query_flow_table_out_bits {
6012 	u8         status[0x8];
6013 	u8         reserved_at_8[0x18];
6014 
6015 	u8         syndrome[0x20];
6016 
6017 	u8         reserved_at_40[0x80];
6018 
6019 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
6020 };
6021 
6022 struct mlx5_ifc_query_flow_table_in_bits {
6023 	u8         opcode[0x10];
6024 	u8         reserved_at_10[0x10];
6025 
6026 	u8         reserved_at_20[0x10];
6027 	u8         op_mod[0x10];
6028 
6029 	u8         reserved_at_40[0x40];
6030 
6031 	u8         table_type[0x8];
6032 	u8         reserved_at_88[0x18];
6033 
6034 	u8         reserved_at_a0[0x8];
6035 	u8         table_id[0x18];
6036 
6037 	u8         reserved_at_c0[0x140];
6038 };
6039 
6040 struct mlx5_ifc_query_fte_out_bits {
6041 	u8         status[0x8];
6042 	u8         reserved_at_8[0x18];
6043 
6044 	u8         syndrome[0x20];
6045 
6046 	u8         reserved_at_40[0x1c0];
6047 
6048 	struct mlx5_ifc_flow_context_bits flow_context;
6049 };
6050 
6051 struct mlx5_ifc_query_fte_in_bits {
6052 	u8         opcode[0x10];
6053 	u8         reserved_at_10[0x10];
6054 
6055 	u8         reserved_at_20[0x10];
6056 	u8         op_mod[0x10];
6057 
6058 	u8         reserved_at_40[0x40];
6059 
6060 	u8         table_type[0x8];
6061 	u8         reserved_at_88[0x18];
6062 
6063 	u8         reserved_at_a0[0x8];
6064 	u8         table_id[0x18];
6065 
6066 	u8         reserved_at_c0[0x40];
6067 
6068 	u8         flow_index[0x20];
6069 
6070 	u8         reserved_at_120[0xe0];
6071 };
6072 
6073 struct mlx5_ifc_match_definer_format_0_bits {
6074 	u8         reserved_at_0[0x100];
6075 
6076 	u8         metadata_reg_c_0[0x20];
6077 
6078 	u8         metadata_reg_c_1[0x20];
6079 
6080 	u8         outer_dmac_47_16[0x20];
6081 
6082 	u8         outer_dmac_15_0[0x10];
6083 	u8         outer_ethertype[0x10];
6084 
6085 	u8         reserved_at_180[0x1];
6086 	u8         sx_sniffer[0x1];
6087 	u8         functional_lb[0x1];
6088 	u8         outer_ip_frag[0x1];
6089 	u8         outer_qp_type[0x2];
6090 	u8         outer_encap_type[0x2];
6091 	u8         port_number[0x2];
6092 	u8         outer_l3_type[0x2];
6093 	u8         outer_l4_type[0x2];
6094 	u8         outer_first_vlan_type[0x2];
6095 	u8         outer_first_vlan_prio[0x3];
6096 	u8         outer_first_vlan_cfi[0x1];
6097 	u8         outer_first_vlan_vid[0xc];
6098 
6099 	u8         outer_l4_type_ext[0x4];
6100 	u8         reserved_at_1a4[0x2];
6101 	u8         outer_ipsec_layer[0x2];
6102 	u8         outer_l2_type[0x2];
6103 	u8         force_lb[0x1];
6104 	u8         outer_l2_ok[0x1];
6105 	u8         outer_l3_ok[0x1];
6106 	u8         outer_l4_ok[0x1];
6107 	u8         outer_second_vlan_type[0x2];
6108 	u8         outer_second_vlan_prio[0x3];
6109 	u8         outer_second_vlan_cfi[0x1];
6110 	u8         outer_second_vlan_vid[0xc];
6111 
6112 	u8         outer_smac_47_16[0x20];
6113 
6114 	u8         outer_smac_15_0[0x10];
6115 	u8         inner_ipv4_checksum_ok[0x1];
6116 	u8         inner_l4_checksum_ok[0x1];
6117 	u8         outer_ipv4_checksum_ok[0x1];
6118 	u8         outer_l4_checksum_ok[0x1];
6119 	u8         inner_l3_ok[0x1];
6120 	u8         inner_l4_ok[0x1];
6121 	u8         outer_l3_ok_duplicate[0x1];
6122 	u8         outer_l4_ok_duplicate[0x1];
6123 	u8         outer_tcp_cwr[0x1];
6124 	u8         outer_tcp_ece[0x1];
6125 	u8         outer_tcp_urg[0x1];
6126 	u8         outer_tcp_ack[0x1];
6127 	u8         outer_tcp_psh[0x1];
6128 	u8         outer_tcp_rst[0x1];
6129 	u8         outer_tcp_syn[0x1];
6130 	u8         outer_tcp_fin[0x1];
6131 };
6132 
6133 struct mlx5_ifc_match_definer_format_22_bits {
6134 	u8         reserved_at_0[0x100];
6135 
6136 	u8         outer_ip_src_addr[0x20];
6137 
6138 	u8         outer_ip_dest_addr[0x20];
6139 
6140 	u8         outer_l4_sport[0x10];
6141 	u8         outer_l4_dport[0x10];
6142 
6143 	u8         reserved_at_160[0x1];
6144 	u8         sx_sniffer[0x1];
6145 	u8         functional_lb[0x1];
6146 	u8         outer_ip_frag[0x1];
6147 	u8         outer_qp_type[0x2];
6148 	u8         outer_encap_type[0x2];
6149 	u8         port_number[0x2];
6150 	u8         outer_l3_type[0x2];
6151 	u8         outer_l4_type[0x2];
6152 	u8         outer_first_vlan_type[0x2];
6153 	u8         outer_first_vlan_prio[0x3];
6154 	u8         outer_first_vlan_cfi[0x1];
6155 	u8         outer_first_vlan_vid[0xc];
6156 
6157 	u8         metadata_reg_c_0[0x20];
6158 
6159 	u8         outer_dmac_47_16[0x20];
6160 
6161 	u8         outer_smac_47_16[0x20];
6162 
6163 	u8         outer_smac_15_0[0x10];
6164 	u8         outer_dmac_15_0[0x10];
6165 };
6166 
6167 struct mlx5_ifc_match_definer_format_23_bits {
6168 	u8         reserved_at_0[0x100];
6169 
6170 	u8         inner_ip_src_addr[0x20];
6171 
6172 	u8         inner_ip_dest_addr[0x20];
6173 
6174 	u8         inner_l4_sport[0x10];
6175 	u8         inner_l4_dport[0x10];
6176 
6177 	u8         reserved_at_160[0x1];
6178 	u8         sx_sniffer[0x1];
6179 	u8         functional_lb[0x1];
6180 	u8         inner_ip_frag[0x1];
6181 	u8         inner_qp_type[0x2];
6182 	u8         inner_encap_type[0x2];
6183 	u8         port_number[0x2];
6184 	u8         inner_l3_type[0x2];
6185 	u8         inner_l4_type[0x2];
6186 	u8         inner_first_vlan_type[0x2];
6187 	u8         inner_first_vlan_prio[0x3];
6188 	u8         inner_first_vlan_cfi[0x1];
6189 	u8         inner_first_vlan_vid[0xc];
6190 
6191 	u8         tunnel_header_0[0x20];
6192 
6193 	u8         inner_dmac_47_16[0x20];
6194 
6195 	u8         inner_smac_47_16[0x20];
6196 
6197 	u8         inner_smac_15_0[0x10];
6198 	u8         inner_dmac_15_0[0x10];
6199 };
6200 
6201 struct mlx5_ifc_match_definer_format_29_bits {
6202 	u8         reserved_at_0[0xc0];
6203 
6204 	u8         outer_ip_dest_addr[0x80];
6205 
6206 	u8         outer_ip_src_addr[0x80];
6207 
6208 	u8         outer_l4_sport[0x10];
6209 	u8         outer_l4_dport[0x10];
6210 
6211 	u8         reserved_at_1e0[0x20];
6212 };
6213 
6214 struct mlx5_ifc_match_definer_format_30_bits {
6215 	u8         reserved_at_0[0xa0];
6216 
6217 	u8         outer_ip_dest_addr[0x80];
6218 
6219 	u8         outer_ip_src_addr[0x80];
6220 
6221 	u8         outer_dmac_47_16[0x20];
6222 
6223 	u8         outer_smac_47_16[0x20];
6224 
6225 	u8         outer_smac_15_0[0x10];
6226 	u8         outer_dmac_15_0[0x10];
6227 };
6228 
6229 struct mlx5_ifc_match_definer_format_31_bits {
6230 	u8         reserved_at_0[0xc0];
6231 
6232 	u8         inner_ip_dest_addr[0x80];
6233 
6234 	u8         inner_ip_src_addr[0x80];
6235 
6236 	u8         inner_l4_sport[0x10];
6237 	u8         inner_l4_dport[0x10];
6238 
6239 	u8         reserved_at_1e0[0x20];
6240 };
6241 
6242 struct mlx5_ifc_match_definer_format_32_bits {
6243 	u8         reserved_at_0[0xa0];
6244 
6245 	u8         inner_ip_dest_addr[0x80];
6246 
6247 	u8         inner_ip_src_addr[0x80];
6248 
6249 	u8         inner_dmac_47_16[0x20];
6250 
6251 	u8         inner_smac_47_16[0x20];
6252 
6253 	u8         inner_smac_15_0[0x10];
6254 	u8         inner_dmac_15_0[0x10];
6255 };
6256 
6257 enum {
6258 	MLX5_IFC_DEFINER_FORMAT_ID_SELECT = 61,
6259 };
6260 
6261 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_UNUSED 0x0
6262 #define MLX5_IFC_DEFINER_FORMAT_OFFSET_OUTER_ETH_PKT_LEN 0x48
6263 #define MLX5_IFC_DEFINER_DW_SELECTORS_NUM 9
6264 #define MLX5_IFC_DEFINER_BYTE_SELECTORS_NUM 8
6265 
6266 struct mlx5_ifc_match_definer_match_mask_bits {
6267 	u8         reserved_at_1c0[5][0x20];
6268 	u8         match_dw_8[0x20];
6269 	u8         match_dw_7[0x20];
6270 	u8         match_dw_6[0x20];
6271 	u8         match_dw_5[0x20];
6272 	u8         match_dw_4[0x20];
6273 	u8         match_dw_3[0x20];
6274 	u8         match_dw_2[0x20];
6275 	u8         match_dw_1[0x20];
6276 	u8         match_dw_0[0x20];
6277 
6278 	u8         match_byte_7[0x8];
6279 	u8         match_byte_6[0x8];
6280 	u8         match_byte_5[0x8];
6281 	u8         match_byte_4[0x8];
6282 
6283 	u8         match_byte_3[0x8];
6284 	u8         match_byte_2[0x8];
6285 	u8         match_byte_1[0x8];
6286 	u8         match_byte_0[0x8];
6287 };
6288 
6289 struct mlx5_ifc_match_definer_bits {
6290 	u8         modify_field_select[0x40];
6291 
6292 	u8         reserved_at_40[0x40];
6293 
6294 	u8         reserved_at_80[0x10];
6295 	u8         format_id[0x10];
6296 
6297 	u8         reserved_at_a0[0x60];
6298 
6299 	u8         format_select_dw3[0x8];
6300 	u8         format_select_dw2[0x8];
6301 	u8         format_select_dw1[0x8];
6302 	u8         format_select_dw0[0x8];
6303 
6304 	u8         format_select_dw7[0x8];
6305 	u8         format_select_dw6[0x8];
6306 	u8         format_select_dw5[0x8];
6307 	u8         format_select_dw4[0x8];
6308 
6309 	u8         reserved_at_100[0x18];
6310 	u8         format_select_dw8[0x8];
6311 
6312 	u8         reserved_at_120[0x20];
6313 
6314 	u8         format_select_byte3[0x8];
6315 	u8         format_select_byte2[0x8];
6316 	u8         format_select_byte1[0x8];
6317 	u8         format_select_byte0[0x8];
6318 
6319 	u8         format_select_byte7[0x8];
6320 	u8         format_select_byte6[0x8];
6321 	u8         format_select_byte5[0x8];
6322 	u8         format_select_byte4[0x8];
6323 
6324 	u8         reserved_at_180[0x40];
6325 
6326 	union {
6327 		struct {
6328 			u8         match_mask[16][0x20];
6329 		};
6330 		struct mlx5_ifc_match_definer_match_mask_bits match_mask_format;
6331 	};
6332 };
6333 
6334 struct mlx5_ifc_general_obj_create_param_bits {
6335 	u8         alias_object[0x1];
6336 	u8         reserved_at_1[0x2];
6337 	u8         log_obj_range[0x5];
6338 	u8         reserved_at_8[0x18];
6339 };
6340 
6341 struct mlx5_ifc_general_obj_query_param_bits {
6342 	u8         alias_object[0x1];
6343 	u8         obj_offset[0x1f];
6344 };
6345 
6346 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
6347 	u8         opcode[0x10];
6348 	u8         uid[0x10];
6349 
6350 	u8         vhca_tunnel_id[0x10];
6351 	u8         obj_type[0x10];
6352 
6353 	u8         obj_id[0x20];
6354 
6355 	union {
6356 		struct mlx5_ifc_general_obj_create_param_bits create;
6357 		struct mlx5_ifc_general_obj_query_param_bits query;
6358 	} op_param;
6359 };
6360 
6361 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
6362 	u8         status[0x8];
6363 	u8         reserved_at_8[0x18];
6364 
6365 	u8         syndrome[0x20];
6366 
6367 	u8         obj_id[0x20];
6368 
6369 	u8         reserved_at_60[0x20];
6370 };
6371 
6372 struct mlx5_ifc_modify_header_arg_bits {
6373 	u8         reserved_at_0[0x80];
6374 
6375 	u8         reserved_at_80[0x8];
6376 	u8         access_pd[0x18];
6377 };
6378 
6379 struct mlx5_ifc_create_modify_header_arg_in_bits {
6380 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
6381 	struct mlx5_ifc_modify_header_arg_bits arg;
6382 };
6383 
6384 struct mlx5_ifc_create_match_definer_in_bits {
6385 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
6386 
6387 	struct mlx5_ifc_match_definer_bits obj_context;
6388 };
6389 
6390 struct mlx5_ifc_create_match_definer_out_bits {
6391 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
6392 };
6393 
6394 enum {
6395 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6396 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6397 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6398 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
6399 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
6400 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5,
6401 	MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6,
6402 };
6403 
6404 struct mlx5_ifc_query_flow_group_out_bits {
6405 	u8         status[0x8];
6406 	u8         reserved_at_8[0x18];
6407 
6408 	u8         syndrome[0x20];
6409 
6410 	u8         reserved_at_40[0xa0];
6411 
6412 	u8         start_flow_index[0x20];
6413 
6414 	u8         reserved_at_100[0x20];
6415 
6416 	u8         end_flow_index[0x20];
6417 
6418 	u8         reserved_at_140[0xa0];
6419 
6420 	u8         reserved_at_1e0[0x18];
6421 	u8         match_criteria_enable[0x8];
6422 
6423 	struct mlx5_ifc_fte_match_param_bits match_criteria;
6424 
6425 	u8         reserved_at_1200[0xe00];
6426 };
6427 
6428 struct mlx5_ifc_query_flow_group_in_bits {
6429 	u8         opcode[0x10];
6430 	u8         reserved_at_10[0x10];
6431 
6432 	u8         reserved_at_20[0x10];
6433 	u8         op_mod[0x10];
6434 
6435 	u8         reserved_at_40[0x40];
6436 
6437 	u8         table_type[0x8];
6438 	u8         reserved_at_88[0x18];
6439 
6440 	u8         reserved_at_a0[0x8];
6441 	u8         table_id[0x18];
6442 
6443 	u8         group_id[0x20];
6444 
6445 	u8         reserved_at_e0[0x120];
6446 };
6447 
6448 struct mlx5_ifc_query_flow_counter_out_bits {
6449 	u8         status[0x8];
6450 	u8         reserved_at_8[0x18];
6451 
6452 	u8         syndrome[0x20];
6453 
6454 	u8         reserved_at_40[0x40];
6455 
6456 	struct mlx5_ifc_traffic_counter_bits flow_statistics[];
6457 };
6458 
6459 struct mlx5_ifc_query_flow_counter_in_bits {
6460 	u8         opcode[0x10];
6461 	u8         reserved_at_10[0x10];
6462 
6463 	u8         reserved_at_20[0x10];
6464 	u8         op_mod[0x10];
6465 
6466 	u8         reserved_at_40[0x80];
6467 
6468 	u8         clear[0x1];
6469 	u8         reserved_at_c1[0xf];
6470 	u8         num_of_counters[0x10];
6471 
6472 	u8         flow_counter_id[0x20];
6473 };
6474 
6475 struct mlx5_ifc_query_esw_vport_context_out_bits {
6476 	u8         status[0x8];
6477 	u8         reserved_at_8[0x18];
6478 
6479 	u8         syndrome[0x20];
6480 
6481 	u8         reserved_at_40[0x40];
6482 
6483 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6484 };
6485 
6486 struct mlx5_ifc_query_esw_vport_context_in_bits {
6487 	u8         opcode[0x10];
6488 	u8         reserved_at_10[0x10];
6489 
6490 	u8         reserved_at_20[0x10];
6491 	u8         op_mod[0x10];
6492 
6493 	u8         other_vport[0x1];
6494 	u8         reserved_at_41[0xf];
6495 	u8         vport_number[0x10];
6496 
6497 	u8         reserved_at_60[0x20];
6498 };
6499 
6500 struct mlx5_ifc_modify_esw_vport_context_out_bits {
6501 	u8         status[0x8];
6502 	u8         reserved_at_8[0x18];
6503 
6504 	u8         syndrome[0x20];
6505 
6506 	u8         reserved_at_40[0x40];
6507 };
6508 
6509 struct mlx5_ifc_esw_vport_context_fields_select_bits {
6510 	u8         reserved_at_0[0x1b];
6511 	u8         fdb_to_vport_reg_c_id[0x1];
6512 	u8         vport_cvlan_insert[0x1];
6513 	u8         vport_svlan_insert[0x1];
6514 	u8         vport_cvlan_strip[0x1];
6515 	u8         vport_svlan_strip[0x1];
6516 };
6517 
6518 struct mlx5_ifc_modify_esw_vport_context_in_bits {
6519 	u8         opcode[0x10];
6520 	u8         reserved_at_10[0x10];
6521 
6522 	u8         reserved_at_20[0x10];
6523 	u8         op_mod[0x10];
6524 
6525 	u8         other_vport[0x1];
6526 	u8         reserved_at_41[0xf];
6527 	u8         vport_number[0x10];
6528 
6529 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
6530 
6531 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
6532 };
6533 
6534 struct mlx5_ifc_query_eq_out_bits {
6535 	u8         status[0x8];
6536 	u8         reserved_at_8[0x18];
6537 
6538 	u8         syndrome[0x20];
6539 
6540 	u8         reserved_at_40[0x40];
6541 
6542 	struct mlx5_ifc_eqc_bits eq_context_entry;
6543 
6544 	u8         reserved_at_280[0x40];
6545 
6546 	u8         event_bitmask[0x40];
6547 
6548 	u8         reserved_at_300[0x580];
6549 
6550 	u8         pas[][0x40];
6551 };
6552 
6553 struct mlx5_ifc_query_eq_in_bits {
6554 	u8         opcode[0x10];
6555 	u8         reserved_at_10[0x10];
6556 
6557 	u8         reserved_at_20[0x10];
6558 	u8         op_mod[0x10];
6559 
6560 	u8         reserved_at_40[0x18];
6561 	u8         eq_number[0x8];
6562 
6563 	u8         reserved_at_60[0x20];
6564 };
6565 
6566 struct mlx5_ifc_packet_reformat_context_in_bits {
6567 	u8         reformat_type[0x8];
6568 	u8         reserved_at_8[0x4];
6569 	u8         reformat_param_0[0x4];
6570 	u8         reserved_at_10[0x6];
6571 	u8         reformat_data_size[0xa];
6572 
6573 	u8         reformat_param_1[0x8];
6574 	u8         reserved_at_28[0x8];
6575 	u8         reformat_data[2][0x8];
6576 
6577 	u8         more_reformat_data[][0x8];
6578 };
6579 
6580 struct mlx5_ifc_query_packet_reformat_context_out_bits {
6581 	u8         status[0x8];
6582 	u8         reserved_at_8[0x18];
6583 
6584 	u8         syndrome[0x20];
6585 
6586 	u8         reserved_at_40[0xa0];
6587 
6588 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[];
6589 };
6590 
6591 struct mlx5_ifc_query_packet_reformat_context_in_bits {
6592 	u8         opcode[0x10];
6593 	u8         reserved_at_10[0x10];
6594 
6595 	u8         reserved_at_20[0x10];
6596 	u8         op_mod[0x10];
6597 
6598 	u8         packet_reformat_id[0x20];
6599 
6600 	u8         reserved_at_60[0xa0];
6601 };
6602 
6603 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
6604 	u8         status[0x8];
6605 	u8         reserved_at_8[0x18];
6606 
6607 	u8         syndrome[0x20];
6608 
6609 	u8         packet_reformat_id[0x20];
6610 
6611 	u8         reserved_at_60[0x20];
6612 };
6613 
6614 enum {
6615 	MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1,
6616 	MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7,
6617 	MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9,
6618 };
6619 
6620 enum mlx5_reformat_ctx_type {
6621 	MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
6622 	MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
6623 	MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
6624 	MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
6625 	MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
6626 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
6627 	MLX5_REFORMAT_TYPE_L2_TO_L3_ESP_TUNNEL = 0x6,
6628 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
6629 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
6630 	MLX5_REFORMAT_TYPE_L3_ESP_TUNNEL_TO_L2 = 0x9,
6631 	MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
6632 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
6633 	MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
6634 	MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
6635 	MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
6636 	MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
6637 	MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12,
6638 };
6639 
6640 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
6641 	u8         opcode[0x10];
6642 	u8         reserved_at_10[0x10];
6643 
6644 	u8         reserved_at_20[0x10];
6645 	u8         op_mod[0x10];
6646 
6647 	u8         reserved_at_40[0xa0];
6648 
6649 	struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
6650 };
6651 
6652 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
6653 	u8         status[0x8];
6654 	u8         reserved_at_8[0x18];
6655 
6656 	u8         syndrome[0x20];
6657 
6658 	u8         reserved_at_40[0x40];
6659 };
6660 
6661 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
6662 	u8         opcode[0x10];
6663 	u8         reserved_at_10[0x10];
6664 
6665 	u8         reserved_20[0x10];
6666 	u8         op_mod[0x10];
6667 
6668 	u8         packet_reformat_id[0x20];
6669 
6670 	u8         reserved_60[0x20];
6671 };
6672 
6673 struct mlx5_ifc_set_action_in_bits {
6674 	u8         action_type[0x4];
6675 	u8         field[0xc];
6676 	u8         reserved_at_10[0x3];
6677 	u8         offset[0x5];
6678 	u8         reserved_at_18[0x3];
6679 	u8         length[0x5];
6680 
6681 	u8         data[0x20];
6682 };
6683 
6684 struct mlx5_ifc_add_action_in_bits {
6685 	u8         action_type[0x4];
6686 	u8         field[0xc];
6687 	u8         reserved_at_10[0x10];
6688 
6689 	u8         data[0x20];
6690 };
6691 
6692 struct mlx5_ifc_copy_action_in_bits {
6693 	u8         action_type[0x4];
6694 	u8         src_field[0xc];
6695 	u8         reserved_at_10[0x3];
6696 	u8         src_offset[0x5];
6697 	u8         reserved_at_18[0x3];
6698 	u8         length[0x5];
6699 
6700 	u8         reserved_at_20[0x4];
6701 	u8         dst_field[0xc];
6702 	u8         reserved_at_30[0x3];
6703 	u8         dst_offset[0x5];
6704 	u8         reserved_at_38[0x8];
6705 };
6706 
6707 union mlx5_ifc_set_add_copy_action_in_auto_bits {
6708 	struct mlx5_ifc_set_action_in_bits  set_action_in;
6709 	struct mlx5_ifc_add_action_in_bits  add_action_in;
6710 	struct mlx5_ifc_copy_action_in_bits copy_action_in;
6711 	u8         reserved_at_0[0x40];
6712 };
6713 
6714 enum {
6715 	MLX5_ACTION_TYPE_SET   = 0x1,
6716 	MLX5_ACTION_TYPE_ADD   = 0x2,
6717 	MLX5_ACTION_TYPE_COPY  = 0x3,
6718 };
6719 
6720 enum {
6721 	MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
6722 	MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
6723 	MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
6724 	MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
6725 	MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
6726 	MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
6727 	MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
6728 	MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
6729 	MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
6730 	MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
6731 	MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
6732 	MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
6733 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
6734 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
6735 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
6736 	MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
6737 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
6738 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
6739 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
6740 	MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
6741 	MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
6742 	MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
6743 	MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
6744 	MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
6745 	MLX5_ACTION_IN_FIELD_METADATA_REG_A    = 0x49,
6746 	MLX5_ACTION_IN_FIELD_METADATA_REG_B    = 0x50,
6747 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
6748 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_1  = 0x52,
6749 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_2  = 0x53,
6750 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_3  = 0x54,
6751 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_4  = 0x55,
6752 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_5  = 0x56,
6753 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_6  = 0x57,
6754 	MLX5_ACTION_IN_FIELD_METADATA_REG_C_7  = 0x58,
6755 	MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM   = 0x59,
6756 	MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM   = 0x5B,
6757 	MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME    = 0x5D,
6758 	MLX5_ACTION_IN_FIELD_OUT_EMD_47_32     = 0x6F,
6759 	MLX5_ACTION_IN_FIELD_OUT_EMD_31_0      = 0x70,
6760 };
6761 
6762 struct mlx5_ifc_alloc_modify_header_context_out_bits {
6763 	u8         status[0x8];
6764 	u8         reserved_at_8[0x18];
6765 
6766 	u8         syndrome[0x20];
6767 
6768 	u8         modify_header_id[0x20];
6769 
6770 	u8         reserved_at_60[0x20];
6771 };
6772 
6773 struct mlx5_ifc_alloc_modify_header_context_in_bits {
6774 	u8         opcode[0x10];
6775 	u8         reserved_at_10[0x10];
6776 
6777 	u8         reserved_at_20[0x10];
6778 	u8         op_mod[0x10];
6779 
6780 	u8         reserved_at_40[0x20];
6781 
6782 	u8         table_type[0x8];
6783 	u8         reserved_at_68[0x10];
6784 	u8         num_of_actions[0x8];
6785 
6786 	union mlx5_ifc_set_add_copy_action_in_auto_bits actions[];
6787 };
6788 
6789 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
6790 	u8         status[0x8];
6791 	u8         reserved_at_8[0x18];
6792 
6793 	u8         syndrome[0x20];
6794 
6795 	u8         reserved_at_40[0x40];
6796 };
6797 
6798 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
6799 	u8         opcode[0x10];
6800 	u8         reserved_at_10[0x10];
6801 
6802 	u8         reserved_at_20[0x10];
6803 	u8         op_mod[0x10];
6804 
6805 	u8         modify_header_id[0x20];
6806 
6807 	u8         reserved_at_60[0x20];
6808 };
6809 
6810 struct mlx5_ifc_query_modify_header_context_in_bits {
6811 	u8         opcode[0x10];
6812 	u8         uid[0x10];
6813 
6814 	u8         reserved_at_20[0x10];
6815 	u8         op_mod[0x10];
6816 
6817 	u8         modify_header_id[0x20];
6818 
6819 	u8         reserved_at_60[0xa0];
6820 };
6821 
6822 struct mlx5_ifc_query_dct_out_bits {
6823 	u8         status[0x8];
6824 	u8         reserved_at_8[0x18];
6825 
6826 	u8         syndrome[0x20];
6827 
6828 	u8         reserved_at_40[0x40];
6829 
6830 	struct mlx5_ifc_dctc_bits dct_context_entry;
6831 
6832 	u8         reserved_at_280[0x180];
6833 };
6834 
6835 struct mlx5_ifc_query_dct_in_bits {
6836 	u8         opcode[0x10];
6837 	u8         reserved_at_10[0x10];
6838 
6839 	u8         reserved_at_20[0x10];
6840 	u8         op_mod[0x10];
6841 
6842 	u8         reserved_at_40[0x8];
6843 	u8         dctn[0x18];
6844 
6845 	u8         reserved_at_60[0x20];
6846 };
6847 
6848 struct mlx5_ifc_query_cq_out_bits {
6849 	u8         status[0x8];
6850 	u8         reserved_at_8[0x18];
6851 
6852 	u8         syndrome[0x20];
6853 
6854 	u8         reserved_at_40[0x40];
6855 
6856 	struct mlx5_ifc_cqc_bits cq_context;
6857 
6858 	u8         reserved_at_280[0x600];
6859 
6860 	u8         pas[][0x40];
6861 };
6862 
6863 struct mlx5_ifc_query_cq_in_bits {
6864 	u8         opcode[0x10];
6865 	u8         reserved_at_10[0x10];
6866 
6867 	u8         reserved_at_20[0x10];
6868 	u8         op_mod[0x10];
6869 
6870 	u8         reserved_at_40[0x8];
6871 	u8         cqn[0x18];
6872 
6873 	u8         reserved_at_60[0x20];
6874 };
6875 
6876 struct mlx5_ifc_query_cong_status_out_bits {
6877 	u8         status[0x8];
6878 	u8         reserved_at_8[0x18];
6879 
6880 	u8         syndrome[0x20];
6881 
6882 	u8         reserved_at_40[0x20];
6883 
6884 	u8         enable[0x1];
6885 	u8         tag_enable[0x1];
6886 	u8         reserved_at_62[0x1e];
6887 };
6888 
6889 struct mlx5_ifc_query_cong_status_in_bits {
6890 	u8         opcode[0x10];
6891 	u8         reserved_at_10[0x10];
6892 
6893 	u8         reserved_at_20[0x10];
6894 	u8         op_mod[0x10];
6895 
6896 	u8         reserved_at_40[0x18];
6897 	u8         priority[0x4];
6898 	u8         cong_protocol[0x4];
6899 
6900 	u8         reserved_at_60[0x20];
6901 };
6902 
6903 struct mlx5_ifc_query_cong_statistics_out_bits {
6904 	u8         status[0x8];
6905 	u8         reserved_at_8[0x18];
6906 
6907 	u8         syndrome[0x20];
6908 
6909 	u8         reserved_at_40[0x40];
6910 
6911 	u8         rp_cur_flows[0x20];
6912 
6913 	u8         sum_flows[0x20];
6914 
6915 	u8         rp_cnp_ignored_high[0x20];
6916 
6917 	u8         rp_cnp_ignored_low[0x20];
6918 
6919 	u8         rp_cnp_handled_high[0x20];
6920 
6921 	u8         rp_cnp_handled_low[0x20];
6922 
6923 	u8         reserved_at_140[0x100];
6924 
6925 	u8         time_stamp_high[0x20];
6926 
6927 	u8         time_stamp_low[0x20];
6928 
6929 	u8         accumulators_period[0x20];
6930 
6931 	u8         np_ecn_marked_roce_packets_high[0x20];
6932 
6933 	u8         np_ecn_marked_roce_packets_low[0x20];
6934 
6935 	u8         np_cnp_sent_high[0x20];
6936 
6937 	u8         np_cnp_sent_low[0x20];
6938 
6939 	u8         reserved_at_320[0x560];
6940 };
6941 
6942 struct mlx5_ifc_query_cong_statistics_in_bits {
6943 	u8         opcode[0x10];
6944 	u8         reserved_at_10[0x10];
6945 
6946 	u8         reserved_at_20[0x10];
6947 	u8         op_mod[0x10];
6948 
6949 	u8         clear[0x1];
6950 	u8         reserved_at_41[0x1f];
6951 
6952 	u8         reserved_at_60[0x20];
6953 };
6954 
6955 struct mlx5_ifc_query_cong_params_out_bits {
6956 	u8         status[0x8];
6957 	u8         reserved_at_8[0x18];
6958 
6959 	u8         syndrome[0x20];
6960 
6961 	u8         reserved_at_40[0x40];
6962 
6963 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6964 };
6965 
6966 struct mlx5_ifc_query_cong_params_in_bits {
6967 	u8         opcode[0x10];
6968 	u8         reserved_at_10[0x10];
6969 
6970 	u8         reserved_at_20[0x10];
6971 	u8         op_mod[0x10];
6972 
6973 	u8         reserved_at_40[0x1c];
6974 	u8         cong_protocol[0x4];
6975 
6976 	u8         reserved_at_60[0x20];
6977 };
6978 
6979 struct mlx5_ifc_query_adapter_out_bits {
6980 	u8         status[0x8];
6981 	u8         reserved_at_8[0x18];
6982 
6983 	u8         syndrome[0x20];
6984 
6985 	u8         reserved_at_40[0x40];
6986 
6987 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
6988 };
6989 
6990 struct mlx5_ifc_query_adapter_in_bits {
6991 	u8         opcode[0x10];
6992 	u8         reserved_at_10[0x10];
6993 
6994 	u8         reserved_at_20[0x10];
6995 	u8         op_mod[0x10];
6996 
6997 	u8         reserved_at_40[0x40];
6998 };
6999 
7000 struct mlx5_ifc_qp_2rst_out_bits {
7001 	u8         status[0x8];
7002 	u8         reserved_at_8[0x18];
7003 
7004 	u8         syndrome[0x20];
7005 
7006 	u8         reserved_at_40[0x40];
7007 };
7008 
7009 struct mlx5_ifc_qp_2rst_in_bits {
7010 	u8         opcode[0x10];
7011 	u8         uid[0x10];
7012 
7013 	u8         reserved_at_20[0x10];
7014 	u8         op_mod[0x10];
7015 
7016 	u8         reserved_at_40[0x8];
7017 	u8         qpn[0x18];
7018 
7019 	u8         reserved_at_60[0x20];
7020 };
7021 
7022 struct mlx5_ifc_qp_2err_out_bits {
7023 	u8         status[0x8];
7024 	u8         reserved_at_8[0x18];
7025 
7026 	u8         syndrome[0x20];
7027 
7028 	u8         reserved_at_40[0x40];
7029 };
7030 
7031 struct mlx5_ifc_qp_2err_in_bits {
7032 	u8         opcode[0x10];
7033 	u8         uid[0x10];
7034 
7035 	u8         reserved_at_20[0x10];
7036 	u8         op_mod[0x10];
7037 
7038 	u8         reserved_at_40[0x8];
7039 	u8         qpn[0x18];
7040 
7041 	u8         reserved_at_60[0x20];
7042 };
7043 
7044 struct mlx5_ifc_page_fault_resume_out_bits {
7045 	u8         status[0x8];
7046 	u8         reserved_at_8[0x18];
7047 
7048 	u8         syndrome[0x20];
7049 
7050 	u8         reserved_at_40[0x40];
7051 };
7052 
7053 struct mlx5_ifc_page_fault_resume_in_bits {
7054 	u8         opcode[0x10];
7055 	u8         reserved_at_10[0x10];
7056 
7057 	u8         reserved_at_20[0x10];
7058 	u8         op_mod[0x10];
7059 
7060 	u8         error[0x1];
7061 	u8         reserved_at_41[0x4];
7062 	u8         page_fault_type[0x3];
7063 	u8         wq_number[0x18];
7064 
7065 	u8         reserved_at_60[0x8];
7066 	u8         token[0x18];
7067 };
7068 
7069 struct mlx5_ifc_nop_out_bits {
7070 	u8         status[0x8];
7071 	u8         reserved_at_8[0x18];
7072 
7073 	u8         syndrome[0x20];
7074 
7075 	u8         reserved_at_40[0x40];
7076 };
7077 
7078 struct mlx5_ifc_nop_in_bits {
7079 	u8         opcode[0x10];
7080 	u8         reserved_at_10[0x10];
7081 
7082 	u8         reserved_at_20[0x10];
7083 	u8         op_mod[0x10];
7084 
7085 	u8         reserved_at_40[0x40];
7086 };
7087 
7088 struct mlx5_ifc_modify_vport_state_out_bits {
7089 	u8         status[0x8];
7090 	u8         reserved_at_8[0x18];
7091 
7092 	u8         syndrome[0x20];
7093 
7094 	u8         reserved_at_40[0x40];
7095 };
7096 
7097 struct mlx5_ifc_modify_vport_state_in_bits {
7098 	u8         opcode[0x10];
7099 	u8         reserved_at_10[0x10];
7100 
7101 	u8         reserved_at_20[0x10];
7102 	u8         op_mod[0x10];
7103 
7104 	u8         other_vport[0x1];
7105 	u8         reserved_at_41[0xf];
7106 	u8         vport_number[0x10];
7107 
7108 	u8         reserved_at_60[0x18];
7109 	u8         admin_state[0x4];
7110 	u8         reserved_at_7c[0x4];
7111 };
7112 
7113 struct mlx5_ifc_modify_tis_out_bits {
7114 	u8         status[0x8];
7115 	u8         reserved_at_8[0x18];
7116 
7117 	u8         syndrome[0x20];
7118 
7119 	u8         reserved_at_40[0x40];
7120 };
7121 
7122 struct mlx5_ifc_modify_tis_bitmask_bits {
7123 	u8         reserved_at_0[0x20];
7124 
7125 	u8         reserved_at_20[0x1d];
7126 	u8         lag_tx_port_affinity[0x1];
7127 	u8         strict_lag_tx_port_affinity[0x1];
7128 	u8         prio[0x1];
7129 };
7130 
7131 struct mlx5_ifc_modify_tis_in_bits {
7132 	u8         opcode[0x10];
7133 	u8         uid[0x10];
7134 
7135 	u8         reserved_at_20[0x10];
7136 	u8         op_mod[0x10];
7137 
7138 	u8         reserved_at_40[0x8];
7139 	u8         tisn[0x18];
7140 
7141 	u8         reserved_at_60[0x20];
7142 
7143 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
7144 
7145 	u8         reserved_at_c0[0x40];
7146 
7147 	struct mlx5_ifc_tisc_bits ctx;
7148 };
7149 
7150 struct mlx5_ifc_modify_tir_bitmask_bits {
7151 	u8	   reserved_at_0[0x20];
7152 
7153 	u8         reserved_at_20[0x1b];
7154 	u8         self_lb_en[0x1];
7155 	u8         reserved_at_3c[0x1];
7156 	u8         hash[0x1];
7157 	u8         reserved_at_3e[0x1];
7158 	u8         packet_merge[0x1];
7159 };
7160 
7161 struct mlx5_ifc_modify_tir_out_bits {
7162 	u8         status[0x8];
7163 	u8         reserved_at_8[0x18];
7164 
7165 	u8         syndrome[0x20];
7166 
7167 	u8         reserved_at_40[0x40];
7168 };
7169 
7170 struct mlx5_ifc_modify_tir_in_bits {
7171 	u8         opcode[0x10];
7172 	u8         uid[0x10];
7173 
7174 	u8         reserved_at_20[0x10];
7175 	u8         op_mod[0x10];
7176 
7177 	u8         reserved_at_40[0x8];
7178 	u8         tirn[0x18];
7179 
7180 	u8         reserved_at_60[0x20];
7181 
7182 	struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
7183 
7184 	u8         reserved_at_c0[0x40];
7185 
7186 	struct mlx5_ifc_tirc_bits ctx;
7187 };
7188 
7189 struct mlx5_ifc_modify_sq_out_bits {
7190 	u8         status[0x8];
7191 	u8         reserved_at_8[0x18];
7192 
7193 	u8         syndrome[0x20];
7194 
7195 	u8         reserved_at_40[0x40];
7196 };
7197 
7198 struct mlx5_ifc_modify_sq_in_bits {
7199 	u8         opcode[0x10];
7200 	u8         uid[0x10];
7201 
7202 	u8         reserved_at_20[0x10];
7203 	u8         op_mod[0x10];
7204 
7205 	u8         sq_state[0x4];
7206 	u8         reserved_at_44[0x4];
7207 	u8         sqn[0x18];
7208 
7209 	u8         reserved_at_60[0x20];
7210 
7211 	u8         modify_bitmask[0x40];
7212 
7213 	u8         reserved_at_c0[0x40];
7214 
7215 	struct mlx5_ifc_sqc_bits ctx;
7216 };
7217 
7218 struct mlx5_ifc_modify_scheduling_element_out_bits {
7219 	u8         status[0x8];
7220 	u8         reserved_at_8[0x18];
7221 
7222 	u8         syndrome[0x20];
7223 
7224 	u8         reserved_at_40[0x1c0];
7225 };
7226 
7227 enum {
7228 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
7229 	MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
7230 };
7231 
7232 struct mlx5_ifc_modify_scheduling_element_in_bits {
7233 	u8         opcode[0x10];
7234 	u8         reserved_at_10[0x10];
7235 
7236 	u8         reserved_at_20[0x10];
7237 	u8         op_mod[0x10];
7238 
7239 	u8         scheduling_hierarchy[0x8];
7240 	u8         reserved_at_48[0x18];
7241 
7242 	u8         scheduling_element_id[0x20];
7243 
7244 	u8         reserved_at_80[0x20];
7245 
7246 	u8         modify_bitmask[0x20];
7247 
7248 	u8         reserved_at_c0[0x40];
7249 
7250 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
7251 
7252 	u8         reserved_at_300[0x100];
7253 };
7254 
7255 struct mlx5_ifc_modify_rqt_out_bits {
7256 	u8         status[0x8];
7257 	u8         reserved_at_8[0x18];
7258 
7259 	u8         syndrome[0x20];
7260 
7261 	u8         reserved_at_40[0x40];
7262 };
7263 
7264 struct mlx5_ifc_rqt_bitmask_bits {
7265 	u8	   reserved_at_0[0x20];
7266 
7267 	u8         reserved_at_20[0x1f];
7268 	u8         rqn_list[0x1];
7269 };
7270 
7271 struct mlx5_ifc_modify_rqt_in_bits {
7272 	u8         opcode[0x10];
7273 	u8         uid[0x10];
7274 
7275 	u8         reserved_at_20[0x10];
7276 	u8         op_mod[0x10];
7277 
7278 	u8         reserved_at_40[0x8];
7279 	u8         rqtn[0x18];
7280 
7281 	u8         reserved_at_60[0x20];
7282 
7283 	struct mlx5_ifc_rqt_bitmask_bits bitmask;
7284 
7285 	u8         reserved_at_c0[0x40];
7286 
7287 	struct mlx5_ifc_rqtc_bits ctx;
7288 };
7289 
7290 struct mlx5_ifc_modify_rq_out_bits {
7291 	u8         status[0x8];
7292 	u8         reserved_at_8[0x18];
7293 
7294 	u8         syndrome[0x20];
7295 
7296 	u8         reserved_at_40[0x40];
7297 };
7298 
7299 enum {
7300 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
7301 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
7302 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
7303 };
7304 
7305 struct mlx5_ifc_modify_rq_in_bits {
7306 	u8         opcode[0x10];
7307 	u8         uid[0x10];
7308 
7309 	u8         reserved_at_20[0x10];
7310 	u8         op_mod[0x10];
7311 
7312 	u8         rq_state[0x4];
7313 	u8         reserved_at_44[0x4];
7314 	u8         rqn[0x18];
7315 
7316 	u8         reserved_at_60[0x20];
7317 
7318 	u8         modify_bitmask[0x40];
7319 
7320 	u8         reserved_at_c0[0x40];
7321 
7322 	struct mlx5_ifc_rqc_bits ctx;
7323 };
7324 
7325 struct mlx5_ifc_modify_rmp_out_bits {
7326 	u8         status[0x8];
7327 	u8         reserved_at_8[0x18];
7328 
7329 	u8         syndrome[0x20];
7330 
7331 	u8         reserved_at_40[0x40];
7332 };
7333 
7334 struct mlx5_ifc_rmp_bitmask_bits {
7335 	u8	   reserved_at_0[0x20];
7336 
7337 	u8         reserved_at_20[0x1f];
7338 	u8         lwm[0x1];
7339 };
7340 
7341 struct mlx5_ifc_modify_rmp_in_bits {
7342 	u8         opcode[0x10];
7343 	u8         uid[0x10];
7344 
7345 	u8         reserved_at_20[0x10];
7346 	u8         op_mod[0x10];
7347 
7348 	u8         rmp_state[0x4];
7349 	u8         reserved_at_44[0x4];
7350 	u8         rmpn[0x18];
7351 
7352 	u8         reserved_at_60[0x20];
7353 
7354 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
7355 
7356 	u8         reserved_at_c0[0x40];
7357 
7358 	struct mlx5_ifc_rmpc_bits ctx;
7359 };
7360 
7361 struct mlx5_ifc_modify_nic_vport_context_out_bits {
7362 	u8         status[0x8];
7363 	u8         reserved_at_8[0x18];
7364 
7365 	u8         syndrome[0x20];
7366 
7367 	u8         reserved_at_40[0x40];
7368 };
7369 
7370 struct mlx5_ifc_modify_nic_vport_field_select_bits {
7371 	u8         reserved_at_0[0x12];
7372 	u8	   affiliation[0x1];
7373 	u8	   reserved_at_13[0x1];
7374 	u8         disable_uc_local_lb[0x1];
7375 	u8         disable_mc_local_lb[0x1];
7376 	u8         node_guid[0x1];
7377 	u8         port_guid[0x1];
7378 	u8         min_inline[0x1];
7379 	u8         mtu[0x1];
7380 	u8         change_event[0x1];
7381 	u8         promisc[0x1];
7382 	u8         permanent_address[0x1];
7383 	u8         addresses_list[0x1];
7384 	u8         roce_en[0x1];
7385 	u8         reserved_at_1f[0x1];
7386 };
7387 
7388 struct mlx5_ifc_modify_nic_vport_context_in_bits {
7389 	u8         opcode[0x10];
7390 	u8         reserved_at_10[0x10];
7391 
7392 	u8         reserved_at_20[0x10];
7393 	u8         op_mod[0x10];
7394 
7395 	u8         other_vport[0x1];
7396 	u8         reserved_at_41[0xf];
7397 	u8         vport_number[0x10];
7398 
7399 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
7400 
7401 	u8         reserved_at_80[0x780];
7402 
7403 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
7404 };
7405 
7406 struct mlx5_ifc_modify_hca_vport_context_out_bits {
7407 	u8         status[0x8];
7408 	u8         reserved_at_8[0x18];
7409 
7410 	u8         syndrome[0x20];
7411 
7412 	u8         reserved_at_40[0x40];
7413 };
7414 
7415 struct mlx5_ifc_modify_hca_vport_context_in_bits {
7416 	u8         opcode[0x10];
7417 	u8         reserved_at_10[0x10];
7418 
7419 	u8         reserved_at_20[0x10];
7420 	u8         op_mod[0x10];
7421 
7422 	u8         other_vport[0x1];
7423 	u8         reserved_at_41[0xb];
7424 	u8         port_num[0x4];
7425 	u8         vport_number[0x10];
7426 
7427 	u8         reserved_at_60[0x20];
7428 
7429 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
7430 };
7431 
7432 struct mlx5_ifc_modify_cq_out_bits {
7433 	u8         status[0x8];
7434 	u8         reserved_at_8[0x18];
7435 
7436 	u8         syndrome[0x20];
7437 
7438 	u8         reserved_at_40[0x40];
7439 };
7440 
7441 enum {
7442 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
7443 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
7444 };
7445 
7446 struct mlx5_ifc_modify_cq_in_bits {
7447 	u8         opcode[0x10];
7448 	u8         uid[0x10];
7449 
7450 	u8         reserved_at_20[0x10];
7451 	u8         op_mod[0x10];
7452 
7453 	u8         reserved_at_40[0x8];
7454 	u8         cqn[0x18];
7455 
7456 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
7457 
7458 	struct mlx5_ifc_cqc_bits cq_context;
7459 
7460 	u8         reserved_at_280[0x60];
7461 
7462 	u8         cq_umem_valid[0x1];
7463 	u8         reserved_at_2e1[0x1f];
7464 
7465 	u8         reserved_at_300[0x580];
7466 
7467 	u8         pas[][0x40];
7468 };
7469 
7470 struct mlx5_ifc_modify_cong_status_out_bits {
7471 	u8         status[0x8];
7472 	u8         reserved_at_8[0x18];
7473 
7474 	u8         syndrome[0x20];
7475 
7476 	u8         reserved_at_40[0x40];
7477 };
7478 
7479 struct mlx5_ifc_modify_cong_status_in_bits {
7480 	u8         opcode[0x10];
7481 	u8         reserved_at_10[0x10];
7482 
7483 	u8         reserved_at_20[0x10];
7484 	u8         op_mod[0x10];
7485 
7486 	u8         reserved_at_40[0x18];
7487 	u8         priority[0x4];
7488 	u8         cong_protocol[0x4];
7489 
7490 	u8         enable[0x1];
7491 	u8         tag_enable[0x1];
7492 	u8         reserved_at_62[0x1e];
7493 };
7494 
7495 struct mlx5_ifc_modify_cong_params_out_bits {
7496 	u8         status[0x8];
7497 	u8         reserved_at_8[0x18];
7498 
7499 	u8         syndrome[0x20];
7500 
7501 	u8         reserved_at_40[0x40];
7502 };
7503 
7504 struct mlx5_ifc_modify_cong_params_in_bits {
7505 	u8         opcode[0x10];
7506 	u8         reserved_at_10[0x10];
7507 
7508 	u8         reserved_at_20[0x10];
7509 	u8         op_mod[0x10];
7510 
7511 	u8         reserved_at_40[0x1c];
7512 	u8         cong_protocol[0x4];
7513 
7514 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
7515 
7516 	u8         reserved_at_80[0x80];
7517 
7518 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
7519 };
7520 
7521 struct mlx5_ifc_manage_pages_out_bits {
7522 	u8         status[0x8];
7523 	u8         reserved_at_8[0x18];
7524 
7525 	u8         syndrome[0x20];
7526 
7527 	u8         output_num_entries[0x20];
7528 
7529 	u8         reserved_at_60[0x20];
7530 
7531 	u8         pas[][0x40];
7532 };
7533 
7534 enum {
7535 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
7536 	MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
7537 	MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
7538 };
7539 
7540 struct mlx5_ifc_manage_pages_in_bits {
7541 	u8         opcode[0x10];
7542 	u8         reserved_at_10[0x10];
7543 
7544 	u8         reserved_at_20[0x10];
7545 	u8         op_mod[0x10];
7546 
7547 	u8         embedded_cpu_function[0x1];
7548 	u8         reserved_at_41[0xf];
7549 	u8         function_id[0x10];
7550 
7551 	u8         input_num_entries[0x20];
7552 
7553 	u8         pas[][0x40];
7554 };
7555 
7556 struct mlx5_ifc_mad_ifc_out_bits {
7557 	u8         status[0x8];
7558 	u8         reserved_at_8[0x18];
7559 
7560 	u8         syndrome[0x20];
7561 
7562 	u8         reserved_at_40[0x40];
7563 
7564 	u8         response_mad_packet[256][0x8];
7565 };
7566 
7567 struct mlx5_ifc_mad_ifc_in_bits {
7568 	u8         opcode[0x10];
7569 	u8         reserved_at_10[0x10];
7570 
7571 	u8         reserved_at_20[0x10];
7572 	u8         op_mod[0x10];
7573 
7574 	u8         remote_lid[0x10];
7575 	u8         reserved_at_50[0x8];
7576 	u8         port[0x8];
7577 
7578 	u8         reserved_at_60[0x20];
7579 
7580 	u8         mad[256][0x8];
7581 };
7582 
7583 struct mlx5_ifc_init_hca_out_bits {
7584 	u8         status[0x8];
7585 	u8         reserved_at_8[0x18];
7586 
7587 	u8         syndrome[0x20];
7588 
7589 	u8         reserved_at_40[0x40];
7590 };
7591 
7592 struct mlx5_ifc_init_hca_in_bits {
7593 	u8         opcode[0x10];
7594 	u8         reserved_at_10[0x10];
7595 
7596 	u8         reserved_at_20[0x10];
7597 	u8         op_mod[0x10];
7598 
7599 	u8         reserved_at_40[0x20];
7600 
7601 	u8         reserved_at_60[0x2];
7602 	u8         sw_vhca_id[0xe];
7603 	u8         reserved_at_70[0x10];
7604 
7605 	u8	   sw_owner_id[4][0x20];
7606 };
7607 
7608 struct mlx5_ifc_init2rtr_qp_out_bits {
7609 	u8         status[0x8];
7610 	u8         reserved_at_8[0x18];
7611 
7612 	u8         syndrome[0x20];
7613 
7614 	u8         reserved_at_40[0x20];
7615 	u8         ece[0x20];
7616 };
7617 
7618 struct mlx5_ifc_init2rtr_qp_in_bits {
7619 	u8         opcode[0x10];
7620 	u8         uid[0x10];
7621 
7622 	u8         reserved_at_20[0x10];
7623 	u8         op_mod[0x10];
7624 
7625 	u8         reserved_at_40[0x8];
7626 	u8         qpn[0x18];
7627 
7628 	u8         reserved_at_60[0x20];
7629 
7630 	u8         opt_param_mask[0x20];
7631 
7632 	u8         ece[0x20];
7633 
7634 	struct mlx5_ifc_qpc_bits qpc;
7635 
7636 	u8         reserved_at_800[0x80];
7637 };
7638 
7639 struct mlx5_ifc_init2init_qp_out_bits {
7640 	u8         status[0x8];
7641 	u8         reserved_at_8[0x18];
7642 
7643 	u8         syndrome[0x20];
7644 
7645 	u8         reserved_at_40[0x20];
7646 	u8         ece[0x20];
7647 };
7648 
7649 struct mlx5_ifc_init2init_qp_in_bits {
7650 	u8         opcode[0x10];
7651 	u8         uid[0x10];
7652 
7653 	u8         reserved_at_20[0x10];
7654 	u8         op_mod[0x10];
7655 
7656 	u8         reserved_at_40[0x8];
7657 	u8         qpn[0x18];
7658 
7659 	u8         reserved_at_60[0x20];
7660 
7661 	u8         opt_param_mask[0x20];
7662 
7663 	u8         ece[0x20];
7664 
7665 	struct mlx5_ifc_qpc_bits qpc;
7666 
7667 	u8         reserved_at_800[0x80];
7668 };
7669 
7670 struct mlx5_ifc_get_dropped_packet_log_out_bits {
7671 	u8         status[0x8];
7672 	u8         reserved_at_8[0x18];
7673 
7674 	u8         syndrome[0x20];
7675 
7676 	u8         reserved_at_40[0x40];
7677 
7678 	u8         packet_headers_log[128][0x8];
7679 
7680 	u8         packet_syndrome[64][0x8];
7681 };
7682 
7683 struct mlx5_ifc_get_dropped_packet_log_in_bits {
7684 	u8         opcode[0x10];
7685 	u8         reserved_at_10[0x10];
7686 
7687 	u8         reserved_at_20[0x10];
7688 	u8         op_mod[0x10];
7689 
7690 	u8         reserved_at_40[0x40];
7691 };
7692 
7693 struct mlx5_ifc_gen_eqe_in_bits {
7694 	u8         opcode[0x10];
7695 	u8         reserved_at_10[0x10];
7696 
7697 	u8         reserved_at_20[0x10];
7698 	u8         op_mod[0x10];
7699 
7700 	u8         reserved_at_40[0x18];
7701 	u8         eq_number[0x8];
7702 
7703 	u8         reserved_at_60[0x20];
7704 
7705 	u8         eqe[64][0x8];
7706 };
7707 
7708 struct mlx5_ifc_gen_eq_out_bits {
7709 	u8         status[0x8];
7710 	u8         reserved_at_8[0x18];
7711 
7712 	u8         syndrome[0x20];
7713 
7714 	u8         reserved_at_40[0x40];
7715 };
7716 
7717 struct mlx5_ifc_enable_hca_out_bits {
7718 	u8         status[0x8];
7719 	u8         reserved_at_8[0x18];
7720 
7721 	u8         syndrome[0x20];
7722 
7723 	u8         reserved_at_40[0x20];
7724 };
7725 
7726 struct mlx5_ifc_enable_hca_in_bits {
7727 	u8         opcode[0x10];
7728 	u8         reserved_at_10[0x10];
7729 
7730 	u8         reserved_at_20[0x10];
7731 	u8         op_mod[0x10];
7732 
7733 	u8         embedded_cpu_function[0x1];
7734 	u8         reserved_at_41[0xf];
7735 	u8         function_id[0x10];
7736 
7737 	u8         reserved_at_60[0x20];
7738 };
7739 
7740 struct mlx5_ifc_drain_dct_out_bits {
7741 	u8         status[0x8];
7742 	u8         reserved_at_8[0x18];
7743 
7744 	u8         syndrome[0x20];
7745 
7746 	u8         reserved_at_40[0x40];
7747 };
7748 
7749 struct mlx5_ifc_drain_dct_in_bits {
7750 	u8         opcode[0x10];
7751 	u8         uid[0x10];
7752 
7753 	u8         reserved_at_20[0x10];
7754 	u8         op_mod[0x10];
7755 
7756 	u8         reserved_at_40[0x8];
7757 	u8         dctn[0x18];
7758 
7759 	u8         reserved_at_60[0x20];
7760 };
7761 
7762 struct mlx5_ifc_disable_hca_out_bits {
7763 	u8         status[0x8];
7764 	u8         reserved_at_8[0x18];
7765 
7766 	u8         syndrome[0x20];
7767 
7768 	u8         reserved_at_40[0x20];
7769 };
7770 
7771 struct mlx5_ifc_disable_hca_in_bits {
7772 	u8         opcode[0x10];
7773 	u8         reserved_at_10[0x10];
7774 
7775 	u8         reserved_at_20[0x10];
7776 	u8         op_mod[0x10];
7777 
7778 	u8         embedded_cpu_function[0x1];
7779 	u8         reserved_at_41[0xf];
7780 	u8         function_id[0x10];
7781 
7782 	u8         reserved_at_60[0x20];
7783 };
7784 
7785 struct mlx5_ifc_detach_from_mcg_out_bits {
7786 	u8         status[0x8];
7787 	u8         reserved_at_8[0x18];
7788 
7789 	u8         syndrome[0x20];
7790 
7791 	u8         reserved_at_40[0x40];
7792 };
7793 
7794 struct mlx5_ifc_detach_from_mcg_in_bits {
7795 	u8         opcode[0x10];
7796 	u8         uid[0x10];
7797 
7798 	u8         reserved_at_20[0x10];
7799 	u8         op_mod[0x10];
7800 
7801 	u8         reserved_at_40[0x8];
7802 	u8         qpn[0x18];
7803 
7804 	u8         reserved_at_60[0x20];
7805 
7806 	u8         multicast_gid[16][0x8];
7807 };
7808 
7809 struct mlx5_ifc_destroy_xrq_out_bits {
7810 	u8         status[0x8];
7811 	u8         reserved_at_8[0x18];
7812 
7813 	u8         syndrome[0x20];
7814 
7815 	u8         reserved_at_40[0x40];
7816 };
7817 
7818 struct mlx5_ifc_destroy_xrq_in_bits {
7819 	u8         opcode[0x10];
7820 	u8         uid[0x10];
7821 
7822 	u8         reserved_at_20[0x10];
7823 	u8         op_mod[0x10];
7824 
7825 	u8         reserved_at_40[0x8];
7826 	u8         xrqn[0x18];
7827 
7828 	u8         reserved_at_60[0x20];
7829 };
7830 
7831 struct mlx5_ifc_destroy_xrc_srq_out_bits {
7832 	u8         status[0x8];
7833 	u8         reserved_at_8[0x18];
7834 
7835 	u8         syndrome[0x20];
7836 
7837 	u8         reserved_at_40[0x40];
7838 };
7839 
7840 struct mlx5_ifc_destroy_xrc_srq_in_bits {
7841 	u8         opcode[0x10];
7842 	u8         uid[0x10];
7843 
7844 	u8         reserved_at_20[0x10];
7845 	u8         op_mod[0x10];
7846 
7847 	u8         reserved_at_40[0x8];
7848 	u8         xrc_srqn[0x18];
7849 
7850 	u8         reserved_at_60[0x20];
7851 };
7852 
7853 struct mlx5_ifc_destroy_tis_out_bits {
7854 	u8         status[0x8];
7855 	u8         reserved_at_8[0x18];
7856 
7857 	u8         syndrome[0x20];
7858 
7859 	u8         reserved_at_40[0x40];
7860 };
7861 
7862 struct mlx5_ifc_destroy_tis_in_bits {
7863 	u8         opcode[0x10];
7864 	u8         uid[0x10];
7865 
7866 	u8         reserved_at_20[0x10];
7867 	u8         op_mod[0x10];
7868 
7869 	u8         reserved_at_40[0x8];
7870 	u8         tisn[0x18];
7871 
7872 	u8         reserved_at_60[0x20];
7873 };
7874 
7875 struct mlx5_ifc_destroy_tir_out_bits {
7876 	u8         status[0x8];
7877 	u8         reserved_at_8[0x18];
7878 
7879 	u8         syndrome[0x20];
7880 
7881 	u8         reserved_at_40[0x40];
7882 };
7883 
7884 struct mlx5_ifc_destroy_tir_in_bits {
7885 	u8         opcode[0x10];
7886 	u8         uid[0x10];
7887 
7888 	u8         reserved_at_20[0x10];
7889 	u8         op_mod[0x10];
7890 
7891 	u8         reserved_at_40[0x8];
7892 	u8         tirn[0x18];
7893 
7894 	u8         reserved_at_60[0x20];
7895 };
7896 
7897 struct mlx5_ifc_destroy_srq_out_bits {
7898 	u8         status[0x8];
7899 	u8         reserved_at_8[0x18];
7900 
7901 	u8         syndrome[0x20];
7902 
7903 	u8         reserved_at_40[0x40];
7904 };
7905 
7906 struct mlx5_ifc_destroy_srq_in_bits {
7907 	u8         opcode[0x10];
7908 	u8         uid[0x10];
7909 
7910 	u8         reserved_at_20[0x10];
7911 	u8         op_mod[0x10];
7912 
7913 	u8         reserved_at_40[0x8];
7914 	u8         srqn[0x18];
7915 
7916 	u8         reserved_at_60[0x20];
7917 };
7918 
7919 struct mlx5_ifc_destroy_sq_out_bits {
7920 	u8         status[0x8];
7921 	u8         reserved_at_8[0x18];
7922 
7923 	u8         syndrome[0x20];
7924 
7925 	u8         reserved_at_40[0x40];
7926 };
7927 
7928 struct mlx5_ifc_destroy_sq_in_bits {
7929 	u8         opcode[0x10];
7930 	u8         uid[0x10];
7931 
7932 	u8         reserved_at_20[0x10];
7933 	u8         op_mod[0x10];
7934 
7935 	u8         reserved_at_40[0x8];
7936 	u8         sqn[0x18];
7937 
7938 	u8         reserved_at_60[0x20];
7939 };
7940 
7941 struct mlx5_ifc_destroy_scheduling_element_out_bits {
7942 	u8         status[0x8];
7943 	u8         reserved_at_8[0x18];
7944 
7945 	u8         syndrome[0x20];
7946 
7947 	u8         reserved_at_40[0x1c0];
7948 };
7949 
7950 struct mlx5_ifc_destroy_scheduling_element_in_bits {
7951 	u8         opcode[0x10];
7952 	u8         reserved_at_10[0x10];
7953 
7954 	u8         reserved_at_20[0x10];
7955 	u8         op_mod[0x10];
7956 
7957 	u8         scheduling_hierarchy[0x8];
7958 	u8         reserved_at_48[0x18];
7959 
7960 	u8         scheduling_element_id[0x20];
7961 
7962 	u8         reserved_at_80[0x180];
7963 };
7964 
7965 struct mlx5_ifc_destroy_rqt_out_bits {
7966 	u8         status[0x8];
7967 	u8         reserved_at_8[0x18];
7968 
7969 	u8         syndrome[0x20];
7970 
7971 	u8         reserved_at_40[0x40];
7972 };
7973 
7974 struct mlx5_ifc_destroy_rqt_in_bits {
7975 	u8         opcode[0x10];
7976 	u8         uid[0x10];
7977 
7978 	u8         reserved_at_20[0x10];
7979 	u8         op_mod[0x10];
7980 
7981 	u8         reserved_at_40[0x8];
7982 	u8         rqtn[0x18];
7983 
7984 	u8         reserved_at_60[0x20];
7985 };
7986 
7987 struct mlx5_ifc_destroy_rq_out_bits {
7988 	u8         status[0x8];
7989 	u8         reserved_at_8[0x18];
7990 
7991 	u8         syndrome[0x20];
7992 
7993 	u8         reserved_at_40[0x40];
7994 };
7995 
7996 struct mlx5_ifc_destroy_rq_in_bits {
7997 	u8         opcode[0x10];
7998 	u8         uid[0x10];
7999 
8000 	u8         reserved_at_20[0x10];
8001 	u8         op_mod[0x10];
8002 
8003 	u8         reserved_at_40[0x8];
8004 	u8         rqn[0x18];
8005 
8006 	u8         reserved_at_60[0x20];
8007 };
8008 
8009 struct mlx5_ifc_set_delay_drop_params_in_bits {
8010 	u8         opcode[0x10];
8011 	u8         reserved_at_10[0x10];
8012 
8013 	u8         reserved_at_20[0x10];
8014 	u8         op_mod[0x10];
8015 
8016 	u8         reserved_at_40[0x20];
8017 
8018 	u8         reserved_at_60[0x10];
8019 	u8         delay_drop_timeout[0x10];
8020 };
8021 
8022 struct mlx5_ifc_set_delay_drop_params_out_bits {
8023 	u8         status[0x8];
8024 	u8         reserved_at_8[0x18];
8025 
8026 	u8         syndrome[0x20];
8027 
8028 	u8         reserved_at_40[0x40];
8029 };
8030 
8031 struct mlx5_ifc_destroy_rmp_out_bits {
8032 	u8         status[0x8];
8033 	u8         reserved_at_8[0x18];
8034 
8035 	u8         syndrome[0x20];
8036 
8037 	u8         reserved_at_40[0x40];
8038 };
8039 
8040 struct mlx5_ifc_destroy_rmp_in_bits {
8041 	u8         opcode[0x10];
8042 	u8         uid[0x10];
8043 
8044 	u8         reserved_at_20[0x10];
8045 	u8         op_mod[0x10];
8046 
8047 	u8         reserved_at_40[0x8];
8048 	u8         rmpn[0x18];
8049 
8050 	u8         reserved_at_60[0x20];
8051 };
8052 
8053 struct mlx5_ifc_destroy_qp_out_bits {
8054 	u8         status[0x8];
8055 	u8         reserved_at_8[0x18];
8056 
8057 	u8         syndrome[0x20];
8058 
8059 	u8         reserved_at_40[0x40];
8060 };
8061 
8062 struct mlx5_ifc_destroy_qp_in_bits {
8063 	u8         opcode[0x10];
8064 	u8         uid[0x10];
8065 
8066 	u8         reserved_at_20[0x10];
8067 	u8         op_mod[0x10];
8068 
8069 	u8         reserved_at_40[0x8];
8070 	u8         qpn[0x18];
8071 
8072 	u8         reserved_at_60[0x20];
8073 };
8074 
8075 struct mlx5_ifc_destroy_psv_out_bits {
8076 	u8         status[0x8];
8077 	u8         reserved_at_8[0x18];
8078 
8079 	u8         syndrome[0x20];
8080 
8081 	u8         reserved_at_40[0x40];
8082 };
8083 
8084 struct mlx5_ifc_destroy_psv_in_bits {
8085 	u8         opcode[0x10];
8086 	u8         reserved_at_10[0x10];
8087 
8088 	u8         reserved_at_20[0x10];
8089 	u8         op_mod[0x10];
8090 
8091 	u8         reserved_at_40[0x8];
8092 	u8         psvn[0x18];
8093 
8094 	u8         reserved_at_60[0x20];
8095 };
8096 
8097 struct mlx5_ifc_destroy_mkey_out_bits {
8098 	u8         status[0x8];
8099 	u8         reserved_at_8[0x18];
8100 
8101 	u8         syndrome[0x20];
8102 
8103 	u8         reserved_at_40[0x40];
8104 };
8105 
8106 struct mlx5_ifc_destroy_mkey_in_bits {
8107 	u8         opcode[0x10];
8108 	u8         uid[0x10];
8109 
8110 	u8         reserved_at_20[0x10];
8111 	u8         op_mod[0x10];
8112 
8113 	u8         reserved_at_40[0x8];
8114 	u8         mkey_index[0x18];
8115 
8116 	u8         reserved_at_60[0x20];
8117 };
8118 
8119 struct mlx5_ifc_destroy_flow_table_out_bits {
8120 	u8         status[0x8];
8121 	u8         reserved_at_8[0x18];
8122 
8123 	u8         syndrome[0x20];
8124 
8125 	u8         reserved_at_40[0x40];
8126 };
8127 
8128 struct mlx5_ifc_destroy_flow_table_in_bits {
8129 	u8         opcode[0x10];
8130 	u8         reserved_at_10[0x10];
8131 
8132 	u8         reserved_at_20[0x10];
8133 	u8         op_mod[0x10];
8134 
8135 	u8         other_vport[0x1];
8136 	u8         reserved_at_41[0xf];
8137 	u8         vport_number[0x10];
8138 
8139 	u8         reserved_at_60[0x20];
8140 
8141 	u8         table_type[0x8];
8142 	u8         reserved_at_88[0x18];
8143 
8144 	u8         reserved_at_a0[0x8];
8145 	u8         table_id[0x18];
8146 
8147 	u8         reserved_at_c0[0x140];
8148 };
8149 
8150 struct mlx5_ifc_destroy_flow_group_out_bits {
8151 	u8         status[0x8];
8152 	u8         reserved_at_8[0x18];
8153 
8154 	u8         syndrome[0x20];
8155 
8156 	u8         reserved_at_40[0x40];
8157 };
8158 
8159 struct mlx5_ifc_destroy_flow_group_in_bits {
8160 	u8         opcode[0x10];
8161 	u8         reserved_at_10[0x10];
8162 
8163 	u8         reserved_at_20[0x10];
8164 	u8         op_mod[0x10];
8165 
8166 	u8         other_vport[0x1];
8167 	u8         reserved_at_41[0xf];
8168 	u8         vport_number[0x10];
8169 
8170 	u8         reserved_at_60[0x20];
8171 
8172 	u8         table_type[0x8];
8173 	u8         reserved_at_88[0x18];
8174 
8175 	u8         reserved_at_a0[0x8];
8176 	u8         table_id[0x18];
8177 
8178 	u8         group_id[0x20];
8179 
8180 	u8         reserved_at_e0[0x120];
8181 };
8182 
8183 struct mlx5_ifc_destroy_eq_out_bits {
8184 	u8         status[0x8];
8185 	u8         reserved_at_8[0x18];
8186 
8187 	u8         syndrome[0x20];
8188 
8189 	u8         reserved_at_40[0x40];
8190 };
8191 
8192 struct mlx5_ifc_destroy_eq_in_bits {
8193 	u8         opcode[0x10];
8194 	u8         reserved_at_10[0x10];
8195 
8196 	u8         reserved_at_20[0x10];
8197 	u8         op_mod[0x10];
8198 
8199 	u8         reserved_at_40[0x18];
8200 	u8         eq_number[0x8];
8201 
8202 	u8         reserved_at_60[0x20];
8203 };
8204 
8205 struct mlx5_ifc_destroy_dct_out_bits {
8206 	u8         status[0x8];
8207 	u8         reserved_at_8[0x18];
8208 
8209 	u8         syndrome[0x20];
8210 
8211 	u8         reserved_at_40[0x40];
8212 };
8213 
8214 struct mlx5_ifc_destroy_dct_in_bits {
8215 	u8         opcode[0x10];
8216 	u8         uid[0x10];
8217 
8218 	u8         reserved_at_20[0x10];
8219 	u8         op_mod[0x10];
8220 
8221 	u8         reserved_at_40[0x8];
8222 	u8         dctn[0x18];
8223 
8224 	u8         reserved_at_60[0x20];
8225 };
8226 
8227 struct mlx5_ifc_destroy_cq_out_bits {
8228 	u8         status[0x8];
8229 	u8         reserved_at_8[0x18];
8230 
8231 	u8         syndrome[0x20];
8232 
8233 	u8         reserved_at_40[0x40];
8234 };
8235 
8236 struct mlx5_ifc_destroy_cq_in_bits {
8237 	u8         opcode[0x10];
8238 	u8         uid[0x10];
8239 
8240 	u8         reserved_at_20[0x10];
8241 	u8         op_mod[0x10];
8242 
8243 	u8         reserved_at_40[0x8];
8244 	u8         cqn[0x18];
8245 
8246 	u8         reserved_at_60[0x20];
8247 };
8248 
8249 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
8250 	u8         status[0x8];
8251 	u8         reserved_at_8[0x18];
8252 
8253 	u8         syndrome[0x20];
8254 
8255 	u8         reserved_at_40[0x40];
8256 };
8257 
8258 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
8259 	u8         opcode[0x10];
8260 	u8         reserved_at_10[0x10];
8261 
8262 	u8         reserved_at_20[0x10];
8263 	u8         op_mod[0x10];
8264 
8265 	u8         reserved_at_40[0x20];
8266 
8267 	u8         reserved_at_60[0x10];
8268 	u8         vxlan_udp_port[0x10];
8269 };
8270 
8271 struct mlx5_ifc_delete_l2_table_entry_out_bits {
8272 	u8         status[0x8];
8273 	u8         reserved_at_8[0x18];
8274 
8275 	u8         syndrome[0x20];
8276 
8277 	u8         reserved_at_40[0x40];
8278 };
8279 
8280 struct mlx5_ifc_delete_l2_table_entry_in_bits {
8281 	u8         opcode[0x10];
8282 	u8         reserved_at_10[0x10];
8283 
8284 	u8         reserved_at_20[0x10];
8285 	u8         op_mod[0x10];
8286 
8287 	u8         reserved_at_40[0x60];
8288 
8289 	u8         reserved_at_a0[0x8];
8290 	u8         table_index[0x18];
8291 
8292 	u8         reserved_at_c0[0x140];
8293 };
8294 
8295 struct mlx5_ifc_delete_fte_out_bits {
8296 	u8         status[0x8];
8297 	u8         reserved_at_8[0x18];
8298 
8299 	u8         syndrome[0x20];
8300 
8301 	u8         reserved_at_40[0x40];
8302 };
8303 
8304 struct mlx5_ifc_delete_fte_in_bits {
8305 	u8         opcode[0x10];
8306 	u8         reserved_at_10[0x10];
8307 
8308 	u8         reserved_at_20[0x10];
8309 	u8         op_mod[0x10];
8310 
8311 	u8         other_vport[0x1];
8312 	u8         reserved_at_41[0xf];
8313 	u8         vport_number[0x10];
8314 
8315 	u8         reserved_at_60[0x20];
8316 
8317 	u8         table_type[0x8];
8318 	u8         reserved_at_88[0x18];
8319 
8320 	u8         reserved_at_a0[0x8];
8321 	u8         table_id[0x18];
8322 
8323 	u8         reserved_at_c0[0x40];
8324 
8325 	u8         flow_index[0x20];
8326 
8327 	u8         reserved_at_120[0xe0];
8328 };
8329 
8330 struct mlx5_ifc_dealloc_xrcd_out_bits {
8331 	u8         status[0x8];
8332 	u8         reserved_at_8[0x18];
8333 
8334 	u8         syndrome[0x20];
8335 
8336 	u8         reserved_at_40[0x40];
8337 };
8338 
8339 struct mlx5_ifc_dealloc_xrcd_in_bits {
8340 	u8         opcode[0x10];
8341 	u8         uid[0x10];
8342 
8343 	u8         reserved_at_20[0x10];
8344 	u8         op_mod[0x10];
8345 
8346 	u8         reserved_at_40[0x8];
8347 	u8         xrcd[0x18];
8348 
8349 	u8         reserved_at_60[0x20];
8350 };
8351 
8352 struct mlx5_ifc_dealloc_uar_out_bits {
8353 	u8         status[0x8];
8354 	u8         reserved_at_8[0x18];
8355 
8356 	u8         syndrome[0x20];
8357 
8358 	u8         reserved_at_40[0x40];
8359 };
8360 
8361 struct mlx5_ifc_dealloc_uar_in_bits {
8362 	u8         opcode[0x10];
8363 	u8         uid[0x10];
8364 
8365 	u8         reserved_at_20[0x10];
8366 	u8         op_mod[0x10];
8367 
8368 	u8         reserved_at_40[0x8];
8369 	u8         uar[0x18];
8370 
8371 	u8         reserved_at_60[0x20];
8372 };
8373 
8374 struct mlx5_ifc_dealloc_transport_domain_out_bits {
8375 	u8         status[0x8];
8376 	u8         reserved_at_8[0x18];
8377 
8378 	u8         syndrome[0x20];
8379 
8380 	u8         reserved_at_40[0x40];
8381 };
8382 
8383 struct mlx5_ifc_dealloc_transport_domain_in_bits {
8384 	u8         opcode[0x10];
8385 	u8         uid[0x10];
8386 
8387 	u8         reserved_at_20[0x10];
8388 	u8         op_mod[0x10];
8389 
8390 	u8         reserved_at_40[0x8];
8391 	u8         transport_domain[0x18];
8392 
8393 	u8         reserved_at_60[0x20];
8394 };
8395 
8396 struct mlx5_ifc_dealloc_q_counter_out_bits {
8397 	u8         status[0x8];
8398 	u8         reserved_at_8[0x18];
8399 
8400 	u8         syndrome[0x20];
8401 
8402 	u8         reserved_at_40[0x40];
8403 };
8404 
8405 struct mlx5_ifc_dealloc_q_counter_in_bits {
8406 	u8         opcode[0x10];
8407 	u8         reserved_at_10[0x10];
8408 
8409 	u8         reserved_at_20[0x10];
8410 	u8         op_mod[0x10];
8411 
8412 	u8         reserved_at_40[0x18];
8413 	u8         counter_set_id[0x8];
8414 
8415 	u8         reserved_at_60[0x20];
8416 };
8417 
8418 struct mlx5_ifc_dealloc_pd_out_bits {
8419 	u8         status[0x8];
8420 	u8         reserved_at_8[0x18];
8421 
8422 	u8         syndrome[0x20];
8423 
8424 	u8         reserved_at_40[0x40];
8425 };
8426 
8427 struct mlx5_ifc_dealloc_pd_in_bits {
8428 	u8         opcode[0x10];
8429 	u8         uid[0x10];
8430 
8431 	u8         reserved_at_20[0x10];
8432 	u8         op_mod[0x10];
8433 
8434 	u8         reserved_at_40[0x8];
8435 	u8         pd[0x18];
8436 
8437 	u8         reserved_at_60[0x20];
8438 };
8439 
8440 struct mlx5_ifc_dealloc_flow_counter_out_bits {
8441 	u8         status[0x8];
8442 	u8         reserved_at_8[0x18];
8443 
8444 	u8         syndrome[0x20];
8445 
8446 	u8         reserved_at_40[0x40];
8447 };
8448 
8449 struct mlx5_ifc_dealloc_flow_counter_in_bits {
8450 	u8         opcode[0x10];
8451 	u8         reserved_at_10[0x10];
8452 
8453 	u8         reserved_at_20[0x10];
8454 	u8         op_mod[0x10];
8455 
8456 	u8         flow_counter_id[0x20];
8457 
8458 	u8         reserved_at_60[0x20];
8459 };
8460 
8461 struct mlx5_ifc_create_xrq_out_bits {
8462 	u8         status[0x8];
8463 	u8         reserved_at_8[0x18];
8464 
8465 	u8         syndrome[0x20];
8466 
8467 	u8         reserved_at_40[0x8];
8468 	u8         xrqn[0x18];
8469 
8470 	u8         reserved_at_60[0x20];
8471 };
8472 
8473 struct mlx5_ifc_create_xrq_in_bits {
8474 	u8         opcode[0x10];
8475 	u8         uid[0x10];
8476 
8477 	u8         reserved_at_20[0x10];
8478 	u8         op_mod[0x10];
8479 
8480 	u8         reserved_at_40[0x40];
8481 
8482 	struct mlx5_ifc_xrqc_bits xrq_context;
8483 };
8484 
8485 struct mlx5_ifc_create_xrc_srq_out_bits {
8486 	u8         status[0x8];
8487 	u8         reserved_at_8[0x18];
8488 
8489 	u8         syndrome[0x20];
8490 
8491 	u8         reserved_at_40[0x8];
8492 	u8         xrc_srqn[0x18];
8493 
8494 	u8         reserved_at_60[0x20];
8495 };
8496 
8497 struct mlx5_ifc_create_xrc_srq_in_bits {
8498 	u8         opcode[0x10];
8499 	u8         uid[0x10];
8500 
8501 	u8         reserved_at_20[0x10];
8502 	u8         op_mod[0x10];
8503 
8504 	u8         reserved_at_40[0x40];
8505 
8506 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
8507 
8508 	u8         reserved_at_280[0x60];
8509 
8510 	u8         xrc_srq_umem_valid[0x1];
8511 	u8         reserved_at_2e1[0x1f];
8512 
8513 	u8         reserved_at_300[0x580];
8514 
8515 	u8         pas[][0x40];
8516 };
8517 
8518 struct mlx5_ifc_create_tis_out_bits {
8519 	u8         status[0x8];
8520 	u8         reserved_at_8[0x18];
8521 
8522 	u8         syndrome[0x20];
8523 
8524 	u8         reserved_at_40[0x8];
8525 	u8         tisn[0x18];
8526 
8527 	u8         reserved_at_60[0x20];
8528 };
8529 
8530 struct mlx5_ifc_create_tis_in_bits {
8531 	u8         opcode[0x10];
8532 	u8         uid[0x10];
8533 
8534 	u8         reserved_at_20[0x10];
8535 	u8         op_mod[0x10];
8536 
8537 	u8         reserved_at_40[0xc0];
8538 
8539 	struct mlx5_ifc_tisc_bits ctx;
8540 };
8541 
8542 struct mlx5_ifc_create_tir_out_bits {
8543 	u8         status[0x8];
8544 	u8         icm_address_63_40[0x18];
8545 
8546 	u8         syndrome[0x20];
8547 
8548 	u8         icm_address_39_32[0x8];
8549 	u8         tirn[0x18];
8550 
8551 	u8         icm_address_31_0[0x20];
8552 };
8553 
8554 struct mlx5_ifc_create_tir_in_bits {
8555 	u8         opcode[0x10];
8556 	u8         uid[0x10];
8557 
8558 	u8         reserved_at_20[0x10];
8559 	u8         op_mod[0x10];
8560 
8561 	u8         reserved_at_40[0xc0];
8562 
8563 	struct mlx5_ifc_tirc_bits ctx;
8564 };
8565 
8566 struct mlx5_ifc_create_srq_out_bits {
8567 	u8         status[0x8];
8568 	u8         reserved_at_8[0x18];
8569 
8570 	u8         syndrome[0x20];
8571 
8572 	u8         reserved_at_40[0x8];
8573 	u8         srqn[0x18];
8574 
8575 	u8         reserved_at_60[0x20];
8576 };
8577 
8578 struct mlx5_ifc_create_srq_in_bits {
8579 	u8         opcode[0x10];
8580 	u8         uid[0x10];
8581 
8582 	u8         reserved_at_20[0x10];
8583 	u8         op_mod[0x10];
8584 
8585 	u8         reserved_at_40[0x40];
8586 
8587 	struct mlx5_ifc_srqc_bits srq_context_entry;
8588 
8589 	u8         reserved_at_280[0x600];
8590 
8591 	u8         pas[][0x40];
8592 };
8593 
8594 struct mlx5_ifc_create_sq_out_bits {
8595 	u8         status[0x8];
8596 	u8         reserved_at_8[0x18];
8597 
8598 	u8         syndrome[0x20];
8599 
8600 	u8         reserved_at_40[0x8];
8601 	u8         sqn[0x18];
8602 
8603 	u8         reserved_at_60[0x20];
8604 };
8605 
8606 struct mlx5_ifc_create_sq_in_bits {
8607 	u8         opcode[0x10];
8608 	u8         uid[0x10];
8609 
8610 	u8         reserved_at_20[0x10];
8611 	u8         op_mod[0x10];
8612 
8613 	u8         reserved_at_40[0xc0];
8614 
8615 	struct mlx5_ifc_sqc_bits ctx;
8616 };
8617 
8618 struct mlx5_ifc_create_scheduling_element_out_bits {
8619 	u8         status[0x8];
8620 	u8         reserved_at_8[0x18];
8621 
8622 	u8         syndrome[0x20];
8623 
8624 	u8         reserved_at_40[0x40];
8625 
8626 	u8         scheduling_element_id[0x20];
8627 
8628 	u8         reserved_at_a0[0x160];
8629 };
8630 
8631 struct mlx5_ifc_create_scheduling_element_in_bits {
8632 	u8         opcode[0x10];
8633 	u8         reserved_at_10[0x10];
8634 
8635 	u8         reserved_at_20[0x10];
8636 	u8         op_mod[0x10];
8637 
8638 	u8         scheduling_hierarchy[0x8];
8639 	u8         reserved_at_48[0x18];
8640 
8641 	u8         reserved_at_60[0xa0];
8642 
8643 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
8644 
8645 	u8         reserved_at_300[0x100];
8646 };
8647 
8648 struct mlx5_ifc_create_rqt_out_bits {
8649 	u8         status[0x8];
8650 	u8         reserved_at_8[0x18];
8651 
8652 	u8         syndrome[0x20];
8653 
8654 	u8         reserved_at_40[0x8];
8655 	u8         rqtn[0x18];
8656 
8657 	u8         reserved_at_60[0x20];
8658 };
8659 
8660 struct mlx5_ifc_create_rqt_in_bits {
8661 	u8         opcode[0x10];
8662 	u8         uid[0x10];
8663 
8664 	u8         reserved_at_20[0x10];
8665 	u8         op_mod[0x10];
8666 
8667 	u8         reserved_at_40[0xc0];
8668 
8669 	struct mlx5_ifc_rqtc_bits rqt_context;
8670 };
8671 
8672 struct mlx5_ifc_create_rq_out_bits {
8673 	u8         status[0x8];
8674 	u8         reserved_at_8[0x18];
8675 
8676 	u8         syndrome[0x20];
8677 
8678 	u8         reserved_at_40[0x8];
8679 	u8         rqn[0x18];
8680 
8681 	u8         reserved_at_60[0x20];
8682 };
8683 
8684 struct mlx5_ifc_create_rq_in_bits {
8685 	u8         opcode[0x10];
8686 	u8         uid[0x10];
8687 
8688 	u8         reserved_at_20[0x10];
8689 	u8         op_mod[0x10];
8690 
8691 	u8         reserved_at_40[0xc0];
8692 
8693 	struct mlx5_ifc_rqc_bits ctx;
8694 };
8695 
8696 struct mlx5_ifc_create_rmp_out_bits {
8697 	u8         status[0x8];
8698 	u8         reserved_at_8[0x18];
8699 
8700 	u8         syndrome[0x20];
8701 
8702 	u8         reserved_at_40[0x8];
8703 	u8         rmpn[0x18];
8704 
8705 	u8         reserved_at_60[0x20];
8706 };
8707 
8708 struct mlx5_ifc_create_rmp_in_bits {
8709 	u8         opcode[0x10];
8710 	u8         uid[0x10];
8711 
8712 	u8         reserved_at_20[0x10];
8713 	u8         op_mod[0x10];
8714 
8715 	u8         reserved_at_40[0xc0];
8716 
8717 	struct mlx5_ifc_rmpc_bits ctx;
8718 };
8719 
8720 struct mlx5_ifc_create_qp_out_bits {
8721 	u8         status[0x8];
8722 	u8         reserved_at_8[0x18];
8723 
8724 	u8         syndrome[0x20];
8725 
8726 	u8         reserved_at_40[0x8];
8727 	u8         qpn[0x18];
8728 
8729 	u8         ece[0x20];
8730 };
8731 
8732 struct mlx5_ifc_create_qp_in_bits {
8733 	u8         opcode[0x10];
8734 	u8         uid[0x10];
8735 
8736 	u8         reserved_at_20[0x10];
8737 	u8         op_mod[0x10];
8738 
8739 	u8         qpc_ext[0x1];
8740 	u8         reserved_at_41[0x7];
8741 	u8         input_qpn[0x18];
8742 
8743 	u8         reserved_at_60[0x20];
8744 	u8         opt_param_mask[0x20];
8745 
8746 	u8         ece[0x20];
8747 
8748 	struct mlx5_ifc_qpc_bits qpc;
8749 
8750 	u8         reserved_at_800[0x60];
8751 
8752 	u8         wq_umem_valid[0x1];
8753 	u8         reserved_at_861[0x1f];
8754 
8755 	u8         pas[][0x40];
8756 };
8757 
8758 struct mlx5_ifc_create_psv_out_bits {
8759 	u8         status[0x8];
8760 	u8         reserved_at_8[0x18];
8761 
8762 	u8         syndrome[0x20];
8763 
8764 	u8         reserved_at_40[0x40];
8765 
8766 	u8         reserved_at_80[0x8];
8767 	u8         psv0_index[0x18];
8768 
8769 	u8         reserved_at_a0[0x8];
8770 	u8         psv1_index[0x18];
8771 
8772 	u8         reserved_at_c0[0x8];
8773 	u8         psv2_index[0x18];
8774 
8775 	u8         reserved_at_e0[0x8];
8776 	u8         psv3_index[0x18];
8777 };
8778 
8779 struct mlx5_ifc_create_psv_in_bits {
8780 	u8         opcode[0x10];
8781 	u8         reserved_at_10[0x10];
8782 
8783 	u8         reserved_at_20[0x10];
8784 	u8         op_mod[0x10];
8785 
8786 	u8         num_psv[0x4];
8787 	u8         reserved_at_44[0x4];
8788 	u8         pd[0x18];
8789 
8790 	u8         reserved_at_60[0x20];
8791 };
8792 
8793 struct mlx5_ifc_create_mkey_out_bits {
8794 	u8         status[0x8];
8795 	u8         reserved_at_8[0x18];
8796 
8797 	u8         syndrome[0x20];
8798 
8799 	u8         reserved_at_40[0x8];
8800 	u8         mkey_index[0x18];
8801 
8802 	u8         reserved_at_60[0x20];
8803 };
8804 
8805 struct mlx5_ifc_create_mkey_in_bits {
8806 	u8         opcode[0x10];
8807 	u8         uid[0x10];
8808 
8809 	u8         reserved_at_20[0x10];
8810 	u8         op_mod[0x10];
8811 
8812 	u8         reserved_at_40[0x20];
8813 
8814 	u8         pg_access[0x1];
8815 	u8         mkey_umem_valid[0x1];
8816 	u8         reserved_at_62[0x1e];
8817 
8818 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
8819 
8820 	u8         reserved_at_280[0x80];
8821 
8822 	u8         translations_octword_actual_size[0x20];
8823 
8824 	u8         reserved_at_320[0x560];
8825 
8826 	u8         klm_pas_mtt[][0x20];
8827 };
8828 
8829 enum {
8830 	MLX5_FLOW_TABLE_TYPE_NIC_RX		= 0x0,
8831 	MLX5_FLOW_TABLE_TYPE_NIC_TX		= 0x1,
8832 	MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL	= 0x2,
8833 	MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL	= 0x3,
8834 	MLX5_FLOW_TABLE_TYPE_FDB		= 0X4,
8835 	MLX5_FLOW_TABLE_TYPE_SNIFFER_RX		= 0X5,
8836 	MLX5_FLOW_TABLE_TYPE_SNIFFER_TX		= 0X6,
8837 };
8838 
8839 struct mlx5_ifc_create_flow_table_out_bits {
8840 	u8         status[0x8];
8841 	u8         icm_address_63_40[0x18];
8842 
8843 	u8         syndrome[0x20];
8844 
8845 	u8         icm_address_39_32[0x8];
8846 	u8         table_id[0x18];
8847 
8848 	u8         icm_address_31_0[0x20];
8849 };
8850 
8851 struct mlx5_ifc_create_flow_table_in_bits {
8852 	u8         opcode[0x10];
8853 	u8         uid[0x10];
8854 
8855 	u8         reserved_at_20[0x10];
8856 	u8         op_mod[0x10];
8857 
8858 	u8         other_vport[0x1];
8859 	u8         reserved_at_41[0xf];
8860 	u8         vport_number[0x10];
8861 
8862 	u8         reserved_at_60[0x20];
8863 
8864 	u8         table_type[0x8];
8865 	u8         reserved_at_88[0x18];
8866 
8867 	u8         reserved_at_a0[0x20];
8868 
8869 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
8870 };
8871 
8872 struct mlx5_ifc_create_flow_group_out_bits {
8873 	u8         status[0x8];
8874 	u8         reserved_at_8[0x18];
8875 
8876 	u8         syndrome[0x20];
8877 
8878 	u8         reserved_at_40[0x8];
8879 	u8         group_id[0x18];
8880 
8881 	u8         reserved_at_60[0x20];
8882 };
8883 
8884 enum {
8885 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE  = 0x0,
8886 	MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT     = 0x1,
8887 };
8888 
8889 enum {
8890 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
8891 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
8892 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
8893 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8894 };
8895 
8896 struct mlx5_ifc_create_flow_group_in_bits {
8897 	u8         opcode[0x10];
8898 	u8         reserved_at_10[0x10];
8899 
8900 	u8         reserved_at_20[0x10];
8901 	u8         op_mod[0x10];
8902 
8903 	u8         other_vport[0x1];
8904 	u8         reserved_at_41[0xf];
8905 	u8         vport_number[0x10];
8906 
8907 	u8         reserved_at_60[0x20];
8908 
8909 	u8         table_type[0x8];
8910 	u8         reserved_at_88[0x4];
8911 	u8         group_type[0x4];
8912 	u8         reserved_at_90[0x10];
8913 
8914 	u8         reserved_at_a0[0x8];
8915 	u8         table_id[0x18];
8916 
8917 	u8         source_eswitch_owner_vhca_id_valid[0x1];
8918 
8919 	u8         reserved_at_c1[0x1f];
8920 
8921 	u8         start_flow_index[0x20];
8922 
8923 	u8         reserved_at_100[0x20];
8924 
8925 	u8         end_flow_index[0x20];
8926 
8927 	u8         reserved_at_140[0x10];
8928 	u8         match_definer_id[0x10];
8929 
8930 	u8         reserved_at_160[0x80];
8931 
8932 	u8         reserved_at_1e0[0x18];
8933 	u8         match_criteria_enable[0x8];
8934 
8935 	struct mlx5_ifc_fte_match_param_bits match_criteria;
8936 
8937 	u8         reserved_at_1200[0xe00];
8938 };
8939 
8940 struct mlx5_ifc_create_eq_out_bits {
8941 	u8         status[0x8];
8942 	u8         reserved_at_8[0x18];
8943 
8944 	u8         syndrome[0x20];
8945 
8946 	u8         reserved_at_40[0x18];
8947 	u8         eq_number[0x8];
8948 
8949 	u8         reserved_at_60[0x20];
8950 };
8951 
8952 struct mlx5_ifc_create_eq_in_bits {
8953 	u8         opcode[0x10];
8954 	u8         uid[0x10];
8955 
8956 	u8         reserved_at_20[0x10];
8957 	u8         op_mod[0x10];
8958 
8959 	u8         reserved_at_40[0x40];
8960 
8961 	struct mlx5_ifc_eqc_bits eq_context_entry;
8962 
8963 	u8         reserved_at_280[0x40];
8964 
8965 	u8         event_bitmask[4][0x40];
8966 
8967 	u8         reserved_at_3c0[0x4c0];
8968 
8969 	u8         pas[][0x40];
8970 };
8971 
8972 struct mlx5_ifc_create_dct_out_bits {
8973 	u8         status[0x8];
8974 	u8         reserved_at_8[0x18];
8975 
8976 	u8         syndrome[0x20];
8977 
8978 	u8         reserved_at_40[0x8];
8979 	u8         dctn[0x18];
8980 
8981 	u8         ece[0x20];
8982 };
8983 
8984 struct mlx5_ifc_create_dct_in_bits {
8985 	u8         opcode[0x10];
8986 	u8         uid[0x10];
8987 
8988 	u8         reserved_at_20[0x10];
8989 	u8         op_mod[0x10];
8990 
8991 	u8         reserved_at_40[0x40];
8992 
8993 	struct mlx5_ifc_dctc_bits dct_context_entry;
8994 
8995 	u8         reserved_at_280[0x180];
8996 };
8997 
8998 struct mlx5_ifc_create_cq_out_bits {
8999 	u8         status[0x8];
9000 	u8         reserved_at_8[0x18];
9001 
9002 	u8         syndrome[0x20];
9003 
9004 	u8         reserved_at_40[0x8];
9005 	u8         cqn[0x18];
9006 
9007 	u8         reserved_at_60[0x20];
9008 };
9009 
9010 struct mlx5_ifc_create_cq_in_bits {
9011 	u8         opcode[0x10];
9012 	u8         uid[0x10];
9013 
9014 	u8         reserved_at_20[0x10];
9015 	u8         op_mod[0x10];
9016 
9017 	u8         reserved_at_40[0x40];
9018 
9019 	struct mlx5_ifc_cqc_bits cq_context;
9020 
9021 	u8         reserved_at_280[0x60];
9022 
9023 	u8         cq_umem_valid[0x1];
9024 	u8         reserved_at_2e1[0x59f];
9025 
9026 	u8         pas[][0x40];
9027 };
9028 
9029 struct mlx5_ifc_config_int_moderation_out_bits {
9030 	u8         status[0x8];
9031 	u8         reserved_at_8[0x18];
9032 
9033 	u8         syndrome[0x20];
9034 
9035 	u8         reserved_at_40[0x4];
9036 	u8         min_delay[0xc];
9037 	u8         int_vector[0x10];
9038 
9039 	u8         reserved_at_60[0x20];
9040 };
9041 
9042 enum {
9043 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
9044 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
9045 };
9046 
9047 struct mlx5_ifc_config_int_moderation_in_bits {
9048 	u8         opcode[0x10];
9049 	u8         reserved_at_10[0x10];
9050 
9051 	u8         reserved_at_20[0x10];
9052 	u8         op_mod[0x10];
9053 
9054 	u8         reserved_at_40[0x4];
9055 	u8         min_delay[0xc];
9056 	u8         int_vector[0x10];
9057 
9058 	u8         reserved_at_60[0x20];
9059 };
9060 
9061 struct mlx5_ifc_attach_to_mcg_out_bits {
9062 	u8         status[0x8];
9063 	u8         reserved_at_8[0x18];
9064 
9065 	u8         syndrome[0x20];
9066 
9067 	u8         reserved_at_40[0x40];
9068 };
9069 
9070 struct mlx5_ifc_attach_to_mcg_in_bits {
9071 	u8         opcode[0x10];
9072 	u8         uid[0x10];
9073 
9074 	u8         reserved_at_20[0x10];
9075 	u8         op_mod[0x10];
9076 
9077 	u8         reserved_at_40[0x8];
9078 	u8         qpn[0x18];
9079 
9080 	u8         reserved_at_60[0x20];
9081 
9082 	u8         multicast_gid[16][0x8];
9083 };
9084 
9085 struct mlx5_ifc_arm_xrq_out_bits {
9086 	u8         status[0x8];
9087 	u8         reserved_at_8[0x18];
9088 
9089 	u8         syndrome[0x20];
9090 
9091 	u8         reserved_at_40[0x40];
9092 };
9093 
9094 struct mlx5_ifc_arm_xrq_in_bits {
9095 	u8         opcode[0x10];
9096 	u8         reserved_at_10[0x10];
9097 
9098 	u8         reserved_at_20[0x10];
9099 	u8         op_mod[0x10];
9100 
9101 	u8         reserved_at_40[0x8];
9102 	u8         xrqn[0x18];
9103 
9104 	u8         reserved_at_60[0x10];
9105 	u8         lwm[0x10];
9106 };
9107 
9108 struct mlx5_ifc_arm_xrc_srq_out_bits {
9109 	u8         status[0x8];
9110 	u8         reserved_at_8[0x18];
9111 
9112 	u8         syndrome[0x20];
9113 
9114 	u8         reserved_at_40[0x40];
9115 };
9116 
9117 enum {
9118 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
9119 };
9120 
9121 struct mlx5_ifc_arm_xrc_srq_in_bits {
9122 	u8         opcode[0x10];
9123 	u8         uid[0x10];
9124 
9125 	u8         reserved_at_20[0x10];
9126 	u8         op_mod[0x10];
9127 
9128 	u8         reserved_at_40[0x8];
9129 	u8         xrc_srqn[0x18];
9130 
9131 	u8         reserved_at_60[0x10];
9132 	u8         lwm[0x10];
9133 };
9134 
9135 struct mlx5_ifc_arm_rq_out_bits {
9136 	u8         status[0x8];
9137 	u8         reserved_at_8[0x18];
9138 
9139 	u8         syndrome[0x20];
9140 
9141 	u8         reserved_at_40[0x40];
9142 };
9143 
9144 enum {
9145 	MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
9146 	MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
9147 };
9148 
9149 struct mlx5_ifc_arm_rq_in_bits {
9150 	u8         opcode[0x10];
9151 	u8         uid[0x10];
9152 
9153 	u8         reserved_at_20[0x10];
9154 	u8         op_mod[0x10];
9155 
9156 	u8         reserved_at_40[0x8];
9157 	u8         srq_number[0x18];
9158 
9159 	u8         reserved_at_60[0x10];
9160 	u8         lwm[0x10];
9161 };
9162 
9163 struct mlx5_ifc_arm_dct_out_bits {
9164 	u8         status[0x8];
9165 	u8         reserved_at_8[0x18];
9166 
9167 	u8         syndrome[0x20];
9168 
9169 	u8         reserved_at_40[0x40];
9170 };
9171 
9172 struct mlx5_ifc_arm_dct_in_bits {
9173 	u8         opcode[0x10];
9174 	u8         reserved_at_10[0x10];
9175 
9176 	u8         reserved_at_20[0x10];
9177 	u8         op_mod[0x10];
9178 
9179 	u8         reserved_at_40[0x8];
9180 	u8         dct_number[0x18];
9181 
9182 	u8         reserved_at_60[0x20];
9183 };
9184 
9185 struct mlx5_ifc_alloc_xrcd_out_bits {
9186 	u8         status[0x8];
9187 	u8         reserved_at_8[0x18];
9188 
9189 	u8         syndrome[0x20];
9190 
9191 	u8         reserved_at_40[0x8];
9192 	u8         xrcd[0x18];
9193 
9194 	u8         reserved_at_60[0x20];
9195 };
9196 
9197 struct mlx5_ifc_alloc_xrcd_in_bits {
9198 	u8         opcode[0x10];
9199 	u8         uid[0x10];
9200 
9201 	u8         reserved_at_20[0x10];
9202 	u8         op_mod[0x10];
9203 
9204 	u8         reserved_at_40[0x40];
9205 };
9206 
9207 struct mlx5_ifc_alloc_uar_out_bits {
9208 	u8         status[0x8];
9209 	u8         reserved_at_8[0x18];
9210 
9211 	u8         syndrome[0x20];
9212 
9213 	u8         reserved_at_40[0x8];
9214 	u8         uar[0x18];
9215 
9216 	u8         reserved_at_60[0x20];
9217 };
9218 
9219 struct mlx5_ifc_alloc_uar_in_bits {
9220 	u8         opcode[0x10];
9221 	u8         uid[0x10];
9222 
9223 	u8         reserved_at_20[0x10];
9224 	u8         op_mod[0x10];
9225 
9226 	u8         reserved_at_40[0x40];
9227 };
9228 
9229 struct mlx5_ifc_alloc_transport_domain_out_bits {
9230 	u8         status[0x8];
9231 	u8         reserved_at_8[0x18];
9232 
9233 	u8         syndrome[0x20];
9234 
9235 	u8         reserved_at_40[0x8];
9236 	u8         transport_domain[0x18];
9237 
9238 	u8         reserved_at_60[0x20];
9239 };
9240 
9241 struct mlx5_ifc_alloc_transport_domain_in_bits {
9242 	u8         opcode[0x10];
9243 	u8         uid[0x10];
9244 
9245 	u8         reserved_at_20[0x10];
9246 	u8         op_mod[0x10];
9247 
9248 	u8         reserved_at_40[0x40];
9249 };
9250 
9251 struct mlx5_ifc_alloc_q_counter_out_bits {
9252 	u8         status[0x8];
9253 	u8         reserved_at_8[0x18];
9254 
9255 	u8         syndrome[0x20];
9256 
9257 	u8         reserved_at_40[0x18];
9258 	u8         counter_set_id[0x8];
9259 
9260 	u8         reserved_at_60[0x20];
9261 };
9262 
9263 struct mlx5_ifc_alloc_q_counter_in_bits {
9264 	u8         opcode[0x10];
9265 	u8         uid[0x10];
9266 
9267 	u8         reserved_at_20[0x10];
9268 	u8         op_mod[0x10];
9269 
9270 	u8         reserved_at_40[0x40];
9271 };
9272 
9273 struct mlx5_ifc_alloc_pd_out_bits {
9274 	u8         status[0x8];
9275 	u8         reserved_at_8[0x18];
9276 
9277 	u8         syndrome[0x20];
9278 
9279 	u8         reserved_at_40[0x8];
9280 	u8         pd[0x18];
9281 
9282 	u8         reserved_at_60[0x20];
9283 };
9284 
9285 struct mlx5_ifc_alloc_pd_in_bits {
9286 	u8         opcode[0x10];
9287 	u8         uid[0x10];
9288 
9289 	u8         reserved_at_20[0x10];
9290 	u8         op_mod[0x10];
9291 
9292 	u8         reserved_at_40[0x40];
9293 };
9294 
9295 struct mlx5_ifc_alloc_flow_counter_out_bits {
9296 	u8         status[0x8];
9297 	u8         reserved_at_8[0x18];
9298 
9299 	u8         syndrome[0x20];
9300 
9301 	u8         flow_counter_id[0x20];
9302 
9303 	u8         reserved_at_60[0x20];
9304 };
9305 
9306 struct mlx5_ifc_alloc_flow_counter_in_bits {
9307 	u8         opcode[0x10];
9308 	u8         reserved_at_10[0x10];
9309 
9310 	u8         reserved_at_20[0x10];
9311 	u8         op_mod[0x10];
9312 
9313 	u8         reserved_at_40[0x33];
9314 	u8         flow_counter_bulk_log_size[0x5];
9315 	u8         flow_counter_bulk[0x8];
9316 };
9317 
9318 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
9319 	u8         status[0x8];
9320 	u8         reserved_at_8[0x18];
9321 
9322 	u8         syndrome[0x20];
9323 
9324 	u8         reserved_at_40[0x40];
9325 };
9326 
9327 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
9328 	u8         opcode[0x10];
9329 	u8         reserved_at_10[0x10];
9330 
9331 	u8         reserved_at_20[0x10];
9332 	u8         op_mod[0x10];
9333 
9334 	u8         reserved_at_40[0x20];
9335 
9336 	u8         reserved_at_60[0x10];
9337 	u8         vxlan_udp_port[0x10];
9338 };
9339 
9340 struct mlx5_ifc_set_pp_rate_limit_out_bits {
9341 	u8         status[0x8];
9342 	u8         reserved_at_8[0x18];
9343 
9344 	u8         syndrome[0x20];
9345 
9346 	u8         reserved_at_40[0x40];
9347 };
9348 
9349 struct mlx5_ifc_set_pp_rate_limit_context_bits {
9350 	u8         rate_limit[0x20];
9351 
9352 	u8	   burst_upper_bound[0x20];
9353 
9354 	u8         reserved_at_40[0x10];
9355 	u8	   typical_packet_size[0x10];
9356 
9357 	u8         reserved_at_60[0x120];
9358 };
9359 
9360 struct mlx5_ifc_set_pp_rate_limit_in_bits {
9361 	u8         opcode[0x10];
9362 	u8         uid[0x10];
9363 
9364 	u8         reserved_at_20[0x10];
9365 	u8         op_mod[0x10];
9366 
9367 	u8         reserved_at_40[0x10];
9368 	u8         rate_limit_index[0x10];
9369 
9370 	u8         reserved_at_60[0x20];
9371 
9372 	struct mlx5_ifc_set_pp_rate_limit_context_bits ctx;
9373 };
9374 
9375 struct mlx5_ifc_access_register_out_bits {
9376 	u8         status[0x8];
9377 	u8         reserved_at_8[0x18];
9378 
9379 	u8         syndrome[0x20];
9380 
9381 	u8         reserved_at_40[0x40];
9382 
9383 	u8         register_data[][0x20];
9384 };
9385 
9386 enum {
9387 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
9388 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
9389 };
9390 
9391 struct mlx5_ifc_access_register_in_bits {
9392 	u8         opcode[0x10];
9393 	u8         reserved_at_10[0x10];
9394 
9395 	u8         reserved_at_20[0x10];
9396 	u8         op_mod[0x10];
9397 
9398 	u8         reserved_at_40[0x10];
9399 	u8         register_id[0x10];
9400 
9401 	u8         argument[0x20];
9402 
9403 	u8         register_data[][0x20];
9404 };
9405 
9406 struct mlx5_ifc_sltp_reg_bits {
9407 	u8         status[0x4];
9408 	u8         version[0x4];
9409 	u8         local_port[0x8];
9410 	u8         pnat[0x2];
9411 	u8         reserved_at_12[0x2];
9412 	u8         lane[0x4];
9413 	u8         reserved_at_18[0x8];
9414 
9415 	u8         reserved_at_20[0x20];
9416 
9417 	u8         reserved_at_40[0x7];
9418 	u8         polarity[0x1];
9419 	u8         ob_tap0[0x8];
9420 	u8         ob_tap1[0x8];
9421 	u8         ob_tap2[0x8];
9422 
9423 	u8         reserved_at_60[0xc];
9424 	u8         ob_preemp_mode[0x4];
9425 	u8         ob_reg[0x8];
9426 	u8         ob_bias[0x8];
9427 
9428 	u8         reserved_at_80[0x20];
9429 };
9430 
9431 struct mlx5_ifc_slrg_reg_bits {
9432 	u8         status[0x4];
9433 	u8         version[0x4];
9434 	u8         local_port[0x8];
9435 	u8         pnat[0x2];
9436 	u8         reserved_at_12[0x2];
9437 	u8         lane[0x4];
9438 	u8         reserved_at_18[0x8];
9439 
9440 	u8         time_to_link_up[0x10];
9441 	u8         reserved_at_30[0xc];
9442 	u8         grade_lane_speed[0x4];
9443 
9444 	u8         grade_version[0x8];
9445 	u8         grade[0x18];
9446 
9447 	u8         reserved_at_60[0x4];
9448 	u8         height_grade_type[0x4];
9449 	u8         height_grade[0x18];
9450 
9451 	u8         height_dz[0x10];
9452 	u8         height_dv[0x10];
9453 
9454 	u8         reserved_at_a0[0x10];
9455 	u8         height_sigma[0x10];
9456 
9457 	u8         reserved_at_c0[0x20];
9458 
9459 	u8         reserved_at_e0[0x4];
9460 	u8         phase_grade_type[0x4];
9461 	u8         phase_grade[0x18];
9462 
9463 	u8         reserved_at_100[0x8];
9464 	u8         phase_eo_pos[0x8];
9465 	u8         reserved_at_110[0x8];
9466 	u8         phase_eo_neg[0x8];
9467 
9468 	u8         ffe_set_tested[0x10];
9469 	u8         test_errors_per_lane[0x10];
9470 };
9471 
9472 struct mlx5_ifc_pvlc_reg_bits {
9473 	u8         reserved_at_0[0x8];
9474 	u8         local_port[0x8];
9475 	u8         reserved_at_10[0x10];
9476 
9477 	u8         reserved_at_20[0x1c];
9478 	u8         vl_hw_cap[0x4];
9479 
9480 	u8         reserved_at_40[0x1c];
9481 	u8         vl_admin[0x4];
9482 
9483 	u8         reserved_at_60[0x1c];
9484 	u8         vl_operational[0x4];
9485 };
9486 
9487 struct mlx5_ifc_pude_reg_bits {
9488 	u8         swid[0x8];
9489 	u8         local_port[0x8];
9490 	u8         reserved_at_10[0x4];
9491 	u8         admin_status[0x4];
9492 	u8         reserved_at_18[0x4];
9493 	u8         oper_status[0x4];
9494 
9495 	u8         reserved_at_20[0x60];
9496 };
9497 
9498 struct mlx5_ifc_ptys_reg_bits {
9499 	u8         reserved_at_0[0x1];
9500 	u8         an_disable_admin[0x1];
9501 	u8         an_disable_cap[0x1];
9502 	u8         reserved_at_3[0x5];
9503 	u8         local_port[0x8];
9504 	u8         reserved_at_10[0xd];
9505 	u8         proto_mask[0x3];
9506 
9507 	u8         an_status[0x4];
9508 	u8         reserved_at_24[0xc];
9509 	u8         data_rate_oper[0x10];
9510 
9511 	u8         ext_eth_proto_capability[0x20];
9512 
9513 	u8         eth_proto_capability[0x20];
9514 
9515 	u8         ib_link_width_capability[0x10];
9516 	u8         ib_proto_capability[0x10];
9517 
9518 	u8         ext_eth_proto_admin[0x20];
9519 
9520 	u8         eth_proto_admin[0x20];
9521 
9522 	u8         ib_link_width_admin[0x10];
9523 	u8         ib_proto_admin[0x10];
9524 
9525 	u8         ext_eth_proto_oper[0x20];
9526 
9527 	u8         eth_proto_oper[0x20];
9528 
9529 	u8         ib_link_width_oper[0x10];
9530 	u8         ib_proto_oper[0x10];
9531 
9532 	u8         reserved_at_160[0x1c];
9533 	u8         connector_type[0x4];
9534 
9535 	u8         eth_proto_lp_advertise[0x20];
9536 
9537 	u8         reserved_at_1a0[0x60];
9538 };
9539 
9540 struct mlx5_ifc_mlcr_reg_bits {
9541 	u8         reserved_at_0[0x8];
9542 	u8         local_port[0x8];
9543 	u8         reserved_at_10[0x20];
9544 
9545 	u8         beacon_duration[0x10];
9546 	u8         reserved_at_40[0x10];
9547 
9548 	u8         beacon_remain[0x10];
9549 };
9550 
9551 struct mlx5_ifc_ptas_reg_bits {
9552 	u8         reserved_at_0[0x20];
9553 
9554 	u8         algorithm_options[0x10];
9555 	u8         reserved_at_30[0x4];
9556 	u8         repetitions_mode[0x4];
9557 	u8         num_of_repetitions[0x8];
9558 
9559 	u8         grade_version[0x8];
9560 	u8         height_grade_type[0x4];
9561 	u8         phase_grade_type[0x4];
9562 	u8         height_grade_weight[0x8];
9563 	u8         phase_grade_weight[0x8];
9564 
9565 	u8         gisim_measure_bits[0x10];
9566 	u8         adaptive_tap_measure_bits[0x10];
9567 
9568 	u8         ber_bath_high_error_threshold[0x10];
9569 	u8         ber_bath_mid_error_threshold[0x10];
9570 
9571 	u8         ber_bath_low_error_threshold[0x10];
9572 	u8         one_ratio_high_threshold[0x10];
9573 
9574 	u8         one_ratio_high_mid_threshold[0x10];
9575 	u8         one_ratio_low_mid_threshold[0x10];
9576 
9577 	u8         one_ratio_low_threshold[0x10];
9578 	u8         ndeo_error_threshold[0x10];
9579 
9580 	u8         mixer_offset_step_size[0x10];
9581 	u8         reserved_at_110[0x8];
9582 	u8         mix90_phase_for_voltage_bath[0x8];
9583 
9584 	u8         mixer_offset_start[0x10];
9585 	u8         mixer_offset_end[0x10];
9586 
9587 	u8         reserved_at_140[0x15];
9588 	u8         ber_test_time[0xb];
9589 };
9590 
9591 struct mlx5_ifc_pspa_reg_bits {
9592 	u8         swid[0x8];
9593 	u8         local_port[0x8];
9594 	u8         sub_port[0x8];
9595 	u8         reserved_at_18[0x8];
9596 
9597 	u8         reserved_at_20[0x20];
9598 };
9599 
9600 struct mlx5_ifc_pqdr_reg_bits {
9601 	u8         reserved_at_0[0x8];
9602 	u8         local_port[0x8];
9603 	u8         reserved_at_10[0x5];
9604 	u8         prio[0x3];
9605 	u8         reserved_at_18[0x6];
9606 	u8         mode[0x2];
9607 
9608 	u8         reserved_at_20[0x20];
9609 
9610 	u8         reserved_at_40[0x10];
9611 	u8         min_threshold[0x10];
9612 
9613 	u8         reserved_at_60[0x10];
9614 	u8         max_threshold[0x10];
9615 
9616 	u8         reserved_at_80[0x10];
9617 	u8         mark_probability_denominator[0x10];
9618 
9619 	u8         reserved_at_a0[0x60];
9620 };
9621 
9622 struct mlx5_ifc_ppsc_reg_bits {
9623 	u8         reserved_at_0[0x8];
9624 	u8         local_port[0x8];
9625 	u8         reserved_at_10[0x10];
9626 
9627 	u8         reserved_at_20[0x60];
9628 
9629 	u8         reserved_at_80[0x1c];
9630 	u8         wrps_admin[0x4];
9631 
9632 	u8         reserved_at_a0[0x1c];
9633 	u8         wrps_status[0x4];
9634 
9635 	u8         reserved_at_c0[0x8];
9636 	u8         up_threshold[0x8];
9637 	u8         reserved_at_d0[0x8];
9638 	u8         down_threshold[0x8];
9639 
9640 	u8         reserved_at_e0[0x20];
9641 
9642 	u8         reserved_at_100[0x1c];
9643 	u8         srps_admin[0x4];
9644 
9645 	u8         reserved_at_120[0x1c];
9646 	u8         srps_status[0x4];
9647 
9648 	u8         reserved_at_140[0x40];
9649 };
9650 
9651 struct mlx5_ifc_pplr_reg_bits {
9652 	u8         reserved_at_0[0x8];
9653 	u8         local_port[0x8];
9654 	u8         reserved_at_10[0x10];
9655 
9656 	u8         reserved_at_20[0x8];
9657 	u8         lb_cap[0x8];
9658 	u8         reserved_at_30[0x8];
9659 	u8         lb_en[0x8];
9660 };
9661 
9662 struct mlx5_ifc_pplm_reg_bits {
9663 	u8         reserved_at_0[0x8];
9664 	u8	   local_port[0x8];
9665 	u8	   reserved_at_10[0x10];
9666 
9667 	u8	   reserved_at_20[0x20];
9668 
9669 	u8	   port_profile_mode[0x8];
9670 	u8	   static_port_profile[0x8];
9671 	u8	   active_port_profile[0x8];
9672 	u8	   reserved_at_58[0x8];
9673 
9674 	u8	   retransmission_active[0x8];
9675 	u8	   fec_mode_active[0x18];
9676 
9677 	u8	   rs_fec_correction_bypass_cap[0x4];
9678 	u8	   reserved_at_84[0x8];
9679 	u8	   fec_override_cap_56g[0x4];
9680 	u8	   fec_override_cap_100g[0x4];
9681 	u8	   fec_override_cap_50g[0x4];
9682 	u8	   fec_override_cap_25g[0x4];
9683 	u8	   fec_override_cap_10g_40g[0x4];
9684 
9685 	u8	   rs_fec_correction_bypass_admin[0x4];
9686 	u8	   reserved_at_a4[0x8];
9687 	u8	   fec_override_admin_56g[0x4];
9688 	u8	   fec_override_admin_100g[0x4];
9689 	u8	   fec_override_admin_50g[0x4];
9690 	u8	   fec_override_admin_25g[0x4];
9691 	u8	   fec_override_admin_10g_40g[0x4];
9692 
9693 	u8         fec_override_cap_400g_8x[0x10];
9694 	u8         fec_override_cap_200g_4x[0x10];
9695 
9696 	u8         fec_override_cap_100g_2x[0x10];
9697 	u8         fec_override_cap_50g_1x[0x10];
9698 
9699 	u8         fec_override_admin_400g_8x[0x10];
9700 	u8         fec_override_admin_200g_4x[0x10];
9701 
9702 	u8         fec_override_admin_100g_2x[0x10];
9703 	u8         fec_override_admin_50g_1x[0x10];
9704 
9705 	u8         reserved_at_140[0x140];
9706 };
9707 
9708 struct mlx5_ifc_ppcnt_reg_bits {
9709 	u8         swid[0x8];
9710 	u8         local_port[0x8];
9711 	u8         pnat[0x2];
9712 	u8         reserved_at_12[0x8];
9713 	u8         grp[0x6];
9714 
9715 	u8         clr[0x1];
9716 	u8         reserved_at_21[0x1c];
9717 	u8         prio_tc[0x3];
9718 
9719 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
9720 };
9721 
9722 struct mlx5_ifc_mpein_reg_bits {
9723 	u8         reserved_at_0[0x2];
9724 	u8         depth[0x6];
9725 	u8         pcie_index[0x8];
9726 	u8         node[0x8];
9727 	u8         reserved_at_18[0x8];
9728 
9729 	u8         capability_mask[0x20];
9730 
9731 	u8         reserved_at_40[0x8];
9732 	u8         link_width_enabled[0x8];
9733 	u8         link_speed_enabled[0x10];
9734 
9735 	u8         lane0_physical_position[0x8];
9736 	u8         link_width_active[0x8];
9737 	u8         link_speed_active[0x10];
9738 
9739 	u8         num_of_pfs[0x10];
9740 	u8         num_of_vfs[0x10];
9741 
9742 	u8         bdf0[0x10];
9743 	u8         reserved_at_b0[0x10];
9744 
9745 	u8         max_read_request_size[0x4];
9746 	u8         max_payload_size[0x4];
9747 	u8         reserved_at_c8[0x5];
9748 	u8         pwr_status[0x3];
9749 	u8         port_type[0x4];
9750 	u8         reserved_at_d4[0xb];
9751 	u8         lane_reversal[0x1];
9752 
9753 	u8         reserved_at_e0[0x14];
9754 	u8         pci_power[0xc];
9755 
9756 	u8         reserved_at_100[0x20];
9757 
9758 	u8         device_status[0x10];
9759 	u8         port_state[0x8];
9760 	u8         reserved_at_138[0x8];
9761 
9762 	u8         reserved_at_140[0x10];
9763 	u8         receiver_detect_result[0x10];
9764 
9765 	u8         reserved_at_160[0x20];
9766 };
9767 
9768 struct mlx5_ifc_mpcnt_reg_bits {
9769 	u8         reserved_at_0[0x8];
9770 	u8         pcie_index[0x8];
9771 	u8         reserved_at_10[0xa];
9772 	u8         grp[0x6];
9773 
9774 	u8         clr[0x1];
9775 	u8         reserved_at_21[0x1f];
9776 
9777 	union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
9778 };
9779 
9780 struct mlx5_ifc_ppad_reg_bits {
9781 	u8         reserved_at_0[0x3];
9782 	u8         single_mac[0x1];
9783 	u8         reserved_at_4[0x4];
9784 	u8         local_port[0x8];
9785 	u8         mac_47_32[0x10];
9786 
9787 	u8         mac_31_0[0x20];
9788 
9789 	u8         reserved_at_40[0x40];
9790 };
9791 
9792 struct mlx5_ifc_pmtu_reg_bits {
9793 	u8         reserved_at_0[0x8];
9794 	u8         local_port[0x8];
9795 	u8         reserved_at_10[0x10];
9796 
9797 	u8         max_mtu[0x10];
9798 	u8         reserved_at_30[0x10];
9799 
9800 	u8         admin_mtu[0x10];
9801 	u8         reserved_at_50[0x10];
9802 
9803 	u8         oper_mtu[0x10];
9804 	u8         reserved_at_70[0x10];
9805 };
9806 
9807 struct mlx5_ifc_pmpr_reg_bits {
9808 	u8         reserved_at_0[0x8];
9809 	u8         module[0x8];
9810 	u8         reserved_at_10[0x10];
9811 
9812 	u8         reserved_at_20[0x18];
9813 	u8         attenuation_5g[0x8];
9814 
9815 	u8         reserved_at_40[0x18];
9816 	u8         attenuation_7g[0x8];
9817 
9818 	u8         reserved_at_60[0x18];
9819 	u8         attenuation_12g[0x8];
9820 };
9821 
9822 struct mlx5_ifc_pmpe_reg_bits {
9823 	u8         reserved_at_0[0x8];
9824 	u8         module[0x8];
9825 	u8         reserved_at_10[0xc];
9826 	u8         module_status[0x4];
9827 
9828 	u8         reserved_at_20[0x60];
9829 };
9830 
9831 struct mlx5_ifc_pmpc_reg_bits {
9832 	u8         module_state_updated[32][0x8];
9833 };
9834 
9835 struct mlx5_ifc_pmlpn_reg_bits {
9836 	u8         reserved_at_0[0x4];
9837 	u8         mlpn_status[0x4];
9838 	u8         local_port[0x8];
9839 	u8         reserved_at_10[0x10];
9840 
9841 	u8         e[0x1];
9842 	u8         reserved_at_21[0x1f];
9843 };
9844 
9845 struct mlx5_ifc_pmlp_reg_bits {
9846 	u8         rxtx[0x1];
9847 	u8         reserved_at_1[0x7];
9848 	u8         local_port[0x8];
9849 	u8         reserved_at_10[0x8];
9850 	u8         width[0x8];
9851 
9852 	u8         lane0_module_mapping[0x20];
9853 
9854 	u8         lane1_module_mapping[0x20];
9855 
9856 	u8         lane2_module_mapping[0x20];
9857 
9858 	u8         lane3_module_mapping[0x20];
9859 
9860 	u8         reserved_at_a0[0x160];
9861 };
9862 
9863 struct mlx5_ifc_pmaos_reg_bits {
9864 	u8         reserved_at_0[0x8];
9865 	u8         module[0x8];
9866 	u8         reserved_at_10[0x4];
9867 	u8         admin_status[0x4];
9868 	u8         reserved_at_18[0x4];
9869 	u8         oper_status[0x4];
9870 
9871 	u8         ase[0x1];
9872 	u8         ee[0x1];
9873 	u8         reserved_at_22[0x1c];
9874 	u8         e[0x2];
9875 
9876 	u8         reserved_at_40[0x40];
9877 };
9878 
9879 struct mlx5_ifc_plpc_reg_bits {
9880 	u8         reserved_at_0[0x4];
9881 	u8         profile_id[0xc];
9882 	u8         reserved_at_10[0x4];
9883 	u8         proto_mask[0x4];
9884 	u8         reserved_at_18[0x8];
9885 
9886 	u8         reserved_at_20[0x10];
9887 	u8         lane_speed[0x10];
9888 
9889 	u8         reserved_at_40[0x17];
9890 	u8         lpbf[0x1];
9891 	u8         fec_mode_policy[0x8];
9892 
9893 	u8         retransmission_capability[0x8];
9894 	u8         fec_mode_capability[0x18];
9895 
9896 	u8         retransmission_support_admin[0x8];
9897 	u8         fec_mode_support_admin[0x18];
9898 
9899 	u8         retransmission_request_admin[0x8];
9900 	u8         fec_mode_request_admin[0x18];
9901 
9902 	u8         reserved_at_c0[0x80];
9903 };
9904 
9905 struct mlx5_ifc_plib_reg_bits {
9906 	u8         reserved_at_0[0x8];
9907 	u8         local_port[0x8];
9908 	u8         reserved_at_10[0x8];
9909 	u8         ib_port[0x8];
9910 
9911 	u8         reserved_at_20[0x60];
9912 };
9913 
9914 struct mlx5_ifc_plbf_reg_bits {
9915 	u8         reserved_at_0[0x8];
9916 	u8         local_port[0x8];
9917 	u8         reserved_at_10[0xd];
9918 	u8         lbf_mode[0x3];
9919 
9920 	u8         reserved_at_20[0x20];
9921 };
9922 
9923 struct mlx5_ifc_pipg_reg_bits {
9924 	u8         reserved_at_0[0x8];
9925 	u8         local_port[0x8];
9926 	u8         reserved_at_10[0x10];
9927 
9928 	u8         dic[0x1];
9929 	u8         reserved_at_21[0x19];
9930 	u8         ipg[0x4];
9931 	u8         reserved_at_3e[0x2];
9932 };
9933 
9934 struct mlx5_ifc_pifr_reg_bits {
9935 	u8         reserved_at_0[0x8];
9936 	u8         local_port[0x8];
9937 	u8         reserved_at_10[0x10];
9938 
9939 	u8         reserved_at_20[0xe0];
9940 
9941 	u8         port_filter[8][0x20];
9942 
9943 	u8         port_filter_update_en[8][0x20];
9944 };
9945 
9946 struct mlx5_ifc_pfcc_reg_bits {
9947 	u8         reserved_at_0[0x8];
9948 	u8         local_port[0x8];
9949 	u8         reserved_at_10[0xb];
9950 	u8         ppan_mask_n[0x1];
9951 	u8         minor_stall_mask[0x1];
9952 	u8         critical_stall_mask[0x1];
9953 	u8         reserved_at_1e[0x2];
9954 
9955 	u8         ppan[0x4];
9956 	u8         reserved_at_24[0x4];
9957 	u8         prio_mask_tx[0x8];
9958 	u8         reserved_at_30[0x8];
9959 	u8         prio_mask_rx[0x8];
9960 
9961 	u8         pptx[0x1];
9962 	u8         aptx[0x1];
9963 	u8         pptx_mask_n[0x1];
9964 	u8         reserved_at_43[0x5];
9965 	u8         pfctx[0x8];
9966 	u8         reserved_at_50[0x10];
9967 
9968 	u8         pprx[0x1];
9969 	u8         aprx[0x1];
9970 	u8         pprx_mask_n[0x1];
9971 	u8         reserved_at_63[0x5];
9972 	u8         pfcrx[0x8];
9973 	u8         reserved_at_70[0x10];
9974 
9975 	u8         device_stall_minor_watermark[0x10];
9976 	u8         device_stall_critical_watermark[0x10];
9977 
9978 	u8         reserved_at_a0[0x60];
9979 };
9980 
9981 struct mlx5_ifc_pelc_reg_bits {
9982 	u8         op[0x4];
9983 	u8         reserved_at_4[0x4];
9984 	u8         local_port[0x8];
9985 	u8         reserved_at_10[0x10];
9986 
9987 	u8         op_admin[0x8];
9988 	u8         op_capability[0x8];
9989 	u8         op_request[0x8];
9990 	u8         op_active[0x8];
9991 
9992 	u8         admin[0x40];
9993 
9994 	u8         capability[0x40];
9995 
9996 	u8         request[0x40];
9997 
9998 	u8         active[0x40];
9999 
10000 	u8         reserved_at_140[0x80];
10001 };
10002 
10003 struct mlx5_ifc_peir_reg_bits {
10004 	u8         reserved_at_0[0x8];
10005 	u8         local_port[0x8];
10006 	u8         reserved_at_10[0x10];
10007 
10008 	u8         reserved_at_20[0xc];
10009 	u8         error_count[0x4];
10010 	u8         reserved_at_30[0x10];
10011 
10012 	u8         reserved_at_40[0xc];
10013 	u8         lane[0x4];
10014 	u8         reserved_at_50[0x8];
10015 	u8         error_type[0x8];
10016 };
10017 
10018 struct mlx5_ifc_mpegc_reg_bits {
10019 	u8         reserved_at_0[0x30];
10020 	u8         field_select[0x10];
10021 
10022 	u8         tx_overflow_sense[0x1];
10023 	u8         mark_cqe[0x1];
10024 	u8         mark_cnp[0x1];
10025 	u8         reserved_at_43[0x1b];
10026 	u8         tx_lossy_overflow_oper[0x2];
10027 
10028 	u8         reserved_at_60[0x100];
10029 };
10030 
10031 enum {
10032 	MLX5_MTUTC_FREQ_ADJ_UNITS_PPB          = 0x0,
10033 	MLX5_MTUTC_FREQ_ADJ_UNITS_SCALED_PPM   = 0x1,
10034 };
10035 
10036 enum {
10037 	MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE   = 0x1,
10038 	MLX5_MTUTC_OPERATION_ADJUST_TIME          = 0x2,
10039 	MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC      = 0x3,
10040 };
10041 
10042 struct mlx5_ifc_mtutc_reg_bits {
10043 	u8         reserved_at_0[0x5];
10044 	u8         freq_adj_units[0x3];
10045 	u8         reserved_at_8[0x14];
10046 	u8         operation[0x4];
10047 
10048 	u8         freq_adjustment[0x20];
10049 
10050 	u8         reserved_at_40[0x40];
10051 
10052 	u8         utc_sec[0x20];
10053 
10054 	u8         reserved_at_a0[0x2];
10055 	u8         utc_nsec[0x1e];
10056 
10057 	u8         time_adjustment[0x20];
10058 };
10059 
10060 struct mlx5_ifc_pcam_enhanced_features_bits {
10061 	u8         reserved_at_0[0x68];
10062 	u8         fec_50G_per_lane_in_pplm[0x1];
10063 	u8         reserved_at_69[0x4];
10064 	u8         rx_icrc_encapsulated_counter[0x1];
10065 	u8	   reserved_at_6e[0x4];
10066 	u8         ptys_extended_ethernet[0x1];
10067 	u8	   reserved_at_73[0x3];
10068 	u8         pfcc_mask[0x1];
10069 	u8         reserved_at_77[0x3];
10070 	u8         per_lane_error_counters[0x1];
10071 	u8         rx_buffer_fullness_counters[0x1];
10072 	u8         ptys_connector_type[0x1];
10073 	u8         reserved_at_7d[0x1];
10074 	u8         ppcnt_discard_group[0x1];
10075 	u8         ppcnt_statistical_group[0x1];
10076 };
10077 
10078 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
10079 	u8         port_access_reg_cap_mask_127_to_96[0x20];
10080 	u8         port_access_reg_cap_mask_95_to_64[0x20];
10081 
10082 	u8         port_access_reg_cap_mask_63_to_36[0x1c];
10083 	u8         pplm[0x1];
10084 	u8         port_access_reg_cap_mask_34_to_32[0x3];
10085 
10086 	u8         port_access_reg_cap_mask_31_to_13[0x13];
10087 	u8         pbmc[0x1];
10088 	u8         pptb[0x1];
10089 	u8         port_access_reg_cap_mask_10_to_09[0x2];
10090 	u8         ppcnt[0x1];
10091 	u8         port_access_reg_cap_mask_07_to_00[0x8];
10092 };
10093 
10094 struct mlx5_ifc_pcam_reg_bits {
10095 	u8         reserved_at_0[0x8];
10096 	u8         feature_group[0x8];
10097 	u8         reserved_at_10[0x8];
10098 	u8         access_reg_group[0x8];
10099 
10100 	u8         reserved_at_20[0x20];
10101 
10102 	union {
10103 		struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
10104 		u8         reserved_at_0[0x80];
10105 	} port_access_reg_cap_mask;
10106 
10107 	u8         reserved_at_c0[0x80];
10108 
10109 	union {
10110 		struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
10111 		u8         reserved_at_0[0x80];
10112 	} feature_cap_mask;
10113 
10114 	u8         reserved_at_1c0[0xc0];
10115 };
10116 
10117 struct mlx5_ifc_mcam_enhanced_features_bits {
10118 	u8         reserved_at_0[0x50];
10119 	u8         mtutc_freq_adj_units[0x1];
10120 	u8         mtutc_time_adjustment_extended_range[0x1];
10121 	u8         reserved_at_52[0xb];
10122 	u8         mcia_32dwords[0x1];
10123 	u8         out_pulse_duration_ns[0x1];
10124 	u8         npps_period[0x1];
10125 	u8         reserved_at_60[0xa];
10126 	u8         reset_state[0x1];
10127 	u8         ptpcyc2realtime_modify[0x1];
10128 	u8         reserved_at_6c[0x2];
10129 	u8         pci_status_and_power[0x1];
10130 	u8         reserved_at_6f[0x5];
10131 	u8         mark_tx_action_cnp[0x1];
10132 	u8         mark_tx_action_cqe[0x1];
10133 	u8         dynamic_tx_overflow[0x1];
10134 	u8         reserved_at_77[0x4];
10135 	u8         pcie_outbound_stalled[0x1];
10136 	u8         tx_overflow_buffer_pkt[0x1];
10137 	u8         mtpps_enh_out_per_adj[0x1];
10138 	u8         mtpps_fs[0x1];
10139 	u8         pcie_performance_group[0x1];
10140 };
10141 
10142 struct mlx5_ifc_mcam_access_reg_bits {
10143 	u8         reserved_at_0[0x1c];
10144 	u8         mcda[0x1];
10145 	u8         mcc[0x1];
10146 	u8         mcqi[0x1];
10147 	u8         mcqs[0x1];
10148 
10149 	u8         regs_95_to_87[0x9];
10150 	u8         mpegc[0x1];
10151 	u8         mtutc[0x1];
10152 	u8         regs_84_to_68[0x11];
10153 	u8         tracer_registers[0x4];
10154 
10155 	u8         regs_63_to_46[0x12];
10156 	u8         mrtc[0x1];
10157 	u8         regs_44_to_32[0xd];
10158 
10159 	u8         regs_31_to_10[0x16];
10160 	u8         mtmp[0x1];
10161 	u8         regs_8_to_0[0x9];
10162 };
10163 
10164 struct mlx5_ifc_mcam_access_reg_bits1 {
10165 	u8         regs_127_to_96[0x20];
10166 
10167 	u8         regs_95_to_64[0x20];
10168 
10169 	u8         regs_63_to_32[0x20];
10170 
10171 	u8         regs_31_to_0[0x20];
10172 };
10173 
10174 struct mlx5_ifc_mcam_access_reg_bits2 {
10175 	u8         regs_127_to_99[0x1d];
10176 	u8         mirc[0x1];
10177 	u8         regs_97_to_96[0x2];
10178 
10179 	u8         regs_95_to_64[0x20];
10180 
10181 	u8         regs_63_to_32[0x20];
10182 
10183 	u8         regs_31_to_0[0x20];
10184 };
10185 
10186 struct mlx5_ifc_mcam_reg_bits {
10187 	u8         reserved_at_0[0x8];
10188 	u8         feature_group[0x8];
10189 	u8         reserved_at_10[0x8];
10190 	u8         access_reg_group[0x8];
10191 
10192 	u8         reserved_at_20[0x20];
10193 
10194 	union {
10195 		struct mlx5_ifc_mcam_access_reg_bits access_regs;
10196 		struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
10197 		struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
10198 		u8         reserved_at_0[0x80];
10199 	} mng_access_reg_cap_mask;
10200 
10201 	u8         reserved_at_c0[0x80];
10202 
10203 	union {
10204 		struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
10205 		u8         reserved_at_0[0x80];
10206 	} mng_feature_cap_mask;
10207 
10208 	u8         reserved_at_1c0[0x80];
10209 };
10210 
10211 struct mlx5_ifc_qcam_access_reg_cap_mask {
10212 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
10213 	u8         qpdpm[0x1];
10214 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
10215 	u8         qdpm[0x1];
10216 	u8         qpts[0x1];
10217 	u8         qcap[0x1];
10218 	u8         qcam_access_reg_cap_mask_0[0x1];
10219 };
10220 
10221 struct mlx5_ifc_qcam_qos_feature_cap_mask {
10222 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
10223 	u8         qpts_trust_both[0x1];
10224 };
10225 
10226 struct mlx5_ifc_qcam_reg_bits {
10227 	u8         reserved_at_0[0x8];
10228 	u8         feature_group[0x8];
10229 	u8         reserved_at_10[0x8];
10230 	u8         access_reg_group[0x8];
10231 	u8         reserved_at_20[0x20];
10232 
10233 	union {
10234 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
10235 		u8  reserved_at_0[0x80];
10236 	} qos_access_reg_cap_mask;
10237 
10238 	u8         reserved_at_c0[0x80];
10239 
10240 	union {
10241 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
10242 		u8  reserved_at_0[0x80];
10243 	} qos_feature_cap_mask;
10244 
10245 	u8         reserved_at_1c0[0x80];
10246 };
10247 
10248 struct mlx5_ifc_core_dump_reg_bits {
10249 	u8         reserved_at_0[0x18];
10250 	u8         core_dump_type[0x8];
10251 
10252 	u8         reserved_at_20[0x30];
10253 	u8         vhca_id[0x10];
10254 
10255 	u8         reserved_at_60[0x8];
10256 	u8         qpn[0x18];
10257 	u8         reserved_at_80[0x180];
10258 };
10259 
10260 struct mlx5_ifc_pcap_reg_bits {
10261 	u8         reserved_at_0[0x8];
10262 	u8         local_port[0x8];
10263 	u8         reserved_at_10[0x10];
10264 
10265 	u8         port_capability_mask[4][0x20];
10266 };
10267 
10268 struct mlx5_ifc_paos_reg_bits {
10269 	u8         swid[0x8];
10270 	u8         local_port[0x8];
10271 	u8         reserved_at_10[0x4];
10272 	u8         admin_status[0x4];
10273 	u8         reserved_at_18[0x4];
10274 	u8         oper_status[0x4];
10275 
10276 	u8         ase[0x1];
10277 	u8         ee[0x1];
10278 	u8         reserved_at_22[0x1c];
10279 	u8         e[0x2];
10280 
10281 	u8         reserved_at_40[0x40];
10282 };
10283 
10284 struct mlx5_ifc_pamp_reg_bits {
10285 	u8         reserved_at_0[0x8];
10286 	u8         opamp_group[0x8];
10287 	u8         reserved_at_10[0xc];
10288 	u8         opamp_group_type[0x4];
10289 
10290 	u8         start_index[0x10];
10291 	u8         reserved_at_30[0x4];
10292 	u8         num_of_indices[0xc];
10293 
10294 	u8         index_data[18][0x10];
10295 };
10296 
10297 struct mlx5_ifc_pcmr_reg_bits {
10298 	u8         reserved_at_0[0x8];
10299 	u8         local_port[0x8];
10300 	u8         reserved_at_10[0x10];
10301 
10302 	u8         entropy_force_cap[0x1];
10303 	u8         entropy_calc_cap[0x1];
10304 	u8         entropy_gre_calc_cap[0x1];
10305 	u8         reserved_at_23[0xf];
10306 	u8         rx_ts_over_crc_cap[0x1];
10307 	u8         reserved_at_33[0xb];
10308 	u8         fcs_cap[0x1];
10309 	u8         reserved_at_3f[0x1];
10310 
10311 	u8         entropy_force[0x1];
10312 	u8         entropy_calc[0x1];
10313 	u8         entropy_gre_calc[0x1];
10314 	u8         reserved_at_43[0xf];
10315 	u8         rx_ts_over_crc[0x1];
10316 	u8         reserved_at_53[0xb];
10317 	u8         fcs_chk[0x1];
10318 	u8         reserved_at_5f[0x1];
10319 };
10320 
10321 struct mlx5_ifc_lane_2_module_mapping_bits {
10322 	u8         reserved_at_0[0x4];
10323 	u8         rx_lane[0x4];
10324 	u8         reserved_at_8[0x4];
10325 	u8         tx_lane[0x4];
10326 	u8         reserved_at_10[0x8];
10327 	u8         module[0x8];
10328 };
10329 
10330 struct mlx5_ifc_bufferx_reg_bits {
10331 	u8         reserved_at_0[0x6];
10332 	u8         lossy[0x1];
10333 	u8         epsb[0x1];
10334 	u8         reserved_at_8[0x8];
10335 	u8         size[0x10];
10336 
10337 	u8         xoff_threshold[0x10];
10338 	u8         xon_threshold[0x10];
10339 };
10340 
10341 struct mlx5_ifc_set_node_in_bits {
10342 	u8         node_description[64][0x8];
10343 };
10344 
10345 struct mlx5_ifc_register_power_settings_bits {
10346 	u8         reserved_at_0[0x18];
10347 	u8         power_settings_level[0x8];
10348 
10349 	u8         reserved_at_20[0x60];
10350 };
10351 
10352 struct mlx5_ifc_register_host_endianness_bits {
10353 	u8         he[0x1];
10354 	u8         reserved_at_1[0x1f];
10355 
10356 	u8         reserved_at_20[0x60];
10357 };
10358 
10359 struct mlx5_ifc_umr_pointer_desc_argument_bits {
10360 	u8         reserved_at_0[0x20];
10361 
10362 	u8         mkey[0x20];
10363 
10364 	u8         addressh_63_32[0x20];
10365 
10366 	u8         addressl_31_0[0x20];
10367 };
10368 
10369 struct mlx5_ifc_ud_adrs_vector_bits {
10370 	u8         dc_key[0x40];
10371 
10372 	u8         ext[0x1];
10373 	u8         reserved_at_41[0x7];
10374 	u8         destination_qp_dct[0x18];
10375 
10376 	u8         static_rate[0x4];
10377 	u8         sl_eth_prio[0x4];
10378 	u8         fl[0x1];
10379 	u8         mlid[0x7];
10380 	u8         rlid_udp_sport[0x10];
10381 
10382 	u8         reserved_at_80[0x20];
10383 
10384 	u8         rmac_47_16[0x20];
10385 
10386 	u8         rmac_15_0[0x10];
10387 	u8         tclass[0x8];
10388 	u8         hop_limit[0x8];
10389 
10390 	u8         reserved_at_e0[0x1];
10391 	u8         grh[0x1];
10392 	u8         reserved_at_e2[0x2];
10393 	u8         src_addr_index[0x8];
10394 	u8         flow_label[0x14];
10395 
10396 	u8         rgid_rip[16][0x8];
10397 };
10398 
10399 struct mlx5_ifc_pages_req_event_bits {
10400 	u8         reserved_at_0[0x10];
10401 	u8         function_id[0x10];
10402 
10403 	u8         num_pages[0x20];
10404 
10405 	u8         reserved_at_40[0xa0];
10406 };
10407 
10408 struct mlx5_ifc_eqe_bits {
10409 	u8         reserved_at_0[0x8];
10410 	u8         event_type[0x8];
10411 	u8         reserved_at_10[0x8];
10412 	u8         event_sub_type[0x8];
10413 
10414 	u8         reserved_at_20[0xe0];
10415 
10416 	union mlx5_ifc_event_auto_bits event_data;
10417 
10418 	u8         reserved_at_1e0[0x10];
10419 	u8         signature[0x8];
10420 	u8         reserved_at_1f8[0x7];
10421 	u8         owner[0x1];
10422 };
10423 
10424 enum {
10425 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
10426 };
10427 
10428 struct mlx5_ifc_cmd_queue_entry_bits {
10429 	u8         type[0x8];
10430 	u8         reserved_at_8[0x18];
10431 
10432 	u8         input_length[0x20];
10433 
10434 	u8         input_mailbox_pointer_63_32[0x20];
10435 
10436 	u8         input_mailbox_pointer_31_9[0x17];
10437 	u8         reserved_at_77[0x9];
10438 
10439 	u8         command_input_inline_data[16][0x8];
10440 
10441 	u8         command_output_inline_data[16][0x8];
10442 
10443 	u8         output_mailbox_pointer_63_32[0x20];
10444 
10445 	u8         output_mailbox_pointer_31_9[0x17];
10446 	u8         reserved_at_1b7[0x9];
10447 
10448 	u8         output_length[0x20];
10449 
10450 	u8         token[0x8];
10451 	u8         signature[0x8];
10452 	u8         reserved_at_1f0[0x8];
10453 	u8         status[0x7];
10454 	u8         ownership[0x1];
10455 };
10456 
10457 struct mlx5_ifc_cmd_out_bits {
10458 	u8         status[0x8];
10459 	u8         reserved_at_8[0x18];
10460 
10461 	u8         syndrome[0x20];
10462 
10463 	u8         command_output[0x20];
10464 };
10465 
10466 struct mlx5_ifc_cmd_in_bits {
10467 	u8         opcode[0x10];
10468 	u8         reserved_at_10[0x10];
10469 
10470 	u8         reserved_at_20[0x10];
10471 	u8         op_mod[0x10];
10472 
10473 	u8         command[][0x20];
10474 };
10475 
10476 struct mlx5_ifc_cmd_if_box_bits {
10477 	u8         mailbox_data[512][0x8];
10478 
10479 	u8         reserved_at_1000[0x180];
10480 
10481 	u8         next_pointer_63_32[0x20];
10482 
10483 	u8         next_pointer_31_10[0x16];
10484 	u8         reserved_at_11b6[0xa];
10485 
10486 	u8         block_number[0x20];
10487 
10488 	u8         reserved_at_11e0[0x8];
10489 	u8         token[0x8];
10490 	u8         ctrl_signature[0x8];
10491 	u8         signature[0x8];
10492 };
10493 
10494 struct mlx5_ifc_mtt_bits {
10495 	u8         ptag_63_32[0x20];
10496 
10497 	u8         ptag_31_8[0x18];
10498 	u8         reserved_at_38[0x6];
10499 	u8         wr_en[0x1];
10500 	u8         rd_en[0x1];
10501 };
10502 
10503 struct mlx5_ifc_query_wol_rol_out_bits {
10504 	u8         status[0x8];
10505 	u8         reserved_at_8[0x18];
10506 
10507 	u8         syndrome[0x20];
10508 
10509 	u8         reserved_at_40[0x10];
10510 	u8         rol_mode[0x8];
10511 	u8         wol_mode[0x8];
10512 
10513 	u8         reserved_at_60[0x20];
10514 };
10515 
10516 struct mlx5_ifc_query_wol_rol_in_bits {
10517 	u8         opcode[0x10];
10518 	u8         reserved_at_10[0x10];
10519 
10520 	u8         reserved_at_20[0x10];
10521 	u8         op_mod[0x10];
10522 
10523 	u8         reserved_at_40[0x40];
10524 };
10525 
10526 struct mlx5_ifc_set_wol_rol_out_bits {
10527 	u8         status[0x8];
10528 	u8         reserved_at_8[0x18];
10529 
10530 	u8         syndrome[0x20];
10531 
10532 	u8         reserved_at_40[0x40];
10533 };
10534 
10535 struct mlx5_ifc_set_wol_rol_in_bits {
10536 	u8         opcode[0x10];
10537 	u8         reserved_at_10[0x10];
10538 
10539 	u8         reserved_at_20[0x10];
10540 	u8         op_mod[0x10];
10541 
10542 	u8         rol_mode_valid[0x1];
10543 	u8         wol_mode_valid[0x1];
10544 	u8         reserved_at_42[0xe];
10545 	u8         rol_mode[0x8];
10546 	u8         wol_mode[0x8];
10547 
10548 	u8         reserved_at_60[0x20];
10549 };
10550 
10551 enum {
10552 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
10553 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
10554 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
10555 };
10556 
10557 enum {
10558 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
10559 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
10560 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
10561 };
10562 
10563 enum {
10564 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
10565 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
10566 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
10567 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
10568 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
10569 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
10570 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
10571 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
10572 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
10573 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
10574 	MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
10575 };
10576 
10577 struct mlx5_ifc_initial_seg_bits {
10578 	u8         fw_rev_minor[0x10];
10579 	u8         fw_rev_major[0x10];
10580 
10581 	u8         cmd_interface_rev[0x10];
10582 	u8         fw_rev_subminor[0x10];
10583 
10584 	u8         reserved_at_40[0x40];
10585 
10586 	u8         cmdq_phy_addr_63_32[0x20];
10587 
10588 	u8         cmdq_phy_addr_31_12[0x14];
10589 	u8         reserved_at_b4[0x2];
10590 	u8         nic_interface[0x2];
10591 	u8         log_cmdq_size[0x4];
10592 	u8         log_cmdq_stride[0x4];
10593 
10594 	u8         command_doorbell_vector[0x20];
10595 
10596 	u8         reserved_at_e0[0xf00];
10597 
10598 	u8         initializing[0x1];
10599 	u8         reserved_at_fe1[0x4];
10600 	u8         nic_interface_supported[0x3];
10601 	u8         embedded_cpu[0x1];
10602 	u8         reserved_at_fe9[0x17];
10603 
10604 	struct mlx5_ifc_health_buffer_bits health_buffer;
10605 
10606 	u8         no_dram_nic_offset[0x20];
10607 
10608 	u8         reserved_at_1220[0x6e40];
10609 
10610 	u8         reserved_at_8060[0x1f];
10611 	u8         clear_int[0x1];
10612 
10613 	u8         health_syndrome[0x8];
10614 	u8         health_counter[0x18];
10615 
10616 	u8         reserved_at_80a0[0x17fc0];
10617 };
10618 
10619 struct mlx5_ifc_mtpps_reg_bits {
10620 	u8         reserved_at_0[0xc];
10621 	u8         cap_number_of_pps_pins[0x4];
10622 	u8         reserved_at_10[0x4];
10623 	u8         cap_max_num_of_pps_in_pins[0x4];
10624 	u8         reserved_at_18[0x4];
10625 	u8         cap_max_num_of_pps_out_pins[0x4];
10626 
10627 	u8         reserved_at_20[0x13];
10628 	u8         cap_log_min_npps_period[0x5];
10629 	u8         reserved_at_38[0x3];
10630 	u8         cap_log_min_out_pulse_duration_ns[0x5];
10631 
10632 	u8         reserved_at_40[0x4];
10633 	u8         cap_pin_3_mode[0x4];
10634 	u8         reserved_at_48[0x4];
10635 	u8         cap_pin_2_mode[0x4];
10636 	u8         reserved_at_50[0x4];
10637 	u8         cap_pin_1_mode[0x4];
10638 	u8         reserved_at_58[0x4];
10639 	u8         cap_pin_0_mode[0x4];
10640 
10641 	u8         reserved_at_60[0x4];
10642 	u8         cap_pin_7_mode[0x4];
10643 	u8         reserved_at_68[0x4];
10644 	u8         cap_pin_6_mode[0x4];
10645 	u8         reserved_at_70[0x4];
10646 	u8         cap_pin_5_mode[0x4];
10647 	u8         reserved_at_78[0x4];
10648 	u8         cap_pin_4_mode[0x4];
10649 
10650 	u8         field_select[0x20];
10651 	u8         reserved_at_a0[0x20];
10652 
10653 	u8         npps_period[0x40];
10654 
10655 	u8         enable[0x1];
10656 	u8         reserved_at_101[0xb];
10657 	u8         pattern[0x4];
10658 	u8         reserved_at_110[0x4];
10659 	u8         pin_mode[0x4];
10660 	u8         pin[0x8];
10661 
10662 	u8         reserved_at_120[0x2];
10663 	u8         out_pulse_duration_ns[0x1e];
10664 
10665 	u8         time_stamp[0x40];
10666 
10667 	u8         out_pulse_duration[0x10];
10668 	u8         out_periodic_adjustment[0x10];
10669 	u8         enhanced_out_periodic_adjustment[0x20];
10670 
10671 	u8         reserved_at_1c0[0x20];
10672 };
10673 
10674 struct mlx5_ifc_mtppse_reg_bits {
10675 	u8         reserved_at_0[0x18];
10676 	u8         pin[0x8];
10677 	u8         event_arm[0x1];
10678 	u8         reserved_at_21[0x1b];
10679 	u8         event_generation_mode[0x4];
10680 	u8         reserved_at_40[0x40];
10681 };
10682 
10683 struct mlx5_ifc_mcqs_reg_bits {
10684 	u8         last_index_flag[0x1];
10685 	u8         reserved_at_1[0x7];
10686 	u8         fw_device[0x8];
10687 	u8         component_index[0x10];
10688 
10689 	u8         reserved_at_20[0x10];
10690 	u8         identifier[0x10];
10691 
10692 	u8         reserved_at_40[0x17];
10693 	u8         component_status[0x5];
10694 	u8         component_update_state[0x4];
10695 
10696 	u8         last_update_state_changer_type[0x4];
10697 	u8         last_update_state_changer_host_id[0x4];
10698 	u8         reserved_at_68[0x18];
10699 };
10700 
10701 struct mlx5_ifc_mcqi_cap_bits {
10702 	u8         supported_info_bitmask[0x20];
10703 
10704 	u8         component_size[0x20];
10705 
10706 	u8         max_component_size[0x20];
10707 
10708 	u8         log_mcda_word_size[0x4];
10709 	u8         reserved_at_64[0xc];
10710 	u8         mcda_max_write_size[0x10];
10711 
10712 	u8         rd_en[0x1];
10713 	u8         reserved_at_81[0x1];
10714 	u8         match_chip_id[0x1];
10715 	u8         match_psid[0x1];
10716 	u8         check_user_timestamp[0x1];
10717 	u8         match_base_guid_mac[0x1];
10718 	u8         reserved_at_86[0x1a];
10719 };
10720 
10721 struct mlx5_ifc_mcqi_version_bits {
10722 	u8         reserved_at_0[0x2];
10723 	u8         build_time_valid[0x1];
10724 	u8         user_defined_time_valid[0x1];
10725 	u8         reserved_at_4[0x14];
10726 	u8         version_string_length[0x8];
10727 
10728 	u8         version[0x20];
10729 
10730 	u8         build_time[0x40];
10731 
10732 	u8         user_defined_time[0x40];
10733 
10734 	u8         build_tool_version[0x20];
10735 
10736 	u8         reserved_at_e0[0x20];
10737 
10738 	u8         version_string[92][0x8];
10739 };
10740 
10741 struct mlx5_ifc_mcqi_activation_method_bits {
10742 	u8         pending_server_ac_power_cycle[0x1];
10743 	u8         pending_server_dc_power_cycle[0x1];
10744 	u8         pending_server_reboot[0x1];
10745 	u8         pending_fw_reset[0x1];
10746 	u8         auto_activate[0x1];
10747 	u8         all_hosts_sync[0x1];
10748 	u8         device_hw_reset[0x1];
10749 	u8         reserved_at_7[0x19];
10750 };
10751 
10752 union mlx5_ifc_mcqi_reg_data_bits {
10753 	struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
10754 	struct mlx5_ifc_mcqi_version_bits           mcqi_version;
10755 	struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
10756 };
10757 
10758 struct mlx5_ifc_mcqi_reg_bits {
10759 	u8         read_pending_component[0x1];
10760 	u8         reserved_at_1[0xf];
10761 	u8         component_index[0x10];
10762 
10763 	u8         reserved_at_20[0x20];
10764 
10765 	u8         reserved_at_40[0x1b];
10766 	u8         info_type[0x5];
10767 
10768 	u8         info_size[0x20];
10769 
10770 	u8         offset[0x20];
10771 
10772 	u8         reserved_at_a0[0x10];
10773 	u8         data_size[0x10];
10774 
10775 	union mlx5_ifc_mcqi_reg_data_bits data[];
10776 };
10777 
10778 struct mlx5_ifc_mcc_reg_bits {
10779 	u8         reserved_at_0[0x4];
10780 	u8         time_elapsed_since_last_cmd[0xc];
10781 	u8         reserved_at_10[0x8];
10782 	u8         instruction[0x8];
10783 
10784 	u8         reserved_at_20[0x10];
10785 	u8         component_index[0x10];
10786 
10787 	u8         reserved_at_40[0x8];
10788 	u8         update_handle[0x18];
10789 
10790 	u8         handle_owner_type[0x4];
10791 	u8         handle_owner_host_id[0x4];
10792 	u8         reserved_at_68[0x1];
10793 	u8         control_progress[0x7];
10794 	u8         error_code[0x8];
10795 	u8         reserved_at_78[0x4];
10796 	u8         control_state[0x4];
10797 
10798 	u8         component_size[0x20];
10799 
10800 	u8         reserved_at_a0[0x60];
10801 };
10802 
10803 struct mlx5_ifc_mcda_reg_bits {
10804 	u8         reserved_at_0[0x8];
10805 	u8         update_handle[0x18];
10806 
10807 	u8         offset[0x20];
10808 
10809 	u8         reserved_at_40[0x10];
10810 	u8         size[0x10];
10811 
10812 	u8         reserved_at_60[0x20];
10813 
10814 	u8         data[][0x20];
10815 };
10816 
10817 enum {
10818 	MLX5_MFRL_REG_RESET_STATE_IDLE = 0,
10819 	MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1,
10820 	MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2,
10821 	MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT = 3,
10822 	MLX5_MFRL_REG_RESET_STATE_NACK = 4,
10823 	MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT = 5,
10824 };
10825 
10826 enum {
10827 	MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0),
10828 	MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1),
10829 };
10830 
10831 enum {
10832 	MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0),
10833 	MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3),
10834 	MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6),
10835 };
10836 
10837 struct mlx5_ifc_mfrl_reg_bits {
10838 	u8         reserved_at_0[0x20];
10839 
10840 	u8         reserved_at_20[0x2];
10841 	u8         pci_sync_for_fw_update_start[0x1];
10842 	u8         pci_sync_for_fw_update_resp[0x2];
10843 	u8         rst_type_sel[0x3];
10844 	u8         reserved_at_28[0x4];
10845 	u8         reset_state[0x4];
10846 	u8         reset_type[0x8];
10847 	u8         reset_level[0x8];
10848 };
10849 
10850 struct mlx5_ifc_mirc_reg_bits {
10851 	u8         reserved_at_0[0x18];
10852 	u8         status_code[0x8];
10853 
10854 	u8         reserved_at_20[0x20];
10855 };
10856 
10857 struct mlx5_ifc_pddr_monitor_opcode_bits {
10858 	u8         reserved_at_0[0x10];
10859 	u8         monitor_opcode[0x10];
10860 };
10861 
10862 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits {
10863 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10864 	u8         reserved_at_0[0x20];
10865 };
10866 
10867 enum {
10868 	/* Monitor opcodes */
10869 	MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0,
10870 };
10871 
10872 struct mlx5_ifc_pddr_troubleshooting_page_bits {
10873 	u8         reserved_at_0[0x10];
10874 	u8         group_opcode[0x10];
10875 
10876 	union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode;
10877 
10878 	u8         reserved_at_40[0x20];
10879 
10880 	u8         status_message[59][0x20];
10881 };
10882 
10883 union mlx5_ifc_pddr_reg_page_data_auto_bits {
10884 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10885 	u8         reserved_at_0[0x7c0];
10886 };
10887 
10888 enum {
10889 	MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE      = 0x1,
10890 };
10891 
10892 struct mlx5_ifc_pddr_reg_bits {
10893 	u8         reserved_at_0[0x8];
10894 	u8         local_port[0x8];
10895 	u8         pnat[0x2];
10896 	u8         reserved_at_12[0xe];
10897 
10898 	u8         reserved_at_20[0x18];
10899 	u8         page_select[0x8];
10900 
10901 	union mlx5_ifc_pddr_reg_page_data_auto_bits page_data;
10902 };
10903 
10904 struct mlx5_ifc_mrtc_reg_bits {
10905 	u8         time_synced[0x1];
10906 	u8         reserved_at_1[0x1f];
10907 
10908 	u8         reserved_at_20[0x20];
10909 
10910 	u8         time_h[0x20];
10911 
10912 	u8         time_l[0x20];
10913 };
10914 
10915 struct mlx5_ifc_mtcap_reg_bits {
10916 	u8         reserved_at_0[0x19];
10917 	u8         sensor_count[0x7];
10918 
10919 	u8         reserved_at_20[0x20];
10920 
10921 	u8         sensor_map[0x40];
10922 };
10923 
10924 struct mlx5_ifc_mtmp_reg_bits {
10925 	u8         reserved_at_0[0x14];
10926 	u8         sensor_index[0xc];
10927 
10928 	u8         reserved_at_20[0x10];
10929 	u8         temperature[0x10];
10930 
10931 	u8         mte[0x1];
10932 	u8         mtr[0x1];
10933 	u8         reserved_at_42[0xe];
10934 	u8         max_temperature[0x10];
10935 
10936 	u8         tee[0x2];
10937 	u8         reserved_at_62[0xe];
10938 	u8         temp_threshold_hi[0x10];
10939 
10940 	u8         reserved_at_80[0x10];
10941 	u8         temp_threshold_lo[0x10];
10942 
10943 	u8         reserved_at_a0[0x20];
10944 
10945 	u8         sensor_name_hi[0x20];
10946 	u8         sensor_name_lo[0x20];
10947 };
10948 
10949 union mlx5_ifc_ports_control_registers_document_bits {
10950 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
10951 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
10952 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
10953 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
10954 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
10955 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
10956 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
10957 	struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
10958 	struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
10959 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
10960 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
10961 	struct mlx5_ifc_paos_reg_bits paos_reg;
10962 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
10963 	struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode;
10964 	struct mlx5_ifc_pddr_reg_bits pddr_reg;
10965 	struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page;
10966 	struct mlx5_ifc_peir_reg_bits peir_reg;
10967 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
10968 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
10969 	struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
10970 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
10971 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
10972 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
10973 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
10974 	struct mlx5_ifc_plib_reg_bits plib_reg;
10975 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
10976 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
10977 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
10978 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
10979 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
10980 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
10981 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
10982 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
10983 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
10984 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
10985 	struct mlx5_ifc_mpein_reg_bits mpein_reg;
10986 	struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
10987 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
10988 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
10989 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
10990 	struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
10991 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
10992 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
10993 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
10994 	struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
10995 	struct mlx5_ifc_pude_reg_bits pude_reg;
10996 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
10997 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
10998 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
10999 	struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
11000 	struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
11001 	struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
11002 	struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
11003 	struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
11004 	struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
11005 	struct mlx5_ifc_mcc_reg_bits mcc_reg;
11006 	struct mlx5_ifc_mcda_reg_bits mcda_reg;
11007 	struct mlx5_ifc_mirc_reg_bits mirc_reg;
11008 	struct mlx5_ifc_mfrl_reg_bits mfrl_reg;
11009 	struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
11010 	struct mlx5_ifc_mrtc_reg_bits mrtc_reg;
11011 	struct mlx5_ifc_mtcap_reg_bits mtcap_reg;
11012 	struct mlx5_ifc_mtmp_reg_bits mtmp_reg;
11013 	u8         reserved_at_0[0x60e0];
11014 };
11015 
11016 union mlx5_ifc_debug_enhancements_document_bits {
11017 	struct mlx5_ifc_health_buffer_bits health_buffer;
11018 	u8         reserved_at_0[0x200];
11019 };
11020 
11021 union mlx5_ifc_uplink_pci_interface_document_bits {
11022 	struct mlx5_ifc_initial_seg_bits initial_seg;
11023 	u8         reserved_at_0[0x20060];
11024 };
11025 
11026 struct mlx5_ifc_set_flow_table_root_out_bits {
11027 	u8         status[0x8];
11028 	u8         reserved_at_8[0x18];
11029 
11030 	u8         syndrome[0x20];
11031 
11032 	u8         reserved_at_40[0x40];
11033 };
11034 
11035 struct mlx5_ifc_set_flow_table_root_in_bits {
11036 	u8         opcode[0x10];
11037 	u8         reserved_at_10[0x10];
11038 
11039 	u8         reserved_at_20[0x10];
11040 	u8         op_mod[0x10];
11041 
11042 	u8         other_vport[0x1];
11043 	u8         reserved_at_41[0xf];
11044 	u8         vport_number[0x10];
11045 
11046 	u8         reserved_at_60[0x20];
11047 
11048 	u8         table_type[0x8];
11049 	u8         reserved_at_88[0x7];
11050 	u8         table_of_other_vport[0x1];
11051 	u8         table_vport_number[0x10];
11052 
11053 	u8         reserved_at_a0[0x8];
11054 	u8         table_id[0x18];
11055 
11056 	u8         reserved_at_c0[0x8];
11057 	u8         underlay_qpn[0x18];
11058 	u8         table_eswitch_owner_vhca_id_valid[0x1];
11059 	u8         reserved_at_e1[0xf];
11060 	u8         table_eswitch_owner_vhca_id[0x10];
11061 	u8         reserved_at_100[0x100];
11062 };
11063 
11064 enum {
11065 	MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
11066 	MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
11067 };
11068 
11069 struct mlx5_ifc_modify_flow_table_out_bits {
11070 	u8         status[0x8];
11071 	u8         reserved_at_8[0x18];
11072 
11073 	u8         syndrome[0x20];
11074 
11075 	u8         reserved_at_40[0x40];
11076 };
11077 
11078 struct mlx5_ifc_modify_flow_table_in_bits {
11079 	u8         opcode[0x10];
11080 	u8         reserved_at_10[0x10];
11081 
11082 	u8         reserved_at_20[0x10];
11083 	u8         op_mod[0x10];
11084 
11085 	u8         other_vport[0x1];
11086 	u8         reserved_at_41[0xf];
11087 	u8         vport_number[0x10];
11088 
11089 	u8         reserved_at_60[0x10];
11090 	u8         modify_field_select[0x10];
11091 
11092 	u8         table_type[0x8];
11093 	u8         reserved_at_88[0x18];
11094 
11095 	u8         reserved_at_a0[0x8];
11096 	u8         table_id[0x18];
11097 
11098 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
11099 };
11100 
11101 struct mlx5_ifc_ets_tcn_config_reg_bits {
11102 	u8         g[0x1];
11103 	u8         b[0x1];
11104 	u8         r[0x1];
11105 	u8         reserved_at_3[0x9];
11106 	u8         group[0x4];
11107 	u8         reserved_at_10[0x9];
11108 	u8         bw_allocation[0x7];
11109 
11110 	u8         reserved_at_20[0xc];
11111 	u8         max_bw_units[0x4];
11112 	u8         reserved_at_30[0x8];
11113 	u8         max_bw_value[0x8];
11114 };
11115 
11116 struct mlx5_ifc_ets_global_config_reg_bits {
11117 	u8         reserved_at_0[0x2];
11118 	u8         r[0x1];
11119 	u8         reserved_at_3[0x1d];
11120 
11121 	u8         reserved_at_20[0xc];
11122 	u8         max_bw_units[0x4];
11123 	u8         reserved_at_30[0x8];
11124 	u8         max_bw_value[0x8];
11125 };
11126 
11127 struct mlx5_ifc_qetc_reg_bits {
11128 	u8                                         reserved_at_0[0x8];
11129 	u8                                         port_number[0x8];
11130 	u8                                         reserved_at_10[0x30];
11131 
11132 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
11133 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
11134 };
11135 
11136 struct mlx5_ifc_qpdpm_dscp_reg_bits {
11137 	u8         e[0x1];
11138 	u8         reserved_at_01[0x0b];
11139 	u8         prio[0x04];
11140 };
11141 
11142 struct mlx5_ifc_qpdpm_reg_bits {
11143 	u8                                     reserved_at_0[0x8];
11144 	u8                                     local_port[0x8];
11145 	u8                                     reserved_at_10[0x10];
11146 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
11147 };
11148 
11149 struct mlx5_ifc_qpts_reg_bits {
11150 	u8         reserved_at_0[0x8];
11151 	u8         local_port[0x8];
11152 	u8         reserved_at_10[0x2d];
11153 	u8         trust_state[0x3];
11154 };
11155 
11156 struct mlx5_ifc_pptb_reg_bits {
11157 	u8         reserved_at_0[0x2];
11158 	u8         mm[0x2];
11159 	u8         reserved_at_4[0x4];
11160 	u8         local_port[0x8];
11161 	u8         reserved_at_10[0x6];
11162 	u8         cm[0x1];
11163 	u8         um[0x1];
11164 	u8         pm[0x8];
11165 
11166 	u8         prio_x_buff[0x20];
11167 
11168 	u8         pm_msb[0x8];
11169 	u8         reserved_at_48[0x10];
11170 	u8         ctrl_buff[0x4];
11171 	u8         untagged_buff[0x4];
11172 };
11173 
11174 struct mlx5_ifc_sbcam_reg_bits {
11175 	u8         reserved_at_0[0x8];
11176 	u8         feature_group[0x8];
11177 	u8         reserved_at_10[0x8];
11178 	u8         access_reg_group[0x8];
11179 
11180 	u8         reserved_at_20[0x20];
11181 
11182 	u8         sb_access_reg_cap_mask[4][0x20];
11183 
11184 	u8         reserved_at_c0[0x80];
11185 
11186 	u8         sb_feature_cap_mask[4][0x20];
11187 
11188 	u8         reserved_at_1c0[0x40];
11189 
11190 	u8         cap_total_buffer_size[0x20];
11191 
11192 	u8         cap_cell_size[0x10];
11193 	u8         cap_max_pg_buffers[0x8];
11194 	u8         cap_num_pool_supported[0x8];
11195 
11196 	u8         reserved_at_240[0x8];
11197 	u8         cap_sbsr_stat_size[0x8];
11198 	u8         cap_max_tclass_data[0x8];
11199 	u8         cap_max_cpu_ingress_tclass_sb[0x8];
11200 };
11201 
11202 struct mlx5_ifc_pbmc_reg_bits {
11203 	u8         reserved_at_0[0x8];
11204 	u8         local_port[0x8];
11205 	u8         reserved_at_10[0x10];
11206 
11207 	u8         xoff_timer_value[0x10];
11208 	u8         xoff_refresh[0x10];
11209 
11210 	u8         reserved_at_40[0x9];
11211 	u8         fullness_threshold[0x7];
11212 	u8         port_buffer_size[0x10];
11213 
11214 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
11215 
11216 	u8         reserved_at_2e0[0x80];
11217 };
11218 
11219 struct mlx5_ifc_sbpr_reg_bits {
11220 	u8         desc[0x1];
11221 	u8         snap[0x1];
11222 	u8         reserved_at_2[0x4];
11223 	u8         dir[0x2];
11224 	u8         reserved_at_8[0x14];
11225 	u8         pool[0x4];
11226 
11227 	u8         infi_size[0x1];
11228 	u8         reserved_at_21[0x7];
11229 	u8         size[0x18];
11230 
11231 	u8         reserved_at_40[0x1c];
11232 	u8         mode[0x4];
11233 
11234 	u8         reserved_at_60[0x8];
11235 	u8         buff_occupancy[0x18];
11236 
11237 	u8         clr[0x1];
11238 	u8         reserved_at_81[0x7];
11239 	u8         max_buff_occupancy[0x18];
11240 
11241 	u8         reserved_at_a0[0x8];
11242 	u8         ext_buff_occupancy[0x18];
11243 };
11244 
11245 struct mlx5_ifc_sbcm_reg_bits {
11246 	u8         desc[0x1];
11247 	u8         snap[0x1];
11248 	u8         reserved_at_2[0x6];
11249 	u8         local_port[0x8];
11250 	u8         pnat[0x2];
11251 	u8         pg_buff[0x6];
11252 	u8         reserved_at_18[0x6];
11253 	u8         dir[0x2];
11254 
11255 	u8         reserved_at_20[0x1f];
11256 	u8         exc[0x1];
11257 
11258 	u8         reserved_at_40[0x40];
11259 
11260 	u8         reserved_at_80[0x8];
11261 	u8         buff_occupancy[0x18];
11262 
11263 	u8         clr[0x1];
11264 	u8         reserved_at_a1[0x7];
11265 	u8         max_buff_occupancy[0x18];
11266 
11267 	u8         reserved_at_c0[0x8];
11268 	u8         min_buff[0x18];
11269 
11270 	u8         infi_max[0x1];
11271 	u8         reserved_at_e1[0x7];
11272 	u8         max_buff[0x18];
11273 
11274 	u8         reserved_at_100[0x20];
11275 
11276 	u8         reserved_at_120[0x1c];
11277 	u8         pool[0x4];
11278 };
11279 
11280 struct mlx5_ifc_qtct_reg_bits {
11281 	u8         reserved_at_0[0x8];
11282 	u8         port_number[0x8];
11283 	u8         reserved_at_10[0xd];
11284 	u8         prio[0x3];
11285 
11286 	u8         reserved_at_20[0x1d];
11287 	u8         tclass[0x3];
11288 };
11289 
11290 struct mlx5_ifc_mcia_reg_bits {
11291 	u8         l[0x1];
11292 	u8         reserved_at_1[0x7];
11293 	u8         module[0x8];
11294 	u8         reserved_at_10[0x8];
11295 	u8         status[0x8];
11296 
11297 	u8         i2c_device_address[0x8];
11298 	u8         page_number[0x8];
11299 	u8         device_address[0x10];
11300 
11301 	u8         reserved_at_40[0x10];
11302 	u8         size[0x10];
11303 
11304 	u8         reserved_at_60[0x20];
11305 
11306 	u8         dword_0[0x20];
11307 	u8         dword_1[0x20];
11308 	u8         dword_2[0x20];
11309 	u8         dword_3[0x20];
11310 	u8         dword_4[0x20];
11311 	u8         dword_5[0x20];
11312 	u8         dword_6[0x20];
11313 	u8         dword_7[0x20];
11314 	u8         dword_8[0x20];
11315 	u8         dword_9[0x20];
11316 	u8         dword_10[0x20];
11317 	u8         dword_11[0x20];
11318 };
11319 
11320 struct mlx5_ifc_dcbx_param_bits {
11321 	u8         dcbx_cee_cap[0x1];
11322 	u8         dcbx_ieee_cap[0x1];
11323 	u8         dcbx_standby_cap[0x1];
11324 	u8         reserved_at_3[0x5];
11325 	u8         port_number[0x8];
11326 	u8         reserved_at_10[0xa];
11327 	u8         max_application_table_size[6];
11328 	u8         reserved_at_20[0x15];
11329 	u8         version_oper[0x3];
11330 	u8         reserved_at_38[5];
11331 	u8         version_admin[0x3];
11332 	u8         willing_admin[0x1];
11333 	u8         reserved_at_41[0x3];
11334 	u8         pfc_cap_oper[0x4];
11335 	u8         reserved_at_48[0x4];
11336 	u8         pfc_cap_admin[0x4];
11337 	u8         reserved_at_50[0x4];
11338 	u8         num_of_tc_oper[0x4];
11339 	u8         reserved_at_58[0x4];
11340 	u8         num_of_tc_admin[0x4];
11341 	u8         remote_willing[0x1];
11342 	u8         reserved_at_61[3];
11343 	u8         remote_pfc_cap[4];
11344 	u8         reserved_at_68[0x14];
11345 	u8         remote_num_of_tc[0x4];
11346 	u8         reserved_at_80[0x18];
11347 	u8         error[0x8];
11348 	u8         reserved_at_a0[0x160];
11349 };
11350 
11351 enum {
11352 	MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0,
11353 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1,
11354 	MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2,
11355 };
11356 
11357 struct mlx5_ifc_lagc_bits {
11358 	u8         fdb_selection_mode[0x1];
11359 	u8         reserved_at_1[0x14];
11360 	u8         port_select_mode[0x3];
11361 	u8         reserved_at_18[0x5];
11362 	u8         lag_state[0x3];
11363 
11364 	u8         reserved_at_20[0xc];
11365 	u8         active_port[0x4];
11366 	u8         reserved_at_30[0x4];
11367 	u8         tx_remap_affinity_2[0x4];
11368 	u8         reserved_at_38[0x4];
11369 	u8         tx_remap_affinity_1[0x4];
11370 };
11371 
11372 struct mlx5_ifc_create_lag_out_bits {
11373 	u8         status[0x8];
11374 	u8         reserved_at_8[0x18];
11375 
11376 	u8         syndrome[0x20];
11377 
11378 	u8         reserved_at_40[0x40];
11379 };
11380 
11381 struct mlx5_ifc_create_lag_in_bits {
11382 	u8         opcode[0x10];
11383 	u8         reserved_at_10[0x10];
11384 
11385 	u8         reserved_at_20[0x10];
11386 	u8         op_mod[0x10];
11387 
11388 	struct mlx5_ifc_lagc_bits ctx;
11389 };
11390 
11391 struct mlx5_ifc_modify_lag_out_bits {
11392 	u8         status[0x8];
11393 	u8         reserved_at_8[0x18];
11394 
11395 	u8         syndrome[0x20];
11396 
11397 	u8         reserved_at_40[0x40];
11398 };
11399 
11400 struct mlx5_ifc_modify_lag_in_bits {
11401 	u8         opcode[0x10];
11402 	u8         reserved_at_10[0x10];
11403 
11404 	u8         reserved_at_20[0x10];
11405 	u8         op_mod[0x10];
11406 
11407 	u8         reserved_at_40[0x20];
11408 	u8         field_select[0x20];
11409 
11410 	struct mlx5_ifc_lagc_bits ctx;
11411 };
11412 
11413 struct mlx5_ifc_query_lag_out_bits {
11414 	u8         status[0x8];
11415 	u8         reserved_at_8[0x18];
11416 
11417 	u8         syndrome[0x20];
11418 
11419 	struct mlx5_ifc_lagc_bits ctx;
11420 };
11421 
11422 struct mlx5_ifc_query_lag_in_bits {
11423 	u8         opcode[0x10];
11424 	u8         reserved_at_10[0x10];
11425 
11426 	u8         reserved_at_20[0x10];
11427 	u8         op_mod[0x10];
11428 
11429 	u8         reserved_at_40[0x40];
11430 };
11431 
11432 struct mlx5_ifc_destroy_lag_out_bits {
11433 	u8         status[0x8];
11434 	u8         reserved_at_8[0x18];
11435 
11436 	u8         syndrome[0x20];
11437 
11438 	u8         reserved_at_40[0x40];
11439 };
11440 
11441 struct mlx5_ifc_destroy_lag_in_bits {
11442 	u8         opcode[0x10];
11443 	u8         reserved_at_10[0x10];
11444 
11445 	u8         reserved_at_20[0x10];
11446 	u8         op_mod[0x10];
11447 
11448 	u8         reserved_at_40[0x40];
11449 };
11450 
11451 struct mlx5_ifc_create_vport_lag_out_bits {
11452 	u8         status[0x8];
11453 	u8         reserved_at_8[0x18];
11454 
11455 	u8         syndrome[0x20];
11456 
11457 	u8         reserved_at_40[0x40];
11458 };
11459 
11460 struct mlx5_ifc_create_vport_lag_in_bits {
11461 	u8         opcode[0x10];
11462 	u8         reserved_at_10[0x10];
11463 
11464 	u8         reserved_at_20[0x10];
11465 	u8         op_mod[0x10];
11466 
11467 	u8         reserved_at_40[0x40];
11468 };
11469 
11470 struct mlx5_ifc_destroy_vport_lag_out_bits {
11471 	u8         status[0x8];
11472 	u8         reserved_at_8[0x18];
11473 
11474 	u8         syndrome[0x20];
11475 
11476 	u8         reserved_at_40[0x40];
11477 };
11478 
11479 struct mlx5_ifc_destroy_vport_lag_in_bits {
11480 	u8         opcode[0x10];
11481 	u8         reserved_at_10[0x10];
11482 
11483 	u8         reserved_at_20[0x10];
11484 	u8         op_mod[0x10];
11485 
11486 	u8         reserved_at_40[0x40];
11487 };
11488 
11489 enum {
11490 	MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
11491 	MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
11492 };
11493 
11494 struct mlx5_ifc_modify_memic_in_bits {
11495 	u8         opcode[0x10];
11496 	u8         uid[0x10];
11497 
11498 	u8         reserved_at_20[0x10];
11499 	u8         op_mod[0x10];
11500 
11501 	u8         reserved_at_40[0x20];
11502 
11503 	u8         reserved_at_60[0x18];
11504 	u8         memic_operation_type[0x8];
11505 
11506 	u8         memic_start_addr[0x40];
11507 
11508 	u8         reserved_at_c0[0x140];
11509 };
11510 
11511 struct mlx5_ifc_modify_memic_out_bits {
11512 	u8         status[0x8];
11513 	u8         reserved_at_8[0x18];
11514 
11515 	u8         syndrome[0x20];
11516 
11517 	u8         reserved_at_40[0x40];
11518 
11519 	u8         memic_operation_addr[0x40];
11520 
11521 	u8         reserved_at_c0[0x140];
11522 };
11523 
11524 struct mlx5_ifc_alloc_memic_in_bits {
11525 	u8         opcode[0x10];
11526 	u8         reserved_at_10[0x10];
11527 
11528 	u8         reserved_at_20[0x10];
11529 	u8         op_mod[0x10];
11530 
11531 	u8         reserved_at_30[0x20];
11532 
11533 	u8	   reserved_at_40[0x18];
11534 	u8	   log_memic_addr_alignment[0x8];
11535 
11536 	u8         range_start_addr[0x40];
11537 
11538 	u8         range_size[0x20];
11539 
11540 	u8         memic_size[0x20];
11541 };
11542 
11543 struct mlx5_ifc_alloc_memic_out_bits {
11544 	u8         status[0x8];
11545 	u8         reserved_at_8[0x18];
11546 
11547 	u8         syndrome[0x20];
11548 
11549 	u8         memic_start_addr[0x40];
11550 };
11551 
11552 struct mlx5_ifc_dealloc_memic_in_bits {
11553 	u8         opcode[0x10];
11554 	u8         reserved_at_10[0x10];
11555 
11556 	u8         reserved_at_20[0x10];
11557 	u8         op_mod[0x10];
11558 
11559 	u8         reserved_at_40[0x40];
11560 
11561 	u8         memic_start_addr[0x40];
11562 
11563 	u8         memic_size[0x20];
11564 
11565 	u8         reserved_at_e0[0x20];
11566 };
11567 
11568 struct mlx5_ifc_dealloc_memic_out_bits {
11569 	u8         status[0x8];
11570 	u8         reserved_at_8[0x18];
11571 
11572 	u8         syndrome[0x20];
11573 
11574 	u8         reserved_at_40[0x40];
11575 };
11576 
11577 struct mlx5_ifc_umem_bits {
11578 	u8         reserved_at_0[0x80];
11579 
11580 	u8         ats[0x1];
11581 	u8         reserved_at_81[0x1a];
11582 	u8         log_page_size[0x5];
11583 
11584 	u8         page_offset[0x20];
11585 
11586 	u8         num_of_mtt[0x40];
11587 
11588 	struct mlx5_ifc_mtt_bits  mtt[];
11589 };
11590 
11591 struct mlx5_ifc_uctx_bits {
11592 	u8         cap[0x20];
11593 
11594 	u8         reserved_at_20[0x160];
11595 };
11596 
11597 struct mlx5_ifc_sw_icm_bits {
11598 	u8         modify_field_select[0x40];
11599 
11600 	u8	   reserved_at_40[0x18];
11601 	u8         log_sw_icm_size[0x8];
11602 
11603 	u8         reserved_at_60[0x20];
11604 
11605 	u8         sw_icm_start_addr[0x40];
11606 
11607 	u8         reserved_at_c0[0x140];
11608 };
11609 
11610 struct mlx5_ifc_geneve_tlv_option_bits {
11611 	u8         modify_field_select[0x40];
11612 
11613 	u8         reserved_at_40[0x18];
11614 	u8         geneve_option_fte_index[0x8];
11615 
11616 	u8         option_class[0x10];
11617 	u8         option_type[0x8];
11618 	u8         reserved_at_78[0x3];
11619 	u8         option_data_length[0x5];
11620 
11621 	u8         reserved_at_80[0x180];
11622 };
11623 
11624 struct mlx5_ifc_create_umem_in_bits {
11625 	u8         opcode[0x10];
11626 	u8         uid[0x10];
11627 
11628 	u8         reserved_at_20[0x10];
11629 	u8         op_mod[0x10];
11630 
11631 	u8         reserved_at_40[0x40];
11632 
11633 	struct mlx5_ifc_umem_bits  umem;
11634 };
11635 
11636 struct mlx5_ifc_create_umem_out_bits {
11637 	u8         status[0x8];
11638 	u8         reserved_at_8[0x18];
11639 
11640 	u8         syndrome[0x20];
11641 
11642 	u8         reserved_at_40[0x8];
11643 	u8         umem_id[0x18];
11644 
11645 	u8         reserved_at_60[0x20];
11646 };
11647 
11648 struct mlx5_ifc_destroy_umem_in_bits {
11649 	u8        opcode[0x10];
11650 	u8        uid[0x10];
11651 
11652 	u8        reserved_at_20[0x10];
11653 	u8        op_mod[0x10];
11654 
11655 	u8        reserved_at_40[0x8];
11656 	u8        umem_id[0x18];
11657 
11658 	u8        reserved_at_60[0x20];
11659 };
11660 
11661 struct mlx5_ifc_destroy_umem_out_bits {
11662 	u8        status[0x8];
11663 	u8        reserved_at_8[0x18];
11664 
11665 	u8        syndrome[0x20];
11666 
11667 	u8        reserved_at_40[0x40];
11668 };
11669 
11670 struct mlx5_ifc_create_uctx_in_bits {
11671 	u8         opcode[0x10];
11672 	u8         reserved_at_10[0x10];
11673 
11674 	u8         reserved_at_20[0x10];
11675 	u8         op_mod[0x10];
11676 
11677 	u8         reserved_at_40[0x40];
11678 
11679 	struct mlx5_ifc_uctx_bits  uctx;
11680 };
11681 
11682 struct mlx5_ifc_create_uctx_out_bits {
11683 	u8         status[0x8];
11684 	u8         reserved_at_8[0x18];
11685 
11686 	u8         syndrome[0x20];
11687 
11688 	u8         reserved_at_40[0x10];
11689 	u8         uid[0x10];
11690 
11691 	u8         reserved_at_60[0x20];
11692 };
11693 
11694 struct mlx5_ifc_destroy_uctx_in_bits {
11695 	u8         opcode[0x10];
11696 	u8         reserved_at_10[0x10];
11697 
11698 	u8         reserved_at_20[0x10];
11699 	u8         op_mod[0x10];
11700 
11701 	u8         reserved_at_40[0x10];
11702 	u8         uid[0x10];
11703 
11704 	u8         reserved_at_60[0x20];
11705 };
11706 
11707 struct mlx5_ifc_destroy_uctx_out_bits {
11708 	u8         status[0x8];
11709 	u8         reserved_at_8[0x18];
11710 
11711 	u8         syndrome[0x20];
11712 
11713 	u8          reserved_at_40[0x40];
11714 };
11715 
11716 struct mlx5_ifc_create_sw_icm_in_bits {
11717 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11718 	struct mlx5_ifc_sw_icm_bits		      sw_icm;
11719 };
11720 
11721 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
11722 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
11723 	struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
11724 };
11725 
11726 struct mlx5_ifc_mtrc_string_db_param_bits {
11727 	u8         string_db_base_address[0x20];
11728 
11729 	u8         reserved_at_20[0x8];
11730 	u8         string_db_size[0x18];
11731 };
11732 
11733 struct mlx5_ifc_mtrc_cap_bits {
11734 	u8         trace_owner[0x1];
11735 	u8         trace_to_memory[0x1];
11736 	u8         reserved_at_2[0x4];
11737 	u8         trc_ver[0x2];
11738 	u8         reserved_at_8[0x14];
11739 	u8         num_string_db[0x4];
11740 
11741 	u8         first_string_trace[0x8];
11742 	u8         num_string_trace[0x8];
11743 	u8         reserved_at_30[0x28];
11744 
11745 	u8         log_max_trace_buffer_size[0x8];
11746 
11747 	u8         reserved_at_60[0x20];
11748 
11749 	struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
11750 
11751 	u8         reserved_at_280[0x180];
11752 };
11753 
11754 struct mlx5_ifc_mtrc_conf_bits {
11755 	u8         reserved_at_0[0x1c];
11756 	u8         trace_mode[0x4];
11757 	u8         reserved_at_20[0x18];
11758 	u8         log_trace_buffer_size[0x8];
11759 	u8         trace_mkey[0x20];
11760 	u8         reserved_at_60[0x3a0];
11761 };
11762 
11763 struct mlx5_ifc_mtrc_stdb_bits {
11764 	u8         string_db_index[0x4];
11765 	u8         reserved_at_4[0x4];
11766 	u8         read_size[0x18];
11767 	u8         start_offset[0x20];
11768 	u8         string_db_data[];
11769 };
11770 
11771 struct mlx5_ifc_mtrc_ctrl_bits {
11772 	u8         trace_status[0x2];
11773 	u8         reserved_at_2[0x2];
11774 	u8         arm_event[0x1];
11775 	u8         reserved_at_5[0xb];
11776 	u8         modify_field_select[0x10];
11777 	u8         reserved_at_20[0x2b];
11778 	u8         current_timestamp52_32[0x15];
11779 	u8         current_timestamp31_0[0x20];
11780 	u8         reserved_at_80[0x180];
11781 };
11782 
11783 struct mlx5_ifc_host_params_context_bits {
11784 	u8         host_number[0x8];
11785 	u8         reserved_at_8[0x7];
11786 	u8         host_pf_disabled[0x1];
11787 	u8         host_num_of_vfs[0x10];
11788 
11789 	u8         host_total_vfs[0x10];
11790 	u8         host_pci_bus[0x10];
11791 
11792 	u8         reserved_at_40[0x10];
11793 	u8         host_pci_device[0x10];
11794 
11795 	u8         reserved_at_60[0x10];
11796 	u8         host_pci_function[0x10];
11797 
11798 	u8         reserved_at_80[0x180];
11799 };
11800 
11801 struct mlx5_ifc_query_esw_functions_in_bits {
11802 	u8         opcode[0x10];
11803 	u8         reserved_at_10[0x10];
11804 
11805 	u8         reserved_at_20[0x10];
11806 	u8         op_mod[0x10];
11807 
11808 	u8         reserved_at_40[0x40];
11809 };
11810 
11811 struct mlx5_ifc_query_esw_functions_out_bits {
11812 	u8         status[0x8];
11813 	u8         reserved_at_8[0x18];
11814 
11815 	u8         syndrome[0x20];
11816 
11817 	u8         reserved_at_40[0x40];
11818 
11819 	struct mlx5_ifc_host_params_context_bits host_params_context;
11820 
11821 	u8         reserved_at_280[0x180];
11822 	u8         host_sf_enable[][0x40];
11823 };
11824 
11825 struct mlx5_ifc_sf_partition_bits {
11826 	u8         reserved_at_0[0x10];
11827 	u8         log_num_sf[0x8];
11828 	u8         log_sf_bar_size[0x8];
11829 };
11830 
11831 struct mlx5_ifc_query_sf_partitions_out_bits {
11832 	u8         status[0x8];
11833 	u8         reserved_at_8[0x18];
11834 
11835 	u8         syndrome[0x20];
11836 
11837 	u8         reserved_at_40[0x18];
11838 	u8         num_sf_partitions[0x8];
11839 
11840 	u8         reserved_at_60[0x20];
11841 
11842 	struct mlx5_ifc_sf_partition_bits sf_partition[];
11843 };
11844 
11845 struct mlx5_ifc_query_sf_partitions_in_bits {
11846 	u8         opcode[0x10];
11847 	u8         reserved_at_10[0x10];
11848 
11849 	u8         reserved_at_20[0x10];
11850 	u8         op_mod[0x10];
11851 
11852 	u8         reserved_at_40[0x40];
11853 };
11854 
11855 struct mlx5_ifc_dealloc_sf_out_bits {
11856 	u8         status[0x8];
11857 	u8         reserved_at_8[0x18];
11858 
11859 	u8         syndrome[0x20];
11860 
11861 	u8         reserved_at_40[0x40];
11862 };
11863 
11864 struct mlx5_ifc_dealloc_sf_in_bits {
11865 	u8         opcode[0x10];
11866 	u8         reserved_at_10[0x10];
11867 
11868 	u8         reserved_at_20[0x10];
11869 	u8         op_mod[0x10];
11870 
11871 	u8         reserved_at_40[0x10];
11872 	u8         function_id[0x10];
11873 
11874 	u8         reserved_at_60[0x20];
11875 };
11876 
11877 struct mlx5_ifc_alloc_sf_out_bits {
11878 	u8         status[0x8];
11879 	u8         reserved_at_8[0x18];
11880 
11881 	u8         syndrome[0x20];
11882 
11883 	u8         reserved_at_40[0x40];
11884 };
11885 
11886 struct mlx5_ifc_alloc_sf_in_bits {
11887 	u8         opcode[0x10];
11888 	u8         reserved_at_10[0x10];
11889 
11890 	u8         reserved_at_20[0x10];
11891 	u8         op_mod[0x10];
11892 
11893 	u8         reserved_at_40[0x10];
11894 	u8         function_id[0x10];
11895 
11896 	u8         reserved_at_60[0x20];
11897 };
11898 
11899 struct mlx5_ifc_affiliated_event_header_bits {
11900 	u8         reserved_at_0[0x10];
11901 	u8         obj_type[0x10];
11902 
11903 	u8         obj_id[0x20];
11904 };
11905 
11906 enum {
11907 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc),
11908 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13),
11909 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20),
11910 	MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24),
11911 };
11912 
11913 enum {
11914 	MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
11915 	MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
11916 	MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20,
11917 	MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24,
11918 	MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27,
11919 	MLX5_GENERAL_OBJECT_TYPES_INT_KEK = 0x47,
11920 };
11921 
11922 enum {
11923 	MLX5_IPSEC_OBJECT_ICV_LEN_16B,
11924 };
11925 
11926 enum {
11927 	MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
11928 	MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
11929 	MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
11930 	MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
11931 };
11932 
11933 enum {
11934 	MLX5_IPSEC_ASO_MODE              = 0x0,
11935 	MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
11936 	MLX5_IPSEC_ASO_INC_SN            = 0x2,
11937 };
11938 
11939 struct mlx5_ifc_ipsec_aso_bits {
11940 	u8         valid[0x1];
11941 	u8         reserved_at_201[0x1];
11942 	u8         mode[0x2];
11943 	u8         window_sz[0x2];
11944 	u8         soft_lft_arm[0x1];
11945 	u8         hard_lft_arm[0x1];
11946 	u8         remove_flow_enable[0x1];
11947 	u8         esn_event_arm[0x1];
11948 	u8         reserved_at_20a[0x16];
11949 
11950 	u8         remove_flow_pkt_cnt[0x20];
11951 
11952 	u8         remove_flow_soft_lft[0x20];
11953 
11954 	u8         reserved_at_260[0x80];
11955 
11956 	u8         mode_parameter[0x20];
11957 
11958 	u8         replay_protection_window[0x100];
11959 };
11960 
11961 struct mlx5_ifc_ipsec_obj_bits {
11962 	u8         modify_field_select[0x40];
11963 	u8         full_offload[0x1];
11964 	u8         reserved_at_41[0x1];
11965 	u8         esn_en[0x1];
11966 	u8         esn_overlap[0x1];
11967 	u8         reserved_at_44[0x2];
11968 	u8         icv_length[0x2];
11969 	u8         reserved_at_48[0x4];
11970 	u8         aso_return_reg[0x4];
11971 	u8         reserved_at_50[0x10];
11972 
11973 	u8         esn_msb[0x20];
11974 
11975 	u8         reserved_at_80[0x8];
11976 	u8         dekn[0x18];
11977 
11978 	u8         salt[0x20];
11979 
11980 	u8         implicit_iv[0x40];
11981 
11982 	u8         reserved_at_100[0x8];
11983 	u8         ipsec_aso_access_pd[0x18];
11984 	u8         reserved_at_120[0xe0];
11985 
11986 	struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
11987 };
11988 
11989 struct mlx5_ifc_create_ipsec_obj_in_bits {
11990 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
11991 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
11992 };
11993 
11994 enum {
11995 	MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0),
11996 	MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1),
11997 };
11998 
11999 struct mlx5_ifc_query_ipsec_obj_out_bits {
12000 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12001 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12002 };
12003 
12004 struct mlx5_ifc_modify_ipsec_obj_in_bits {
12005 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12006 	struct mlx5_ifc_ipsec_obj_bits ipsec_object;
12007 };
12008 
12009 enum {
12010 	MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1,
12011 };
12012 
12013 enum {
12014 	MLX5_MACSEC_ASO_REPLAY_WIN_32BIT  = 0x0,
12015 	MLX5_MACSEC_ASO_REPLAY_WIN_64BIT  = 0x1,
12016 	MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2,
12017 	MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3,
12018 };
12019 
12020 #define MLX5_MACSEC_ASO_INC_SN  0x2
12021 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2
12022 
12023 struct mlx5_ifc_macsec_aso_bits {
12024 	u8    valid[0x1];
12025 	u8    reserved_at_1[0x1];
12026 	u8    mode[0x2];
12027 	u8    window_size[0x2];
12028 	u8    soft_lifetime_arm[0x1];
12029 	u8    hard_lifetime_arm[0x1];
12030 	u8    remove_flow_enable[0x1];
12031 	u8    epn_event_arm[0x1];
12032 	u8    reserved_at_a[0x16];
12033 
12034 	u8    remove_flow_packet_count[0x20];
12035 
12036 	u8    remove_flow_soft_lifetime[0x20];
12037 
12038 	u8    reserved_at_60[0x80];
12039 
12040 	u8    mode_parameter[0x20];
12041 
12042 	u8    replay_protection_window[8][0x20];
12043 };
12044 
12045 struct mlx5_ifc_macsec_offload_obj_bits {
12046 	u8    modify_field_select[0x40];
12047 
12048 	u8    confidentiality_en[0x1];
12049 	u8    reserved_at_41[0x1];
12050 	u8    epn_en[0x1];
12051 	u8    epn_overlap[0x1];
12052 	u8    reserved_at_44[0x2];
12053 	u8    confidentiality_offset[0x2];
12054 	u8    reserved_at_48[0x4];
12055 	u8    aso_return_reg[0x4];
12056 	u8    reserved_at_50[0x10];
12057 
12058 	u8    epn_msb[0x20];
12059 
12060 	u8    reserved_at_80[0x8];
12061 	u8    dekn[0x18];
12062 
12063 	u8    reserved_at_a0[0x20];
12064 
12065 	u8    sci[0x40];
12066 
12067 	u8    reserved_at_100[0x8];
12068 	u8    macsec_aso_access_pd[0x18];
12069 
12070 	u8    reserved_at_120[0x60];
12071 
12072 	u8    salt[3][0x20];
12073 
12074 	u8    reserved_at_1e0[0x20];
12075 
12076 	struct mlx5_ifc_macsec_aso_bits macsec_aso;
12077 };
12078 
12079 struct mlx5_ifc_create_macsec_obj_in_bits {
12080 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12081 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12082 };
12083 
12084 struct mlx5_ifc_modify_macsec_obj_in_bits {
12085 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12086 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12087 };
12088 
12089 enum {
12090 	MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0),
12091 	MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1),
12092 };
12093 
12094 struct mlx5_ifc_query_macsec_obj_out_bits {
12095 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12096 	struct mlx5_ifc_macsec_offload_obj_bits macsec_object;
12097 };
12098 
12099 struct mlx5_ifc_wrapped_dek_bits {
12100 	u8         gcm_iv[0x60];
12101 
12102 	u8         reserved_at_60[0x20];
12103 
12104 	u8         const0[0x1];
12105 	u8         key_size[0x1];
12106 	u8         reserved_at_82[0x2];
12107 	u8         key2_invalid[0x1];
12108 	u8         reserved_at_85[0x3];
12109 	u8         pd[0x18];
12110 
12111 	u8         key_purpose[0x5];
12112 	u8         reserved_at_a5[0x13];
12113 	u8         kek_id[0x8];
12114 
12115 	u8         reserved_at_c0[0x40];
12116 
12117 	u8         key1[0x8][0x20];
12118 
12119 	u8         key2[0x8][0x20];
12120 
12121 	u8         reserved_at_300[0x40];
12122 
12123 	u8         const1[0x1];
12124 	u8         reserved_at_341[0x1f];
12125 
12126 	u8         reserved_at_360[0x20];
12127 
12128 	u8         auth_tag[0x80];
12129 };
12130 
12131 struct mlx5_ifc_encryption_key_obj_bits {
12132 	u8         modify_field_select[0x40];
12133 
12134 	u8         state[0x8];
12135 	u8         sw_wrapped[0x1];
12136 	u8         reserved_at_49[0xb];
12137 	u8         key_size[0x4];
12138 	u8         reserved_at_58[0x4];
12139 	u8         key_purpose[0x4];
12140 
12141 	u8         reserved_at_60[0x8];
12142 	u8         pd[0x18];
12143 
12144 	u8         reserved_at_80[0x100];
12145 
12146 	u8         opaque[0x40];
12147 
12148 	u8         reserved_at_1c0[0x40];
12149 
12150 	u8         key[8][0x80];
12151 
12152 	u8         sw_wrapped_dek[8][0x80];
12153 
12154 	u8         reserved_at_a00[0x600];
12155 };
12156 
12157 struct mlx5_ifc_create_encryption_key_in_bits {
12158 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12159 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12160 };
12161 
12162 struct mlx5_ifc_modify_encryption_key_in_bits {
12163 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12164 	struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
12165 };
12166 
12167 enum {
12168 	MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH		= 0x0,
12169 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2		= 0x1,
12170 	MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG	= 0x2,
12171 	MLX5_FLOW_METER_MODE_NUM_PACKETS		= 0x3,
12172 };
12173 
12174 struct mlx5_ifc_flow_meter_parameters_bits {
12175 	u8         valid[0x1];
12176 	u8         bucket_overflow[0x1];
12177 	u8         start_color[0x2];
12178 	u8         both_buckets_on_green[0x1];
12179 	u8         reserved_at_5[0x1];
12180 	u8         meter_mode[0x2];
12181 	u8         reserved_at_8[0x18];
12182 
12183 	u8         reserved_at_20[0x20];
12184 
12185 	u8         reserved_at_40[0x3];
12186 	u8         cbs_exponent[0x5];
12187 	u8         cbs_mantissa[0x8];
12188 	u8         reserved_at_50[0x3];
12189 	u8         cir_exponent[0x5];
12190 	u8         cir_mantissa[0x8];
12191 
12192 	u8         reserved_at_60[0x20];
12193 
12194 	u8         reserved_at_80[0x3];
12195 	u8         ebs_exponent[0x5];
12196 	u8         ebs_mantissa[0x8];
12197 	u8         reserved_at_90[0x3];
12198 	u8         eir_exponent[0x5];
12199 	u8         eir_mantissa[0x8];
12200 
12201 	u8         reserved_at_a0[0x60];
12202 };
12203 
12204 struct mlx5_ifc_flow_meter_aso_obj_bits {
12205 	u8         modify_field_select[0x40];
12206 
12207 	u8         reserved_at_40[0x40];
12208 
12209 	u8         reserved_at_80[0x8];
12210 	u8         meter_aso_access_pd[0x18];
12211 
12212 	u8         reserved_at_a0[0x160];
12213 
12214 	struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2];
12215 };
12216 
12217 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits {
12218 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
12219 	struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj;
12220 };
12221 
12222 struct mlx5_ifc_int_kek_obj_bits {
12223 	u8         modify_field_select[0x40];
12224 
12225 	u8         state[0x8];
12226 	u8         auto_gen[0x1];
12227 	u8         reserved_at_49[0xb];
12228 	u8         key_size[0x4];
12229 	u8         reserved_at_58[0x8];
12230 
12231 	u8         reserved_at_60[0x8];
12232 	u8         pd[0x18];
12233 
12234 	u8         reserved_at_80[0x180];
12235 	u8         key[8][0x80];
12236 
12237 	u8         reserved_at_600[0x200];
12238 };
12239 
12240 struct mlx5_ifc_create_int_kek_obj_in_bits {
12241 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12242 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12243 };
12244 
12245 struct mlx5_ifc_create_int_kek_obj_out_bits {
12246 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12247 	struct mlx5_ifc_int_kek_obj_bits int_kek_object;
12248 };
12249 
12250 struct mlx5_ifc_sampler_obj_bits {
12251 	u8         modify_field_select[0x40];
12252 
12253 	u8         table_type[0x8];
12254 	u8         level[0x8];
12255 	u8         reserved_at_50[0xf];
12256 	u8         ignore_flow_level[0x1];
12257 
12258 	u8         sample_ratio[0x20];
12259 
12260 	u8         reserved_at_80[0x8];
12261 	u8         sample_table_id[0x18];
12262 
12263 	u8         reserved_at_a0[0x8];
12264 	u8         default_table_id[0x18];
12265 
12266 	u8         sw_steering_icm_address_rx[0x40];
12267 	u8         sw_steering_icm_address_tx[0x40];
12268 
12269 	u8         reserved_at_140[0xa0];
12270 };
12271 
12272 struct mlx5_ifc_create_sampler_obj_in_bits {
12273 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12274 	struct mlx5_ifc_sampler_obj_bits sampler_object;
12275 };
12276 
12277 struct mlx5_ifc_query_sampler_obj_out_bits {
12278 	struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
12279 	struct mlx5_ifc_sampler_obj_bits sampler_object;
12280 };
12281 
12282 enum {
12283 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
12284 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
12285 };
12286 
12287 enum {
12288 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12289 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12290 	MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,
12291 };
12292 
12293 struct mlx5_ifc_tls_static_params_bits {
12294 	u8         const_2[0x2];
12295 	u8         tls_version[0x4];
12296 	u8         const_1[0x2];
12297 	u8         reserved_at_8[0x14];
12298 	u8         encryption_standard[0x4];
12299 
12300 	u8         reserved_at_20[0x20];
12301 
12302 	u8         initial_record_number[0x40];
12303 
12304 	u8         resync_tcp_sn[0x20];
12305 
12306 	u8         gcm_iv[0x20];
12307 
12308 	u8         implicit_iv[0x40];
12309 
12310 	u8         reserved_at_100[0x8];
12311 	u8         dek_index[0x18];
12312 
12313 	u8         reserved_at_120[0xe0];
12314 };
12315 
12316 struct mlx5_ifc_tls_progress_params_bits {
12317 	u8         next_record_tcp_sn[0x20];
12318 
12319 	u8         hw_resync_tcp_sn[0x20];
12320 
12321 	u8         record_tracker_state[0x2];
12322 	u8         auth_state[0x2];
12323 	u8         reserved_at_44[0x4];
12324 	u8         hw_offset_record_number[0x18];
12325 };
12326 
12327 enum {
12328 	MLX5_MTT_PERM_READ	= 1 << 0,
12329 	MLX5_MTT_PERM_WRITE	= 1 << 1,
12330 	MLX5_MTT_PERM_RW	= MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE,
12331 };
12332 
12333 enum {
12334 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR  = 0x0,
12335 	MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER  = 0x1,
12336 };
12337 
12338 struct mlx5_ifc_suspend_vhca_in_bits {
12339 	u8         opcode[0x10];
12340 	u8         uid[0x10];
12341 
12342 	u8         reserved_at_20[0x10];
12343 	u8         op_mod[0x10];
12344 
12345 	u8         reserved_at_40[0x10];
12346 	u8         vhca_id[0x10];
12347 
12348 	u8         reserved_at_60[0x20];
12349 };
12350 
12351 struct mlx5_ifc_suspend_vhca_out_bits {
12352 	u8         status[0x8];
12353 	u8         reserved_at_8[0x18];
12354 
12355 	u8         syndrome[0x20];
12356 
12357 	u8         reserved_at_40[0x40];
12358 };
12359 
12360 enum {
12361 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER  = 0x0,
12362 	MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR  = 0x1,
12363 };
12364 
12365 struct mlx5_ifc_resume_vhca_in_bits {
12366 	u8         opcode[0x10];
12367 	u8         uid[0x10];
12368 
12369 	u8         reserved_at_20[0x10];
12370 	u8         op_mod[0x10];
12371 
12372 	u8         reserved_at_40[0x10];
12373 	u8         vhca_id[0x10];
12374 
12375 	u8         reserved_at_60[0x20];
12376 };
12377 
12378 struct mlx5_ifc_resume_vhca_out_bits {
12379 	u8         status[0x8];
12380 	u8         reserved_at_8[0x18];
12381 
12382 	u8         syndrome[0x20];
12383 
12384 	u8         reserved_at_40[0x40];
12385 };
12386 
12387 struct mlx5_ifc_query_vhca_migration_state_in_bits {
12388 	u8         opcode[0x10];
12389 	u8         uid[0x10];
12390 
12391 	u8         reserved_at_20[0x10];
12392 	u8         op_mod[0x10];
12393 
12394 	u8         incremental[0x1];
12395 	u8         reserved_at_41[0xf];
12396 	u8         vhca_id[0x10];
12397 
12398 	u8         reserved_at_60[0x20];
12399 };
12400 
12401 struct mlx5_ifc_query_vhca_migration_state_out_bits {
12402 	u8         status[0x8];
12403 	u8         reserved_at_8[0x18];
12404 
12405 	u8         syndrome[0x20];
12406 
12407 	u8         reserved_at_40[0x40];
12408 
12409 	u8         required_umem_size[0x20];
12410 
12411 	u8         reserved_at_a0[0x160];
12412 };
12413 
12414 struct mlx5_ifc_save_vhca_state_in_bits {
12415 	u8         opcode[0x10];
12416 	u8         uid[0x10];
12417 
12418 	u8         reserved_at_20[0x10];
12419 	u8         op_mod[0x10];
12420 
12421 	u8         incremental[0x1];
12422 	u8         set_track[0x1];
12423 	u8         reserved_at_42[0xe];
12424 	u8         vhca_id[0x10];
12425 
12426 	u8         reserved_at_60[0x20];
12427 
12428 	u8         va[0x40];
12429 
12430 	u8         mkey[0x20];
12431 
12432 	u8         size[0x20];
12433 };
12434 
12435 struct mlx5_ifc_save_vhca_state_out_bits {
12436 	u8         status[0x8];
12437 	u8         reserved_at_8[0x18];
12438 
12439 	u8         syndrome[0x20];
12440 
12441 	u8         actual_image_size[0x20];
12442 
12443 	u8         reserved_at_60[0x20];
12444 };
12445 
12446 struct mlx5_ifc_load_vhca_state_in_bits {
12447 	u8         opcode[0x10];
12448 	u8         uid[0x10];
12449 
12450 	u8         reserved_at_20[0x10];
12451 	u8         op_mod[0x10];
12452 
12453 	u8         reserved_at_40[0x10];
12454 	u8         vhca_id[0x10];
12455 
12456 	u8         reserved_at_60[0x20];
12457 
12458 	u8         va[0x40];
12459 
12460 	u8         mkey[0x20];
12461 
12462 	u8         size[0x20];
12463 };
12464 
12465 struct mlx5_ifc_load_vhca_state_out_bits {
12466 	u8         status[0x8];
12467 	u8         reserved_at_8[0x18];
12468 
12469 	u8         syndrome[0x20];
12470 
12471 	u8         reserved_at_40[0x40];
12472 };
12473 
12474 struct mlx5_ifc_adv_virtualization_cap_bits {
12475 	u8         reserved_at_0[0x3];
12476 	u8         pg_track_log_max_num[0x5];
12477 	u8         pg_track_max_num_range[0x8];
12478 	u8         pg_track_log_min_addr_space[0x8];
12479 	u8         pg_track_log_max_addr_space[0x8];
12480 
12481 	u8         reserved_at_20[0x3];
12482 	u8         pg_track_log_min_msg_size[0x5];
12483 	u8         reserved_at_28[0x3];
12484 	u8         pg_track_log_max_msg_size[0x5];
12485 	u8         reserved_at_30[0x3];
12486 	u8         pg_track_log_min_page_size[0x5];
12487 	u8         reserved_at_38[0x3];
12488 	u8         pg_track_log_max_page_size[0x5];
12489 
12490 	u8         reserved_at_40[0x7c0];
12491 };
12492 
12493 struct mlx5_ifc_page_track_report_entry_bits {
12494 	u8         dirty_address_high[0x20];
12495 
12496 	u8         dirty_address_low[0x20];
12497 };
12498 
12499 enum {
12500 	MLX5_PAGE_TRACK_STATE_TRACKING,
12501 	MLX5_PAGE_TRACK_STATE_REPORTING,
12502 	MLX5_PAGE_TRACK_STATE_ERROR,
12503 };
12504 
12505 struct mlx5_ifc_page_track_range_bits {
12506 	u8         start_address[0x40];
12507 
12508 	u8         length[0x40];
12509 };
12510 
12511 struct mlx5_ifc_page_track_bits {
12512 	u8         modify_field_select[0x40];
12513 
12514 	u8         reserved_at_40[0x10];
12515 	u8         vhca_id[0x10];
12516 
12517 	u8         reserved_at_60[0x20];
12518 
12519 	u8         state[0x4];
12520 	u8         track_type[0x4];
12521 	u8         log_addr_space_size[0x8];
12522 	u8         reserved_at_90[0x3];
12523 	u8         log_page_size[0x5];
12524 	u8         reserved_at_98[0x3];
12525 	u8         log_msg_size[0x5];
12526 
12527 	u8         reserved_at_a0[0x8];
12528 	u8         reporting_qpn[0x18];
12529 
12530 	u8         reserved_at_c0[0x18];
12531 	u8         num_ranges[0x8];
12532 
12533 	u8         reserved_at_e0[0x20];
12534 
12535 	u8         range_start_address[0x40];
12536 
12537 	u8         length[0x40];
12538 
12539 	struct     mlx5_ifc_page_track_range_bits track_range[0];
12540 };
12541 
12542 struct mlx5_ifc_create_page_track_obj_in_bits {
12543 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12544 	struct mlx5_ifc_page_track_bits obj_context;
12545 };
12546 
12547 struct mlx5_ifc_modify_page_track_obj_in_bits {
12548 	struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
12549 	struct mlx5_ifc_page_track_bits obj_context;
12550 };
12551 
12552 #endif /* MLX5_IFC_H */
12553