1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/mlx5/fs.h>
48 #include <linux/rhashtable.h>
49 #include <net/switchdev.h>
50 #include <net/xdp.h>
51 #include <linux/dim.h>
52 #include <linux/bits.h>
53 #include "wq.h"
54 #include "mlx5_core.h"
55 #include "en_stats.h"
56 #include "en/fs.h"
57 #include "lib/hv_vhca.h"
58
59 extern const struct net_device_ops mlx5e_netdev_ops;
60 struct page_pool;
61
62 #define MLX5E_METADATA_ETHER_TYPE (0x8CE4)
63 #define MLX5E_METADATA_ETHER_LEN 8
64
65 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
66
67 #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
68
69 #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu))
70 #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu))
71
72 #define MLX5E_MAX_PRIORITY 8
73 #define MLX5E_MAX_DSCP 64
74 #define MLX5E_MAX_NUM_TC 8
75
76 #define MLX5_RX_HEADROOM NET_SKB_PAD
77 #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \
78 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
79
80 #define MLX5E_RX_MAX_HEAD (256)
81
82 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
83 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
84 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
85 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
86 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \
87 MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD))
88
89 #define MLX5_MPWRQ_LOG_WQE_SZ 18
90 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
91 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
92 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
93
94 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
95 #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
96 #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS))
97 #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS)
98 #define MLX5E_MAX_RQ_NUM_MTTS \
99 ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */
100 #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024))
101 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \
102 (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS))
103 #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \
104 (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \
105 (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU))
106
107 #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM))
108 #define MLX5E_LOG_MAX_RX_WQE_BULK \
109 (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ)))
110
111 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
112 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
113 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
114
115 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK)
116 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
117 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \
118 MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW)
119
120 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2
121
122 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
123 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
124 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
125
126 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
127 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
128 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
129 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
130 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10
131 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
132 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
133 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
134
135 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
136 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
137 #define MLX5E_MIN_NUM_CHANNELS 0x1
138 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
139 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
140 #define MLX5E_TX_CQ_POLL_BUDGET 128
141 #define MLX5E_TX_XSK_POLL_BUDGET 64
142 #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */
143
144 #define MLX5E_UMR_WQE_INLINE_SZ \
145 (sizeof(struct mlx5e_umr_wqe) + \
146 ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \
147 MLX5_UMR_MTT_ALIGNMENT))
148 #define MLX5E_UMR_WQEBBS \
149 (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB))
150
151 #define MLX5E_MSG_LEVEL NETIF_MSG_LINK
152
153 #define mlx5e_dbg(mlevel, priv, format, ...) \
154 do { \
155 if (NETIF_MSG_##mlevel & (priv)->msglevel) \
156 netdev_warn(priv->netdev, format, \
157 ##__VA_ARGS__); \
158 } while (0)
159
160 enum mlx5e_rq_group {
161 MLX5E_RQ_GROUP_REGULAR,
162 MLX5E_RQ_GROUP_XSK,
163 #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g)
164 };
165
mlx5e_get_num_lag_ports(struct mlx5_core_dev * mdev)166 static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev)
167 {
168 if (mlx5_lag_is_lacp_owner(mdev))
169 return 1;
170
171 return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS);
172 }
173
mlx5_min_rx_wqes(int wq_type,u32 wq_size)174 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
175 {
176 switch (wq_type) {
177 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
178 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
179 wq_size / 2);
180 default:
181 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
182 wq_size / 2);
183 }
184 }
185
186 /* Use this function to get max num channels (rxqs/txqs) only to create netdev */
mlx5e_get_max_num_channels(struct mlx5_core_dev * mdev)187 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
188 {
189 return is_kdump_kernel() ?
190 MLX5E_MIN_NUM_CHANNELS :
191 min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS);
192 }
193
194 struct mlx5e_tx_wqe {
195 struct mlx5_wqe_ctrl_seg ctrl;
196 union {
197 struct {
198 struct mlx5_wqe_eth_seg eth;
199 struct mlx5_wqe_data_seg data[0];
200 };
201 u8 tls_progress_params_ctx[0];
202 };
203 };
204
205 struct mlx5e_rx_wqe_ll {
206 struct mlx5_wqe_srq_next_seg next;
207 struct mlx5_wqe_data_seg data[0];
208 };
209
210 struct mlx5e_rx_wqe_cyc {
211 struct mlx5_wqe_data_seg data[0];
212 };
213
214 struct mlx5e_umr_wqe {
215 struct mlx5_wqe_ctrl_seg ctrl;
216 struct mlx5_wqe_umr_ctrl_seg uctrl;
217 struct mlx5_mkey_seg mkc;
218 union {
219 struct mlx5_mtt inline_mtts[0];
220 u8 tls_static_params_ctx[0];
221 };
222 };
223
224 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
225
226 enum mlx5e_priv_flag {
227 MLX5E_PFLAG_RX_CQE_BASED_MODER,
228 MLX5E_PFLAG_TX_CQE_BASED_MODER,
229 MLX5E_PFLAG_RX_CQE_COMPRESS,
230 MLX5E_PFLAG_RX_STRIDING_RQ,
231 MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
232 MLX5E_PFLAG_XDP_TX_MPWQE,
233 MLX5E_NUM_PFLAGS, /* Keep last */
234 };
235
236 #define MLX5E_SET_PFLAG(params, pflag, enable) \
237 do { \
238 if (enable) \
239 (params)->pflags |= BIT(pflag); \
240 else \
241 (params)->pflags &= ~(BIT(pflag)); \
242 } while (0)
243
244 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag))))
245
246 #ifdef CONFIG_MLX5_CORE_EN_DCB
247 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
248 #endif
249
250 struct mlx5e_params {
251 u8 log_sq_size;
252 u8 rq_wq_type;
253 u8 log_rq_mtu_frames;
254 u16 num_channels;
255 u8 num_tc;
256 bool rx_cqe_compress_def;
257 bool tunneled_offload_en;
258 struct dim_cq_moder rx_cq_moderation;
259 struct dim_cq_moder tx_cq_moderation;
260 bool lro_en;
261 u8 tx_min_inline_mode;
262 bool vlan_strip_disable;
263 bool scatter_fcs_en;
264 bool rx_dim_enabled;
265 bool tx_dim_enabled;
266 u32 lro_timeout;
267 u32 pflags;
268 struct bpf_prog *xdp_prog;
269 struct mlx5e_xsk *xsk;
270 unsigned int sw_mtu;
271 int hard_mtu;
272 };
273
274 #ifdef CONFIG_MLX5_CORE_EN_DCB
275 struct mlx5e_cee_config {
276 /* bw pct for priority group */
277 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
278 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
279 bool pfc_setting[CEE_DCBX_MAX_PRIO];
280 bool pfc_enable;
281 };
282
283 enum {
284 MLX5_DCB_CHG_RESET,
285 MLX5_DCB_NO_CHG,
286 MLX5_DCB_CHG_NO_RESET,
287 };
288
289 struct mlx5e_dcbx {
290 enum mlx5_dcbx_oper_mode mode;
291 struct mlx5e_cee_config cee_cfg; /* pending configuration */
292 u8 dscp_app_cnt;
293
294 /* The only setting that cannot be read from FW */
295 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
296 u8 cap;
297
298 /* Buffer configuration */
299 bool manual_buffer;
300 u32 cable_len;
301 u32 xoff;
302 };
303
304 struct mlx5e_dcbx_dp {
305 u8 dscp2prio[MLX5E_MAX_DSCP];
306 u8 trust_state;
307 };
308 #endif
309
310 enum {
311 MLX5E_RQ_STATE_ENABLED,
312 MLX5E_RQ_STATE_RECOVERING,
313 MLX5E_RQ_STATE_AM,
314 MLX5E_RQ_STATE_NO_CSUM_COMPLETE,
315 MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */
316 };
317
318 struct mlx5e_cq {
319 /* data path - accessed per cqe */
320 struct mlx5_cqwq wq;
321
322 /* data path - accessed per napi poll */
323 u16 event_ctr;
324 struct napi_struct *napi;
325 struct mlx5_core_cq mcq;
326 struct mlx5e_channel *channel;
327
328 /* control */
329 struct mlx5_core_dev *mdev;
330 struct mlx5_wq_ctrl wq_ctrl;
331 } ____cacheline_aligned_in_smp;
332
333 struct mlx5e_cq_decomp {
334 /* cqe decompression */
335 struct mlx5_cqe64 title;
336 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
337 u8 mini_arr_idx;
338 u16 left;
339 u16 wqe_counter;
340 } ____cacheline_aligned_in_smp;
341
342 struct mlx5e_tx_wqe_info {
343 struct sk_buff *skb;
344 u32 num_bytes;
345 u8 num_wqebbs;
346 u8 num_dma;
347 #ifdef CONFIG_MLX5_EN_TLS
348 struct page *resync_dump_frag_page;
349 #endif
350 };
351
352 enum mlx5e_dma_map_type {
353 MLX5E_DMA_MAP_SINGLE,
354 MLX5E_DMA_MAP_PAGE
355 };
356
357 struct mlx5e_sq_dma {
358 dma_addr_t addr;
359 u32 size;
360 enum mlx5e_dma_map_type type;
361 };
362
363 enum {
364 MLX5E_SQ_STATE_ENABLED,
365 MLX5E_SQ_STATE_RECOVERING,
366 MLX5E_SQ_STATE_IPSEC,
367 MLX5E_SQ_STATE_AM,
368 MLX5E_SQ_STATE_TLS,
369 MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE,
370 };
371
372 struct mlx5e_sq_wqe_info {
373 u8 opcode;
374
375 /* Auxiliary data for different opcodes. */
376 union {
377 struct {
378 struct mlx5e_rq *rq;
379 } umr;
380 };
381 };
382
383 struct mlx5e_txqsq {
384 /* data path */
385
386 /* dirtied @completion */
387 u16 cc;
388 u32 dma_fifo_cc;
389 struct dim dim; /* Adaptive Moderation */
390
391 /* dirtied @xmit */
392 u16 pc ____cacheline_aligned_in_smp;
393 u32 dma_fifo_pc;
394
395 struct mlx5e_cq cq;
396
397 /* read only */
398 struct mlx5_wq_cyc wq;
399 u32 dma_fifo_mask;
400 struct mlx5e_sq_stats *stats;
401 struct {
402 struct mlx5e_sq_dma *dma_fifo;
403 struct mlx5e_tx_wqe_info *wqe_info;
404 } db;
405 void __iomem *uar_map;
406 struct netdev_queue *txq;
407 u32 sqn;
408 u16 stop_room;
409 u8 min_inline_mode;
410 struct device *pdev;
411 __be32 mkey_be;
412 unsigned long state;
413 unsigned int hw_mtu;
414 struct hwtstamp_config *tstamp;
415 struct mlx5_clock *clock;
416
417 /* control path */
418 struct mlx5_wq_ctrl wq_ctrl;
419 struct mlx5e_channel *channel;
420 int ch_ix;
421 int txq_ix;
422 u32 rate_limit;
423 struct work_struct recover_work;
424 } ____cacheline_aligned_in_smp;
425
426 struct mlx5e_dma_info {
427 dma_addr_t addr;
428 union {
429 struct page *page;
430 struct {
431 u64 handle;
432 void *data;
433 } xsk;
434 };
435 };
436
437 /* XDP packets can be transmitted in different ways. On completion, we need to
438 * distinguish between them to clean up things in a proper way.
439 */
440 enum mlx5e_xdp_xmit_mode {
441 /* An xdp_frame was transmitted due to either XDP_REDIRECT from another
442 * device or XDP_TX from an XSK RQ. The frame has to be unmapped and
443 * returned.
444 */
445 MLX5E_XDP_XMIT_MODE_FRAME,
446
447 /* The xdp_frame was created in place as a result of XDP_TX from a
448 * regular RQ. No DMA remapping happened, and the page belongs to us.
449 */
450 MLX5E_XDP_XMIT_MODE_PAGE,
451
452 /* No xdp_frame was created at all, the transmit happened from a UMEM
453 * page. The UMEM Completion Ring producer pointer has to be increased.
454 */
455 MLX5E_XDP_XMIT_MODE_XSK,
456 };
457
458 struct mlx5e_xdp_info {
459 enum mlx5e_xdp_xmit_mode mode;
460 union {
461 struct {
462 struct xdp_frame *xdpf;
463 dma_addr_t dma_addr;
464 } frame;
465 struct {
466 struct mlx5e_rq *rq;
467 struct mlx5e_dma_info di;
468 } page;
469 };
470 };
471
472 struct mlx5e_xdp_xmit_data {
473 dma_addr_t dma_addr;
474 void *data;
475 u32 len;
476 };
477
478 struct mlx5e_xdp_info_fifo {
479 struct mlx5e_xdp_info *xi;
480 u32 *cc;
481 u32 *pc;
482 u32 mask;
483 };
484
485 struct mlx5e_xdp_wqe_info {
486 u8 num_wqebbs;
487 u8 num_pkts;
488 };
489
490 struct mlx5e_xdp_mpwqe {
491 /* Current MPWQE session */
492 struct mlx5e_tx_wqe *wqe;
493 u8 ds_count;
494 u8 pkt_count;
495 u8 inline_on;
496 };
497
498 struct mlx5e_xdpsq;
499 typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *);
500 typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *,
501 struct mlx5e_xdp_xmit_data *,
502 struct mlx5e_xdp_info *,
503 int);
504
505 struct mlx5e_xdpsq {
506 /* data path */
507
508 /* dirtied @completion */
509 u32 xdpi_fifo_cc;
510 u16 cc;
511
512 /* dirtied @xmit */
513 u32 xdpi_fifo_pc ____cacheline_aligned_in_smp;
514 u16 pc;
515 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
516 struct mlx5e_xdp_mpwqe mpwqe;
517
518 struct mlx5e_cq cq;
519
520 /* read only */
521 struct xdp_umem *umem;
522 struct mlx5_wq_cyc wq;
523 struct mlx5e_xdpsq_stats *stats;
524 mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check;
525 mlx5e_fp_xmit_xdp_frame xmit_xdp_frame;
526 struct {
527 struct mlx5e_xdp_wqe_info *wqe_info;
528 struct mlx5e_xdp_info_fifo xdpi_fifo;
529 } db;
530 void __iomem *uar_map;
531 u32 sqn;
532 struct device *pdev;
533 __be32 mkey_be;
534 u8 min_inline_mode;
535 unsigned long state;
536 unsigned int hw_mtu;
537
538 /* control path */
539 struct mlx5_wq_ctrl wq_ctrl;
540 struct mlx5e_channel *channel;
541 } ____cacheline_aligned_in_smp;
542
543 struct mlx5e_icosq {
544 /* data path */
545 u16 cc;
546 u16 pc;
547
548 struct mlx5_wqe_ctrl_seg *doorbell_cseg;
549 struct mlx5e_cq cq;
550
551 /* write@xmit, read@completion */
552 struct {
553 struct mlx5e_sq_wqe_info *ico_wqe;
554 } db;
555
556 /* read only */
557 struct mlx5_wq_cyc wq;
558 void __iomem *uar_map;
559 u32 sqn;
560 unsigned long state;
561
562 /* control path */
563 struct mlx5_wq_ctrl wq_ctrl;
564 struct mlx5e_channel *channel;
565
566 struct work_struct recover_work;
567 } ____cacheline_aligned_in_smp;
568
569 struct mlx5e_wqe_frag_info {
570 struct mlx5e_dma_info *di;
571 u32 offset;
572 bool last_in_page;
573 };
574
575 struct mlx5e_umr_dma_info {
576 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
577 };
578
579 struct mlx5e_mpw_info {
580 struct mlx5e_umr_dma_info umr;
581 u16 consumed_strides;
582 DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
583 };
584
585 #define MLX5E_MAX_RX_FRAGS 4
586
587 /* a single cache unit is capable to serve one napi call (for non-striding rq)
588 * or a MPWQE (for striding rq).
589 */
590 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
591 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
592 #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
593 struct mlx5e_page_cache {
594 u32 head;
595 u32 tail;
596 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
597 };
598
599 struct mlx5e_rq;
600 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
601 typedef struct sk_buff *
602 (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
603 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
604 typedef struct sk_buff *
605 (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
606 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
607 typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq);
608 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
609
610 enum mlx5e_rq_flag {
611 MLX5E_RQ_FLAG_XDP_XMIT,
612 MLX5E_RQ_FLAG_XDP_REDIRECT,
613 };
614
615 struct mlx5e_rq_frag_info {
616 int frag_size;
617 int frag_stride;
618 };
619
620 struct mlx5e_rq_frags_info {
621 struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS];
622 u8 num_frags;
623 u8 log_num_frags;
624 u8 wqe_bulk;
625 };
626
627 struct mlx5e_rq {
628 /* data path */
629 union {
630 struct {
631 struct mlx5_wq_cyc wq;
632 struct mlx5e_wqe_frag_info *frags;
633 struct mlx5e_dma_info *di;
634 struct mlx5e_rq_frags_info info;
635 mlx5e_fp_skb_from_cqe skb_from_cqe;
636 } wqe;
637 struct {
638 struct mlx5_wq_ll wq;
639 struct mlx5e_umr_wqe umr_wqe;
640 struct mlx5e_mpw_info *info;
641 mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq;
642 u16 num_strides;
643 u16 actual_wq_head;
644 u8 log_stride_sz;
645 u8 umr_in_progress;
646 u8 umr_last_bulk;
647 u8 umr_completed;
648 } mpwqe;
649 };
650 struct {
651 u16 umem_headroom;
652 u16 headroom;
653 u8 map_dir; /* dma map direction */
654 } buff;
655
656 struct mlx5e_channel *channel;
657 struct device *pdev;
658 struct net_device *netdev;
659 struct mlx5e_rq_stats *stats;
660 struct mlx5e_cq cq;
661 struct mlx5e_cq_decomp cqd;
662 struct mlx5e_page_cache page_cache;
663 struct hwtstamp_config *tstamp;
664 struct mlx5_clock *clock;
665
666 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
667 mlx5e_fp_post_rx_wqes post_wqes;
668 mlx5e_fp_dealloc_wqe dealloc_wqe;
669
670 unsigned long state;
671 int ix;
672 unsigned int hw_mtu;
673
674 struct dim dim; /* Dynamic Interrupt Moderation */
675
676 /* XDP */
677 struct bpf_prog *xdp_prog;
678 struct mlx5e_xdpsq *xdpsq;
679 DECLARE_BITMAP(flags, 8);
680 struct page_pool *page_pool;
681
682 /* AF_XDP zero-copy */
683 struct zero_copy_allocator zca;
684 struct xdp_umem *umem;
685
686 struct work_struct recover_work;
687
688 /* control */
689 struct mlx5_wq_ctrl wq_ctrl;
690 __be32 mkey_be;
691 u8 wq_type;
692 u32 rqn;
693 struct mlx5_core_dev *mdev;
694 struct mlx5_core_mkey umr_mkey;
695
696 /* XDP read-mostly */
697 struct xdp_rxq_info xdp_rxq;
698 } ____cacheline_aligned_in_smp;
699
700 enum mlx5e_channel_state {
701 MLX5E_CHANNEL_STATE_XSK,
702 MLX5E_CHANNEL_NUM_STATES
703 };
704
705 struct mlx5e_channel {
706 /* data path */
707 struct mlx5e_rq rq;
708 struct mlx5e_xdpsq rq_xdpsq;
709 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
710 struct mlx5e_icosq icosq; /* internal control operations */
711 bool xdp;
712 struct napi_struct napi;
713 struct device *pdev;
714 struct net_device *netdev;
715 __be32 mkey_be;
716 u8 num_tc;
717 u8 lag_port;
718
719 /* XDP_REDIRECT */
720 struct mlx5e_xdpsq xdpsq;
721
722 /* AF_XDP zero-copy */
723 struct mlx5e_rq xskrq;
724 struct mlx5e_xdpsq xsksq;
725 struct mlx5e_icosq xskicosq;
726 /* xskicosq can be accessed from any CPU - the spinlock protects it. */
727 spinlock_t xskicosq_lock;
728
729 /* data path - accessed per napi poll */
730 struct irq_desc *irq_desc;
731 struct mlx5e_ch_stats *stats;
732
733 /* control */
734 struct mlx5e_priv *priv;
735 struct mlx5_core_dev *mdev;
736 struct hwtstamp_config *tstamp;
737 DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES);
738 int ix;
739 int cpu;
740 cpumask_var_t xps_cpumask;
741 };
742
743 struct mlx5e_channels {
744 struct mlx5e_channel **c;
745 unsigned int num;
746 struct mlx5e_params params;
747 };
748
749 struct mlx5e_channel_stats {
750 struct mlx5e_ch_stats ch;
751 struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
752 struct mlx5e_rq_stats rq;
753 struct mlx5e_rq_stats xskrq;
754 struct mlx5e_xdpsq_stats rq_xdpsq;
755 struct mlx5e_xdpsq_stats xdpsq;
756 struct mlx5e_xdpsq_stats xsksq;
757 } ____cacheline_aligned_in_smp;
758
759 enum {
760 MLX5E_STATE_OPENED,
761 MLX5E_STATE_DESTROYING,
762 MLX5E_STATE_XDP_TX_ENABLED,
763 MLX5E_STATE_XDP_OPEN,
764 };
765
766 struct mlx5e_rqt {
767 u32 rqtn;
768 bool enabled;
769 };
770
771 struct mlx5e_tir {
772 u32 tirn;
773 struct mlx5e_rqt rqt;
774 struct list_head list;
775 };
776
777 enum {
778 MLX5E_TC_PRIO = 0,
779 MLX5E_NIC_PRIO
780 };
781
782 struct mlx5e_rss_params {
783 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
784 u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];
785 u8 toeplitz_hash_key[40];
786 u8 hfunc;
787 };
788
789 struct mlx5e_modify_sq_param {
790 int curr_state;
791 int next_state;
792 int rl_update;
793 int rl_index;
794 };
795
796 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
797 struct mlx5e_hv_vhca_stats_agent {
798 struct mlx5_hv_vhca_agent *agent;
799 struct delayed_work work;
800 u16 delay;
801 void *buf;
802 };
803 #endif
804
805 struct mlx5e_xsk {
806 /* UMEMs are stored separately from channels, because we don't want to
807 * lose them when channels are recreated. The kernel also stores UMEMs,
808 * but it doesn't distinguish between zero-copy and non-zero-copy UMEMs,
809 * so rely on our mechanism.
810 */
811 struct xdp_umem **umems;
812 u16 refcnt;
813 bool ever_used;
814 };
815
816 struct mlx5e_priv {
817 /* priv data path fields - start */
818 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
819 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
820 #ifdef CONFIG_MLX5_CORE_EN_DCB
821 struct mlx5e_dcbx_dp dcbx_dp;
822 #endif
823 /* priv data path fields - end */
824
825 u32 msglevel;
826 unsigned long state;
827 struct mutex state_lock; /* Protects Interface state */
828 struct mlx5e_rq drop_rq;
829
830 struct mlx5e_channels channels;
831 u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC];
832 struct mlx5e_rqt indir_rqt;
833 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
834 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
835 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
836 struct mlx5e_tir xsk_tir[MLX5E_MAX_NUM_CHANNELS];
837 struct mlx5e_rss_params rss_params;
838 u32 tx_rates[MLX5E_MAX_NUM_SQS];
839
840 struct mlx5e_flow_steering fs;
841
842 struct workqueue_struct *wq;
843 struct work_struct update_carrier_work;
844 struct work_struct set_rx_mode_work;
845 struct work_struct tx_timeout_work;
846 struct work_struct update_stats_work;
847 struct work_struct monitor_counters_work;
848 struct mlx5_nb monitor_counters_nb;
849
850 struct mlx5_core_dev *mdev;
851 struct net_device *netdev;
852 struct mlx5e_stats stats;
853 struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
854 u16 max_nch;
855 u8 max_opened_tc;
856 struct hwtstamp_config tstamp;
857 u16 q_counter;
858 u16 drop_rq_q_counter;
859 struct notifier_block events_nb;
860
861 #ifdef CONFIG_MLX5_CORE_EN_DCB
862 struct mlx5e_dcbx dcbx;
863 #endif
864
865 const struct mlx5e_profile *profile;
866 void *ppriv;
867 #ifdef CONFIG_MLX5_EN_IPSEC
868 struct mlx5e_ipsec *ipsec;
869 #endif
870 #ifdef CONFIG_MLX5_EN_TLS
871 struct mlx5e_tls *tls;
872 #endif
873 struct devlink_health_reporter *tx_reporter;
874 struct devlink_health_reporter *rx_reporter;
875 struct mlx5e_xsk xsk;
876 #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE)
877 struct mlx5e_hv_vhca_stats_agent stats_agent;
878 #endif
879 };
880
881 struct mlx5e_profile {
882 int (*init)(struct mlx5_core_dev *mdev,
883 struct net_device *netdev,
884 const struct mlx5e_profile *profile, void *ppriv);
885 void (*cleanup)(struct mlx5e_priv *priv);
886 int (*init_rx)(struct mlx5e_priv *priv);
887 void (*cleanup_rx)(struct mlx5e_priv *priv);
888 int (*init_tx)(struct mlx5e_priv *priv);
889 void (*cleanup_tx)(struct mlx5e_priv *priv);
890 void (*enable)(struct mlx5e_priv *priv);
891 void (*disable)(struct mlx5e_priv *priv);
892 int (*update_rx)(struct mlx5e_priv *priv);
893 void (*update_stats)(struct mlx5e_priv *priv);
894 void (*update_carrier)(struct mlx5e_priv *priv);
895 struct {
896 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
897 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
898 } rx_handlers;
899 int max_tc;
900 u8 rq_groups;
901 };
902
903 void mlx5e_build_ptys2ethtool_map(void);
904
905 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
906 struct net_device *sb_dev);
907 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
908 netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb,
909 struct mlx5e_tx_wqe *wqe, u16 pi, bool xmit_more);
910
911 void mlx5e_trigger_irq(struct mlx5e_icosq *sq);
912 void mlx5e_completion_event(struct mlx5_core_cq *mcq, struct mlx5_eqe *eqe);
913 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
914 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
915 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
916 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
917 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
918
mlx5e_rqwq_get_size(struct mlx5e_rq * rq)919 static inline u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
920 {
921 switch (rq->wq_type) {
922 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
923 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
924 default:
925 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
926 }
927 }
928
mlx5e_rqwq_get_cur_sz(struct mlx5e_rq * rq)929 static inline u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
930 {
931 switch (rq->wq_type) {
932 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
933 return rq->mpwqe.wq.cur_sz;
934 default:
935 return rq->wqe.wq.cur_sz;
936 }
937 }
938
939 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev);
940 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
941 struct mlx5e_params *params);
942
943 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info);
944 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
945 struct mlx5e_dma_info *dma_info,
946 bool recycle);
947 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
948 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
949 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
950 void mlx5e_poll_ico_cq(struct mlx5e_cq *cq);
951 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq);
952 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
953 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
954 struct sk_buff *
955 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
956 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
957 struct sk_buff *
958 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
959 u16 cqe_bcnt, u32 head_offset, u32 page_idx);
960 struct sk_buff *
961 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
962 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
963 struct sk_buff *
964 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
965 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt);
966
967 void mlx5e_update_stats(struct mlx5e_priv *priv);
968 void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats);
969 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s);
970
971 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
972 int mlx5e_self_test_num(struct mlx5e_priv *priv);
973 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
974 u64 *buf);
975 void mlx5e_set_rx_mode_work(struct work_struct *work);
976
977 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr);
978 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr);
979 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
980
981 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
982 u16 vid);
983 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
984 u16 vid);
985 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
986
987 struct mlx5e_redirect_rqt_param {
988 bool is_rss;
989 union {
990 u32 rqn; /* Direct RQN (Non-RSS) */
991 struct {
992 u8 hfunc;
993 struct mlx5e_channels *channels;
994 } rss; /* RSS data */
995 };
996 };
997
998 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
999 struct mlx5e_redirect_rqt_param rrp);
1000 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
1001 const struct mlx5e_tirc_config *ttconfig,
1002 void *tirc, bool inner);
1003 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen);
1004 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt);
1005
1006 struct mlx5e_xsk_param;
1007
1008 struct mlx5e_rq_param;
1009 int mlx5e_open_rq(struct mlx5e_channel *c, struct mlx5e_params *params,
1010 struct mlx5e_rq_param *param, struct mlx5e_xsk_param *xsk,
1011 struct xdp_umem *umem, struct mlx5e_rq *rq);
1012 int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time);
1013 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1014 void mlx5e_close_rq(struct mlx5e_rq *rq);
1015
1016 struct mlx5e_sq_param;
1017 int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params,
1018 struct mlx5e_sq_param *param, struct mlx5e_icosq *sq);
1019 void mlx5e_close_icosq(struct mlx5e_icosq *sq);
1020 int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
1021 struct mlx5e_sq_param *param, struct xdp_umem *umem,
1022 struct mlx5e_xdpsq *sq, bool is_redirect);
1023 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
1024
1025 struct mlx5e_cq_param;
1026 int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
1027 struct mlx5e_cq_param *param, struct mlx5e_cq *cq);
1028 void mlx5e_close_cq(struct mlx5e_cq *cq);
1029
1030 int mlx5e_open_locked(struct net_device *netdev);
1031 int mlx5e_close_locked(struct net_device *netdev);
1032
1033 int mlx5e_open_channels(struct mlx5e_priv *priv,
1034 struct mlx5e_channels *chs);
1035 void mlx5e_close_channels(struct mlx5e_channels *chs);
1036
1037 /* Function pointer to be used to modify WH settings while
1038 * switching channels
1039 */
1040 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
1041 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv);
1042 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
1043 struct mlx5e_channels *new_chs,
1044 mlx5e_fp_hw_modify hw_modify);
1045 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
1046 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
1047
1048 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
1049 int num_channels);
1050 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params,
1051 u8 cq_period_mode);
1052 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
1053 u8 cq_period_mode);
1054 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params);
1055 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
1056 struct mlx5e_params *params);
1057 int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state);
1058 void mlx5e_activate_rq(struct mlx5e_rq *rq);
1059 void mlx5e_deactivate_rq(struct mlx5e_rq *rq);
1060 void mlx5e_free_rx_descs(struct mlx5e_rq *rq);
1061 void mlx5e_activate_icosq(struct mlx5e_icosq *icosq);
1062 void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
1063
1064 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1065 struct mlx5e_modify_sq_param *p);
1066 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
1067 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
1068
mlx5_tx_swp_supported(struct mlx5_core_dev * mdev)1069 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
1070 {
1071 return MLX5_CAP_ETH(mdev, swp) &&
1072 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso);
1073 }
1074
1075 extern const struct ethtool_ops mlx5e_ethtool_ops;
1076 #ifdef CONFIG_MLX5_CORE_EN_DCB
1077 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
1078 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
1079 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
1080 void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv);
1081 void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv);
1082 #endif
1083
1084 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
1085 struct mlx5e_tir *tir, u32 *in, int inlen);
1086 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
1087 struct mlx5e_tir *tir);
1088 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
1089 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
1090 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
1091
1092 /* common netdev helpers */
1093 void mlx5e_create_q_counters(struct mlx5e_priv *priv);
1094 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv);
1095 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
1096 struct mlx5e_rq *drop_rq);
1097 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq);
1098
1099 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
1100
1101 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1102 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc);
1103
1104 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1105 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1106 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1107 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv, struct mlx5e_tir *tirs);
1108 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1109
1110 int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn);
1111 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1112
1113 int mlx5e_create_tises(struct mlx5e_priv *priv);
1114 void mlx5e_destroy_tises(struct mlx5e_priv *priv);
1115 int mlx5e_update_nic_rx(struct mlx5e_priv *priv);
1116 void mlx5e_update_carrier(struct mlx5e_priv *priv);
1117 int mlx5e_close(struct net_device *netdev);
1118 int mlx5e_open(struct net_device *netdev);
1119 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv);
1120
1121 void mlx5e_queue_update_stats(struct mlx5e_priv *priv);
1122 int mlx5e_bits_invert(unsigned long a, int size);
1123
1124 typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv);
1125 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv);
1126 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
1127 change_hw_mtu_cb set_mtu_cb);
1128
1129 /* ethtool helpers */
1130 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
1131 struct ethtool_drvinfo *drvinfo);
1132 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv,
1133 uint32_t stringset, uint8_t *data);
1134 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset);
1135 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
1136 struct ethtool_stats *stats, u64 *data);
1137 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
1138 struct ethtool_ringparam *param);
1139 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
1140 struct ethtool_ringparam *param);
1141 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
1142 struct ethtool_channels *ch);
1143 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
1144 struct ethtool_channels *ch);
1145 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
1146 struct ethtool_coalesce *coal);
1147 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
1148 struct ethtool_coalesce *coal);
1149 int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv,
1150 struct ethtool_link_ksettings *link_ksettings);
1151 int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv,
1152 const struct ethtool_link_ksettings *link_ksettings);
1153 u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv);
1154 u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv);
1155 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1156 struct ethtool_ts_info *info);
1157 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1158 struct ethtool_flash *flash);
1159 void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv,
1160 struct ethtool_pauseparam *pauseparam);
1161 int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv,
1162 struct ethtool_pauseparam *pauseparam);
1163
1164 /* mlx5e generic netdev management API */
1165 int mlx5e_netdev_init(struct net_device *netdev,
1166 struct mlx5e_priv *priv,
1167 struct mlx5_core_dev *mdev,
1168 const struct mlx5e_profile *profile,
1169 void *ppriv);
1170 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv);
1171 struct net_device*
1172 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1173 int nch, void *ppriv);
1174 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1175 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1176 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1177 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv);
1178 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1179 struct mlx5e_xsk *xsk,
1180 struct mlx5e_rss_params *rss_params,
1181 struct mlx5e_params *params,
1182 u16 max_channels, u16 mtu);
1183 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
1184 struct mlx5e_params *params);
1185 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
1186 u16 num_channels);
1187 void mlx5e_rx_dim_work(struct work_struct *work);
1188 void mlx5e_tx_dim_work(struct work_struct *work);
1189
1190 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1191 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti);
1192 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
1193 struct net_device *netdev,
1194 netdev_features_t features);
1195 int mlx5e_set_features(struct net_device *netdev, netdev_features_t features);
1196 #ifdef CONFIG_MLX5_ESWITCH
1197 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac);
1198 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate);
1199 int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi);
1200 int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats);
1201 #endif
1202 #endif /* __MLX5_EN_H__ */
1203
