1 /* 2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef __MLX5_PORT_H__ 34 #define __MLX5_PORT_H__ 35 36 #include <linux/mlx5/driver.h> 37 38 enum mlx5_beacon_duration { 39 MLX5_BEACON_DURATION_OFF = 0x0, 40 MLX5_BEACON_DURATION_INF = 0xffff, 41 }; 42 43 enum mlx5_module_id { 44 MLX5_MODULE_ID_SFP = 0x3, 45 MLX5_MODULE_ID_QSFP = 0xC, 46 MLX5_MODULE_ID_QSFP_PLUS = 0xD, 47 MLX5_MODULE_ID_QSFP28 = 0x11, 48 }; 49 50 enum mlx5_an_status { 51 MLX5_AN_UNAVAILABLE = 0, 52 MLX5_AN_COMPLETE = 1, 53 MLX5_AN_FAILED = 2, 54 MLX5_AN_LINK_UP = 3, 55 MLX5_AN_LINK_DOWN = 4, 56 }; 57 58 #define MLX5_EEPROM_MAX_BYTES 32 59 #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff 60 #define MLX5_I2C_ADDR_LOW 0x50 61 #define MLX5_I2C_ADDR_HIGH 0x51 62 #define MLX5_EEPROM_PAGE_LENGTH 256 63 #define MLX5_EEPROM_HIGH_PAGE_LENGTH 128 64 65 enum mlx5e_link_mode { 66 MLX5E_1000BASE_CX_SGMII = 0, 67 MLX5E_1000BASE_KX = 1, 68 MLX5E_10GBASE_CX4 = 2, 69 MLX5E_10GBASE_KX4 = 3, 70 MLX5E_10GBASE_KR = 4, 71 MLX5E_20GBASE_KR2 = 5, 72 MLX5E_40GBASE_CR4 = 6, 73 MLX5E_40GBASE_KR4 = 7, 74 MLX5E_56GBASE_R4 = 8, 75 MLX5E_10GBASE_CR = 12, 76 MLX5E_10GBASE_SR = 13, 77 MLX5E_10GBASE_ER = 14, 78 MLX5E_40GBASE_SR4 = 15, 79 MLX5E_40GBASE_LR4 = 16, 80 MLX5E_50GBASE_SR2 = 18, 81 MLX5E_100GBASE_CR4 = 20, 82 MLX5E_100GBASE_SR4 = 21, 83 MLX5E_100GBASE_KR4 = 22, 84 MLX5E_100GBASE_LR4 = 23, 85 MLX5E_100BASE_TX = 24, 86 MLX5E_1000BASE_T = 25, 87 MLX5E_10GBASE_T = 26, 88 MLX5E_25GBASE_CR = 27, 89 MLX5E_25GBASE_KR = 28, 90 MLX5E_25GBASE_SR = 29, 91 MLX5E_50GBASE_CR2 = 30, 92 MLX5E_50GBASE_KR2 = 31, 93 MLX5E_LINK_MODES_NUMBER, 94 }; 95 96 enum mlx5e_ext_link_mode { 97 MLX5E_SGMII_100M = 0, 98 MLX5E_1000BASE_X_SGMII = 1, 99 MLX5E_5GBASE_R = 3, 100 MLX5E_10GBASE_XFI_XAUI_1 = 4, 101 MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5, 102 MLX5E_25GAUI_1_25GBASE_CR_KR = 6, 103 MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7, 104 MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8, 105 MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9, 106 MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10, 107 MLX5E_100GAUI_1_100GBASE_CR_KR = 11, 108 MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12, 109 MLX5E_200GAUI_2_200GBASE_CR2_KR2 = 13, 110 MLX5E_400GAUI_8 = 15, 111 MLX5E_400GAUI_4_400GBASE_CR4_KR4 = 16, 112 MLX5E_EXT_LINK_MODES_NUMBER, 113 }; 114 115 enum mlx5e_connector_type { 116 MLX5E_PORT_UNKNOWN = 0, 117 MLX5E_PORT_NONE = 1, 118 MLX5E_PORT_TP = 2, 119 MLX5E_PORT_AUI = 3, 120 MLX5E_PORT_BNC = 4, 121 MLX5E_PORT_MII = 5, 122 MLX5E_PORT_FIBRE = 6, 123 MLX5E_PORT_DA = 7, 124 MLX5E_PORT_OTHER = 8, 125 MLX5E_CONNECTOR_TYPE_NUMBER, 126 }; 127 128 enum mlx5_ptys_width { 129 MLX5_PTYS_WIDTH_1X = 1 << 0, 130 MLX5_PTYS_WIDTH_2X = 1 << 1, 131 MLX5_PTYS_WIDTH_4X = 1 << 2, 132 MLX5_PTYS_WIDTH_8X = 1 << 3, 133 MLX5_PTYS_WIDTH_12X = 1 << 4, 134 }; 135 136 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) 137 #define MLX5_GET_ETH_PROTO(reg, out, ext, field) \ 138 (ext ? MLX5_GET(reg, out, ext_##field) : \ 139 MLX5_GET(reg, out, field)) 140 141 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 142 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 143 int ptys_size, int proto_mask, u8 local_port); 144 145 int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper, 146 u16 *proto_oper, u8 local_port); 147 void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 148 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, 149 enum mlx5_port_status status); 150 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, 151 enum mlx5_port_status *status); 152 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration); 153 154 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port); 155 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port); 156 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu, 157 u8 port); 158 159 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev, 160 u8 *vl_hw_cap, u8 local_port); 161 162 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause); 163 int mlx5_query_port_pause(struct mlx5_core_dev *dev, 164 u32 *rx_pause, u32 *tx_pause); 165 166 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx); 167 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, 168 u8 *pfc_en_rx); 169 170 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev, 171 u16 stall_critical_watermark, 172 u16 stall_minor_watermark); 173 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev, 174 u16 *stall_critical_watermark, u16 *stall_minor_watermark); 175 176 int mlx5_max_tc(struct mlx5_core_dev *mdev); 177 178 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc); 179 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev, 180 u8 prio, u8 *tc); 181 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group); 182 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev, 183 u8 tc, u8 *tc_group); 184 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw); 185 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, 186 u8 tc, u8 *bw_pct); 187 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev, 188 u8 *max_bw_value, 189 u8 *max_bw_unit); 190 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev, 191 u8 *max_bw_value, 192 u8 *max_bw_unit); 193 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode); 194 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode); 195 196 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen); 197 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen); 198 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable); 199 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported, 200 bool *enabled); 201 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev, 202 u16 offset, u16 size, u8 *data); 203 204 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out); 205 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in); 206 207 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state); 208 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state); 209 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio); 210 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio); 211 #endif /* __MLX5_PORT_H__ */ 212
