1 /*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #ifndef _MLX4_EN_H_
35 #define _MLX4_EN_H_
36
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #include <linux/net_tstamp.h>
44 #ifdef CONFIG_MLX4_EN_DCB
45 #include <linux/dcbnl.h>
46 #endif
47 #include <linux/cpu_rmap.h>
48 #include <linux/ptp_clock_kernel.h>
49 #include <net/xdp.h>
50
51 #include <linux/mlx4/device.h>
52 #include <linux/mlx4/qp.h>
53 #include <linux/mlx4/cq.h>
54 #include <linux/mlx4/srq.h>
55 #include <linux/mlx4/doorbell.h>
56 #include <linux/mlx4/cmd.h>
57
58 #include "en_port.h"
59 #include "mlx4_stats.h"
60
61 #define DRV_NAME "mlx4_en"
62 #define DRV_VERSION "4.0-0"
63
64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
65
66 /*
67 * Device constants
68 */
69
70
71 #define MLX4_EN_PAGE_SHIFT 12
72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
73 #define DEF_RX_RINGS 16
74 #define MAX_RX_RINGS 128
75 #define MIN_RX_RINGS 1
76 #define LOG_TXBB_SIZE 6
77 #define TXBB_SIZE BIT(LOG_TXBB_SIZE)
78 #define HEADROOM (2048 / TXBB_SIZE + 1)
79 #define STAMP_STRIDE 64
80 #define STAMP_DWORDS (STAMP_STRIDE / 4)
81 #define STAMP_SHIFT 31
82 #define STAMP_VAL 0x7fffffff
83 #define STATS_DELAY (HZ / 4)
84 #define SERVICE_TASK_DELAY (HZ / 4)
85 #define MAX_NUM_OF_FS_RULES 256
86
87 #define MLX4_EN_FILTER_HASH_SHIFT 4
88 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
89
90 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
91 #define MAX_DESC_SIZE 512
92 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
93
94 /*
95 * OS related constants and tunables
96 */
97
98 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
99 #define MLX4_EN_PRIV_FLAGS_PHV 2
100
101 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
102
103 /* Use the maximum between 16384 and a single page */
104 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
105
106 #define MLX4_EN_MAX_RX_FRAGS 4
107
108 /* Maximum ring sizes */
109 #define MLX4_EN_MAX_TX_SIZE 8192
110 #define MLX4_EN_MAX_RX_SIZE 8192
111
112 /* Minimum ring size for our page-allocation scheme to work */
113 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
114 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
115
116 #define MLX4_EN_SMALL_PKT_SIZE 64
117 #define MLX4_EN_MIN_TX_RING_P_UP 1
118 #define MLX4_EN_MAX_TX_RING_P_UP 32
119 #define MLX4_EN_NUM_UP_LOW 1
120 #define MLX4_EN_NUM_UP_HIGH 8
121 #define MLX4_EN_DEF_RX_RING_SIZE 1024
122 #define MLX4_EN_DEF_TX_RING_SIZE MLX4_EN_DEF_RX_RING_SIZE
123 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
124 MLX4_EN_NUM_UP_HIGH)
125
126 #define MLX4_EN_DEFAULT_TX_WORK 256
127
128 /* Target number of packets to coalesce with interrupt moderation */
129 #define MLX4_EN_RX_COAL_TARGET 44
130 #define MLX4_EN_RX_COAL_TIME 0x10
131
132 #define MLX4_EN_TX_COAL_PKTS 16
133 #define MLX4_EN_TX_COAL_TIME 0x10
134
135 #define MLX4_EN_MAX_COAL_PKTS U16_MAX
136 #define MLX4_EN_MAX_COAL_TIME U16_MAX
137
138 #define MLX4_EN_RX_RATE_LOW 400000
139 #define MLX4_EN_RX_COAL_TIME_LOW 0
140 #define MLX4_EN_RX_RATE_HIGH 450000
141 #define MLX4_EN_RX_COAL_TIME_HIGH 128
142 #define MLX4_EN_RX_SIZE_THRESH 1024
143 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
144 #define MLX4_EN_SAMPLE_INTERVAL 0
145 #define MLX4_EN_AVG_PKT_SMALL 256
146
147 #define MLX4_EN_AUTO_CONF 0xffff
148
149 #define MLX4_EN_DEF_RX_PAUSE 1
150 #define MLX4_EN_DEF_TX_PAUSE 1
151
152 /* Interval between successive polls in the Tx routine when polling is used
153 instead of interrupts (in per-core Tx rings) - should be power of 2 */
154 #define MLX4_EN_TX_POLL_MODER 16
155 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
156
157 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
158 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
159 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
160 #define PREAMBLE_LEN 8
161 #define MLX4_SELFTEST_LB_MIN_MTU (MLX4_LOOPBACK_TEST_PAYLOAD + NET_IP_ALIGN + \
162 ETH_HLEN + PREAMBLE_LEN)
163
164 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
165 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
166 */
167 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
168 #define ETH_BCAST 0xffffffffffffULL
169
170 #define MLX4_EN_LOOPBACK_RETRIES 5
171 #define MLX4_EN_LOOPBACK_TIMEOUT 100
172
173 #ifdef MLX4_EN_PERF_STAT
174 /* Number of samples to 'average' */
175 #define AVG_SIZE 128
176 #define AVG_FACTOR 1024
177
178 #define INC_PERF_COUNTER(cnt) (++(cnt))
179 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
180 #define AVG_PERF_COUNTER(cnt, sample) \
181 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
182 #define GET_PERF_COUNTER(cnt) (cnt)
183 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
184
185 #else
186
187 #define INC_PERF_COUNTER(cnt) do {} while (0)
188 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
189 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
190 #define GET_PERF_COUNTER(cnt) (0)
191 #define GET_AVG_PERF_COUNTER(cnt) (0)
192 #endif /* MLX4_EN_PERF_STAT */
193
194 /* Constants for TX flow */
195 enum {
196 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
197 MAX_BF = 256,
198 MIN_PKT_LEN = 17,
199 };
200
201 /*
202 * Configurables
203 */
204
205 enum cq_type {
206 /* keep tx types first */
207 TX,
208 TX_XDP,
209 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
210 RX,
211 };
212
213
214 /*
215 * Useful macros
216 */
217 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
218 #define XNOR(x, y) (!(x) == !(y))
219
220
221 struct mlx4_en_tx_info {
222 union {
223 struct sk_buff *skb;
224 struct page *page;
225 };
226 dma_addr_t map0_dma;
227 u32 map0_byte_count;
228 u32 nr_txbb;
229 u32 nr_bytes;
230 u8 linear;
231 u8 data_offset;
232 u8 inl;
233 u8 ts_requested;
234 u8 nr_maps;
235 } ____cacheline_aligned_in_smp;
236
237
238 #define MLX4_EN_BIT_DESC_OWN 0x80000000
239 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
240 #define MLX4_EN_MEMTYPE_PAD 0x100
241 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
242
243
244 struct mlx4_en_tx_desc {
245 struct mlx4_wqe_ctrl_seg ctrl;
246 union {
247 struct mlx4_wqe_data_seg data; /* at least one data segment */
248 struct mlx4_wqe_lso_seg lso;
249 struct mlx4_wqe_inline_seg inl;
250 };
251 };
252
253 #define MLX4_EN_USE_SRQ 0x01000000
254
255 #define MLX4_EN_CX3_LOW_ID 0x1000
256 #define MLX4_EN_CX3_HIGH_ID 0x1005
257
258 struct mlx4_en_rx_alloc {
259 struct page *page;
260 dma_addr_t dma;
261 u32 page_offset;
262 };
263
264 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
265
266 struct mlx4_en_page_cache {
267 u32 index;
268 struct {
269 struct page *page;
270 dma_addr_t dma;
271 } buf[MLX4_EN_CACHE_SIZE];
272 };
273
274 enum {
275 MLX4_EN_TX_RING_STATE_RECOVERING,
276 };
277
278 struct mlx4_en_priv;
279
280 struct mlx4_en_tx_ring {
281 /* cache line used and dirtied in tx completion
282 * (mlx4_en_free_tx_buf())
283 */
284 u32 last_nr_txbb;
285 u32 cons;
286 unsigned long wake_queue;
287 struct netdev_queue *tx_queue;
288 u32 (*free_tx_desc)(struct mlx4_en_priv *priv,
289 struct mlx4_en_tx_ring *ring,
290 int index,
291 u64 timestamp, int napi_mode);
292 struct mlx4_en_rx_ring *recycle_ring;
293
294 /* cache line used and dirtied in mlx4_en_xmit() */
295 u32 prod ____cacheline_aligned_in_smp;
296 unsigned int tx_dropped;
297 unsigned long bytes;
298 unsigned long packets;
299 unsigned long tx_csum;
300 unsigned long tso_packets;
301 unsigned long xmit_more;
302 struct mlx4_bf bf;
303
304 /* Following part should be mostly read */
305 __be32 doorbell_qpn;
306 __be32 mr_key;
307 u32 size; /* number of TXBBs */
308 u32 size_mask;
309 u32 full_size;
310 u32 buf_size;
311 void *buf;
312 struct mlx4_en_tx_info *tx_info;
313 int qpn;
314 u8 queue_index;
315 bool bf_enabled;
316 bool bf_alloced;
317 u8 hwtstamp_tx_type;
318 u8 *bounce_buf;
319
320 /* Not used in fast path
321 * Only queue_stopped might be used if BQL is not properly working.
322 */
323 unsigned long queue_stopped;
324 unsigned long state;
325 struct mlx4_hwq_resources sp_wqres;
326 struct mlx4_qp sp_qp;
327 struct mlx4_qp_context sp_context;
328 cpumask_t sp_affinity_mask;
329 enum mlx4_qp_state sp_qp_state;
330 u16 sp_stride;
331 u16 sp_cqn; /* index of port CQ associated with this ring */
332 } ____cacheline_aligned_in_smp;
333
334 struct mlx4_en_rx_desc {
335 /* actual number of entries depends on rx ring stride */
336 struct mlx4_wqe_data_seg data[0];
337 };
338
339 struct mlx4_en_rx_ring {
340 struct mlx4_hwq_resources wqres;
341 u32 size ; /* number of Rx descs*/
342 u32 actual_size;
343 u32 size_mask;
344 u16 stride;
345 u16 log_stride;
346 u16 cqn; /* index of port CQ associated with this ring */
347 u32 prod;
348 u32 cons;
349 u32 buf_size;
350 u8 fcs_del;
351 void *buf;
352 void *rx_info;
353 struct bpf_prog __rcu *xdp_prog;
354 struct mlx4_en_page_cache page_cache;
355 unsigned long bytes;
356 unsigned long packets;
357 unsigned long csum_ok;
358 unsigned long csum_none;
359 unsigned long csum_complete;
360 unsigned long rx_alloc_pages;
361 unsigned long xdp_drop;
362 unsigned long xdp_tx;
363 unsigned long xdp_tx_full;
364 unsigned long dropped;
365 int hwtstamp_rx_filter;
366 cpumask_var_t affinity_mask;
367 struct xdp_rxq_info xdp_rxq;
368 };
369
370 struct mlx4_en_cq {
371 struct mlx4_cq mcq;
372 struct mlx4_hwq_resources wqres;
373 int ring;
374 struct net_device *dev;
375 union {
376 struct napi_struct napi;
377 bool xdp_busy;
378 };
379 int size;
380 int buf_size;
381 int vector;
382 enum cq_type type;
383 u16 moder_time;
384 u16 moder_cnt;
385 struct mlx4_cqe *buf;
386 #define MLX4_EN_OPCODE_ERROR 0x1e
387
388 struct irq_desc *irq_desc;
389 };
390
391 struct mlx4_en_port_profile {
392 u32 flags;
393 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
394 u32 rx_ring_num;
395 u32 tx_ring_size;
396 u32 rx_ring_size;
397 u8 num_tx_rings_p_up;
398 u8 rx_pause;
399 u8 rx_ppp;
400 u8 tx_pause;
401 u8 tx_ppp;
402 u8 num_up;
403 int rss_rings;
404 int inline_thold;
405 struct hwtstamp_config hwtstamp_config;
406 };
407
408 struct mlx4_en_profile {
409 int udp_rss;
410 u8 rss_mask;
411 u32 active_ports;
412 u32 small_pkt_int;
413 u8 no_reset;
414 u8 max_num_tx_rings_p_up;
415 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
416 };
417
418 struct mlx4_en_dev {
419 struct mlx4_dev *dev;
420 struct pci_dev *pdev;
421 struct mutex state_lock;
422 struct net_device *pndev[MLX4_MAX_PORTS + 1];
423 struct net_device *upper[MLX4_MAX_PORTS + 1];
424 u32 port_cnt;
425 bool device_up;
426 struct mlx4_en_profile profile;
427 u32 LSO_support;
428 struct workqueue_struct *workqueue;
429 struct device *dma_device;
430 void __iomem *uar_map;
431 struct mlx4_uar priv_uar;
432 struct mlx4_mr mr;
433 u32 priv_pdn;
434 spinlock_t uar_lock;
435 u8 mac_removed[MLX4_MAX_PORTS + 1];
436 u32 nominal_c_mult;
437 struct cyclecounter cycles;
438 seqlock_t clock_lock;
439 struct timecounter clock;
440 unsigned long last_overflow_check;
441 struct ptp_clock *ptp_clock;
442 struct ptp_clock_info ptp_clock_info;
443 struct notifier_block nb;
444 };
445
446
447 struct mlx4_en_rss_map {
448 int base_qpn;
449 struct mlx4_qp qps[MAX_RX_RINGS];
450 enum mlx4_qp_state state[MAX_RX_RINGS];
451 struct mlx4_qp *indir_qp;
452 enum mlx4_qp_state indir_state;
453 };
454
455 enum mlx4_en_port_flag {
456 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
457 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
458 };
459
460 struct mlx4_en_port_state {
461 int link_state;
462 int link_speed;
463 int transceiver;
464 u32 flags;
465 };
466
467 enum mlx4_en_mclist_act {
468 MCLIST_NONE,
469 MCLIST_REM,
470 MCLIST_ADD,
471 };
472
473 struct mlx4_en_mc_list {
474 struct list_head list;
475 enum mlx4_en_mclist_act action;
476 u8 addr[ETH_ALEN];
477 u64 reg_id;
478 u64 tunnel_reg_id;
479 };
480
481 struct mlx4_en_frag_info {
482 u16 frag_size;
483 u32 frag_stride;
484 };
485
486 #ifdef CONFIG_MLX4_EN_DCB
487 /* Minimal TC BW - setting to 0 will block traffic */
488 #define MLX4_EN_BW_MIN 1
489 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
490
491 #define MLX4_EN_TC_VENDOR 0
492 #define MLX4_EN_TC_ETS 7
493
494 enum dcb_pfc_type {
495 pfc_disabled = 0,
496 pfc_enabled_full,
497 pfc_enabled_tx,
498 pfc_enabled_rx
499 };
500
501 struct mlx4_en_cee_config {
502 bool pfc_state;
503 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP_HIGH];
504 };
505 #endif
506
507 struct ethtool_flow_id {
508 struct list_head list;
509 struct ethtool_rx_flow_spec flow_spec;
510 u64 id;
511 };
512
513 enum {
514 MLX4_EN_FLAG_PROMISC = (1 << 0),
515 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
516 /* whether we need to enable hardware loopback by putting dmac
517 * in Tx WQE
518 */
519 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
520 /* whether we need to drop packets that hardware loopback-ed */
521 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
522 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
523 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),
524 #ifdef CONFIG_MLX4_EN_DCB
525 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6),
526 #endif
527 };
528
529 #define PORT_BEACON_MAX_LIMIT (65535)
530 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
531 #define MLX4_EN_MAC_HASH_IDX 5
532
533 struct mlx4_en_stats_bitmap {
534 DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
535 struct mutex mutex; /* for mutual access to stats bitmap */
536 };
537
538 enum {
539 MLX4_EN_STATE_FLAG_RESTARTING,
540 };
541
542 struct mlx4_en_priv {
543 struct mlx4_en_dev *mdev;
544 struct mlx4_en_port_profile *prof;
545 struct net_device *dev;
546 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
547 struct mlx4_en_port_state port_state;
548 spinlock_t stats_lock;
549 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
550 /* To allow rules removal while port is going down */
551 struct list_head ethtool_list;
552
553 unsigned long last_moder_packets[MAX_RX_RINGS];
554 unsigned long last_moder_tx_packets;
555 unsigned long last_moder_bytes[MAX_RX_RINGS];
556 unsigned long last_moder_jiffies;
557 int last_moder_time[MAX_RX_RINGS];
558 u16 rx_usecs;
559 u16 rx_frames;
560 u16 tx_usecs;
561 u16 tx_frames;
562 u32 pkt_rate_low;
563 u16 rx_usecs_low;
564 u32 pkt_rate_high;
565 u16 rx_usecs_high;
566 u32 sample_interval;
567 u32 adaptive_rx_coal;
568 u32 msg_enable;
569 u32 loopback_ok;
570 u32 validate_loopback;
571
572 struct mlx4_hwq_resources res;
573 int link_state;
574 int last_link_state;
575 bool port_up;
576 int port;
577 int registered;
578 int allocated;
579 int stride;
580 unsigned char current_mac[ETH_ALEN + 2];
581 int mac_index;
582 unsigned max_mtu;
583 int base_qpn;
584 int cqe_factor;
585 int cqe_size;
586
587 struct mlx4_en_rss_map rss_map;
588 __be32 ctrl_flags;
589 u32 flags;
590 u8 num_tx_rings_p_up;
591 u32 tx_work_limit;
592 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
593 u32 rx_ring_num;
594 u32 rx_skb_size;
595 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
596 u8 num_frags;
597 u8 log_rx_info;
598 u8 dma_dir;
599 u16 rx_headroom;
600
601 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
602 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
603 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
604 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
605 struct mlx4_qp drop_qp;
606 struct work_struct rx_mode_task;
607 struct work_struct restart_task;
608 struct work_struct linkstate_task;
609 struct delayed_work stats_task;
610 struct delayed_work service_task;
611 struct mlx4_en_perf_stats pstats;
612 struct mlx4_en_pkt_stats pkstats;
613 struct mlx4_en_counter_stats pf_stats;
614 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
615 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
616 struct mlx4_en_flow_stats_rx rx_flowstats;
617 struct mlx4_en_flow_stats_tx tx_flowstats;
618 struct mlx4_en_port_stats port_stats;
619 struct mlx4_en_xdp_stats xdp_stats;
620 struct mlx4_en_phy_stats phy_stats;
621 struct mlx4_en_stats_bitmap stats_bitmap;
622 struct list_head mc_list;
623 struct list_head curr_list;
624 u64 broadcast_id;
625 struct mlx4_en_stat_out_mbox hw_stats;
626 int vids[128];
627 bool wol;
628 struct device *ddev;
629 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
630 struct hwtstamp_config hwtstamp_config;
631 u32 counter_index;
632
633 #ifdef CONFIG_MLX4_EN_DCB
634 #define MLX4_EN_DCB_ENABLED 0x3
635 struct ieee_ets ets;
636 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
637 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
638 struct mlx4_en_cee_config cee_config;
639 u8 dcbx_cap;
640 #endif
641 #ifdef CONFIG_RFS_ACCEL
642 spinlock_t filters_lock;
643 int last_filter_id;
644 struct list_head filters;
645 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
646 #endif
647 u64 tunnel_reg_id;
648 __be16 vxlan_port;
649
650 u32 pflags;
651 u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
652 u8 rss_hash_fn;
653 unsigned long state;
654 };
655
656 enum mlx4_en_wol {
657 MLX4_EN_WOL_MAGIC = (1ULL << 61),
658 MLX4_EN_WOL_ENABLED = (1ULL << 62),
659 };
660
661 struct mlx4_mac_entry {
662 struct hlist_node hlist;
663 unsigned char mac[ETH_ALEN + 2];
664 u64 reg_id;
665 struct rcu_head rcu;
666 };
667
mlx4_en_get_cqe(void * buf,int idx,int cqe_sz)668 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
669 {
670 return buf + idx * cqe_sz;
671 }
672
673 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
674
675 void mlx4_en_init_ptys2ethtool_map(void);
676 void mlx4_en_update_loopback_state(struct net_device *dev,
677 netdev_features_t features);
678
679 void mlx4_en_destroy_netdev(struct net_device *dev);
680 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
681 struct mlx4_en_port_profile *prof);
682
683 int mlx4_en_start_port(struct net_device *dev);
684 void mlx4_en_stop_port(struct net_device *dev, int detach);
685
686 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
687 struct mlx4_en_stats_bitmap *stats_bitmap,
688 u8 rx_ppp, u8 rx_pause,
689 u8 tx_ppp, u8 tx_pause);
690
691 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
692 struct mlx4_en_priv *tmp,
693 struct mlx4_en_port_profile *prof,
694 bool carry_xdp_prog);
695 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
696 struct mlx4_en_priv *tmp);
697
698 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
699 int entries, int ring, enum cq_type mode, int node);
700 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
701 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
702 int cq_idx);
703 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
704 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
705 void mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
706
707 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
708 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
709 struct net_device *sb_dev);
710 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
711 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
712 struct mlx4_en_rx_alloc *frame,
713 struct mlx4_en_priv *priv, unsigned int length,
714 int tx_ind, bool *doorbell_pending);
715 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
716 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
717 struct mlx4_en_rx_alloc *frame);
718
719 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
720 struct mlx4_en_tx_ring **pring,
721 u32 size, u16 stride,
722 int node, int queue_index);
723 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
724 struct mlx4_en_tx_ring **pring);
725 void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv,
726 struct mlx4_en_tx_ring *ring);
727 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
728 struct mlx4_en_tx_ring *ring,
729 int cq, int user_prio);
730 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
731 struct mlx4_en_tx_ring *ring);
732 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
733 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
734 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
735 struct mlx4_en_rx_ring **pring,
736 u32 size, u16 stride, int node, int queue_index);
737 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
738 struct mlx4_en_rx_ring **pring,
739 u32 size, u16 stride);
740 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
741 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
742 struct mlx4_en_rx_ring *ring);
743 int mlx4_en_process_rx_cq(struct net_device *dev,
744 struct mlx4_en_cq *cq,
745 int budget);
746 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
747 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
748 int mlx4_en_process_tx_cq(struct net_device *dev,
749 struct mlx4_en_cq *cq, int napi_budget);
750 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
751 struct mlx4_en_tx_ring *ring,
752 int index, u64 timestamp,
753 int napi_mode);
754 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
755 struct mlx4_en_tx_ring *ring,
756 int index, u64 timestamp,
757 int napi_mode);
758 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
759 int is_tx, int rss, int qpn, int cqn, int user_prio,
760 struct mlx4_qp_context *context);
761 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
762 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
763 int loopback);
764 void mlx4_en_calc_rx_buf(struct net_device *dev);
765 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
766 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
767 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
768 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
769 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
770 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
771
772 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
773 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
774
775 void mlx4_en_fold_software_stats(struct net_device *dev);
776 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
777 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
778
779 #ifdef CONFIG_MLX4_EN_DCB
780 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
781 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
782 #endif
783
784 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
785 int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc);
786
787 #ifdef CONFIG_RFS_ACCEL
788 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
789 #endif
790
791 #define MLX4_EN_NUM_SELF_TEST 5
792 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
793 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
794
795 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
796 ((dev->features & feature) ^ (new_features & feature))
797
798 int mlx4_en_reset_config(struct net_device *dev,
799 struct hwtstamp_config ts_config,
800 netdev_features_t new_features);
801 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
802 struct mlx4_en_stats_bitmap *stats_bitmap,
803 u8 rx_ppp, u8 rx_pause,
804 u8 tx_ppp, u8 tx_pause);
805 int mlx4_en_netdev_event(struct notifier_block *this,
806 unsigned long event, void *ptr);
807
808 /*
809 * Functions for time stamping
810 */
811 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
812 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
813 struct skb_shared_hwtstamps *hwts,
814 u64 timestamp);
815 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
816 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
817
818 /* Globals
819 */
820 extern const struct ethtool_ops mlx4_en_ethtool_ops;
821
822
823
824 /*
825 * printk / logging functions
826 */
827
828 __printf(3, 4)
829 void en_print(const char *level, const struct mlx4_en_priv *priv,
830 const char *format, ...);
831
832 #define en_dbg(mlevel, priv, format, ...) \
833 do { \
834 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
835 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
836 } while (0)
837 #define en_warn(priv, format, ...) \
838 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
839 #define en_err(priv, format, ...) \
840 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
841 #define en_info(priv, format, ...) \
842 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
843
844 #define mlx4_err(mdev, format, ...) \
845 pr_err(DRV_NAME " %s: " format, \
846 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
847 #define mlx4_info(mdev, format, ...) \
848 pr_info(DRV_NAME " %s: " format, \
849 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
850 #define mlx4_warn(mdev, format, ...) \
851 pr_warn(DRV_NAME " %s: " format, \
852 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
853
854 #endif
855
