1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /*************************************************************************** 3 * 4 * Copyright (C) 2007-2010 SMSC 5 * 6 *****************************************************************************/ 7 8 #ifndef _SMSC75XX_H 9 #define _SMSC75XX_H 10 11 /* Tx command words */ 12 #define TX_CMD_A_LSO (0x08000000) 13 #define TX_CMD_A_IPE (0x04000000) 14 #define TX_CMD_A_TPE (0x02000000) 15 #define TX_CMD_A_IVTG (0x01000000) 16 #define TX_CMD_A_RVTG (0x00800000) 17 #define TX_CMD_A_FCS (0x00400000) 18 #define TX_CMD_A_LEN (0x000FFFFF) 19 20 #define TX_CMD_B_MSS (0x3FFF0000) 21 #define TX_CMD_B_MSS_SHIFT (16) 22 #define TX_MSS_MIN ((u16)8) 23 #define TX_CMD_B_VTAG (0x0000FFFF) 24 25 /* Rx command words */ 26 #define RX_CMD_A_ICE (0x80000000) 27 #define RX_CMD_A_TCE (0x40000000) 28 #define RX_CMD_A_IPV (0x20000000) 29 #define RX_CMD_A_PID (0x18000000) 30 #define RX_CMD_A_PID_NIP (0x00000000) 31 #define RX_CMD_A_PID_TCP (0x08000000) 32 #define RX_CMD_A_PID_UDP (0x10000000) 33 #define RX_CMD_A_PID_PP (0x18000000) 34 #define RX_CMD_A_PFF (0x04000000) 35 #define RX_CMD_A_BAM (0x02000000) 36 #define RX_CMD_A_MAM (0x01000000) 37 #define RX_CMD_A_FVTG (0x00800000) 38 #define RX_CMD_A_RED (0x00400000) 39 #define RX_CMD_A_RWT (0x00200000) 40 #define RX_CMD_A_RUNT (0x00100000) 41 #define RX_CMD_A_LONG (0x00080000) 42 #define RX_CMD_A_RXE (0x00040000) 43 #define RX_CMD_A_DRB (0x00020000) 44 #define RX_CMD_A_FCS (0x00010000) 45 #define RX_CMD_A_UAM (0x00008000) 46 #define RX_CMD_A_LCSM (0x00004000) 47 #define RX_CMD_A_LEN (0x00003FFF) 48 49 #define RX_CMD_B_CSUM (0xFFFF0000) 50 #define RX_CMD_B_CSUM_SHIFT (16) 51 #define RX_CMD_B_VTAG (0x0000FFFF) 52 53 /* SCSRs */ 54 #define ID_REV (0x0000) 55 56 #define FPGA_REV (0x0004) 57 58 #define BOND_CTL (0x0008) 59 60 #define INT_STS (0x000C) 61 #define INT_STS_RDFO_INT (0x00400000) 62 #define INT_STS_TXE_INT (0x00200000) 63 #define INT_STS_MACRTO_INT (0x00100000) 64 #define INT_STS_TX_DIS_INT (0x00080000) 65 #define INT_STS_RX_DIS_INT (0x00040000) 66 #define INT_STS_PHY_INT_ (0x00020000) 67 #define INT_STS_MAC_ERR_INT (0x00008000) 68 #define INT_STS_TDFU (0x00004000) 69 #define INT_STS_TDFO (0x00002000) 70 #define INT_STS_GPIOS (0x00000FFF) 71 #define INT_STS_CLEAR_ALL (0xFFFFFFFF) 72 73 #define HW_CFG (0x0010) 74 #define HW_CFG_SMDET_STS (0x00008000) 75 #define HW_CFG_SMDET_EN (0x00004000) 76 #define HW_CFG_EEM (0x00002000) 77 #define HW_CFG_RST_PROTECT (0x00001000) 78 #define HW_CFG_PORT_SWAP (0x00000800) 79 #define HW_CFG_PHY_BOOST (0x00000600) 80 #define HW_CFG_PHY_BOOST_NORMAL (0x00000000) 81 #define HW_CFG_PHY_BOOST_4 (0x00002000) 82 #define HW_CFG_PHY_BOOST_8 (0x00004000) 83 #define HW_CFG_PHY_BOOST_12 (0x00006000) 84 #define HW_CFG_LEDB (0x00000100) 85 #define HW_CFG_BIR (0x00000080) 86 #define HW_CFG_SBP (0x00000040) 87 #define HW_CFG_IME (0x00000020) 88 #define HW_CFG_MEF (0x00000010) 89 #define HW_CFG_ETC (0x00000008) 90 #define HW_CFG_BCE (0x00000004) 91 #define HW_CFG_LRST (0x00000002) 92 #define HW_CFG_SRST (0x00000001) 93 94 #define PMT_CTL (0x0014) 95 #define PMT_CTL_PHY_PWRUP (0x00000400) 96 #define PMT_CTL_RES_CLR_WKP_EN (0x00000100) 97 #define PMT_CTL_DEV_RDY (0x00000080) 98 #define PMT_CTL_SUS_MODE (0x00000060) 99 #define PMT_CTL_SUS_MODE_0 (0x00000000) 100 #define PMT_CTL_SUS_MODE_1 (0x00000020) 101 #define PMT_CTL_SUS_MODE_2 (0x00000040) 102 #define PMT_CTL_SUS_MODE_3 (0x00000060) 103 #define PMT_CTL_PHY_RST (0x00000010) 104 #define PMT_CTL_WOL_EN (0x00000008) 105 #define PMT_CTL_ED_EN (0x00000004) 106 #define PMT_CTL_WUPS (0x00000003) 107 #define PMT_CTL_WUPS_NO (0x00000000) 108 #define PMT_CTL_WUPS_ED (0x00000001) 109 #define PMT_CTL_WUPS_WOL (0x00000002) 110 #define PMT_CTL_WUPS_MULTI (0x00000003) 111 112 #define LED_GPIO_CFG (0x0018) 113 #define LED_GPIO_CFG_LED2_FUN_SEL (0x80000000) 114 #define LED_GPIO_CFG_LED10_FUN_SEL (0x40000000) 115 #define LED_GPIO_CFG_LEDGPIO_EN (0x0000F000) 116 #define LED_GPIO_CFG_LEDGPIO_EN_0 (0x00001000) 117 #define LED_GPIO_CFG_LEDGPIO_EN_1 (0x00002000) 118 #define LED_GPIO_CFG_LEDGPIO_EN_2 (0x00004000) 119 #define LED_GPIO_CFG_LEDGPIO_EN_3 (0x00008000) 120 #define LED_GPIO_CFG_GPBUF (0x00000F00) 121 #define LED_GPIO_CFG_GPBUF_0 (0x00000100) 122 #define LED_GPIO_CFG_GPBUF_1 (0x00000200) 123 #define LED_GPIO_CFG_GPBUF_2 (0x00000400) 124 #define LED_GPIO_CFG_GPBUF_3 (0x00000800) 125 #define LED_GPIO_CFG_GPDIR (0x000000F0) 126 #define LED_GPIO_CFG_GPDIR_0 (0x00000010) 127 #define LED_GPIO_CFG_GPDIR_1 (0x00000020) 128 #define LED_GPIO_CFG_GPDIR_2 (0x00000040) 129 #define LED_GPIO_CFG_GPDIR_3 (0x00000080) 130 #define LED_GPIO_CFG_GPDATA (0x0000000F) 131 #define LED_GPIO_CFG_GPDATA_0 (0x00000001) 132 #define LED_GPIO_CFG_GPDATA_1 (0x00000002) 133 #define LED_GPIO_CFG_GPDATA_2 (0x00000004) 134 #define LED_GPIO_CFG_GPDATA_3 (0x00000008) 135 136 #define GPIO_CFG (0x001C) 137 #define GPIO_CFG_SHIFT (24) 138 #define GPIO_CFG_GPEN (0xFF000000) 139 #define GPIO_CFG_GPBUF (0x00FF0000) 140 #define GPIO_CFG_GPDIR (0x0000FF00) 141 #define GPIO_CFG_GPDATA (0x000000FF) 142 143 #define GPIO_WAKE (0x0020) 144 #define GPIO_WAKE_PHY_LINKUP_EN (0x80000000) 145 #define GPIO_WAKE_POL (0x0FFF0000) 146 #define GPIO_WAKE_POL_SHIFT (16) 147 #define GPIO_WAKE_WK (0x00000FFF) 148 149 #define DP_SEL (0x0024) 150 #define DP_SEL_DPRDY (0x80000000) 151 #define DP_SEL_RSEL (0x0000000F) 152 #define DP_SEL_URX (0x00000000) 153 #define DP_SEL_VHF (0x00000001) 154 #define DP_SEL_VHF_HASH_LEN (16) 155 #define DP_SEL_VHF_VLAN_LEN (128) 156 #define DP_SEL_LSO_HEAD (0x00000002) 157 #define DP_SEL_FCT_RX (0x00000003) 158 #define DP_SEL_FCT_TX (0x00000004) 159 #define DP_SEL_DESCRIPTOR (0x00000005) 160 #define DP_SEL_WOL (0x00000006) 161 162 #define DP_CMD (0x0028) 163 #define DP_CMD_WRITE (0x01) 164 #define DP_CMD_READ (0x00) 165 166 #define DP_ADDR (0x002C) 167 168 #define DP_DATA (0x0030) 169 170 #define BURST_CAP (0x0034) 171 #define BURST_CAP_MASK (0x0000000F) 172 173 #define INT_EP_CTL (0x0038) 174 #define INT_EP_CTL_INTEP_ON (0x80000000) 175 #define INT_EP_CTL_RDFO_EN (0x00400000) 176 #define INT_EP_CTL_TXE_EN (0x00200000) 177 #define INT_EP_CTL_MACROTO_EN (0x00100000) 178 #define INT_EP_CTL_TX_DIS_EN (0x00080000) 179 #define INT_EP_CTL_RX_DIS_EN (0x00040000) 180 #define INT_EP_CTL_PHY_EN_ (0x00020000) 181 #define INT_EP_CTL_MAC_ERR_EN (0x00008000) 182 #define INT_EP_CTL_TDFU_EN (0x00004000) 183 #define INT_EP_CTL_TDFO_EN (0x00002000) 184 #define INT_EP_CTL_RX_FIFO_EN (0x00001000) 185 #define INT_EP_CTL_GPIOX_EN (0x00000FFF) 186 187 #define BULK_IN_DLY (0x003C) 188 #define BULK_IN_DLY_MASK (0xFFFF) 189 190 #define E2P_CMD (0x0040) 191 #define E2P_CMD_BUSY (0x80000000) 192 #define E2P_CMD_MASK (0x70000000) 193 #define E2P_CMD_READ (0x00000000) 194 #define E2P_CMD_EWDS (0x10000000) 195 #define E2P_CMD_EWEN (0x20000000) 196 #define E2P_CMD_WRITE (0x30000000) 197 #define E2P_CMD_WRAL (0x40000000) 198 #define E2P_CMD_ERASE (0x50000000) 199 #define E2P_CMD_ERAL (0x60000000) 200 #define E2P_CMD_RELOAD (0x70000000) 201 #define E2P_CMD_TIMEOUT (0x00000400) 202 #define E2P_CMD_LOADED (0x00000200) 203 #define E2P_CMD_ADDR (0x000001FF) 204 205 #define MAX_EEPROM_SIZE (512) 206 207 #define E2P_DATA (0x0044) 208 #define E2P_DATA_MASK_ (0x000000FF) 209 210 #define RFE_CTL (0x0060) 211 #define RFE_CTL_TCPUDP_CKM (0x00001000) 212 #define RFE_CTL_IP_CKM (0x00000800) 213 #define RFE_CTL_AB (0x00000400) 214 #define RFE_CTL_AM (0x00000200) 215 #define RFE_CTL_AU (0x00000100) 216 #define RFE_CTL_VS (0x00000080) 217 #define RFE_CTL_UF (0x00000040) 218 #define RFE_CTL_VF (0x00000020) 219 #define RFE_CTL_SPF (0x00000010) 220 #define RFE_CTL_MHF (0x00000008) 221 #define RFE_CTL_DHF (0x00000004) 222 #define RFE_CTL_DPF (0x00000002) 223 #define RFE_CTL_RST_RF (0x00000001) 224 225 #define VLAN_TYPE (0x0064) 226 #define VLAN_TYPE_MASK (0x0000FFFF) 227 228 #define FCT_RX_CTL (0x0090) 229 #define FCT_RX_CTL_EN (0x80000000) 230 #define FCT_RX_CTL_RST (0x40000000) 231 #define FCT_RX_CTL_SBF (0x02000000) 232 #define FCT_RX_CTL_OVERFLOW (0x01000000) 233 #define FCT_RX_CTL_FRM_DROP (0x00800000) 234 #define FCT_RX_CTL_RX_NOT_EMPTY (0x00400000) 235 #define FCT_RX_CTL_RX_EMPTY (0x00200000) 236 #define FCT_RX_CTL_RX_DISABLED (0x00100000) 237 #define FCT_RX_CTL_RXUSED (0x0000FFFF) 238 239 #define FCT_TX_CTL (0x0094) 240 #define FCT_TX_CTL_EN (0x80000000) 241 #define FCT_TX_CTL_RST (0x40000000) 242 #define FCT_TX_CTL_TX_NOT_EMPTY (0x00400000) 243 #define FCT_TX_CTL_TX_EMPTY (0x00200000) 244 #define FCT_TX_CTL_TX_DISABLED (0x00100000) 245 #define FCT_TX_CTL_TXUSED (0x0000FFFF) 246 247 #define FCT_RX_FIFO_END (0x0098) 248 #define FCT_RX_FIFO_END_MASK (0x0000007F) 249 250 #define FCT_TX_FIFO_END (0x009C) 251 #define FCT_TX_FIFO_END_MASK (0x0000003F) 252 253 #define FCT_FLOW (0x00A0) 254 #define FCT_FLOW_THRESHOLD_OFF (0x00007F00) 255 #define FCT_FLOW_THRESHOLD_OFF_SHIFT (8) 256 #define FCT_FLOW_THRESHOLD_ON (0x0000007F) 257 258 /* MAC CSRs */ 259 #define MAC_CR (0x100) 260 #define MAC_CR_ADP (0x00002000) 261 #define MAC_CR_ADD (0x00001000) 262 #define MAC_CR_ASD (0x00000800) 263 #define MAC_CR_INT_LOOP (0x00000400) 264 #define MAC_CR_BOLMT (0x000000C0) 265 #define MAC_CR_FDPX (0x00000008) 266 #define MAC_CR_CFG (0x00000006) 267 #define MAC_CR_CFG_10 (0x00000000) 268 #define MAC_CR_CFG_100 (0x00000002) 269 #define MAC_CR_CFG_1000 (0x00000004) 270 #define MAC_CR_RST (0x00000001) 271 272 #define MAC_RX (0x104) 273 #define MAC_RX_MAX_SIZE (0x3FFF0000) 274 #define MAC_RX_MAX_SIZE_SHIFT (16) 275 #define MAC_RX_FCS_STRIP (0x00000010) 276 #define MAC_RX_FSE (0x00000004) 277 #define MAC_RX_RXD (0x00000002) 278 #define MAC_RX_RXEN (0x00000001) 279 280 #define MAC_TX (0x108) 281 #define MAC_TX_BFCS (0x00000004) 282 #define MAC_TX_TXD (0x00000002) 283 #define MAC_TX_TXEN (0x00000001) 284 285 #define FLOW (0x10C) 286 #define FLOW_FORCE_FC (0x80000000) 287 #define FLOW_TX_FCEN (0x40000000) 288 #define FLOW_RX_FCEN (0x20000000) 289 #define FLOW_FPF (0x10000000) 290 #define FLOW_PAUSE_TIME (0x0000FFFF) 291 292 #define RAND_SEED (0x110) 293 #define RAND_SEED_MASK (0x0000FFFF) 294 295 #define ERR_STS (0x114) 296 #define ERR_STS_FCS_ERR (0x00000100) 297 #define ERR_STS_LFRM_ERR (0x00000080) 298 #define ERR_STS_RUNT_ERR (0x00000040) 299 #define ERR_STS_COLLISION_ERR (0x00000010) 300 #define ERR_STS_ALIGN_ERR (0x00000008) 301 #define ERR_STS_URUN_ERR (0x00000004) 302 303 #define RX_ADDRH (0x118) 304 #define RX_ADDRH_MASK (0x0000FFFF) 305 306 #define RX_ADDRL (0x11C) 307 308 #define MII_ACCESS (0x120) 309 #define MII_ACCESS_PHY_ADDR (0x0000F800) 310 #define MII_ACCESS_PHY_ADDR_SHIFT (11) 311 #define MII_ACCESS_REG_ADDR (0x000007C0) 312 #define MII_ACCESS_REG_ADDR_SHIFT (6) 313 #define MII_ACCESS_READ (0x00000000) 314 #define MII_ACCESS_WRITE (0x00000002) 315 #define MII_ACCESS_BUSY (0x00000001) 316 317 #define MII_DATA (0x124) 318 #define MII_DATA_MASK (0x0000FFFF) 319 320 #define WUCSR (0x140) 321 #define WUCSR_PFDA_FR (0x00000080) 322 #define WUCSR_WUFR (0x00000040) 323 #define WUCSR_MPR (0x00000020) 324 #define WUCSR_BCAST_FR (0x00000010) 325 #define WUCSR_PFDA_EN (0x00000008) 326 #define WUCSR_WUEN (0x00000004) 327 #define WUCSR_MPEN (0x00000002) 328 #define WUCSR_BCST_EN (0x00000001) 329 330 #define WUF_CFGX (0x144) 331 #define WUF_CFGX_EN (0x80000000) 332 #define WUF_CFGX_ATYPE (0x03000000) 333 #define WUF_CFGX_ATYPE_UNICAST (0x00000000) 334 #define WUF_CFGX_ATYPE_MULTICAST (0x02000000) 335 #define WUF_CFGX_ATYPE_ALL (0x03000000) 336 #define WUF_CFGX_PATTERN_OFFSET (0x007F0000) 337 #define WUF_CFGX_PATTERN_OFFSET_SHIFT (16) 338 #define WUF_CFGX_CRC16 (0x0000FFFF) 339 #define WUF_NUM (8) 340 341 #define WUF_MASKX (0x170) 342 #define WUF_MASKX_AVALID (0x80000000) 343 #define WUF_MASKX_ATYPE (0x40000000) 344 345 #define ADDR_FILTX (0x300) 346 #define ADDR_FILTX_FB_VALID (0x80000000) 347 #define ADDR_FILTX_FB_TYPE (0x40000000) 348 #define ADDR_FILTX_FB_ADDRHI (0x0000FFFF) 349 #define ADDR_FILTX_SB_ADDRLO (0xFFFFFFFF) 350 351 #define WUCSR2 (0x500) 352 #define WUCSR2_NS_RCD (0x00000040) 353 #define WUCSR2_ARP_RCD (0x00000020) 354 #define WUCSR2_TCPSYN_RCD (0x00000010) 355 #define WUCSR2_NS_OFFLOAD (0x00000004) 356 #define WUCSR2_ARP_OFFLOAD (0x00000002) 357 #define WUCSR2_TCPSYN_OFFLOAD (0x00000001) 358 359 #define WOL_FIFO_STS (0x504) 360 361 #define IPV6_ADDRX (0x510) 362 363 #define IPV4_ADDRX (0x590) 364 365 366 /* Vendor-specific PHY Definitions */ 367 368 /* Mode Control/Status Register */ 369 #define PHY_MODE_CTRL_STS (17) 370 #define MODE_CTRL_STS_EDPWRDOWN ((u16)0x2000) 371 #define MODE_CTRL_STS_ENERGYON ((u16)0x0002) 372 373 #define PHY_INT_SRC (29) 374 #define PHY_INT_SRC_ENERGY_ON ((u16)0x0080) 375 #define PHY_INT_SRC_ANEG_COMP ((u16)0x0040) 376 #define PHY_INT_SRC_REMOTE_FAULT ((u16)0x0020) 377 #define PHY_INT_SRC_LINK_DOWN ((u16)0x0010) 378 #define PHY_INT_SRC_CLEAR_ALL ((u16)0xffff) 379 380 #define PHY_INT_MASK (30) 381 #define PHY_INT_MASK_ENERGY_ON ((u16)0x0080) 382 #define PHY_INT_MASK_ANEG_COMP ((u16)0x0040) 383 #define PHY_INT_MASK_REMOTE_FAULT ((u16)0x0020) 384 #define PHY_INT_MASK_LINK_DOWN ((u16)0x0010) 385 #define PHY_INT_MASK_DEFAULT (PHY_INT_MASK_ANEG_COMP | \ 386 PHY_INT_MASK_LINK_DOWN) 387 388 #define PHY_SPECIAL (31) 389 #define PHY_SPECIAL_SPD ((u16)0x001C) 390 #define PHY_SPECIAL_SPD_10HALF ((u16)0x0004) 391 #define PHY_SPECIAL_SPD_10FULL ((u16)0x0014) 392 #define PHY_SPECIAL_SPD_100HALF ((u16)0x0008) 393 #define PHY_SPECIAL_SPD_100FULL ((u16)0x0018) 394 395 /* USB Vendor Requests */ 396 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0 397 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1 398 #define USB_VENDOR_REQUEST_GET_STATS 0xA2 399 400 /* Interrupt Endpoint status word bitfields */ 401 #define INT_ENP_RDFO_INT ((u32)BIT(22)) 402 #define INT_ENP_TXE_INT ((u32)BIT(21)) 403 #define INT_ENP_TX_DIS_INT ((u32)BIT(19)) 404 #define INT_ENP_RX_DIS_INT ((u32)BIT(18)) 405 #define INT_ENP_PHY_INT ((u32)BIT(17)) 406 #define INT_ENP_MAC_ERR_INT ((u32)BIT(15)) 407 #define INT_ENP_RX_FIFO_DATA_INT ((u32)BIT(12)) 408 409 #endif /* _SMSC75XX_H */ 410
