1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7 #ifndef REG_ADDR_H 8 #define REG_ADDR_H 9 10 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \ 11 0 12 13 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \ 14 0xfff << 0) 15 16 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \ 17 12 18 19 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \ 20 0xfff << 12) 21 22 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \ 23 24 24 25 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \ 26 0xff << 24) 27 28 #define CDU_REG_SEGMENT0_PARAMS \ 29 0x580904UL 30 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \ 31 (0xfff << 0) 32 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \ 33 0 34 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \ 35 (0xff << 16) 36 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \ 37 16 38 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \ 39 (0xff << 24) 40 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \ 41 24 42 #define CDU_REG_SEGMENT1_PARAMS \ 43 0x580908UL 44 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \ 45 (0xfff << 0) 46 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \ 47 0 48 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \ 49 (0xff << 16) 50 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \ 51 16 52 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \ 53 (0xff << 24) 54 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \ 55 24 56 57 #define XSDM_REG_OPERATION_GEN \ 58 0xf80408UL 59 #define NIG_REG_RX_BRB_OUT_EN \ 60 0x500e18UL 61 #define NIG_REG_STORM_OUT_EN \ 62 0x500e08UL 63 #define PSWRQ2_REG_L2P_VALIDATE_VFID \ 64 0x240c50UL 65 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \ 66 0x2aae04UL 67 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \ 68 0x2aa16cUL 69 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \ 70 0x2aa118UL 71 #define PSWHST_REG_ZONE_PERMISSION_TABLE \ 72 0x2a0800UL 73 #define BAR0_MAP_REG_MSDM_RAM \ 74 0x1d00000UL 75 #define BAR0_MAP_REG_USDM_RAM \ 76 0x1d80000UL 77 #define BAR0_MAP_REG_PSDM_RAM \ 78 0x1f00000UL 79 #define BAR0_MAP_REG_TSDM_RAM \ 80 0x1c80000UL 81 #define BAR0_MAP_REG_XSDM_RAM \ 82 0x1e00000UL 83 #define BAR0_MAP_REG_YSDM_RAM \ 84 0x1e80000UL 85 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \ 86 0x5011f4UL 87 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE \ 88 0x1f0164UL 89 #define PRS_REG_SEARCH_TCP \ 90 0x1f0400UL 91 #define PRS_REG_SEARCH_UDP \ 92 0x1f0404UL 93 #define PRS_REG_SEARCH_FCOE \ 94 0x1f0408UL 95 #define PRS_REG_SEARCH_ROCE \ 96 0x1f040cUL 97 #define PRS_REG_SEARCH_OPENFLOW \ 98 0x1f0434UL 99 #define PRS_REG_SEARCH_TAG1 \ 100 0x1f0444UL 101 #define PRS_REG_SEARCH_TENANT_ID \ 102 0x1f044cUL 103 #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \ 104 0x1f0a0cUL 105 #define PRS_REG_SEARCH_TCP_FIRST_FRAG \ 106 0x1f0410UL 107 #define TM_REG_PF_ENABLE_CONN \ 108 0x2c043cUL 109 #define TM_REG_PF_ENABLE_TASK \ 110 0x2c0444UL 111 #define TM_REG_PF_SCAN_ACTIVE_CONN \ 112 0x2c04fcUL 113 #define TM_REG_PF_SCAN_ACTIVE_TASK \ 114 0x2c0500UL 115 #define IGU_REG_LEADING_EDGE_LATCH \ 116 0x18082cUL 117 #define IGU_REG_TRAILING_EDGE_LATCH \ 118 0x180830UL 119 #define QM_REG_USG_CNT_PF_TX \ 120 0x2f2eacUL 121 #define QM_REG_USG_CNT_PF_OTHER \ 122 0x2f2eb0UL 123 #define DORQ_REG_PF_DB_ENABLE \ 124 0x100508UL 125 #define DORQ_REG_VF_USAGE_CNT \ 126 0x1009c4UL 127 #define QM_REG_PF_EN \ 128 0x2f2ea4UL 129 #define TCFC_REG_WEAK_ENABLE_VF \ 130 0x2d0704UL 131 #define TCFC_REG_STRONG_ENABLE_PF \ 132 0x2d0708UL 133 #define TCFC_REG_STRONG_ENABLE_VF \ 134 0x2d070cUL 135 #define CCFC_REG_WEAK_ENABLE_VF \ 136 0x2e0704UL 137 #define CCFC_REG_STRONG_ENABLE_PF \ 138 0x2e0708UL 139 #define PGLUE_B_REG_PGL_ADDR_88_F0_BB \ 140 0x2aa404UL 141 #define PGLUE_B_REG_PGL_ADDR_8C_F0_BB \ 142 0x2aa408UL 143 #define PGLUE_B_REG_PGL_ADDR_90_F0_BB \ 144 0x2aa40cUL 145 #define PGLUE_B_REG_PGL_ADDR_94_F0_BB \ 146 0x2aa410UL 147 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \ 148 0x2aa138UL 149 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \ 150 0x2aa174UL 151 #define MISC_REG_GEN_PURP_CR0 \ 152 0x008c80UL 153 #define MCP_REG_SCRATCH \ 154 0xe20000UL 155 #define MCP_REG_SCRATCH_SIZE \ 156 57344 157 #define CNIG_REG_NW_PORT_MODE_BB \ 158 0x218200UL 159 #define MISCS_REG_CHIP_NUM \ 160 0x00976cUL 161 #define MISCS_REG_CHIP_REV \ 162 0x009770UL 163 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \ 164 0x00971cUL 165 #define MISCS_REG_CHIP_TEST_REG \ 166 0x009778UL 167 #define MISCS_REG_CHIP_METAL \ 168 0x009774UL 169 #define MISCS_REG_FUNCTION_HIDE \ 170 0x0096f0UL 171 #define BRB_REG_HEADER_SIZE \ 172 0x340804UL 173 #define BTB_REG_HEADER_SIZE \ 174 0xdb0804UL 175 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \ 176 0x1c0708UL 177 #define CCFC_REG_ACTIVITY_COUNTER \ 178 0x2e8800UL 179 #define CCFC_REG_STRONG_ENABLE_VF \ 180 0x2e070cUL 181 #define CDU_REG_CCFC_CTX_VALID0 \ 182 0x580400UL 183 #define CDU_REG_CCFC_CTX_VALID1 \ 184 0x580404UL 185 #define CDU_REG_TCFC_CTX_VALID0 \ 186 0x580408UL 187 #define CDU_REG_CID_ADDR_PARAMS \ 188 0x580900UL 189 #define DBG_REG_CLIENT_ENABLE \ 190 0x010004UL 191 #define DBG_REG_TIMESTAMP_VALID_EN \ 192 0x010b58UL 193 #define DMAE_REG_INIT \ 194 0x00c000UL 195 #define DORQ_REG_IFEN \ 196 0x100040UL 197 #define DORQ_REG_TAG1_OVRD_MODE \ 198 0x1008b4UL 199 #define DORQ_REG_PF_PCP_BB_K2 \ 200 0x1008c4UL 201 #define DORQ_REG_PF_EXT_VID_BB_K2 \ 202 0x1008c8UL 203 #define DORQ_REG_DB_DROP_REASON \ 204 0x100a2cUL 205 #define DORQ_REG_DB_DROP_DETAILS \ 206 0x100a24UL 207 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \ 208 0x100a1cUL 209 #define GRC_REG_TIMEOUT_EN \ 210 0x050404UL 211 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \ 212 0x050054UL 213 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \ 214 0x05004cUL 215 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \ 216 0x050050UL 217 #define IGU_REG_BLOCK_CONFIGURATION \ 218 0x180040UL 219 #define MCM_REG_INIT \ 220 0x1200000UL 221 #define MCP2_REG_DBG_DWORD_ENABLE \ 222 0x052404UL 223 #define MISC_REG_PORT_MODE \ 224 0x008c00UL 225 #define MISCS_REG_CLK_100G_MODE \ 226 0x009070UL 227 #define MSDM_REG_ENABLE_IN1 \ 228 0xfc0004UL 229 #define MSEM_REG_ENABLE_IN \ 230 0x1800004UL 231 #define NIG_REG_CM_HDR \ 232 0x500840UL 233 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \ 234 0x50196cUL 235 #define NIG_REG_LLH_PPFID2PFID_TBL_0 \ 236 0x501970UL 237 #define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL \ 238 0x50 239 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \ 240 0x501964UL 241 #define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL 242 #define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL 243 #define NIG_REG_LLH_FUNC_FILTER_VALUE \ 244 0x501a00UL 245 #define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \ 246 32 247 #define NIG_REG_LLH_FUNC_FILTER_EN \ 248 0x501a80UL 249 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \ 250 16 251 #define NIG_REG_LLH_FUNC_FILTER_MODE \ 252 0x501ac0UL 253 #define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \ 254 16 255 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \ 256 0x501b00UL 257 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \ 258 16 259 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \ 260 0x501b40UL 261 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \ 262 16 263 #define NCSI_REG_CONFIG \ 264 0x040200UL 265 #define PBF_REG_INIT \ 266 0xd80000UL 267 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \ 268 0xd806c8UL 269 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \ 270 0xd806ccUL 271 #define PTU_REG_ATC_INIT_ARRAY \ 272 0x560000UL 273 #define PCM_REG_INIT \ 274 0x1100000UL 275 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \ 276 0x2a9000UL 277 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \ 278 0x2aa150UL 279 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \ 280 0x2aa144UL 281 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \ 282 0x2aa148UL 283 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \ 284 0x2aa14cUL 285 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \ 286 0x2aa154UL 287 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \ 288 0x2aa158UL 289 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \ 290 0x2aa15cUL 291 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \ 292 0x2aa160UL 293 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \ 294 0x2aa164UL 295 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \ 296 0x2aa54cUL 297 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \ 298 0x2aa544UL 299 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \ 300 0x2aa548UL 301 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \ 302 0x2aae74UL 303 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \ 304 0x2aae78UL 305 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \ 306 0x2aae7cUL 307 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \ 308 0x2aae80UL 309 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \ 310 0x2aa3bcUL 311 #define PRM_REG_DISABLE_PRM \ 312 0x230000UL 313 #define PRS_REG_SOFT_RST \ 314 0x1f0000UL 315 #define PRS_REG_MSG_INFO \ 316 0x1f0a1cUL 317 #define PRS_REG_ROCE_DEST_QP_MAX_PF \ 318 0x1f0430UL 319 #define PRS_REG_USE_LIGHT_L2 \ 320 0x1f096cUL 321 #define PSDM_REG_ENABLE_IN1 \ 322 0xfa0004UL 323 #define PSEM_REG_ENABLE_IN \ 324 0x1600004UL 325 #define PSWRQ_REG_DBG_SELECT \ 326 0x280020UL 327 #define PSWRQ2_REG_CDUT_P_SIZE \ 328 0x24000cUL 329 #define PSWRQ2_REG_ILT_MEMORY \ 330 0x260000UL 331 #define PSWRQ2_REG_ILT_MEMORY_SIZE_BB \ 332 15200 333 #define PSWRQ2_REG_ILT_MEMORY_SIZE_K2 \ 334 22000 335 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \ 336 0x2a0040UL 337 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \ 338 0x29e050UL 339 #define PSWHST_REG_INCORRECT_ACCESS_VALID \ 340 0x2a0070UL 341 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \ 342 0x2a0074UL 343 #define PSWHST_REG_INCORRECT_ACCESS_DATA \ 344 0x2a0068UL 345 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \ 346 0x2a006cUL 347 #define PSWRD_REG_DBG_SELECT \ 348 0x29c040UL 349 #define PSWRD2_REG_CONF11 \ 350 0x29d064UL 351 #define PSWWR_REG_USDM_FULL_TH \ 352 0x29a040UL 353 #define PSWWR2_REG_CDU_FULL_TH2 \ 354 0x29b040UL 355 #define QM_REG_MAXPQSIZE_0 \ 356 0x2f0434UL 357 #define RSS_REG_RSS_INIT_EN \ 358 0x238804UL 359 #define RDIF_REG_STOP_ON_ERROR \ 360 0x300040UL 361 #define RDIF_REG_DEBUG_ERROR_INFO \ 362 0x300400UL 363 #define RDIF_REG_DEBUG_ERROR_INFO_SIZE \ 364 64 365 #define SRC_REG_SOFT_RST \ 366 0x23874cUL 367 #define TCFC_REG_ACTIVITY_COUNTER \ 368 0x2d8800UL 369 #define TCM_REG_INIT \ 370 0x1180000UL 371 #define TM_REG_PXP_READ_DATA_FIFO_INIT \ 372 0x2c0014UL 373 #define TSDM_REG_ENABLE_IN1 \ 374 0xfb0004UL 375 #define TSEM_REG_ENABLE_IN \ 376 0x1700004UL 377 #define TDIF_REG_STOP_ON_ERROR \ 378 0x310040UL 379 #define TDIF_REG_DEBUG_ERROR_INFO \ 380 0x310400UL 381 #define TDIF_REG_DEBUG_ERROR_INFO_SIZE \ 382 64 383 #define UCM_REG_INIT \ 384 0x1280000UL 385 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \ 386 0x051004UL 387 #define USDM_REG_ENABLE_IN1 \ 388 0xfd0004UL 389 #define USEM_REG_ENABLE_IN \ 390 0x1900004UL 391 #define XCM_REG_INIT \ 392 0x1000000UL 393 #define XSDM_REG_ENABLE_IN1 \ 394 0xf80004UL 395 #define XSEM_REG_ENABLE_IN \ 396 0x1400004UL 397 #define YCM_REG_INIT \ 398 0x1080000UL 399 #define YSDM_REG_ENABLE_IN1 \ 400 0xf90004UL 401 #define YSEM_REG_ENABLE_IN \ 402 0x1500004UL 403 #define XYLD_REG_SCBD_STRICT_PRIO \ 404 0x4c0000UL 405 #define TMLD_REG_SCBD_STRICT_PRIO \ 406 0x4d0000UL 407 #define MULD_REG_SCBD_STRICT_PRIO \ 408 0x4e0000UL 409 #define YULD_REG_SCBD_STRICT_PRIO \ 410 0x4c8000UL 411 #define MISC_REG_SHARED_MEM_ADDR \ 412 0x008c20UL 413 #define DMAE_REG_GO_C0 \ 414 0x00c048UL 415 #define DMAE_REG_GO_C1 \ 416 0x00c04cUL 417 #define DMAE_REG_GO_C2 \ 418 0x00c050UL 419 #define DMAE_REG_GO_C3 \ 420 0x00c054UL 421 #define DMAE_REG_GO_C4 \ 422 0x00c058UL 423 #define DMAE_REG_GO_C5 \ 424 0x00c05cUL 425 #define DMAE_REG_GO_C6 \ 426 0x00c060UL 427 #define DMAE_REG_GO_C7 \ 428 0x00c064UL 429 #define DMAE_REG_GO_C8 \ 430 0x00c068UL 431 #define DMAE_REG_GO_C9 \ 432 0x00c06cUL 433 #define DMAE_REG_GO_C10 \ 434 0x00c070UL 435 #define DMAE_REG_GO_C11 \ 436 0x00c074UL 437 #define DMAE_REG_GO_C12 \ 438 0x00c078UL 439 #define DMAE_REG_GO_C13 \ 440 0x00c07cUL 441 #define DMAE_REG_GO_C14 \ 442 0x00c080UL 443 #define DMAE_REG_GO_C15 \ 444 0x00c084UL 445 #define DMAE_REG_GO_C16 \ 446 0x00c088UL 447 #define DMAE_REG_GO_C17 \ 448 0x00c08cUL 449 #define DMAE_REG_GO_C18 \ 450 0x00c090UL 451 #define DMAE_REG_GO_C19 \ 452 0x00c094UL 453 #define DMAE_REG_GO_C20 \ 454 0x00c098UL 455 #define DMAE_REG_GO_C21 \ 456 0x00c09cUL 457 #define DMAE_REG_GO_C22 \ 458 0x00c0a0UL 459 #define DMAE_REG_GO_C23 \ 460 0x00c0a4UL 461 #define DMAE_REG_GO_C24 \ 462 0x00c0a8UL 463 #define DMAE_REG_GO_C25 \ 464 0x00c0acUL 465 #define DMAE_REG_GO_C26 \ 466 0x00c0b0UL 467 #define DMAE_REG_GO_C27 \ 468 0x00c0b4UL 469 #define DMAE_REG_GO_C28 \ 470 0x00c0b8UL 471 #define DMAE_REG_GO_C29 \ 472 0x00c0bcUL 473 #define DMAE_REG_GO_C30 \ 474 0x00c0c0UL 475 #define DMAE_REG_GO_C31 \ 476 0x00c0c4UL 477 #define DMAE_REG_CMD_MEM \ 478 0x00c800UL 479 #define QM_REG_MAXPQSIZETXSEL_0 \ 480 0x2f0440UL 481 #define QM_REG_SDMCMDREADY \ 482 0x2f1e10UL 483 #define QM_REG_SDMCMDADDR \ 484 0x2f1e04UL 485 #define QM_REG_SDMCMDDATALSB \ 486 0x2f1e08UL 487 #define QM_REG_SDMCMDDATAMSB \ 488 0x2f1e0cUL 489 #define QM_REG_SDMCMDGO \ 490 0x2f1e14UL 491 #define QM_REG_RLPFCRD \ 492 0x2f4d80UL 493 #define QM_REG_RLPFINCVAL \ 494 0x2f4c80UL 495 #define QM_REG_RLGLBLCRD \ 496 0x2f4400UL 497 #define QM_REG_RLGLBLINCVAL \ 498 0x2f3400UL 499 #define IGU_REG_ATTENTION_ENABLE \ 500 0x18083cUL 501 #define IGU_REG_ATTN_MSG_ADDR_L \ 502 0x180820UL 503 #define IGU_REG_ATTN_MSG_ADDR_H \ 504 0x180824UL 505 #define MISC_REG_AEU_GENERAL_ATTN_0 \ 506 0x008400UL 507 #define MISC_REG_AEU_GENERAL_ATTN_32 \ 508 0x008480UL 509 #define MISC_REG_AEU_GENERAL_ATTN_35 \ 510 0x00848cUL 511 #define CAU_REG_SB_ADDR_MEMORY \ 512 0x1c8000UL 513 #define CAU_REG_SB_VAR_MEMORY \ 514 0x1c6000UL 515 #define CAU_REG_PI_MEMORY \ 516 0x1d0000UL 517 #define IGU_REG_PF_CONFIGURATION \ 518 0x180800UL 519 #define IGU_REG_VF_CONFIGURATION \ 520 0x180804UL 521 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \ 522 0x00849cUL 523 #define MISC_REG_AEU_ENABLE4_IGU_OUT_0 \ 524 0x0084a8UL 525 #define MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32 \ 526 (0x1UL << 0) 527 #define MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32_SHIFT \ 528 0 529 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \ 530 0x0087b4UL 531 #define MISC_REG_AEU_MASK_ATTN_IGU \ 532 0x008494UL 533 #define IGU_REG_CLEANUP_STATUS_0 \ 534 0x180980UL 535 #define IGU_REG_CLEANUP_STATUS_1 \ 536 0x180a00UL 537 #define IGU_REG_CLEANUP_STATUS_2 \ 538 0x180a80UL 539 #define IGU_REG_CLEANUP_STATUS_3 \ 540 0x180b00UL 541 #define IGU_REG_CLEANUP_STATUS_4 \ 542 0x180b80UL 543 #define IGU_REG_COMMAND_REG_32LSB_DATA \ 544 0x180840UL 545 #define IGU_REG_COMMAND_REG_CTRL \ 546 0x180848UL 547 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \ 548 0x1 << 1) 549 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \ 550 0x1 << 0) 551 #define IGU_REG_MAPPING_MEMORY \ 552 0x184000UL 553 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \ 554 0x180408UL 555 #define IGU_REG_WRITE_DONE_PENDING \ 556 0x180900UL 557 #define MISCS_REG_GENERIC_POR_0 \ 558 0x0096d4UL 559 #define MCP_REG_NVM_CFG4 \ 560 0xe0642cUL 561 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \ 562 0x7 << 0) 563 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ 564 0 565 #define MCP_REG_CPU_STATE \ 566 0xe05004UL 567 #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10) 568 #define MCP_REG_CPU_EVENT_MASK \ 569 0xe05008UL 570 #define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL 571 #define PGLUE_B_REG_PF_BAR0_SIZE \ 572 0x2aae60UL 573 #define PGLUE_B_REG_PF_BAR1_SIZE \ 574 0x2aae64UL 575 #define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL 576 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL 577 #define PRS_REG_GRE_PROTOCOL 0x1f0734UL 578 #define PRS_REG_VXLAN_PORT 0x1f0738UL 579 #define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL 580 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL 581 582 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0) 583 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0 584 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1) 585 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1 586 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2) 587 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2 588 589 #define NIG_REG_VXLAN_CTRL 0x50105cUL 590 #define PBF_REG_VXLAN_PORT 0xd80518UL 591 #define PBF_REG_NGE_PORT 0xd8051cUL 592 #define PRS_REG_NGE_PORT 0x1f086cUL 593 #define NIG_REG_NGE_PORT 0x508b38UL 594 595 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL 596 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL 597 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL 598 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL 599 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL 600 601 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL 602 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL 603 #define NIG_REG_NGE_COMP_VER 0x508b30UL 604 #define PBF_REG_NGE_COMP_VER 0xd80524UL 605 #define PRS_REG_NGE_COMP_VER 0x1f0878UL 606 607 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL 608 #define QM_REG_WFQVPWEIGHT 0x2fa000UL 609 610 #define PGLCS_REG_DBG_SELECT_K2_E5 \ 611 0x001d14UL 612 #define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5 \ 613 0x001d18UL 614 #define PGLCS_REG_DBG_SHIFT_K2_E5 \ 615 0x001d1cUL 616 #define PGLCS_REG_DBG_FORCE_VALID_K2_E5 \ 617 0x001d20UL 618 #define PGLCS_REG_DBG_FORCE_FRAME_K2_E5 \ 619 0x001d24UL 620 #define MISC_REG_RESET_PL_PDA_VMAIN_1 \ 621 0x008070UL 622 #define MISC_REG_RESET_PL_PDA_VMAIN_2 \ 623 0x008080UL 624 #define MISC_REG_RESET_PL_PDA_VAUX \ 625 0x008090UL 626 #define MISCS_REG_RESET_PL_UA \ 627 0x009050UL 628 #define MISCS_REG_RESET_PL_HV \ 629 0x009060UL 630 #define MISCS_REG_RESET_PL_HV_2_K2_E5 \ 631 0x009150UL 632 #define DMAE_REG_DBG_SELECT \ 633 0x00c510UL 634 #define DMAE_REG_DBG_DWORD_ENABLE \ 635 0x00c514UL 636 #define DMAE_REG_DBG_SHIFT \ 637 0x00c518UL 638 #define DMAE_REG_DBG_FORCE_VALID \ 639 0x00c51cUL 640 #define DMAE_REG_DBG_FORCE_FRAME \ 641 0x00c520UL 642 #define NCSI_REG_DBG_SELECT \ 643 0x040474UL 644 #define NCSI_REG_DBG_DWORD_ENABLE \ 645 0x040478UL 646 #define NCSI_REG_DBG_SHIFT \ 647 0x04047cUL 648 #define NCSI_REG_DBG_FORCE_VALID \ 649 0x040480UL 650 #define NCSI_REG_DBG_FORCE_FRAME \ 651 0x040484UL 652 #define GRC_REG_DBG_SELECT \ 653 0x0500a4UL 654 #define GRC_REG_DBG_DWORD_ENABLE \ 655 0x0500a8UL 656 #define GRC_REG_DBG_SHIFT \ 657 0x0500acUL 658 #define GRC_REG_DBG_FORCE_VALID \ 659 0x0500b0UL 660 #define GRC_REG_DBG_FORCE_FRAME \ 661 0x0500b4UL 662 #define UMAC_REG_DBG_SELECT_K2_E5 \ 663 0x051094UL 664 #define UMAC_REG_DBG_DWORD_ENABLE_K2_E5 \ 665 0x051098UL 666 #define UMAC_REG_DBG_SHIFT_K2_E5 \ 667 0x05109cUL 668 #define UMAC_REG_DBG_FORCE_VALID_K2_E5 \ 669 0x0510a0UL 670 #define UMAC_REG_DBG_FORCE_FRAME_K2_E5 \ 671 0x0510a4UL 672 #define MCP2_REG_DBG_SELECT \ 673 0x052400UL 674 #define MCP2_REG_DBG_DWORD_ENABLE \ 675 0x052404UL 676 #define MCP2_REG_DBG_SHIFT \ 677 0x052408UL 678 #define MCP2_REG_DBG_FORCE_VALID \ 679 0x052440UL 680 #define MCP2_REG_DBG_FORCE_FRAME \ 681 0x052444UL 682 #define PCIE_REG_DBG_SELECT \ 683 0x0547e8UL 684 #define PCIE_REG_DBG_DWORD_ENABLE \ 685 0x0547ecUL 686 #define PCIE_REG_DBG_SHIFT \ 687 0x0547f0UL 688 #define PCIE_REG_DBG_FORCE_VALID \ 689 0x0547f4UL 690 #define PCIE_REG_DBG_FORCE_FRAME \ 691 0x0547f8UL 692 #define DORQ_REG_DBG_SELECT \ 693 0x100ad0UL 694 #define DORQ_REG_DBG_DWORD_ENABLE \ 695 0x100ad4UL 696 #define DORQ_REG_DBG_SHIFT \ 697 0x100ad8UL 698 #define DORQ_REG_DBG_FORCE_VALID \ 699 0x100adcUL 700 #define DORQ_REG_DBG_FORCE_FRAME \ 701 0x100ae0UL 702 #define IGU_REG_DBG_SELECT \ 703 0x181578UL 704 #define IGU_REG_DBG_DWORD_ENABLE \ 705 0x18157cUL 706 #define IGU_REG_DBG_SHIFT \ 707 0x181580UL 708 #define IGU_REG_DBG_FORCE_VALID \ 709 0x181584UL 710 #define IGU_REG_DBG_FORCE_FRAME \ 711 0x181588UL 712 #define CAU_REG_DBG_SELECT \ 713 0x1c0ea8UL 714 #define CAU_REG_DBG_DWORD_ENABLE \ 715 0x1c0eacUL 716 #define CAU_REG_DBG_SHIFT \ 717 0x1c0eb0UL 718 #define CAU_REG_DBG_FORCE_VALID \ 719 0x1c0eb4UL 720 #define CAU_REG_DBG_FORCE_FRAME \ 721 0x1c0eb8UL 722 #define PRS_REG_DBG_SELECT \ 723 0x1f0b6cUL 724 #define PRS_REG_DBG_DWORD_ENABLE \ 725 0x1f0b70UL 726 #define PRS_REG_DBG_SHIFT \ 727 0x1f0b74UL 728 #define PRS_REG_DBG_FORCE_VALID \ 729 0x1f0ba0UL 730 #define PRS_REG_DBG_FORCE_FRAME \ 731 0x1f0ba4UL 732 #define CNIG_REG_DBG_SELECT_K2_E5 \ 733 0x218254UL 734 #define CNIG_REG_DBG_DWORD_ENABLE_K2_E5 \ 735 0x218258UL 736 #define CNIG_REG_DBG_SHIFT_K2_E5 \ 737 0x21825cUL 738 #define CNIG_REG_DBG_FORCE_VALID_K2_E5 \ 739 0x218260UL 740 #define CNIG_REG_DBG_FORCE_FRAME_K2_E5 \ 741 0x218264UL 742 #define PRM_REG_DBG_SELECT \ 743 0x2306a8UL 744 #define PRM_REG_DBG_DWORD_ENABLE \ 745 0x2306acUL 746 #define PRM_REG_DBG_SHIFT \ 747 0x2306b0UL 748 #define PRM_REG_DBG_FORCE_VALID \ 749 0x2306b4UL 750 #define PRM_REG_DBG_FORCE_FRAME \ 751 0x2306b8UL 752 #define SRC_REG_DBG_SELECT \ 753 0x238700UL 754 #define SRC_REG_DBG_DWORD_ENABLE \ 755 0x238704UL 756 #define SRC_REG_DBG_SHIFT \ 757 0x238708UL 758 #define SRC_REG_DBG_FORCE_VALID \ 759 0x23870cUL 760 #define SRC_REG_DBG_FORCE_FRAME \ 761 0x238710UL 762 #define RSS_REG_DBG_SELECT \ 763 0x238c4cUL 764 #define RSS_REG_DBG_DWORD_ENABLE \ 765 0x238c50UL 766 #define RSS_REG_DBG_SHIFT \ 767 0x238c54UL 768 #define RSS_REG_DBG_FORCE_VALID \ 769 0x238c58UL 770 #define RSS_REG_DBG_FORCE_FRAME \ 771 0x238c5cUL 772 #define RPB_REG_DBG_SELECT \ 773 0x23c728UL 774 #define RPB_REG_DBG_DWORD_ENABLE \ 775 0x23c72cUL 776 #define RPB_REG_DBG_SHIFT \ 777 0x23c730UL 778 #define RPB_REG_DBG_FORCE_VALID \ 779 0x23c734UL 780 #define RPB_REG_DBG_FORCE_FRAME \ 781 0x23c738UL 782 #define PSWRQ2_REG_DBG_SELECT \ 783 0x240100UL 784 #define PSWRQ2_REG_DBG_DWORD_ENABLE \ 785 0x240104UL 786 #define PSWRQ2_REG_DBG_SHIFT \ 787 0x240108UL 788 #define PSWRQ2_REG_DBG_FORCE_VALID \ 789 0x24010cUL 790 #define PSWRQ2_REG_DBG_FORCE_FRAME \ 791 0x240110UL 792 #define PSWRQ_REG_DBG_SELECT \ 793 0x280020UL 794 #define PSWRQ_REG_DBG_DWORD_ENABLE \ 795 0x280024UL 796 #define PSWRQ_REG_DBG_SHIFT \ 797 0x280028UL 798 #define PSWRQ_REG_DBG_FORCE_VALID \ 799 0x28002cUL 800 #define PSWRQ_REG_DBG_FORCE_FRAME \ 801 0x280030UL 802 #define PSWWR_REG_DBG_SELECT \ 803 0x29a084UL 804 #define PSWWR_REG_DBG_DWORD_ENABLE \ 805 0x29a088UL 806 #define PSWWR_REG_DBG_SHIFT \ 807 0x29a08cUL 808 #define PSWWR_REG_DBG_FORCE_VALID \ 809 0x29a090UL 810 #define PSWWR_REG_DBG_FORCE_FRAME \ 811 0x29a094UL 812 #define PSWRD_REG_DBG_SELECT \ 813 0x29c040UL 814 #define PSWRD_REG_DBG_DWORD_ENABLE \ 815 0x29c044UL 816 #define PSWRD_REG_DBG_SHIFT \ 817 0x29c048UL 818 #define PSWRD_REG_DBG_FORCE_VALID \ 819 0x29c04cUL 820 #define PSWRD_REG_DBG_FORCE_FRAME \ 821 0x29c050UL 822 #define PSWRD2_REG_DBG_SELECT \ 823 0x29d400UL 824 #define PSWRD2_REG_DBG_DWORD_ENABLE \ 825 0x29d404UL 826 #define PSWRD2_REG_DBG_SHIFT \ 827 0x29d408UL 828 #define PSWRD2_REG_DBG_FORCE_VALID \ 829 0x29d40cUL 830 #define PSWRD2_REG_DBG_FORCE_FRAME \ 831 0x29d410UL 832 #define PSWHST2_REG_DBG_SELECT \ 833 0x29e058UL 834 #define PSWHST2_REG_DBG_DWORD_ENABLE \ 835 0x29e05cUL 836 #define PSWHST2_REG_DBG_SHIFT \ 837 0x29e060UL 838 #define PSWHST2_REG_DBG_FORCE_VALID \ 839 0x29e064UL 840 #define PSWHST2_REG_DBG_FORCE_FRAME \ 841 0x29e068UL 842 #define PSWHST_REG_DBG_SELECT \ 843 0x2a0100UL 844 #define PSWHST_REG_DBG_DWORD_ENABLE \ 845 0x2a0104UL 846 #define PSWHST_REG_DBG_SHIFT \ 847 0x2a0108UL 848 #define PSWHST_REG_DBG_FORCE_VALID \ 849 0x2a010cUL 850 #define PSWHST_REG_DBG_FORCE_FRAME \ 851 0x2a0110UL 852 #define PGLUE_B_REG_DBG_SELECT \ 853 0x2a8400UL 854 #define PGLUE_B_REG_DBG_DWORD_ENABLE \ 855 0x2a8404UL 856 #define PGLUE_B_REG_DBG_SHIFT \ 857 0x2a8408UL 858 #define PGLUE_B_REG_DBG_FORCE_VALID \ 859 0x2a840cUL 860 #define PGLUE_B_REG_DBG_FORCE_FRAME \ 861 0x2a8410UL 862 #define TM_REG_DBG_SELECT \ 863 0x2c07a8UL 864 #define TM_REG_DBG_DWORD_ENABLE \ 865 0x2c07acUL 866 #define TM_REG_DBG_SHIFT \ 867 0x2c07b0UL 868 #define TM_REG_DBG_FORCE_VALID \ 869 0x2c07b4UL 870 #define TM_REG_DBG_FORCE_FRAME \ 871 0x2c07b8UL 872 #define TCFC_REG_DBG_SELECT \ 873 0x2d0500UL 874 #define TCFC_REG_DBG_DWORD_ENABLE \ 875 0x2d0504UL 876 #define TCFC_REG_DBG_SHIFT \ 877 0x2d0508UL 878 #define TCFC_REG_DBG_FORCE_VALID \ 879 0x2d050cUL 880 #define TCFC_REG_DBG_FORCE_FRAME \ 881 0x2d0510UL 882 #define CCFC_REG_DBG_SELECT \ 883 0x2e0500UL 884 #define CCFC_REG_DBG_DWORD_ENABLE \ 885 0x2e0504UL 886 #define CCFC_REG_DBG_SHIFT \ 887 0x2e0508UL 888 #define CCFC_REG_DBG_FORCE_VALID \ 889 0x2e050cUL 890 #define CCFC_REG_DBG_FORCE_FRAME \ 891 0x2e0510UL 892 #define QM_REG_DBG_SELECT \ 893 0x2f2e74UL 894 #define QM_REG_DBG_DWORD_ENABLE \ 895 0x2f2e78UL 896 #define QM_REG_DBG_SHIFT \ 897 0x2f2e7cUL 898 #define QM_REG_DBG_FORCE_VALID \ 899 0x2f2e80UL 900 #define QM_REG_DBG_FORCE_FRAME \ 901 0x2f2e84UL 902 #define RDIF_REG_DBG_SELECT \ 903 0x300500UL 904 #define RDIF_REG_DBG_DWORD_ENABLE \ 905 0x300504UL 906 #define RDIF_REG_DBG_SHIFT \ 907 0x300508UL 908 #define RDIF_REG_DBG_FORCE_VALID \ 909 0x30050cUL 910 #define RDIF_REG_DBG_FORCE_FRAME \ 911 0x300510UL 912 #define TDIF_REG_DBG_SELECT \ 913 0x310500UL 914 #define TDIF_REG_DBG_DWORD_ENABLE \ 915 0x310504UL 916 #define TDIF_REG_DBG_SHIFT \ 917 0x310508UL 918 #define TDIF_REG_DBG_FORCE_VALID \ 919 0x31050cUL 920 #define TDIF_REG_DBG_FORCE_FRAME \ 921 0x310510UL 922 #define BRB_REG_DBG_SELECT \ 923 0x340ed0UL 924 #define BRB_REG_DBG_DWORD_ENABLE \ 925 0x340ed4UL 926 #define BRB_REG_DBG_SHIFT \ 927 0x340ed8UL 928 #define BRB_REG_DBG_FORCE_VALID \ 929 0x340edcUL 930 #define BRB_REG_DBG_FORCE_FRAME \ 931 0x340ee0UL 932 #define XYLD_REG_DBG_SELECT \ 933 0x4c1600UL 934 #define XYLD_REG_DBG_DWORD_ENABLE \ 935 0x4c1604UL 936 #define XYLD_REG_DBG_SHIFT \ 937 0x4c1608UL 938 #define XYLD_REG_DBG_FORCE_VALID \ 939 0x4c160cUL 940 #define XYLD_REG_DBG_FORCE_FRAME \ 941 0x4c1610UL 942 #define YULD_REG_DBG_SELECT_BB_K2 \ 943 0x4c9600UL 944 #define YULD_REG_DBG_DWORD_ENABLE_BB_K2 \ 945 0x4c9604UL 946 #define YULD_REG_DBG_SHIFT_BB_K2 \ 947 0x4c9608UL 948 #define YULD_REG_DBG_FORCE_VALID_BB_K2 \ 949 0x4c960cUL 950 #define YULD_REG_DBG_FORCE_FRAME_BB_K2 \ 951 0x4c9610UL 952 #define TMLD_REG_DBG_SELECT \ 953 0x4d1600UL 954 #define TMLD_REG_DBG_DWORD_ENABLE \ 955 0x4d1604UL 956 #define TMLD_REG_DBG_SHIFT \ 957 0x4d1608UL 958 #define TMLD_REG_DBG_FORCE_VALID \ 959 0x4d160cUL 960 #define TMLD_REG_DBG_FORCE_FRAME \ 961 0x4d1610UL 962 #define MULD_REG_DBG_SELECT \ 963 0x4e1600UL 964 #define MULD_REG_DBG_DWORD_ENABLE \ 965 0x4e1604UL 966 #define MULD_REG_DBG_SHIFT \ 967 0x4e1608UL 968 #define MULD_REG_DBG_FORCE_VALID \ 969 0x4e160cUL 970 #define MULD_REG_DBG_FORCE_FRAME \ 971 0x4e1610UL 972 #define NIG_REG_DBG_SELECT \ 973 0x502140UL 974 #define NIG_REG_DBG_DWORD_ENABLE \ 975 0x502144UL 976 #define NIG_REG_DBG_SHIFT \ 977 0x502148UL 978 #define NIG_REG_DBG_FORCE_VALID \ 979 0x50214cUL 980 #define NIG_REG_DBG_FORCE_FRAME \ 981 0x502150UL 982 #define BMB_REG_DBG_SELECT \ 983 0x540a7cUL 984 #define BMB_REG_DBG_DWORD_ENABLE \ 985 0x540a80UL 986 #define BMB_REG_DBG_SHIFT \ 987 0x540a84UL 988 #define BMB_REG_DBG_FORCE_VALID \ 989 0x540a88UL 990 #define BMB_REG_DBG_FORCE_FRAME \ 991 0x540a8cUL 992 #define PTU_REG_DBG_SELECT \ 993 0x560100UL 994 #define PTU_REG_DBG_DWORD_ENABLE \ 995 0x560104UL 996 #define PTU_REG_DBG_SHIFT \ 997 0x560108UL 998 #define PTU_REG_DBG_FORCE_VALID \ 999 0x56010cUL 1000 #define PTU_REG_DBG_FORCE_FRAME \ 1001 0x560110UL 1002 #define CDU_REG_DBG_SELECT \ 1003 0x580704UL 1004 #define CDU_REG_DBG_DWORD_ENABLE \ 1005 0x580708UL 1006 #define CDU_REG_DBG_SHIFT \ 1007 0x58070cUL 1008 #define CDU_REG_DBG_FORCE_VALID \ 1009 0x580710UL 1010 #define CDU_REG_DBG_FORCE_FRAME \ 1011 0x580714UL 1012 #define WOL_REG_DBG_SELECT_K2_E5 \ 1013 0x600140UL 1014 #define WOL_REG_DBG_DWORD_ENABLE_K2_E5 \ 1015 0x600144UL 1016 #define WOL_REG_DBG_SHIFT_K2_E5 \ 1017 0x600148UL 1018 #define WOL_REG_DBG_FORCE_VALID_K2_E5 \ 1019 0x60014cUL 1020 #define WOL_REG_DBG_FORCE_FRAME_K2_E5 \ 1021 0x600150UL 1022 #define BMBN_REG_DBG_SELECT_K2_E5 \ 1023 0x610140UL 1024 #define BMBN_REG_DBG_DWORD_ENABLE_K2_E5 \ 1025 0x610144UL 1026 #define BMBN_REG_DBG_SHIFT_K2_E5 \ 1027 0x610148UL 1028 #define BMBN_REG_DBG_FORCE_VALID_K2_E5 \ 1029 0x61014cUL 1030 #define BMBN_REG_DBG_FORCE_FRAME_K2_E5 \ 1031 0x610150UL 1032 #define NWM_REG_DBG_SELECT_K2_E5 \ 1033 0x8000ecUL 1034 #define NWM_REG_DBG_DWORD_ENABLE_K2_E5 \ 1035 0x8000f0UL 1036 #define NWM_REG_DBG_SHIFT_K2_E5 \ 1037 0x8000f4UL 1038 #define NWM_REG_DBG_FORCE_VALID_K2_E5 \ 1039 0x8000f8UL 1040 #define NWM_REG_DBG_FORCE_FRAME_K2_E5 \ 1041 0x8000fcUL 1042 #define PBF_REG_DBG_SELECT \ 1043 0xd80060UL 1044 #define PBF_REG_DBG_DWORD_ENABLE \ 1045 0xd80064UL 1046 #define PBF_REG_DBG_SHIFT \ 1047 0xd80068UL 1048 #define PBF_REG_DBG_FORCE_VALID \ 1049 0xd8006cUL 1050 #define PBF_REG_DBG_FORCE_FRAME \ 1051 0xd80070UL 1052 #define PBF_PB1_REG_DBG_SELECT \ 1053 0xda0728UL 1054 #define PBF_PB1_REG_DBG_DWORD_ENABLE \ 1055 0xda072cUL 1056 #define PBF_PB1_REG_DBG_SHIFT \ 1057 0xda0730UL 1058 #define PBF_PB1_REG_DBG_FORCE_VALID \ 1059 0xda0734UL 1060 #define PBF_PB1_REG_DBG_FORCE_FRAME \ 1061 0xda0738UL 1062 #define PBF_PB2_REG_DBG_SELECT \ 1063 0xda4728UL 1064 #define PBF_PB2_REG_DBG_DWORD_ENABLE \ 1065 0xda472cUL 1066 #define PBF_PB2_REG_DBG_SHIFT \ 1067 0xda4730UL 1068 #define PBF_PB2_REG_DBG_FORCE_VALID \ 1069 0xda4734UL 1070 #define PBF_PB2_REG_DBG_FORCE_FRAME \ 1071 0xda4738UL 1072 #define BTB_REG_DBG_SELECT \ 1073 0xdb08c8UL 1074 #define BTB_REG_DBG_DWORD_ENABLE \ 1075 0xdb08ccUL 1076 #define BTB_REG_DBG_SHIFT \ 1077 0xdb08d0UL 1078 #define BTB_REG_DBG_FORCE_VALID \ 1079 0xdb08d4UL 1080 #define BTB_REG_DBG_FORCE_FRAME \ 1081 0xdb08d8UL 1082 #define XSDM_REG_DBG_SELECT \ 1083 0xf80e28UL 1084 #define XSDM_REG_DBG_DWORD_ENABLE \ 1085 0xf80e2cUL 1086 #define XSDM_REG_DBG_SHIFT \ 1087 0xf80e30UL 1088 #define XSDM_REG_DBG_FORCE_VALID \ 1089 0xf80e34UL 1090 #define XSDM_REG_DBG_FORCE_FRAME \ 1091 0xf80e38UL 1092 #define YSDM_REG_DBG_SELECT \ 1093 0xf90e28UL 1094 #define YSDM_REG_DBG_DWORD_ENABLE \ 1095 0xf90e2cUL 1096 #define YSDM_REG_DBG_SHIFT \ 1097 0xf90e30UL 1098 #define YSDM_REG_DBG_FORCE_VALID \ 1099 0xf90e34UL 1100 #define YSDM_REG_DBG_FORCE_FRAME \ 1101 0xf90e38UL 1102 #define PSDM_REG_DBG_SELECT \ 1103 0xfa0e28UL 1104 #define PSDM_REG_DBG_DWORD_ENABLE \ 1105 0xfa0e2cUL 1106 #define PSDM_REG_DBG_SHIFT \ 1107 0xfa0e30UL 1108 #define PSDM_REG_DBG_FORCE_VALID \ 1109 0xfa0e34UL 1110 #define PSDM_REG_DBG_FORCE_FRAME \ 1111 0xfa0e38UL 1112 #define TSDM_REG_DBG_SELECT \ 1113 0xfb0e28UL 1114 #define TSDM_REG_DBG_DWORD_ENABLE \ 1115 0xfb0e2cUL 1116 #define TSDM_REG_DBG_SHIFT \ 1117 0xfb0e30UL 1118 #define TSDM_REG_DBG_FORCE_VALID \ 1119 0xfb0e34UL 1120 #define TSDM_REG_DBG_FORCE_FRAME \ 1121 0xfb0e38UL 1122 #define MSDM_REG_DBG_SELECT \ 1123 0xfc0e28UL 1124 #define MSDM_REG_DBG_DWORD_ENABLE \ 1125 0xfc0e2cUL 1126 #define MSDM_REG_DBG_SHIFT \ 1127 0xfc0e30UL 1128 #define MSDM_REG_DBG_FORCE_VALID \ 1129 0xfc0e34UL 1130 #define MSDM_REG_DBG_FORCE_FRAME \ 1131 0xfc0e38UL 1132 #define USDM_REG_DBG_SELECT \ 1133 0xfd0e28UL 1134 #define USDM_REG_DBG_DWORD_ENABLE \ 1135 0xfd0e2cUL 1136 #define USDM_REG_DBG_SHIFT \ 1137 0xfd0e30UL 1138 #define USDM_REG_DBG_FORCE_VALID \ 1139 0xfd0e34UL 1140 #define USDM_REG_DBG_FORCE_FRAME \ 1141 0xfd0e38UL 1142 #define XCM_REG_DBG_SELECT \ 1143 0x1000040UL 1144 #define XCM_REG_DBG_DWORD_ENABLE \ 1145 0x1000044UL 1146 #define XCM_REG_DBG_SHIFT \ 1147 0x1000048UL 1148 #define XCM_REG_DBG_FORCE_VALID \ 1149 0x100004cUL 1150 #define XCM_REG_DBG_FORCE_FRAME \ 1151 0x1000050UL 1152 #define YCM_REG_DBG_SELECT \ 1153 0x1080040UL 1154 #define YCM_REG_DBG_DWORD_ENABLE \ 1155 0x1080044UL 1156 #define YCM_REG_DBG_SHIFT \ 1157 0x1080048UL 1158 #define YCM_REG_DBG_FORCE_VALID \ 1159 0x108004cUL 1160 #define YCM_REG_DBG_FORCE_FRAME \ 1161 0x1080050UL 1162 #define PCM_REG_DBG_SELECT \ 1163 0x1100040UL 1164 #define PCM_REG_DBG_DWORD_ENABLE \ 1165 0x1100044UL 1166 #define PCM_REG_DBG_SHIFT \ 1167 0x1100048UL 1168 #define PCM_REG_DBG_FORCE_VALID \ 1169 0x110004cUL 1170 #define PCM_REG_DBG_FORCE_FRAME \ 1171 0x1100050UL 1172 #define TCM_REG_DBG_SELECT \ 1173 0x1180040UL 1174 #define TCM_REG_DBG_DWORD_ENABLE \ 1175 0x1180044UL 1176 #define TCM_REG_DBG_SHIFT \ 1177 0x1180048UL 1178 #define TCM_REG_DBG_FORCE_VALID \ 1179 0x118004cUL 1180 #define TCM_REG_DBG_FORCE_FRAME \ 1181 0x1180050UL 1182 #define MCM_REG_DBG_SELECT \ 1183 0x1200040UL 1184 #define MCM_REG_DBG_DWORD_ENABLE \ 1185 0x1200044UL 1186 #define MCM_REG_DBG_SHIFT \ 1187 0x1200048UL 1188 #define MCM_REG_DBG_FORCE_VALID \ 1189 0x120004cUL 1190 #define MCM_REG_DBG_FORCE_FRAME \ 1191 0x1200050UL 1192 #define UCM_REG_DBG_SELECT \ 1193 0x1280050UL 1194 #define UCM_REG_DBG_DWORD_ENABLE \ 1195 0x1280054UL 1196 #define UCM_REG_DBG_SHIFT \ 1197 0x1280058UL 1198 #define UCM_REG_DBG_FORCE_VALID \ 1199 0x128005cUL 1200 #define UCM_REG_DBG_FORCE_FRAME \ 1201 0x1280060UL 1202 #define XSEM_REG_DBG_SELECT \ 1203 0x1401528UL 1204 #define XSEM_REG_DBG_DWORD_ENABLE \ 1205 0x140152cUL 1206 #define XSEM_REG_DBG_SHIFT \ 1207 0x1401530UL 1208 #define XSEM_REG_DBG_FORCE_VALID \ 1209 0x1401534UL 1210 #define XSEM_REG_DBG_FORCE_FRAME \ 1211 0x1401538UL 1212 #define YSEM_REG_DBG_SELECT \ 1213 0x1501528UL 1214 #define YSEM_REG_DBG_DWORD_ENABLE \ 1215 0x150152cUL 1216 #define YSEM_REG_DBG_SHIFT \ 1217 0x1501530UL 1218 #define YSEM_REG_DBG_FORCE_VALID \ 1219 0x1501534UL 1220 #define YSEM_REG_DBG_FORCE_FRAME \ 1221 0x1501538UL 1222 #define PSEM_REG_DBG_SELECT \ 1223 0x1601528UL 1224 #define PSEM_REG_DBG_DWORD_ENABLE \ 1225 0x160152cUL 1226 #define PSEM_REG_DBG_SHIFT \ 1227 0x1601530UL 1228 #define PSEM_REG_DBG_FORCE_VALID \ 1229 0x1601534UL 1230 #define PSEM_REG_DBG_FORCE_FRAME \ 1231 0x1601538UL 1232 #define TSEM_REG_DBG_SELECT \ 1233 0x1701528UL 1234 #define TSEM_REG_DBG_DWORD_ENABLE \ 1235 0x170152cUL 1236 #define TSEM_REG_DBG_SHIFT \ 1237 0x1701530UL 1238 #define TSEM_REG_DBG_FORCE_VALID \ 1239 0x1701534UL 1240 #define TSEM_REG_DBG_FORCE_FRAME \ 1241 0x1701538UL 1242 #define DORQ_REG_PF_USAGE_CNT \ 1243 0x1009c0UL 1244 #define DORQ_REG_PF_OVFL_STICKY \ 1245 0x1009d0UL 1246 #define DORQ_REG_DPM_FORCE_ABORT \ 1247 0x1009d8UL 1248 #define DORQ_REG_INT_STS \ 1249 0x100180UL 1250 #define DORQ_REG_INT_STS_ADDRESS_ERROR \ 1251 (0x1UL << 0) 1252 #define DORQ_REG_INT_STS_WR \ 1253 0x100188UL 1254 #define DORQ_REG_DB_DROP_DETAILS_REL \ 1255 0x100a28UL 1256 #define DORQ_REG_INT_STS_ADDRESS_ERROR_SHIFT \ 1257 0 1258 #define DORQ_REG_INT_STS_DB_DROP \ 1259 (0x1UL << 1) 1260 #define DORQ_REG_INT_STS_DB_DROP_SHIFT \ 1261 1 1262 #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR \ 1263 (0x1UL << 2) 1264 #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR_SHIFT \ 1265 2 1266 #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL\ 1267 (0x1UL << 3) 1268 #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL_SHIFT \ 1269 3 1270 #define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR \ 1271 (0x1UL << 4) 1272 #define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR_SHIFT \ 1273 4 1274 #define DORQ_REG_INT_STS_CFC_LD_RESP_ERR \ 1275 (0x1UL << 5) 1276 #define DORQ_REG_INT_STS_CFC_LD_RESP_ERR_SHIFT \ 1277 5 1278 #define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR \ 1279 (0x1UL << 6) 1280 #define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR_SHIFT \ 1281 6 1282 #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR \ 1283 (0x1UL << 7) 1284 #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT \ 1285 7 1286 #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR \ 1287 (0x1UL << 8) 1288 #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT \ 1289 8 1290 #define DORQ_REG_DB_DROP_DETAILS_REASON \ 1291 0x100a20UL 1292 #define MSEM_REG_DBG_SELECT \ 1293 0x1801528UL 1294 #define MSEM_REG_DBG_DWORD_ENABLE \ 1295 0x180152cUL 1296 #define MSEM_REG_DBG_SHIFT \ 1297 0x1801530UL 1298 #define MSEM_REG_DBG_FORCE_VALID \ 1299 0x1801534UL 1300 #define MSEM_REG_DBG_FORCE_FRAME \ 1301 0x1801538UL 1302 #define USEM_REG_DBG_SELECT \ 1303 0x1901528UL 1304 #define USEM_REG_DBG_DWORD_ENABLE \ 1305 0x190152cUL 1306 #define USEM_REG_DBG_SHIFT \ 1307 0x1901530UL 1308 #define USEM_REG_DBG_FORCE_VALID \ 1309 0x1901534UL 1310 #define USEM_REG_DBG_FORCE_FRAME \ 1311 0x1901538UL 1312 #define NWS_REG_DBG_SELECT_K2_E5 \ 1313 0x700128UL 1314 #define NWS_REG_DBG_DWORD_ENABLE_K2_E5 \ 1315 0x70012cUL 1316 #define NWS_REG_DBG_SHIFT_K2_E5 \ 1317 0x700130UL 1318 #define NWS_REG_DBG_FORCE_VALID_K2_E5 \ 1319 0x700134UL 1320 #define NWS_REG_DBG_FORCE_FRAME_K2_E5 \ 1321 0x700138UL 1322 #define MS_REG_DBG_SELECT_K2_E5 \ 1323 0x6a0228UL 1324 #define MS_REG_DBG_DWORD_ENABLE_K2_E5 \ 1325 0x6a022cUL 1326 #define MS_REG_DBG_SHIFT_K2_E5 \ 1327 0x6a0230UL 1328 #define MS_REG_DBG_FORCE_VALID_K2_E5 \ 1329 0x6a0234UL 1330 #define MS_REG_DBG_FORCE_FRAME_K2_E5 \ 1331 0x6a0238UL 1332 #define PCIE_REG_DBG_COMMON_SELECT_K2_E5 \ 1333 0x054398UL 1334 #define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5 \ 1335 0x05439cUL 1336 #define PCIE_REG_DBG_COMMON_SHIFT_K2_E5 \ 1337 0x0543a0UL 1338 #define PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5 \ 1339 0x0543a4UL 1340 #define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5 \ 1341 0x0543a8UL 1342 #define PTLD_REG_DBG_SELECT_E5 \ 1343 0x5a1600UL 1344 #define PTLD_REG_DBG_DWORD_ENABLE_E5 \ 1345 0x5a1604UL 1346 #define PTLD_REG_DBG_SHIFT_E5 \ 1347 0x5a1608UL 1348 #define PTLD_REG_DBG_FORCE_VALID_E5 \ 1349 0x5a160cUL 1350 #define PTLD_REG_DBG_FORCE_FRAME_E5 \ 1351 0x5a1610UL 1352 #define YPLD_REG_DBG_SELECT_E5 \ 1353 0x5c1600UL 1354 #define YPLD_REG_DBG_DWORD_ENABLE_E5 \ 1355 0x5c1604UL 1356 #define YPLD_REG_DBG_SHIFT_E5 \ 1357 0x5c1608UL 1358 #define YPLD_REG_DBG_FORCE_VALID_E5 \ 1359 0x5c160cUL 1360 #define YPLD_REG_DBG_FORCE_FRAME_E5 \ 1361 0x5c1610UL 1362 #define RGSRC_REG_DBG_SELECT_E5 \ 1363 0x320040UL 1364 #define RGSRC_REG_DBG_DWORD_ENABLE_E5 \ 1365 0x320044UL 1366 #define RGSRC_REG_DBG_SHIFT_E5 \ 1367 0x320048UL 1368 #define RGSRC_REG_DBG_FORCE_VALID_E5 \ 1369 0x32004cUL 1370 #define RGSRC_REG_DBG_FORCE_FRAME_E5 \ 1371 0x320050UL 1372 #define TGSRC_REG_DBG_SELECT_E5 \ 1373 0x322040UL 1374 #define TGSRC_REG_DBG_DWORD_ENABLE_E5 \ 1375 0x322044UL 1376 #define TGSRC_REG_DBG_SHIFT_E5 \ 1377 0x322048UL 1378 #define TGSRC_REG_DBG_FORCE_VALID_E5 \ 1379 0x32204cUL 1380 #define TGSRC_REG_DBG_FORCE_FRAME_E5 \ 1381 0x322050UL 1382 #define MISC_REG_RESET_PL_UA \ 1383 0x008050UL 1384 #define MISC_REG_RESET_PL_HV \ 1385 0x008060UL 1386 #define XCM_REG_CTX_RBC_ACCS \ 1387 0x1001800UL 1388 #define XCM_REG_AGG_CON_CTX \ 1389 0x1001804UL 1390 #define XCM_REG_SM_CON_CTX \ 1391 0x1001808UL 1392 #define YCM_REG_CTX_RBC_ACCS \ 1393 0x1081800UL 1394 #define YCM_REG_AGG_CON_CTX \ 1395 0x1081804UL 1396 #define YCM_REG_AGG_TASK_CTX \ 1397 0x1081808UL 1398 #define YCM_REG_SM_CON_CTX \ 1399 0x108180cUL 1400 #define YCM_REG_SM_TASK_CTX \ 1401 0x1081810UL 1402 #define PCM_REG_CTX_RBC_ACCS \ 1403 0x1101440UL 1404 #define PCM_REG_SM_CON_CTX \ 1405 0x1101444UL 1406 #define TCM_REG_CTX_RBC_ACCS \ 1407 0x11814c0UL 1408 #define TCM_REG_AGG_CON_CTX \ 1409 0x11814c4UL 1410 #define TCM_REG_AGG_TASK_CTX \ 1411 0x11814c8UL 1412 #define TCM_REG_SM_CON_CTX \ 1413 0x11814ccUL 1414 #define TCM_REG_SM_TASK_CTX \ 1415 0x11814d0UL 1416 #define MCM_REG_CTX_RBC_ACCS \ 1417 0x1201800UL 1418 #define MCM_REG_AGG_CON_CTX \ 1419 0x1201804UL 1420 #define MCM_REG_AGG_TASK_CTX \ 1421 0x1201808UL 1422 #define MCM_REG_SM_CON_CTX \ 1423 0x120180cUL 1424 #define MCM_REG_SM_TASK_CTX \ 1425 0x1201810UL 1426 #define UCM_REG_CTX_RBC_ACCS \ 1427 0x1281700UL 1428 #define UCM_REG_AGG_CON_CTX \ 1429 0x1281704UL 1430 #define UCM_REG_AGG_TASK_CTX \ 1431 0x1281708UL 1432 #define UCM_REG_SM_CON_CTX \ 1433 0x128170cUL 1434 #define UCM_REG_SM_TASK_CTX \ 1435 0x1281710UL 1436 #define XSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1437 0x1401140UL 1438 #define XSEM_REG_SYNC_DBG_EMPTY \ 1439 0x1401160UL 1440 #define XSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1441 0x1401400UL 1442 #define XSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1443 0x1401404UL 1444 #define XSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1445 0x1401408UL 1446 #define XSEM_REG_DBG_GPRE_VECT \ 1447 0x1401410UL 1448 #define XSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1449 0x1401420UL 1450 #define XSEM_REG_FAST_MEMORY \ 1451 0x1440000UL 1452 #define YSEM_REG_SYNC_DBG_EMPTY \ 1453 0x1501160UL 1454 #define YSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1455 0x1501400UL 1456 #define YSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1457 0x1501404UL 1458 #define YSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1459 0x1501408UL 1460 #define YSEM_REG_DBG_GPRE_VECT \ 1461 0x1501410UL 1462 #define YSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1463 0x1501420UL 1464 #define YSEM_REG_FAST_MEMORY \ 1465 0x1540000UL 1466 #define PSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1467 0x1601140UL 1468 #define PSEM_REG_SYNC_DBG_EMPTY \ 1469 0x1601160UL 1470 #define PSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1471 0x1601400UL 1472 #define PSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1473 0x1601404UL 1474 #define PSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1475 0x1601408UL 1476 #define PSEM_REG_DBG_GPRE_VECT \ 1477 0x1601410UL 1478 #define PSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1479 0x1601420UL 1480 #define PSEM_REG_FAST_MEMORY \ 1481 0x1640000UL 1482 #define TSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1483 0x1701140UL 1484 #define TSEM_REG_SYNC_DBG_EMPTY \ 1485 0x1701160UL 1486 #define TSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1487 0x1701400UL 1488 #define TSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1489 0x1701404UL 1490 #define TSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1491 0x1701408UL 1492 #define TSEM_REG_DBG_GPRE_VECT \ 1493 0x1701410UL 1494 #define TSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1495 0x1701420UL 1496 #define TSEM_REG_FAST_MEMORY \ 1497 0x1740000UL 1498 #define MSEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1499 0x1801140UL 1500 #define MSEM_REG_SYNC_DBG_EMPTY \ 1501 0x1801160UL 1502 #define MSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1503 0x1801400UL 1504 #define MSEM_REG_SLOW_DBG_MODE_BB_K2 \ 1505 0x1801404UL 1506 #define MSEM_REG_DBG_FRAME_MODE_BB_K2 \ 1507 0x1801408UL 1508 #define MSEM_REG_DBG_GPRE_VECT \ 1509 0x1801410UL 1510 #define MSEM_REG_DBG_MODE1_CFG_BB_K2 \ 1511 0x1801420UL 1512 #define MSEM_REG_FAST_MEMORY \ 1513 0x1840000UL 1514 #define USEM_REG_SLOW_DBG_EMPTY_BB_K2 \ 1515 0x1901140UL 1516 #define SEM_FAST_REG_INT_RAM_SIZE \ 1517 20480 1518 #define USEM_REG_SYNC_DBG_EMPTY \ 1519 0x1901160UL 1520 #define USEM_REG_SLOW_DBG_ACTIVE_BB_K2 \ 1521 0x1901400UL 1522 #define USEM_REG_SLOW_DBG_MODE_BB_K2 \ 1523 0x1901404UL 1524 #define USEM_REG_DBG_FRAME_MODE_BB_K2 \ 1525 0x1901408UL 1526 #define USEM_REG_DBG_GPRE_VECT \ 1527 0x1901410UL 1528 #define USEM_REG_DBG_MODE1_CFG_BB_K2 \ 1529 0x1901420UL 1530 #define USEM_REG_FAST_MEMORY \ 1531 0x1940000UL 1532 #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE \ 1533 0x000748UL 1534 #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE \ 1535 0x00074cUL 1536 #define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE \ 1537 0x000750UL 1538 #define SEM_FAST_REG_DEBUG_ACTIVE \ 1539 0x000740UL 1540 #define SEM_FAST_REG_INT_RAM \ 1541 0x020000UL 1542 #define SEM_FAST_REG_INT_RAM_SIZE_BB_K2 \ 1543 20480 1544 #define SEM_FAST_REG_RECORD_FILTER_ENABLE \ 1545 0x000768UL 1546 #define GRC_REG_TRACE_FIFO_VALID_DATA \ 1547 0x050064UL 1548 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \ 1549 0x05040cUL 1550 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW \ 1551 0x050500UL 1552 #define IGU_REG_ERROR_HANDLING_MEMORY \ 1553 0x181520UL 1554 #define MCP_REG_CPU_MODE \ 1555 0xe05000UL 1556 #define MCP_REG_CPU_MODE_SOFT_HALT \ 1557 (0x1 << 10) 1558 #define BRB_REG_BIG_RAM_ADDRESS \ 1559 0x340800UL 1560 #define BRB_REG_BIG_RAM_DATA \ 1561 0x341500UL 1562 #define BRB_REG_BIG_RAM_DATA_SIZE \ 1563 64 1564 #define SEM_FAST_REG_STALL_0_BB_K2 \ 1565 0x000488UL 1566 #define SEM_FAST_REG_STALLED \ 1567 0x000494UL 1568 #define BTB_REG_BIG_RAM_ADDRESS \ 1569 0xdb0800UL 1570 #define BTB_REG_BIG_RAM_DATA \ 1571 0xdb0c00UL 1572 #define BMB_REG_BIG_RAM_ADDRESS \ 1573 0x540800UL 1574 #define BMB_REG_BIG_RAM_DATA \ 1575 0x540f00UL 1576 #define SEM_FAST_REG_STORM_REG_FILE \ 1577 0x008000UL 1578 #define RSS_REG_RSS_RAM_ADDR \ 1579 0x238c30UL 1580 #define MISCS_REG_BLOCK_256B_EN \ 1581 0x009074UL 1582 #define MCP_REG_SCRATCH_SIZE_BB_K2 \ 1583 57344 1584 #define MCP_REG_CPU_REG_FILE \ 1585 0xe05200UL 1586 #define MCP_REG_CPU_REG_FILE_SIZE \ 1587 32 1588 #define DBG_REG_DEBUG_TARGET \ 1589 0x01005cUL 1590 #define DBG_REG_FULL_MODE \ 1591 0x010060UL 1592 #define DBG_REG_CALENDAR_OUT_DATA \ 1593 0x010480UL 1594 #define GRC_REG_TRACE_FIFO \ 1595 0x050068UL 1596 #define IGU_REG_ERROR_HANDLING_DATA_VALID \ 1597 0x181530UL 1598 #define DBG_REG_DBG_BLOCK_ON \ 1599 0x010454UL 1600 #define DBG_REG_FILTER_ENABLE \ 1601 0x0109d0UL 1602 #define DBG_REG_FRAMING_MODE \ 1603 0x010058UL 1604 #define DBG_REG_TRIGGER_ENABLE \ 1605 0x01054cUL 1606 #define SEM_FAST_REG_VFC_DATA_WR \ 1607 0x000b40UL 1608 #define SEM_FAST_REG_VFC_ADDR \ 1609 0x000b44UL 1610 #define SEM_FAST_REG_VFC_DATA_RD \ 1611 0x000b48UL 1612 #define SEM_FAST_REG_VFC_STATUS \ 1613 0x000b4cUL 1614 #define RSS_REG_RSS_RAM_DATA \ 1615 0x238c20UL 1616 #define RSS_REG_RSS_RAM_DATA_SIZE \ 1617 4 1618 #define MISC_REG_BLOCK_256B_EN \ 1619 0x008c14UL 1620 #define NWS_REG_NWS_CMU_K2 \ 1621 0x720000UL 1622 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5 \ 1623 0x000680UL 1624 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5 \ 1625 0x000684UL 1626 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5 \ 1627 0x0006c0UL 1628 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5 \ 1629 0x0006c4UL 1630 #define MS_REG_MS_CMU_K2_E5 \ 1631 0x6a4000UL 1632 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \ 1633 0x000208UL 1634 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \ 1635 0x00020cUL 1636 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \ 1637 0x000210UL 1638 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \ 1639 0x000214UL 1640 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \ 1641 0x000208UL 1642 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \ 1643 0x00020cUL 1644 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \ 1645 0x000210UL 1646 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \ 1647 0x000214UL 1648 #define PHY_PCIE_REG_PHY0_K2_E5 \ 1649 0x620000UL 1650 #define PHY_PCIE_REG_PHY1_K2_E5 \ 1651 0x624000UL 1652 #define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL 1653 #define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL 1654 #define NIG_REG_PPF_TO_ENGINE_SEL_SIZE 8 1655 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL 1656 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL 1657 #define DORQ_REG_PF_DPM_ENABLE 0x100510UL 1658 #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL 1659 #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL 1660 #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL 1661 #define NIG_REG_RX_PTP_EN 0x501900UL 1662 #define NIG_REG_TX_PTP_EN 0x501904UL 1663 #define NIG_REG_LLH_PTP_TO_HOST 0x501908UL 1664 #define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL 1665 #define NIG_REG_PTP_SW_TXTSEN 0x501910UL 1666 #define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL 1667 #define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL 1668 #define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL 1669 #define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL 1670 #define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL 1671 #define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL 1672 #define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL 1673 #define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL 1674 #define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL 1675 #define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB 0x501938UL 1676 #define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL 1677 #define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL 1678 #define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL 1679 #define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL 1680 #define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL 1681 #define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL 1682 #define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL 1683 #define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL 1684 #define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL 1685 #define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL 1686 #define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL 1687 #define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL 1688 #define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL 1689 #define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL 1690 #define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL 1691 #define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL 1692 #define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL 1693 #define PSWRQ2_REG_WR_MBS0 0x240400UL 1694 1695 #define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL 1696 #define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL 1697 #define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL 1698 #define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL 1699 #define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL 1700 #define NIG_REG_TSGEN_FREECNT_UPDATE_K2 0x509008UL 1701 #define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL 1702 1703 #define NIG_REG_TX_EDPM_CTRL 0x501f0cUL 1704 #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN (0x1 << 0) 1705 #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN_SHIFT 0 1706 #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN (0xff << 1) 1707 #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT 1 1708 1709 #define PRS_REG_SEARCH_GFT 0x1f11bcUL 1710 #define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL 1711 #define PRS_REG_CM_HDR_GFT 0x1f11c8UL 1712 #define PRS_REG_GFT_CAM 0x1f1100UL 1713 #define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL 1714 #define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0 1715 #define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8 1716 #define PRS_REG_LOAD_L2_FILTER 0x1f0198UL 1717 1718 #endif 1719
