1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __REGS_2700G_ 3 #define __REGS_2700G_ 4 5 /* extern unsigned long virt_base_2700; */ 6 /* #define __REG_2700G(x) (*(volatile unsigned long*)((x)+virt_base_2700)) */ 7 #define __REG_2700G(x) ((x)+virt_base_2700) 8 9 /* System Configuration Registers (0x0000_0000 0x0000_0010) */ 10 #define SYSCFG __REG_2700G(0x00000000) 11 #define PFBASE __REG_2700G(0x00000004) 12 #define PFCEIL __REG_2700G(0x00000008) 13 #define POLLFLAG __REG_2700G(0x0000000c) 14 #define SYSRST __REG_2700G(0x00000010) 15 16 /* Interrupt Control Registers (0x0000_0014 0x0000_002F) */ 17 #define NINTPW __REG_2700G(0x00000014) 18 #define MINTENABLE __REG_2700G(0x00000018) 19 #define MINTSTAT __REG_2700G(0x0000001c) 20 #define SINTENABLE __REG_2700G(0x00000020) 21 #define SINTSTAT __REG_2700G(0x00000024) 22 #define SINTCLR __REG_2700G(0x00000028) 23 24 /* Clock Control Registers (0x0000_002C 0x0000_005F) */ 25 #define SYSCLKSRC __REG_2700G(0x0000002c) 26 #define PIXCLKSRC __REG_2700G(0x00000030) 27 #define CLKSLEEP __REG_2700G(0x00000034) 28 #define COREPLL __REG_2700G(0x00000038) 29 #define DISPPLL __REG_2700G(0x0000003c) 30 #define PLLSTAT __REG_2700G(0x00000040) 31 #define VOVRCLK __REG_2700G(0x00000044) 32 #define PIXCLK __REG_2700G(0x00000048) 33 #define MEMCLK __REG_2700G(0x0000004c) 34 #define M24CLK __REG_2700G(0x00000050) 35 #define MBXCLK __REG_2700G(0x00000054) 36 #define SDCLK __REG_2700G(0x00000058) 37 #define PIXCLKDIV __REG_2700G(0x0000005c) 38 39 /* LCD Port Control Register (0x0000_0060 0x0000_006F) */ 40 #define LCD_CONFIG __REG_2700G(0x00000060) 41 42 /* On-Die Frame Buffer Registers (0x0000_0064 0x0000_006B) */ 43 #define ODFBPWR __REG_2700G(0x00000064) 44 #define ODFBSTAT __REG_2700G(0x00000068) 45 46 /* GPIO Registers (0x0000_006C 0x0000_007F) */ 47 #define GPIOCGF __REG_2700G(0x0000006c) 48 #define GPIOHI __REG_2700G(0x00000070) 49 #define GPIOLO __REG_2700G(0x00000074) 50 #define GPIOSTAT __REG_2700G(0x00000078) 51 52 /* Pulse Width Modulator (PWM) Registers (0x0000_0200 0x0000_02FF) */ 53 #define PWMRST __REG_2700G(0x00000200) 54 #define PWMCFG __REG_2700G(0x00000204) 55 #define PWM0DIV __REG_2700G(0x00000210) 56 #define PWM0DUTY __REG_2700G(0x00000214) 57 #define PWM0PER __REG_2700G(0x00000218) 58 #define PWM1DIV __REG_2700G(0x00000220) 59 #define PWM1DUTY __REG_2700G(0x00000224) 60 #define PWM1PER __REG_2700G(0x00000228) 61 62 /* Identification (ID) Registers (0x0000_0300 0x0000_0FFF) */ 63 #define ID __REG_2700G(0x00000FF0) 64 65 /* Local Memory (SDRAM) Interface Registers (0x0000_1000 0x0000_1FFF) */ 66 #define LMRST __REG_2700G(0x00001000) 67 #define LMCFG __REG_2700G(0x00001004) 68 #define LMPWR __REG_2700G(0x00001008) 69 #define LMPWRSTAT __REG_2700G(0x0000100c) 70 #define LMCEMR __REG_2700G(0x00001010) 71 #define LMTYPE __REG_2700G(0x00001014) 72 #define LMTIM __REG_2700G(0x00001018) 73 #define LMREFRESH __REG_2700G(0x0000101c) 74 #define LMPROTMIN __REG_2700G(0x00001020) 75 #define LMPROTMAX __REG_2700G(0x00001024) 76 #define LMPROTCFG __REG_2700G(0x00001028) 77 #define LMPROTERR __REG_2700G(0x0000102c) 78 79 /* Plane Controller Registers (0x0000_2000 0x0000_2FFF) */ 80 #define GSCTRL __REG_2700G(0x00002000) 81 #define VSCTRL __REG_2700G(0x00002004) 82 #define GBBASE __REG_2700G(0x00002020) 83 #define VBBASE __REG_2700G(0x00002024) 84 #define GDRCTRL __REG_2700G(0x00002040) 85 #define VCMSK __REG_2700G(0x00002044) 86 #define GSCADR __REG_2700G(0x00002060) 87 #define VSCADR __REG_2700G(0x00002064) 88 #define VUBASE __REG_2700G(0x00002084) 89 #define VVBASE __REG_2700G(0x000020a4) 90 #define GSADR __REG_2700G(0x000020c0) 91 #define VSADR __REG_2700G(0x000020c4) 92 #define HCCTRL __REG_2700G(0x00002100) 93 #define HCSIZE __REG_2700G(0x00002110) 94 #define HCPOS __REG_2700G(0x00002120) 95 #define HCBADR __REG_2700G(0x00002130) 96 #define HCCKMSK __REG_2700G(0x00002140) 97 #define GPLUT __REG_2700G(0x00002150) 98 #define DSCTRL __REG_2700G(0x00002154) 99 #define DHT01 __REG_2700G(0x00002158) 100 #define DHT02 __REG_2700G(0x0000215c) 101 #define DHT03 __REG_2700G(0x00002160) 102 #define DVT01 __REG_2700G(0x00002164) 103 #define DVT02 __REG_2700G(0x00002168) 104 #define DVT03 __REG_2700G(0x0000216c) 105 #define DBCOL __REG_2700G(0x00002170) 106 #define BGCOLOR __REG_2700G(0x00002174) 107 #define DINTRS __REG_2700G(0x00002178) 108 #define DINTRE __REG_2700G(0x0000217c) 109 #define DINTRCNT __REG_2700G(0x00002180) 110 #define DSIG __REG_2700G(0x00002184) 111 #define DMCTRL __REG_2700G(0x00002188) 112 #define CLIPCTRL __REG_2700G(0x0000218c) 113 #define SPOCTRL __REG_2700G(0x00002190) 114 #define SVCTRL __REG_2700G(0x00002194) 115 116 /* 0x0000_2198 */ 117 /* 0x0000_21A8 VSCOEFF[0:4] Video Scalar Vertical Coefficient [0:4] 4.14.5 */ 118 #define VSCOEFF0 __REG_2700G(0x00002198) 119 #define VSCOEFF1 __REG_2700G(0x0000219c) 120 #define VSCOEFF2 __REG_2700G(0x000021a0) 121 #define VSCOEFF3 __REG_2700G(0x000021a4) 122 #define VSCOEFF4 __REG_2700G(0x000021a8) 123 124 #define SHCTRL __REG_2700G(0x000021b0) 125 126 /* 0x0000_21B4 */ 127 /* 0x0000_21D4 HSCOEFF[0:8] Video Scalar Horizontal Coefficient [0:8] 4.14.7 */ 128 #define HSCOEFF0 __REG_2700G(0x000021b4) 129 #define HSCOEFF1 __REG_2700G(0x000021b8) 130 #define HSCOEFF2 __REG_2700G(0x000021bc) 131 #define HSCOEFF3 __REG_2700G(0x000021c0) 132 #define HSCOEFF4 __REG_2700G(0x000021c4) 133 #define HSCOEFF5 __REG_2700G(0x000021c8) 134 #define HSCOEFF6 __REG_2700G(0x000021cc) 135 #define HSCOEFF7 __REG_2700G(0x000021d0) 136 #define HSCOEFF8 __REG_2700G(0x000021d4) 137 138 #define SSSIZE __REG_2700G(0x000021D8) 139 140 /* 0x0000_2200 */ 141 /* 0x0000_2240 VIDGAM[0:16] Video Gamma LUT Index [0:16] 4.15.2 */ 142 #define VIDGAM0 __REG_2700G(0x00002200) 143 #define VIDGAM1 __REG_2700G(0x00002204) 144 #define VIDGAM2 __REG_2700G(0x00002208) 145 #define VIDGAM3 __REG_2700G(0x0000220c) 146 #define VIDGAM4 __REG_2700G(0x00002210) 147 #define VIDGAM5 __REG_2700G(0x00002214) 148 #define VIDGAM6 __REG_2700G(0x00002218) 149 #define VIDGAM7 __REG_2700G(0x0000221c) 150 #define VIDGAM8 __REG_2700G(0x00002220) 151 #define VIDGAM9 __REG_2700G(0x00002224) 152 #define VIDGAM10 __REG_2700G(0x00002228) 153 #define VIDGAM11 __REG_2700G(0x0000222c) 154 #define VIDGAM12 __REG_2700G(0x00002230) 155 #define VIDGAM13 __REG_2700G(0x00002234) 156 #define VIDGAM14 __REG_2700G(0x00002238) 157 #define VIDGAM15 __REG_2700G(0x0000223c) 158 #define VIDGAM16 __REG_2700G(0x00002240) 159 160 /* 0x0000_2250 */ 161 /* 0x0000_2290 GFXGAM[0:16] Graphics Gamma LUT Index [0:16] 4.15.3 */ 162 #define GFXGAM0 __REG_2700G(0x00002250) 163 #define GFXGAM1 __REG_2700G(0x00002254) 164 #define GFXGAM2 __REG_2700G(0x00002258) 165 #define GFXGAM3 __REG_2700G(0x0000225c) 166 #define GFXGAM4 __REG_2700G(0x00002260) 167 #define GFXGAM5 __REG_2700G(0x00002264) 168 #define GFXGAM6 __REG_2700G(0x00002268) 169 #define GFXGAM7 __REG_2700G(0x0000226c) 170 #define GFXGAM8 __REG_2700G(0x00002270) 171 #define GFXGAM9 __REG_2700G(0x00002274) 172 #define GFXGAM10 __REG_2700G(0x00002278) 173 #define GFXGAM11 __REG_2700G(0x0000227c) 174 #define GFXGAM12 __REG_2700G(0x00002280) 175 #define GFXGAM13 __REG_2700G(0x00002284) 176 #define GFXGAM14 __REG_2700G(0x00002288) 177 #define GFXGAM15 __REG_2700G(0x0000228c) 178 #define GFXGAM16 __REG_2700G(0x00002290) 179 180 #define DLSTS __REG_2700G(0x00002300) 181 #define DLLCTRL __REG_2700G(0x00002304) 182 #define DVLNUM __REG_2700G(0x00002308) 183 #define DUCTRL __REG_2700G(0x0000230c) 184 #define DVECTRL __REG_2700G(0x00002310) 185 #define DHDET __REG_2700G(0x00002314) 186 #define DVDET __REG_2700G(0x00002318) 187 #define DODMSK __REG_2700G(0x0000231c) 188 #define CSC01 __REG_2700G(0x00002330) 189 #define CSC02 __REG_2700G(0x00002334) 190 #define CSC03 __REG_2700G(0x00002338) 191 #define CSC04 __REG_2700G(0x0000233c) 192 #define CSC05 __REG_2700G(0x00002340) 193 194 #define FB_MEMORY_START __REG_2700G(0x00060000) 195 196 #endif /* __REGS_2700G_ */ 197
