1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6 * Copyright (C) 2009-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
8 * www.broadcom.com *
9 * *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
22
23 #if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
24 #define CONFIG_SCSI_LPFC_DEBUG_FS
25 #endif
26
27 #define LPFC_ACTIVE_MBOX_WAIT_CNT 100
28 #define LPFC_XRI_EXCH_BUSY_WAIT_TMO 10000
29 #define LPFC_XRI_EXCH_BUSY_WAIT_T1 10
30 #define LPFC_XRI_EXCH_BUSY_WAIT_T2 30000
31 #define LPFC_RPI_LOW_WATER_MARK 10
32
33 #define LPFC_UNREG_FCF 1
34 #define LPFC_SKIP_UNREG_FCF 0
35
36 /* Amount of time in seconds for waiting FCF rediscovery to complete */
37 #define LPFC_FCF_REDISCOVER_WAIT_TMO 2000 /* msec */
38
39 /* Number of SGL entries can be posted in a 4KB nonembedded mbox command */
40 #define LPFC_NEMBED_MBOX_SGL_CNT 254
41
42 /* Multi-queue arrangement for FCP EQ/CQ/WQ tuples */
43 #define LPFC_HBA_HDWQ_MIN 0
44 #define LPFC_HBA_HDWQ_MAX 128
45 #define LPFC_HBA_HDWQ_DEF 0
46
47 /* FCP MQ queue count limiting */
48 #define LPFC_FCP_MQ_THRESHOLD_MIN 0
49 #define LPFC_FCP_MQ_THRESHOLD_MAX 256
50 #define LPFC_FCP_MQ_THRESHOLD_DEF 8
51
52 /*
53 * Provide the default FCF Record attributes used by the driver
54 * when nonFIP mode is configured and there is no other default
55 * FCF Record attributes.
56 */
57 #define LPFC_FCOE_FCF_DEF_INDEX 0
58 #define LPFC_FCOE_FCF_GET_FIRST 0xFFFF
59 #define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF
60
61 #define LPFC_FCOE_NULL_VID 0xFFF
62 #define LPFC_FCOE_IGNORE_VID 0xFFFF
63
64 /* First 3 bytes of default FCF MAC is specified by FC_MAP */
65 #define LPFC_FCOE_FCF_MAC3 0xFF
66 #define LPFC_FCOE_FCF_MAC4 0xFF
67 #define LPFC_FCOE_FCF_MAC5 0xFE
68 #define LPFC_FCOE_FCF_MAP0 0x0E
69 #define LPFC_FCOE_FCF_MAP1 0xFC
70 #define LPFC_FCOE_FCF_MAP2 0x00
71 #define LPFC_FCOE_MAX_RCV_SIZE 0x800
72 #define LPFC_FCOE_FKA_ADV_PER 0
73 #define LPFC_FCOE_FIP_PRIORITY 0x80
74
75 #define sli4_sid_from_fc_hdr(fc_hdr) \
76 ((fc_hdr)->fh_s_id[0] << 16 | \
77 (fc_hdr)->fh_s_id[1] << 8 | \
78 (fc_hdr)->fh_s_id[2])
79
80 #define sli4_did_from_fc_hdr(fc_hdr) \
81 ((fc_hdr)->fh_d_id[0] << 16 | \
82 (fc_hdr)->fh_d_id[1] << 8 | \
83 (fc_hdr)->fh_d_id[2])
84
85 #define sli4_fctl_from_fc_hdr(fc_hdr) \
86 ((fc_hdr)->fh_f_ctl[0] << 16 | \
87 (fc_hdr)->fh_f_ctl[1] << 8 | \
88 (fc_hdr)->fh_f_ctl[2])
89
90 #define sli4_type_from_fc_hdr(fc_hdr) \
91 ((fc_hdr)->fh_type)
92
93 #define LPFC_FW_RESET_MAXIMUM_WAIT_10MS_CNT 12000
94
95 #define INT_FW_UPGRADE 0
96 #define RUN_FW_UPGRADE 1
97
98 enum lpfc_sli4_queue_type {
99 LPFC_EQ,
100 LPFC_GCQ,
101 LPFC_MCQ,
102 LPFC_WCQ,
103 LPFC_RCQ,
104 LPFC_MQ,
105 LPFC_WQ,
106 LPFC_HRQ,
107 LPFC_DRQ
108 };
109
110 /* The queue sub-type defines the functional purpose of the queue */
111 enum lpfc_sli4_queue_subtype {
112 LPFC_NONE,
113 LPFC_MBOX,
114 LPFC_IO,
115 LPFC_ELS,
116 LPFC_NVMET,
117 LPFC_NVME_LS,
118 LPFC_USOL
119 };
120
121 /* RQ buffer list */
122 struct lpfc_rqb {
123 uint16_t entry_count; /* Current number of RQ slots */
124 uint16_t buffer_count; /* Current number of buffers posted */
125 struct list_head rqb_buffer_list; /* buffers assigned to this HBQ */
126 /* Callback for HBQ buffer allocation */
127 struct rqb_dmabuf *(*rqb_alloc_buffer)(struct lpfc_hba *);
128 /* Callback for HBQ buffer free */
129 void (*rqb_free_buffer)(struct lpfc_hba *,
130 struct rqb_dmabuf *);
131 };
132
133 struct lpfc_queue {
134 struct list_head list;
135 struct list_head wq_list;
136 struct list_head wqfull_list;
137 enum lpfc_sli4_queue_type type;
138 enum lpfc_sli4_queue_subtype subtype;
139 struct lpfc_hba *phba;
140 struct list_head child_list;
141 struct list_head page_list;
142 struct list_head sgl_list;
143 struct list_head cpu_list;
144 uint32_t entry_count; /* Number of entries to support on the queue */
145 uint32_t entry_size; /* Size of each queue entry. */
146 uint32_t entry_cnt_per_pg;
147 uint32_t notify_interval; /* Queue Notification Interval
148 * For chip->host queues (EQ, CQ, RQ):
149 * specifies the interval (number of
150 * entries) where the doorbell is rung to
151 * notify the chip of entry consumption.
152 * For host->chip queues (WQ):
153 * specifies the interval (number of
154 * entries) where consumption CQE is
155 * requested to indicate WQ entries
156 * consumed by the chip.
157 * Not used on an MQ.
158 */
159 #define LPFC_EQ_NOTIFY_INTRVL 16
160 #define LPFC_CQ_NOTIFY_INTRVL 16
161 #define LPFC_WQ_NOTIFY_INTRVL 16
162 #define LPFC_RQ_NOTIFY_INTRVL 16
163 uint32_t max_proc_limit; /* Queue Processing Limit
164 * For chip->host queues (EQ, CQ):
165 * specifies the maximum number of
166 * entries to be consumed in one
167 * processing iteration sequence. Queue
168 * will be rearmed after each iteration.
169 * Not used on an MQ, RQ or WQ.
170 */
171 #define LPFC_EQ_MAX_PROC_LIMIT 256
172 #define LPFC_CQ_MIN_PROC_LIMIT 64
173 #define LPFC_CQ_MAX_PROC_LIMIT LPFC_CQE_EXP_COUNT // 4096
174 #define LPFC_CQ_DEF_MAX_PROC_LIMIT LPFC_CQE_DEF_COUNT // 1024
175 #define LPFC_CQ_MIN_THRESHOLD_TO_POLL 64
176 #define LPFC_CQ_MAX_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT
177 #define LPFC_CQ_DEF_THRESHOLD_TO_POLL LPFC_CQ_DEF_MAX_PROC_LIMIT
178 uint32_t queue_claimed; /* indicates queue is being processed */
179 uint32_t queue_id; /* Queue ID assigned by the hardware */
180 uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */
181 uint32_t host_index; /* The host's index for putting or getting */
182 uint32_t hba_index; /* The last known hba index for get or put */
183 uint32_t q_mode;
184
185 struct lpfc_sli_ring *pring; /* ptr to io ring associated with q */
186 struct lpfc_rqb *rqbp; /* ptr to RQ buffers */
187
188 uint16_t page_count; /* Number of pages allocated for this queue */
189 uint16_t page_size; /* size of page allocated for this queue */
190 #define LPFC_EXPANDED_PAGE_SIZE 16384
191 #define LPFC_DEFAULT_PAGE_SIZE 4096
192 uint16_t chann; /* Hardware Queue association WQ/CQ */
193 /* CPU affinity for EQ */
194 #define LPFC_FIND_BY_EQ 0
195 #define LPFC_FIND_BY_HDWQ 1
196 uint8_t db_format;
197 #define LPFC_DB_RING_FORMAT 0x01
198 #define LPFC_DB_LIST_FORMAT 0x02
199 uint8_t q_flag;
200 #define HBA_NVMET_WQFULL 0x1 /* We hit WQ Full condition for NVMET */
201 #define HBA_NVMET_CQ_NOTIFY 0x1 /* LPFC_NVMET_CQ_NOTIFY CQEs this EQE */
202 #define LPFC_NVMET_CQ_NOTIFY 4
203 void __iomem *db_regaddr;
204 uint16_t dpp_enable;
205 uint16_t dpp_id;
206 void __iomem *dpp_regaddr;
207
208 /* For q stats */
209 uint32_t q_cnt_1;
210 uint32_t q_cnt_2;
211 uint32_t q_cnt_3;
212 uint64_t q_cnt_4;
213 /* defines for EQ stats */
214 #define EQ_max_eqe q_cnt_1
215 #define EQ_no_entry q_cnt_2
216 #define EQ_cqe_cnt q_cnt_3
217 #define EQ_processed q_cnt_4
218
219 /* defines for CQ stats */
220 #define CQ_mbox q_cnt_1
221 #define CQ_max_cqe q_cnt_1
222 #define CQ_release_wqe q_cnt_2
223 #define CQ_xri_aborted q_cnt_3
224 #define CQ_wq q_cnt_4
225
226 /* defines for WQ stats */
227 #define WQ_overflow q_cnt_1
228 #define WQ_posted q_cnt_4
229
230 /* defines for RQ stats */
231 #define RQ_no_posted_buf q_cnt_1
232 #define RQ_no_buf_found q_cnt_2
233 #define RQ_buf_posted q_cnt_3
234 #define RQ_rcv_buf q_cnt_4
235
236 struct work_struct irqwork;
237 struct work_struct spwork;
238 struct delayed_work sched_irqwork;
239 struct delayed_work sched_spwork;
240
241 uint64_t isr_timestamp;
242 uint16_t hdwq;
243 uint16_t last_cpu; /* most recent cpu */
244 uint8_t qe_valid;
245 struct lpfc_queue *assoc_qp;
246 void **q_pgs; /* array to index entries per page */
247 };
248
249 struct lpfc_sli4_link {
250 uint32_t speed;
251 uint8_t duplex;
252 uint8_t status;
253 uint8_t type;
254 uint8_t number;
255 uint8_t fault;
256 uint32_t logical_speed;
257 uint16_t topology;
258 };
259
260 struct lpfc_fcf_rec {
261 uint8_t fabric_name[8];
262 uint8_t switch_name[8];
263 uint8_t mac_addr[6];
264 uint16_t fcf_indx;
265 uint32_t priority;
266 uint16_t vlan_id;
267 uint32_t addr_mode;
268 uint32_t flag;
269 #define BOOT_ENABLE 0x01
270 #define RECORD_VALID 0x02
271 };
272
273 struct lpfc_fcf_pri_rec {
274 uint16_t fcf_index;
275 #define LPFC_FCF_ON_PRI_LIST 0x0001
276 #define LPFC_FCF_FLOGI_FAILED 0x0002
277 uint16_t flag;
278 uint32_t priority;
279 };
280
281 struct lpfc_fcf_pri {
282 struct list_head list;
283 struct lpfc_fcf_pri_rec fcf_rec;
284 };
285
286 /*
287 * Maximum FCF table index, it is for driver internal book keeping, it
288 * just needs to be no less than the supported HBA's FCF table size.
289 */
290 #define LPFC_SLI4_FCF_TBL_INDX_MAX 32
291
292 struct lpfc_fcf {
293 uint16_t fcfi;
294 uint32_t fcf_flag;
295 #define FCF_AVAILABLE 0x01 /* FCF available for discovery */
296 #define FCF_REGISTERED 0x02 /* FCF registered with FW */
297 #define FCF_SCAN_DONE 0x04 /* FCF table scan done */
298 #define FCF_IN_USE 0x08 /* Atleast one discovery completed */
299 #define FCF_INIT_DISC 0x10 /* Initial FCF discovery */
300 #define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */
301 #define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */
302 #define FCF_DISCOVERY (FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC)
303 #define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */
304 #define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */
305 #define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */
306 #define FCF_REDISC_PROG (FCF_REDISC_PEND | FCF_REDISC_EVT)
307 uint16_t fcf_redisc_attempted;
308 uint32_t addr_mode;
309 uint32_t eligible_fcf_cnt;
310 struct lpfc_fcf_rec current_rec;
311 struct lpfc_fcf_rec failover_rec;
312 struct list_head fcf_pri_list;
313 struct lpfc_fcf_pri fcf_pri[LPFC_SLI4_FCF_TBL_INDX_MAX];
314 uint32_t current_fcf_scan_pri;
315 struct timer_list redisc_wait;
316 unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */
317 };
318
319
320 #define LPFC_REGION23_SIGNATURE "RG23"
321 #define LPFC_REGION23_VERSION 1
322 #define LPFC_REGION23_LAST_REC 0xff
323 #define DRIVER_SPECIFIC_TYPE 0xA2
324 #define LINUX_DRIVER_ID 0x20
325 #define PORT_STE_TYPE 0x1
326
327 struct lpfc_fip_param_hdr {
328 uint8_t type;
329 #define FCOE_PARAM_TYPE 0xA0
330 uint8_t length;
331 #define FCOE_PARAM_LENGTH 2
332 uint8_t parm_version;
333 #define FIPP_VERSION 0x01
334 uint8_t parm_flags;
335 #define lpfc_fip_param_hdr_fipp_mode_SHIFT 6
336 #define lpfc_fip_param_hdr_fipp_mode_MASK 0x3
337 #define lpfc_fip_param_hdr_fipp_mode_WORD parm_flags
338 #define FIPP_MODE_ON 0x1
339 #define FIPP_MODE_OFF 0x0
340 #define FIPP_VLAN_VALID 0x1
341 };
342
343 struct lpfc_fcoe_params {
344 uint8_t fc_map[3];
345 uint8_t reserved1;
346 uint16_t vlan_tag;
347 uint8_t reserved[2];
348 };
349
350 struct lpfc_fcf_conn_hdr {
351 uint8_t type;
352 #define FCOE_CONN_TBL_TYPE 0xA1
353 uint8_t length; /* words */
354 uint8_t reserved[2];
355 };
356
357 struct lpfc_fcf_conn_rec {
358 uint16_t flags;
359 #define FCFCNCT_VALID 0x0001
360 #define FCFCNCT_BOOT 0x0002
361 #define FCFCNCT_PRIMARY 0x0004 /* if not set, Secondary */
362 #define FCFCNCT_FBNM_VALID 0x0008
363 #define FCFCNCT_SWNM_VALID 0x0010
364 #define FCFCNCT_VLAN_VALID 0x0020
365 #define FCFCNCT_AM_VALID 0x0040
366 #define FCFCNCT_AM_PREFERRED 0x0080 /* if not set, AM Required */
367 #define FCFCNCT_AM_SPMA 0x0100 /* if not set, FPMA */
368
369 uint16_t vlan_tag;
370 uint8_t fabric_name[8];
371 uint8_t switch_name[8];
372 };
373
374 struct lpfc_fcf_conn_entry {
375 struct list_head list;
376 struct lpfc_fcf_conn_rec conn_rec;
377 };
378
379 /*
380 * Define the host's bootstrap mailbox. This structure contains
381 * the member attributes needed to create, use, and destroy the
382 * bootstrap mailbox region.
383 *
384 * The macro definitions for the bmbx data structure are defined
385 * in lpfc_hw4.h with the register definition.
386 */
387 struct lpfc_bmbx {
388 struct lpfc_dmabuf *dmabuf;
389 struct dma_address dma_address;
390 void *avirt;
391 dma_addr_t aphys;
392 uint32_t bmbx_size;
393 };
394
395 #define LPFC_EQE_SIZE LPFC_EQE_SIZE_4
396
397 #define LPFC_EQE_SIZE_4B 4
398 #define LPFC_EQE_SIZE_16B 16
399 #define LPFC_CQE_SIZE 16
400 #define LPFC_WQE_SIZE 64
401 #define LPFC_WQE128_SIZE 128
402 #define LPFC_MQE_SIZE 256
403 #define LPFC_RQE_SIZE 8
404
405 #define LPFC_EQE_DEF_COUNT 1024
406 #define LPFC_CQE_DEF_COUNT 1024
407 #define LPFC_CQE_EXP_COUNT 4096
408 #define LPFC_WQE_DEF_COUNT 256
409 #define LPFC_WQE_EXP_COUNT 1024
410 #define LPFC_MQE_DEF_COUNT 16
411 #define LPFC_RQE_DEF_COUNT 512
412
413 #define LPFC_QUEUE_NOARM false
414 #define LPFC_QUEUE_REARM true
415
416
417 /*
418 * SLI4 CT field defines
419 */
420 #define SLI4_CT_RPI 0
421 #define SLI4_CT_VPI 1
422 #define SLI4_CT_VFI 2
423 #define SLI4_CT_FCFI 3
424
425 /*
426 * SLI4 specific data structures
427 */
428 struct lpfc_max_cfg_param {
429 uint16_t max_xri;
430 uint16_t xri_base;
431 uint16_t xri_used;
432 uint16_t max_rpi;
433 uint16_t rpi_base;
434 uint16_t rpi_used;
435 uint16_t max_vpi;
436 uint16_t vpi_base;
437 uint16_t vpi_used;
438 uint16_t max_vfi;
439 uint16_t vfi_base;
440 uint16_t vfi_used;
441 uint16_t max_fcfi;
442 uint16_t fcfi_used;
443 uint16_t max_eq;
444 uint16_t max_rq;
445 uint16_t max_cq;
446 uint16_t max_wq;
447 };
448
449 struct lpfc_hba;
450 /* SLI4 HBA multi-fcp queue handler struct */
451 #define LPFC_SLI4_HANDLER_NAME_SZ 16
452 struct lpfc_hba_eq_hdl {
453 uint32_t idx;
454 char handler_name[LPFC_SLI4_HANDLER_NAME_SZ];
455 struct lpfc_hba *phba;
456 struct lpfc_queue *eq;
457 };
458
459 /*BB Credit recovery value*/
460 struct lpfc_bbscn_params {
461 uint32_t word0;
462 #define lpfc_bbscn_min_SHIFT 0
463 #define lpfc_bbscn_min_MASK 0x0000000F
464 #define lpfc_bbscn_min_WORD word0
465 #define lpfc_bbscn_max_SHIFT 4
466 #define lpfc_bbscn_max_MASK 0x0000000F
467 #define lpfc_bbscn_max_WORD word0
468 #define lpfc_bbscn_def_SHIFT 8
469 #define lpfc_bbscn_def_MASK 0x0000000F
470 #define lpfc_bbscn_def_WORD word0
471 };
472
473 /* Port Capabilities for SLI4 Parameters */
474 struct lpfc_pc_sli4_params {
475 uint32_t supported;
476 uint32_t if_type;
477 uint32_t sli_rev;
478 uint32_t sli_family;
479 uint32_t featurelevel_1;
480 uint32_t featurelevel_2;
481 uint32_t proto_types;
482 #define LPFC_SLI4_PROTO_FCOE 0x0000001
483 #define LPFC_SLI4_PROTO_FC 0x0000002
484 #define LPFC_SLI4_PROTO_NIC 0x0000004
485 #define LPFC_SLI4_PROTO_ISCSI 0x0000008
486 #define LPFC_SLI4_PROTO_RDMA 0x0000010
487 uint32_t sge_supp_len;
488 uint32_t if_page_sz;
489 uint32_t rq_db_window;
490 uint32_t loopbk_scope;
491 uint32_t oas_supported;
492 uint32_t eq_pages_max;
493 uint32_t eqe_size;
494 uint32_t cq_pages_max;
495 uint32_t cqe_size;
496 uint32_t mq_pages_max;
497 uint32_t mqe_size;
498 uint32_t mq_elem_cnt;
499 uint32_t wq_pages_max;
500 uint32_t wqe_size;
501 uint32_t rq_pages_max;
502 uint32_t rqe_size;
503 uint32_t hdr_pages_max;
504 uint32_t hdr_size;
505 uint32_t hdr_pp_align;
506 uint32_t sgl_pages_max;
507 uint32_t sgl_pp_align;
508 uint8_t cqv;
509 uint8_t mqv;
510 uint8_t wqv;
511 uint8_t rqv;
512 uint8_t eqav;
513 uint8_t cqav;
514 uint8_t wqsize;
515 uint8_t bv1s;
516 #define LPFC_WQ_SZ64_SUPPORT 1
517 #define LPFC_WQ_SZ128_SUPPORT 2
518 uint8_t wqpcnt;
519 uint8_t nvme;
520 };
521
522 #define LPFC_CQ_4K_PAGE_SZ 0x1
523 #define LPFC_CQ_16K_PAGE_SZ 0x4
524 #define LPFC_WQ_4K_PAGE_SZ 0x1
525 #define LPFC_WQ_16K_PAGE_SZ 0x4
526
527 struct lpfc_iov {
528 uint32_t pf_number;
529 uint32_t vf_number;
530 };
531
532 struct lpfc_sli4_lnk_info {
533 uint8_t lnk_dv;
534 #define LPFC_LNK_DAT_INVAL 0
535 #define LPFC_LNK_DAT_VAL 1
536 uint8_t lnk_tp;
537 #define LPFC_LNK_GE 0x0 /* FCoE */
538 #define LPFC_LNK_FC 0x1 /* FC */
539 #define LPFC_LNK_FC_TRUNKED 0x2 /* FC_Trunked */
540 uint8_t lnk_no;
541 uint8_t optic_state;
542 };
543
544 #define LPFC_SLI4_HANDLER_CNT (LPFC_HBA_IO_CHAN_MAX+ \
545 LPFC_FOF_IO_CHAN_NUM)
546
547 /* Used for IRQ vector to CPU mapping */
548 struct lpfc_vector_map_info {
549 uint16_t phys_id;
550 uint16_t core_id;
551 uint16_t irq;
552 uint16_t eq;
553 uint16_t hdwq;
554 uint16_t flag;
555 #define LPFC_CPU_MAP_HYPER 0x1
556 #define LPFC_CPU_MAP_UNASSIGN 0x2
557 #define LPFC_CPU_FIRST_IRQ 0x4
558 };
559 #define LPFC_VECTOR_MAP_EMPTY 0xffff
560
561 /* Multi-XRI pool */
562 #define XRI_BATCH 8
563
564 struct lpfc_pbl_pool {
565 struct list_head list;
566 u32 count;
567 spinlock_t lock; /* lock for pbl_pool*/
568 };
569
570 struct lpfc_pvt_pool {
571 u32 low_watermark;
572 u32 high_watermark;
573
574 struct list_head list;
575 u32 count;
576 spinlock_t lock; /* lock for pvt_pool */
577 };
578
579 struct lpfc_multixri_pool {
580 u32 xri_limit;
581
582 /* Starting point when searching a pbl_pool with round-robin method */
583 u32 rrb_next_hwqid;
584
585 /* Used by lpfc_adjust_pvt_pool_count.
586 * io_req_count is incremented by 1 during IO submission. The heartbeat
587 * handler uses these two variables to determine if pvt_pool is idle or
588 * busy.
589 */
590 u32 prev_io_req_count;
591 u32 io_req_count;
592
593 /* statistics */
594 u32 pbl_empty_count;
595 #ifdef LPFC_MXP_STAT
596 u32 above_limit_count;
597 u32 below_limit_count;
598 u32 local_pbl_hit_count;
599 u32 other_pbl_hit_count;
600 u32 stat_max_hwm;
601
602 #define LPFC_MXP_SNAPSHOT_TAKEN 3 /* snapshot is taken at 3rd heartbeats */
603 u32 stat_pbl_count;
604 u32 stat_pvt_count;
605 u32 stat_busy_count;
606 u32 stat_snapshot_taken;
607 #endif
608
609 /* TODO: Separate pvt_pool into get and put list */
610 struct lpfc_pbl_pool pbl_pool; /* Public free XRI pool */
611 struct lpfc_pvt_pool pvt_pool; /* Private free XRI pool */
612 };
613
614 struct lpfc_fc4_ctrl_stat {
615 u32 input_requests;
616 u32 output_requests;
617 u32 control_requests;
618 u32 io_cmpls;
619 };
620
621 #ifdef LPFC_HDWQ_LOCK_STAT
622 struct lpfc_lock_stat {
623 uint32_t alloc_xri_get;
624 uint32_t alloc_xri_put;
625 uint32_t free_xri;
626 uint32_t wq_access;
627 uint32_t alloc_pvt_pool;
628 uint32_t mv_from_pvt_pool;
629 uint32_t mv_to_pub_pool;
630 uint32_t mv_to_pvt_pool;
631 uint32_t free_pub_pool;
632 uint32_t free_pvt_pool;
633 };
634 #endif
635
636 struct lpfc_eq_intr_info {
637 struct list_head list;
638 uint32_t icnt;
639 };
640
641 /* SLI4 HBA data structure entries */
642 struct lpfc_sli4_hdw_queue {
643 /* Pointers to the constructed SLI4 queues */
644 struct lpfc_queue *hba_eq; /* Event queues for HBA */
645 struct lpfc_queue *io_cq; /* Fast-path FCP & NVME compl queue */
646 struct lpfc_queue *io_wq; /* Fast-path FCP & NVME work queue */
647 uint16_t io_cq_map;
648
649 /* Keep track of IO buffers for this hardware queue */
650 spinlock_t io_buf_list_get_lock; /* Common buf alloc list lock */
651 struct list_head lpfc_io_buf_list_get;
652 spinlock_t io_buf_list_put_lock; /* Common buf free list lock */
653 struct list_head lpfc_io_buf_list_put;
654 spinlock_t abts_io_buf_list_lock; /* list of aborted IOs */
655 struct list_head lpfc_abts_io_buf_list;
656 uint32_t total_io_bufs;
657 uint32_t get_io_bufs;
658 uint32_t put_io_bufs;
659 uint32_t empty_io_bufs;
660 uint32_t abts_scsi_io_bufs;
661 uint32_t abts_nvme_io_bufs;
662
663 /* Multi-XRI pool per HWQ */
664 struct lpfc_multixri_pool *p_multixri_pool;
665
666 /* FC-4 Stats counters */
667 struct lpfc_fc4_ctrl_stat nvme_cstat;
668 struct lpfc_fc4_ctrl_stat scsi_cstat;
669 #ifdef LPFC_HDWQ_LOCK_STAT
670 struct lpfc_lock_stat lock_conflict;
671 #endif
672
673 #ifdef CONFIG_SCSI_LPFC_DEBUG_FS
674 #define LPFC_CHECK_CPU_CNT 128
675 uint32_t cpucheck_rcv_io[LPFC_CHECK_CPU_CNT];
676 uint32_t cpucheck_xmt_io[LPFC_CHECK_CPU_CNT];
677 uint32_t cpucheck_cmpl_io[LPFC_CHECK_CPU_CNT];
678 #endif
679
680 /* Per HDWQ pool resources */
681 struct list_head sgl_list;
682 struct list_head cmd_rsp_buf_list;
683
684 /* Lock for syncing Per HDWQ pool resources */
685 spinlock_t hdwq_lock;
686 };
687
688 #ifdef LPFC_HDWQ_LOCK_STAT
689 /* compile time trylock stats */
690 #define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \
691 { \
692 int only_once = 1; \
693 while (spin_trylock_irqsave(lock, flag) == 0) { \
694 if (only_once) { \
695 only_once = 0; \
696 qp->lock_conflict.lstat++; \
697 } \
698 } \
699 }
700 #define lpfc_qp_spin_lock(lock, qp, lstat) \
701 { \
702 int only_once = 1; \
703 while (spin_trylock(lock) == 0) { \
704 if (only_once) { \
705 only_once = 0; \
706 qp->lock_conflict.lstat++; \
707 } \
708 } \
709 }
710 #else
711 #define lpfc_qp_spin_lock_irqsave(lock, flag, qp, lstat) \
712 spin_lock_irqsave(lock, flag)
713 #define lpfc_qp_spin_lock(lock, qp, lstat) spin_lock(lock)
714 #endif
715
716 struct lpfc_sli4_hba {
717 void __iomem *conf_regs_memmap_p; /* Kernel memory mapped address for
718 * config space registers
719 */
720 void __iomem *ctrl_regs_memmap_p; /* Kernel memory mapped address for
721 * control registers
722 */
723 void __iomem *drbl_regs_memmap_p; /* Kernel memory mapped address for
724 * doorbell registers
725 */
726 void __iomem *dpp_regs_memmap_p; /* Kernel memory mapped address for
727 * dpp registers
728 */
729 union {
730 struct {
731 /* IF Type 0, BAR 0 PCI cfg space reg mem map */
732 void __iomem *UERRLOregaddr;
733 void __iomem *UERRHIregaddr;
734 void __iomem *UEMASKLOregaddr;
735 void __iomem *UEMASKHIregaddr;
736 } if_type0;
737 struct {
738 /* IF Type 2, BAR 0 PCI cfg space reg mem map. */
739 void __iomem *STATUSregaddr;
740 void __iomem *CTRLregaddr;
741 void __iomem *ERR1regaddr;
742 #define SLIPORT_ERR1_REG_ERR_CODE_1 0x1
743 #define SLIPORT_ERR1_REG_ERR_CODE_2 0x2
744 void __iomem *ERR2regaddr;
745 #define SLIPORT_ERR2_REG_FW_RESTART 0x0
746 #define SLIPORT_ERR2_REG_FUNC_PROVISON 0x1
747 #define SLIPORT_ERR2_REG_FORCED_DUMP 0x2
748 #define SLIPORT_ERR2_REG_FAILURE_EQ 0x3
749 #define SLIPORT_ERR2_REG_FAILURE_CQ 0x4
750 #define SLIPORT_ERR2_REG_FAILURE_BUS 0x5
751 #define SLIPORT_ERR2_REG_FAILURE_RQ 0x6
752 void __iomem *EQDregaddr;
753 } if_type2;
754 } u;
755
756 /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */
757 void __iomem *PSMPHRregaddr;
758
759 /* Well-known SLI INTF register memory map. */
760 void __iomem *SLIINTFregaddr;
761
762 /* IF type 0, BAR 1 function CSR register memory map */
763 void __iomem *ISRregaddr; /* HST_ISR register */
764 void __iomem *IMRregaddr; /* HST_IMR register */
765 void __iomem *ISCRregaddr; /* HST_ISCR register */
766 /* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */
767 void __iomem *RQDBregaddr; /* RQ_DOORBELL register */
768 void __iomem *WQDBregaddr; /* WQ_DOORBELL register */
769 void __iomem *CQDBregaddr; /* CQ_DOORBELL register */
770 void __iomem *EQDBregaddr; /* EQ_DOORBELL register */
771 void __iomem *MQDBregaddr; /* MQ_DOORBELL register */
772 void __iomem *BMBXregaddr; /* BootStrap MBX register */
773
774 uint32_t ue_mask_lo;
775 uint32_t ue_mask_hi;
776 uint32_t ue_to_sr;
777 uint32_t ue_to_rp;
778 struct lpfc_register sli_intf;
779 struct lpfc_pc_sli4_params pc_sli4_params;
780 struct lpfc_bbscn_params bbscn_params;
781 struct lpfc_hba_eq_hdl *hba_eq_hdl; /* HBA per-WQ handle */
782
783 void (*sli4_eq_clr_intr)(struct lpfc_queue *q);
784 void (*sli4_write_eq_db)(struct lpfc_hba *phba, struct lpfc_queue *eq,
785 uint32_t count, bool arm);
786 void (*sli4_write_cq_db)(struct lpfc_hba *phba, struct lpfc_queue *cq,
787 uint32_t count, bool arm);
788
789 /* Pointers to the constructed SLI4 queues */
790 struct lpfc_sli4_hdw_queue *hdwq;
791 struct list_head lpfc_wq_list;
792
793 /* Pointers to the constructed SLI4 queues for NVMET */
794 struct lpfc_queue **nvmet_cqset; /* Fast-path NVMET CQ Set queues */
795 struct lpfc_queue **nvmet_mrq_hdr; /* Fast-path NVMET hdr MRQs */
796 struct lpfc_queue **nvmet_mrq_data; /* Fast-path NVMET data MRQs */
797
798 struct lpfc_queue *mbx_cq; /* Slow-path mailbox complete queue */
799 struct lpfc_queue *els_cq; /* Slow-path ELS response complete queue */
800 struct lpfc_queue *nvmels_cq; /* NVME LS complete queue */
801 struct lpfc_queue *mbx_wq; /* Slow-path MBOX work queue */
802 struct lpfc_queue *els_wq; /* Slow-path ELS work queue */
803 struct lpfc_queue *nvmels_wq; /* NVME LS work queue */
804 struct lpfc_queue *hdr_rq; /* Slow-path Header Receive queue */
805 struct lpfc_queue *dat_rq; /* Slow-path Data Receive queue */
806
807 struct lpfc_name wwnn;
808 struct lpfc_name wwpn;
809
810 uint32_t fw_func_mode; /* FW function protocol mode */
811 uint32_t ulp0_mode; /* ULP0 protocol mode */
812 uint32_t ulp1_mode; /* ULP1 protocol mode */
813
814 /* Optimized Access Storage specific queues/structures */
815 uint64_t oas_next_lun;
816 uint8_t oas_next_tgt_wwpn[8];
817 uint8_t oas_next_vpt_wwpn[8];
818
819 /* Setup information for various queue parameters */
820 int eq_esize;
821 int eq_ecount;
822 int cq_esize;
823 int cq_ecount;
824 int wq_esize;
825 int wq_ecount;
826 int mq_esize;
827 int mq_ecount;
828 int rq_esize;
829 int rq_ecount;
830 #define LPFC_SP_EQ_MAX_INTR_SEC 10000
831 #define LPFC_FP_EQ_MAX_INTR_SEC 10000
832
833 uint32_t intr_enable;
834 struct lpfc_bmbx bmbx;
835 struct lpfc_max_cfg_param max_cfg_param;
836 uint16_t extents_in_use; /* must allocate resource extents. */
837 uint16_t rpi_hdrs_in_use; /* must post rpi hdrs if set. */
838 uint16_t next_xri; /* last_xri - max_cfg_param.xri_base = used */
839 uint16_t next_rpi;
840 uint16_t io_xri_max;
841 uint16_t io_xri_cnt;
842 uint16_t io_xri_start;
843 uint16_t els_xri_cnt;
844 uint16_t nvmet_xri_cnt;
845 uint16_t nvmet_io_wait_cnt;
846 uint16_t nvmet_io_wait_total;
847 uint16_t cq_max;
848 struct lpfc_queue **cq_lookup;
849 struct list_head lpfc_els_sgl_list;
850 struct list_head lpfc_abts_els_sgl_list;
851 spinlock_t abts_io_buf_list_lock; /* list of aborted SCSI IOs */
852 struct list_head lpfc_abts_io_buf_list;
853 struct list_head lpfc_nvmet_sgl_list;
854 spinlock_t abts_nvmet_buf_list_lock; /* list of aborted NVMET IOs */
855 struct list_head lpfc_abts_nvmet_ctx_list;
856 spinlock_t t_active_list_lock; /* list of active NVMET IOs */
857 struct list_head t_active_ctx_list;
858 struct list_head lpfc_nvmet_io_wait_list;
859 struct lpfc_nvmet_ctx_info *nvmet_ctx_info;
860 struct lpfc_sglq **lpfc_sglq_active_list;
861 struct list_head lpfc_rpi_hdr_list;
862 unsigned long *rpi_bmask;
863 uint16_t *rpi_ids;
864 uint16_t rpi_count;
865 struct list_head lpfc_rpi_blk_list;
866 unsigned long *xri_bmask;
867 uint16_t *xri_ids;
868 struct list_head lpfc_xri_blk_list;
869 unsigned long *vfi_bmask;
870 uint16_t *vfi_ids;
871 uint16_t vfi_count;
872 struct list_head lpfc_vfi_blk_list;
873 struct lpfc_sli4_flags sli4_flags;
874 struct list_head sp_queue_event;
875 struct list_head sp_cqe_event_pool;
876 struct list_head sp_asynce_work_queue;
877 struct list_head sp_fcp_xri_aborted_work_queue;
878 struct list_head sp_els_xri_aborted_work_queue;
879 struct list_head sp_unsol_work_queue;
880 struct lpfc_sli4_link link_state;
881 struct lpfc_sli4_lnk_info lnk_info;
882 uint32_t pport_name_sta;
883 #define LPFC_SLI4_PPNAME_NON 0
884 #define LPFC_SLI4_PPNAME_GET 1
885 struct lpfc_iov iov;
886 spinlock_t sgl_list_lock; /* list of aborted els IOs */
887 spinlock_t nvmet_io_wait_lock; /* IOs waiting for ctx resources */
888 uint32_t physical_port;
889
890 /* CPU to vector mapping information */
891 struct lpfc_vector_map_info *cpu_map;
892 uint16_t num_possible_cpu;
893 uint16_t num_present_cpu;
894 uint16_t curr_disp_cpu;
895 struct lpfc_eq_intr_info __percpu *eq_info;
896 uint32_t conf_trunk;
897 #define lpfc_conf_trunk_port0_WORD conf_trunk
898 #define lpfc_conf_trunk_port0_SHIFT 0
899 #define lpfc_conf_trunk_port0_MASK 0x1
900 #define lpfc_conf_trunk_port1_WORD conf_trunk
901 #define lpfc_conf_trunk_port1_SHIFT 1
902 #define lpfc_conf_trunk_port1_MASK 0x1
903 #define lpfc_conf_trunk_port2_WORD conf_trunk
904 #define lpfc_conf_trunk_port2_SHIFT 2
905 #define lpfc_conf_trunk_port2_MASK 0x1
906 #define lpfc_conf_trunk_port3_WORD conf_trunk
907 #define lpfc_conf_trunk_port3_SHIFT 3
908 #define lpfc_conf_trunk_port3_MASK 0x1
909 #define lpfc_conf_trunk_port0_nd_WORD conf_trunk
910 #define lpfc_conf_trunk_port0_nd_SHIFT 4
911 #define lpfc_conf_trunk_port0_nd_MASK 0x1
912 #define lpfc_conf_trunk_port1_nd_WORD conf_trunk
913 #define lpfc_conf_trunk_port1_nd_SHIFT 5
914 #define lpfc_conf_trunk_port1_nd_MASK 0x1
915 #define lpfc_conf_trunk_port2_nd_WORD conf_trunk
916 #define lpfc_conf_trunk_port2_nd_SHIFT 6
917 #define lpfc_conf_trunk_port2_nd_MASK 0x1
918 #define lpfc_conf_trunk_port3_nd_WORD conf_trunk
919 #define lpfc_conf_trunk_port3_nd_SHIFT 7
920 #define lpfc_conf_trunk_port3_nd_MASK 0x1
921 };
922
923 enum lpfc_sge_type {
924 GEN_BUFF_TYPE,
925 SCSI_BUFF_TYPE,
926 NVMET_BUFF_TYPE
927 };
928
929 enum lpfc_sgl_state {
930 SGL_FREED,
931 SGL_ALLOCATED,
932 SGL_XRI_ABORTED
933 };
934
935 struct lpfc_sglq {
936 /* lpfc_sglqs are used in double linked lists */
937 struct list_head list;
938 struct list_head clist;
939 enum lpfc_sge_type buff_type; /* is this a scsi sgl */
940 enum lpfc_sgl_state state;
941 struct lpfc_nodelist *ndlp; /* ndlp associated with IO */
942 uint16_t iotag; /* pre-assigned IO tag */
943 uint16_t sli4_lxritag; /* logical pre-assigned xri. */
944 uint16_t sli4_xritag; /* pre-assigned XRI, (OXID) tag. */
945 struct sli4_sge *sgl; /* pre-assigned SGL */
946 void *virt; /* virtual address. */
947 dma_addr_t phys; /* physical address */
948 };
949
950 struct lpfc_rpi_hdr {
951 struct list_head list;
952 uint32_t len;
953 struct lpfc_dmabuf *dmabuf;
954 uint32_t page_count;
955 uint32_t start_rpi;
956 uint16_t next_rpi;
957 };
958
959 struct lpfc_rsrc_blks {
960 struct list_head list;
961 uint16_t rsrc_start;
962 uint16_t rsrc_size;
963 uint16_t rsrc_used;
964 };
965
966 struct lpfc_rdp_context {
967 struct lpfc_nodelist *ndlp;
968 uint16_t ox_id;
969 uint16_t rx_id;
970 READ_LNK_VAR link_stat;
971 uint8_t page_a0[DMP_SFF_PAGE_A0_SIZE];
972 uint8_t page_a2[DMP_SFF_PAGE_A2_SIZE];
973 void (*cmpl)(struct lpfc_hba *, struct lpfc_rdp_context*, int);
974 };
975
976 struct lpfc_lcb_context {
977 uint8_t sub_command;
978 uint8_t type;
979 uint8_t capability;
980 uint8_t frequency;
981 uint16_t duration;
982 uint16_t ox_id;
983 uint16_t rx_id;
984 struct lpfc_nodelist *ndlp;
985 };
986
987
988 /*
989 * SLI4 specific function prototypes
990 */
991 int lpfc_pci_function_reset(struct lpfc_hba *);
992 int lpfc_sli4_pdev_status_reg_wait(struct lpfc_hba *);
993 int lpfc_sli4_hba_setup(struct lpfc_hba *);
994 int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t,
995 uint8_t, uint32_t, bool);
996 void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *);
997 void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t);
998 void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t,
999 struct lpfc_mbx_sge *);
1000 int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *,
1001 uint16_t);
1002
1003 void lpfc_sli4_hba_reset(struct lpfc_hba *);
1004 struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *phba,
1005 uint32_t page_size,
1006 uint32_t entry_size,
1007 uint32_t entry_count, int cpu);
1008 void lpfc_sli4_queue_free(struct lpfc_queue *);
1009 int lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint32_t);
1010 void lpfc_modify_hba_eq_delay(struct lpfc_hba *phba, uint32_t startq,
1011 uint32_t numq, uint32_t usdelay);
1012 int lpfc_cq_create(struct lpfc_hba *, struct lpfc_queue *,
1013 struct lpfc_queue *, uint32_t, uint32_t);
1014 int lpfc_cq_create_set(struct lpfc_hba *phba, struct lpfc_queue **cqp,
1015 struct lpfc_sli4_hdw_queue *hdwq, uint32_t type,
1016 uint32_t subtype);
1017 int32_t lpfc_mq_create(struct lpfc_hba *, struct lpfc_queue *,
1018 struct lpfc_queue *, uint32_t);
1019 int lpfc_wq_create(struct lpfc_hba *, struct lpfc_queue *,
1020 struct lpfc_queue *, uint32_t);
1021 int lpfc_rq_create(struct lpfc_hba *, struct lpfc_queue *,
1022 struct lpfc_queue *, struct lpfc_queue *, uint32_t);
1023 int lpfc_mrq_create(struct lpfc_hba *phba, struct lpfc_queue **hrqp,
1024 struct lpfc_queue **drqp, struct lpfc_queue **cqp,
1025 uint32_t subtype);
1026 int lpfc_eq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1027 int lpfc_cq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1028 int lpfc_mq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1029 int lpfc_wq_destroy(struct lpfc_hba *, struct lpfc_queue *);
1030 int lpfc_rq_destroy(struct lpfc_hba *, struct lpfc_queue *,
1031 struct lpfc_queue *);
1032 int lpfc_sli4_queue_setup(struct lpfc_hba *);
1033 void lpfc_sli4_queue_unset(struct lpfc_hba *);
1034 int lpfc_sli4_post_sgl(struct lpfc_hba *, dma_addr_t, dma_addr_t, uint16_t);
1035 int lpfc_repost_io_sgl_list(struct lpfc_hba *phba);
1036 uint16_t lpfc_sli4_next_xritag(struct lpfc_hba *);
1037 void lpfc_sli4_free_xri(struct lpfc_hba *, int);
1038 int lpfc_sli4_post_async_mbox(struct lpfc_hba *);
1039 struct lpfc_cq_event *__lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
1040 struct lpfc_cq_event *lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
1041 void __lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
1042 void lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
1043 int lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *);
1044 int lpfc_sli4_post_rpi_hdr(struct lpfc_hba *, struct lpfc_rpi_hdr *);
1045 int lpfc_sli4_post_all_rpi_hdrs(struct lpfc_hba *);
1046 struct lpfc_rpi_hdr *lpfc_sli4_create_rpi_hdr(struct lpfc_hba *);
1047 void lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *);
1048 int lpfc_sli4_alloc_rpi(struct lpfc_hba *);
1049 void lpfc_sli4_free_rpi(struct lpfc_hba *, int);
1050 void lpfc_sli4_remove_rpis(struct lpfc_hba *);
1051 void lpfc_sli4_async_event_proc(struct lpfc_hba *);
1052 void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *);
1053 int lpfc_sli4_resume_rpi(struct lpfc_nodelist *,
1054 void (*)(struct lpfc_hba *, LPFC_MBOXQ_t *), void *);
1055 void lpfc_sli4_fcp_xri_abort_event_proc(struct lpfc_hba *);
1056 void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *);
1057 void lpfc_sli4_nvme_xri_aborted(struct lpfc_hba *phba,
1058 struct sli4_wcqe_xri_aborted *axri,
1059 struct lpfc_io_buf *lpfc_ncmd);
1060 void lpfc_sli4_io_xri_aborted(struct lpfc_hba *phba,
1061 struct sli4_wcqe_xri_aborted *axri, int idx);
1062 void lpfc_sli4_nvmet_xri_aborted(struct lpfc_hba *phba,
1063 struct sli4_wcqe_xri_aborted *axri);
1064 void lpfc_sli4_els_xri_aborted(struct lpfc_hba *,
1065 struct sli4_wcqe_xri_aborted *);
1066 void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *);
1067 void lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *);
1068 int lpfc_sli4_brdreset(struct lpfc_hba *);
1069 int lpfc_sli4_add_fcf_record(struct lpfc_hba *, struct fcf_record *);
1070 void lpfc_sli_remove_dflt_fcf(struct lpfc_hba *);
1071 int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *);
1072 int lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba);
1073 int lpfc_sli4_init_vpi(struct lpfc_vport *);
1074 void lpfc_sli4_eq_clr_intr(struct lpfc_queue *);
1075 void lpfc_sli4_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1076 uint32_t count, bool arm);
1077 void lpfc_sli4_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1078 uint32_t count, bool arm);
1079 void lpfc_sli4_if6_eq_clr_intr(struct lpfc_queue *q);
1080 void lpfc_sli4_if6_write_cq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1081 uint32_t count, bool arm);
1082 void lpfc_sli4_if6_write_eq_db(struct lpfc_hba *phba, struct lpfc_queue *q,
1083 uint32_t count, bool arm);
1084 void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t);
1085 int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t);
1086 int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t);
1087 int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t);
1088 void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1089 void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1090 void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
1091 int lpfc_sli4_unregister_fcf(struct lpfc_hba *);
1092 int lpfc_sli4_post_status_check(struct lpfc_hba *);
1093 uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
1094 uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
1095 void lpfc_sli4_ras_dma_free(struct lpfc_hba *phba);
1096 struct sli4_hybrid_sgl *lpfc_get_sgl_per_hdwq(struct lpfc_hba *phba,
1097 struct lpfc_io_buf *buf);
1098 struct fcp_cmd_rsp_buf *lpfc_get_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
1099 struct lpfc_io_buf *buf);
1100 int lpfc_put_sgl_per_hdwq(struct lpfc_hba *phba, struct lpfc_io_buf *buf);
1101 int lpfc_put_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
1102 struct lpfc_io_buf *buf);
1103 void lpfc_free_sgl_per_hdwq(struct lpfc_hba *phba,
1104 struct lpfc_sli4_hdw_queue *hdwq);
1105 void lpfc_free_cmd_rsp_buf_per_hdwq(struct lpfc_hba *phba,
1106 struct lpfc_sli4_hdw_queue *hdwq);
lpfc_sli4_qe(struct lpfc_queue * q,uint16_t idx)1107 static inline void *lpfc_sli4_qe(struct lpfc_queue *q, uint16_t idx)
1108 {
1109 return q->q_pgs[idx / q->entry_cnt_per_pg] +
1110 (q->entry_size * (idx % q->entry_cnt_per_pg));
1111 }
1112
