1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #ifndef __QLA_DEF_H
7 #define __QLA_DEF_H
8
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/module.h>
13 #include <linux/list.h>
14 #include <linux/pci.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/completion.h>
22 #include <linux/interrupt.h>
23 #include <linux/workqueue.h>
24 #include <linux/firmware.h>
25 #include <linux/aer.h>
26 #include <linux/mutex.h>
27 #include <linux/btree.h>
28
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_host.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_cmnd.h>
33 #include <scsi/scsi_transport_fc.h>
34 #include <scsi/scsi_bsg_fc.h>
35
36 #include <uapi/scsi/fc/fc_els.h>
37
38 #define QLA_DFS_DEFINE_DENTRY(_debugfs_file_name) \
39 struct dentry *dfs_##_debugfs_file_name
40 #define QLA_DFS_ROOT_DEFINE_DENTRY(_debugfs_file_name) \
41 struct dentry *qla_dfs_##_debugfs_file_name
42
43 /* Big endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
44 typedef struct {
45 uint8_t domain;
46 uint8_t area;
47 uint8_t al_pa;
48 } be_id_t;
49
50 /* Little endian Fibre Channel S_ID (source ID) or D_ID (destination ID). */
51 typedef struct {
52 uint8_t al_pa;
53 uint8_t area;
54 uint8_t domain;
55 } le_id_t;
56
57 /*
58 * 24 bit port ID type definition.
59 */
60 typedef union {
61 uint32_t b24 : 24;
62 struct {
63 #ifdef __BIG_ENDIAN
64 uint8_t domain;
65 uint8_t area;
66 uint8_t al_pa;
67 #elif defined(__LITTLE_ENDIAN)
68 uint8_t al_pa;
69 uint8_t area;
70 uint8_t domain;
71 #else
72 #error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
73 #endif
74 uint8_t rsvd_1;
75 } b;
76 } port_id_t;
77 #define INVALID_PORT_ID 0xFFFFFF
78
79 #include "qla_bsg.h"
80 #include "qla_dsd.h"
81 #include "qla_nx.h"
82 #include "qla_nx2.h"
83 #include "qla_nvme.h"
84 #define QLA2XXX_DRIVER_NAME "qla2xxx"
85 #define QLA2XXX_APIDEV "ql2xapidev"
86 #define QLA2XXX_MANUFACTURER "Marvell Semiconductor, Inc."
87
88 /*
89 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
90 * but that's fine as we don't look at the last 24 ones for
91 * ISP2100 HBAs.
92 */
93 #define MAILBOX_REGISTER_COUNT_2100 8
94 #define MAILBOX_REGISTER_COUNT_2200 24
95 #define MAILBOX_REGISTER_COUNT 32
96
97 #define QLA2200A_RISC_ROM_VER 4
98 #define FPM_2300 6
99 #define FPM_2310 7
100
101 #include "qla_settings.h"
102
103 #define MODE_DUAL (MODE_TARGET | MODE_INITIATOR)
104
105 /*
106 * Data bit definitions
107 */
108 #define BIT_0 0x1
109 #define BIT_1 0x2
110 #define BIT_2 0x4
111 #define BIT_3 0x8
112 #define BIT_4 0x10
113 #define BIT_5 0x20
114 #define BIT_6 0x40
115 #define BIT_7 0x80
116 #define BIT_8 0x100
117 #define BIT_9 0x200
118 #define BIT_10 0x400
119 #define BIT_11 0x800
120 #define BIT_12 0x1000
121 #define BIT_13 0x2000
122 #define BIT_14 0x4000
123 #define BIT_15 0x8000
124 #define BIT_16 0x10000
125 #define BIT_17 0x20000
126 #define BIT_18 0x40000
127 #define BIT_19 0x80000
128 #define BIT_20 0x100000
129 #define BIT_21 0x200000
130 #define BIT_22 0x400000
131 #define BIT_23 0x800000
132 #define BIT_24 0x1000000
133 #define BIT_25 0x2000000
134 #define BIT_26 0x4000000
135 #define BIT_27 0x8000000
136 #define BIT_28 0x10000000
137 #define BIT_29 0x20000000
138 #define BIT_30 0x40000000
139 #define BIT_31 0x80000000
140
141 #define LSB(x) ((uint8_t)(x))
142 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
143
144 #define LSW(x) ((uint16_t)(x))
145 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
146
147 #define LSD(x) ((uint32_t)((uint64_t)(x)))
148 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
149
make_handle(uint16_t x,uint16_t y)150 static inline uint32_t make_handle(uint16_t x, uint16_t y)
151 {
152 return ((uint32_t)x << 16) | y;
153 }
154
155 /*
156 * I/O register
157 */
158
rd_reg_byte(const volatile u8 __iomem * addr)159 static inline u8 rd_reg_byte(const volatile u8 __iomem *addr)
160 {
161 return readb(addr);
162 }
163
rd_reg_word(const volatile __le16 __iomem * addr)164 static inline u16 rd_reg_word(const volatile __le16 __iomem *addr)
165 {
166 return readw(addr);
167 }
168
rd_reg_dword(const volatile __le32 __iomem * addr)169 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr)
170 {
171 return readl(addr);
172 }
173
rd_reg_byte_relaxed(const volatile u8 __iomem * addr)174 static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr)
175 {
176 return readb_relaxed(addr);
177 }
178
rd_reg_word_relaxed(const volatile __le16 __iomem * addr)179 static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr)
180 {
181 return readw_relaxed(addr);
182 }
183
rd_reg_dword_relaxed(const volatile __le32 __iomem * addr)184 static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr)
185 {
186 return readl_relaxed(addr);
187 }
188
wrt_reg_byte(volatile u8 __iomem * addr,u8 data)189 static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data)
190 {
191 return writeb(data, addr);
192 }
193
wrt_reg_word(volatile __le16 __iomem * addr,u16 data)194 static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data)
195 {
196 return writew(data, addr);
197 }
198
wrt_reg_dword(volatile __le32 __iomem * addr,u32 data)199 static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data)
200 {
201 return writel(data, addr);
202 }
203
204 /*
205 * ISP83XX specific remote register addresses
206 */
207 #define QLA83XX_LED_PORT0 0x00201320
208 #define QLA83XX_LED_PORT1 0x00201328
209 #define QLA83XX_IDC_DEV_STATE 0x22102384
210 #define QLA83XX_IDC_MAJOR_VERSION 0x22102380
211 #define QLA83XX_IDC_MINOR_VERSION 0x22102398
212 #define QLA83XX_IDC_DRV_PRESENCE 0x22102388
213 #define QLA83XX_IDC_DRIVER_ACK 0x2210238c
214 #define QLA83XX_IDC_CONTROL 0x22102390
215 #define QLA83XX_IDC_AUDIT 0x22102394
216 #define QLA83XX_IDC_LOCK_RECOVERY 0x2210239c
217 #define QLA83XX_DRIVER_LOCKID 0x22102104
218 #define QLA83XX_DRIVER_LOCK 0x8111c028
219 #define QLA83XX_DRIVER_UNLOCK 0x8111c02c
220 #define QLA83XX_FLASH_LOCKID 0x22102100
221 #define QLA83XX_FLASH_LOCK 0x8111c010
222 #define QLA83XX_FLASH_UNLOCK 0x8111c014
223 #define QLA83XX_DEV_PARTINFO1 0x221023e0
224 #define QLA83XX_DEV_PARTINFO2 0x221023e4
225 #define QLA83XX_FW_HEARTBEAT 0x221020b0
226 #define QLA83XX_PEG_HALT_STATUS1 0x221020a8
227 #define QLA83XX_PEG_HALT_STATUS2 0x221020ac
228
229 /* 83XX: Macros defining 8200 AEN Reason codes */
230 #define IDC_DEVICE_STATE_CHANGE BIT_0
231 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
232 #define IDC_NIC_FW_REPORTED_FAILURE BIT_2
233 #define IDC_HEARTBEAT_FAILURE BIT_3
234
235 /* 83XX: Macros defining 8200 AEN Error-levels */
236 #define ERR_LEVEL_NON_FATAL 0x1
237 #define ERR_LEVEL_RECOVERABLE_FATAL 0x2
238 #define ERR_LEVEL_UNRECOVERABLE_FATAL 0x4
239
240 /* 83XX: Macros for IDC Version */
241 #define QLA83XX_SUPP_IDC_MAJOR_VERSION 0x01
242 #define QLA83XX_SUPP_IDC_MINOR_VERSION 0x0
243
244 /* 83XX: Macros for scheduling dpc tasks */
245 #define QLA83XX_NIC_CORE_RESET 0x1
246 #define QLA83XX_IDC_STATE_HANDLER 0x2
247 #define QLA83XX_NIC_CORE_UNRECOVERABLE 0x3
248
249 /* 83XX: Macros for defining IDC-Control bits */
250 #define QLA83XX_IDC_RESET_DISABLED BIT_0
251 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
252
253 /* 83XX: Macros for different timeouts */
254 #define QLA83XX_IDC_INITIALIZATION_TIMEOUT 30
255 #define QLA83XX_IDC_RESET_ACK_TIMEOUT 10
256 #define QLA83XX_MAX_LOCK_RECOVERY_WAIT (2 * HZ)
257
258 /* 83XX: Macros for defining class in DEV-Partition Info register */
259 #define QLA83XX_CLASS_TYPE_NONE 0x0
260 #define QLA83XX_CLASS_TYPE_NIC 0x1
261 #define QLA83XX_CLASS_TYPE_FCOE 0x2
262 #define QLA83XX_CLASS_TYPE_ISCSI 0x3
263
264 /* 83XX: Macros for IDC Lock-Recovery stages */
265 #define IDC_LOCK_RECOVERY_STAGE1 0x1 /* Stage1: Intent for
266 * lock-recovery
267 */
268 #define IDC_LOCK_RECOVERY_STAGE2 0x2 /* Stage2: Perform lock-recovery */
269
270 /* 83XX: Macros for IDC Audit type */
271 #define IDC_AUDIT_TIMESTAMP 0x0 /* IDC-AUDIT: Record timestamp of
272 * dev-state change to NEED-RESET
273 * or NEED-QUIESCENT
274 */
275 #define IDC_AUDIT_COMPLETION 0x1 /* IDC-AUDIT: Record duration of
276 * reset-recovery completion is
277 * second
278 */
279 /* ISP2031: Values for laser on/off */
280 #define PORT_0_2031 0x00201340
281 #define PORT_1_2031 0x00201350
282 #define LASER_ON_2031 0x01800100
283 #define LASER_OFF_2031 0x01800180
284
285 /*
286 * The ISP2312 v2 chip cannot access the FLASH/GPIO registers via MMIO in an
287 * 133Mhz slot.
288 */
289 #define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
290 #define WRT_REG_WORD_PIO(addr, data) (outw(data, (unsigned long)addr))
291
292 /*
293 * Fibre Channel device definitions.
294 */
295 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
296 #define MAX_FIBRE_DEVICES_2100 512
297 #define MAX_FIBRE_DEVICES_2400 2048
298 #define MAX_FIBRE_DEVICES_LOOP 128
299 #define MAX_FIBRE_DEVICES_MAX MAX_FIBRE_DEVICES_2400
300 #define LOOPID_MAP_SIZE (ha->max_fibre_devices)
301 #define MAX_FIBRE_LUNS 0xFFFF
302 #define MAX_HOST_COUNT 16
303
304 /*
305 * Host adapter default definitions.
306 */
307 #define MAX_BUSES 1 /* We only have one bus today */
308 #define MIN_LUNS 8
309 #define MAX_LUNS MAX_FIBRE_LUNS
310 #define MAX_CMDS_PER_LUN 255
311
312 /*
313 * Fibre Channel device definitions.
314 */
315 #define SNS_LAST_LOOP_ID_2100 0xfe
316 #define SNS_LAST_LOOP_ID_2300 0x7ff
317
318 #define LAST_LOCAL_LOOP_ID 0x7d
319 #define SNS_FL_PORT 0x7e
320 #define FABRIC_CONTROLLER 0x7f
321 #define SIMPLE_NAME_SERVER 0x80
322 #define SNS_FIRST_LOOP_ID 0x81
323 #define MANAGEMENT_SERVER 0xfe
324 #define BROADCAST 0xff
325
326 /*
327 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
328 * valid range of an N-PORT id is 0 through 0x7ef.
329 */
330 #define NPH_LAST_HANDLE 0x7ee
331 #define NPH_MGMT_SERVER 0x7ef /* FFFFEF */
332 #define NPH_SNS 0x7fc /* FFFFFC */
333 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
334 #define NPH_F_PORT 0x7fe /* FFFFFE */
335 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
336
337 #define NPH_SNS_LID(ha) (IS_FWI2_CAPABLE(ha) ? NPH_SNS : SIMPLE_NAME_SERVER)
338
339 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
340 #include "qla_fw.h"
341
342 struct name_list_extended {
343 struct get_name_list_extended *l;
344 dma_addr_t ldma;
345 struct list_head fcports;
346 u32 size;
347 u8 sent;
348 };
349
350 struct els_reject {
351 struct fc_els_ls_rjt *c;
352 dma_addr_t cdma;
353 u16 size;
354 };
355
356 /*
357 * Timeout timer counts in seconds
358 */
359 #define PORT_RETRY_TIME 1
360 #define LOOP_DOWN_TIMEOUT 60
361 #define LOOP_DOWN_TIME 255 /* 240 */
362 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
363
364 #define DEFAULT_OUTSTANDING_COMMANDS 4096
365 #define MIN_OUTSTANDING_COMMANDS 128
366
367 /* ISP request and response entry counts (37-65535) */
368 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
369 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
370 #define REQUEST_ENTRY_CNT_24XX 2048 /* Number of request entries. */
371 #define REQUEST_ENTRY_CNT_83XX 8192 /* Number of request entries. */
372 #define RESPONSE_ENTRY_CNT_83XX 4096 /* Number of response entries.*/
373 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
374 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
375 #define RESPONSE_ENTRY_CNT_MQ 128 /* Number of response entries.*/
376 #define ATIO_ENTRY_CNT_24XX 4096 /* Number of ATIO entries. */
377 #define RESPONSE_ENTRY_CNT_FX00 256 /* Number of response entries.*/
378 #define FW_DEF_EXCHANGES_CNT 2048
379 #define FW_MAX_EXCHANGES_CNT (32 * 1024)
380 #define REDUCE_EXCHANGES_CNT (8 * 1024)
381
382 #define SET_DID_STATUS(stat_var, status) (stat_var = status << 16)
383
384 struct req_que;
385 struct qla_tgt_sess;
386
387 /*
388 * SCSI Request Block
389 */
390 struct srb_cmd {
391 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
392 uint32_t request_sense_length;
393 uint32_t fw_sense_length;
394 uint8_t *request_sense_ptr;
395 struct ct6_dsd *ct6_ctx;
396 struct crc_context *crc_ctx;
397 };
398
399 /*
400 * SRB flag definitions
401 */
402 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */
403 #define SRB_FCP_CMND_DMA_VALID BIT_12 /* DIF: DSD List valid */
404 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
405 #define SRB_CRC_PROT_DMA_VALID BIT_4 /* DIF: prot DMA valid */
406 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
407 #define SRB_WAKEUP_ON_COMP BIT_6
408 #define SRB_DIF_BUNDL_DMA_VALID BIT_7 /* DIF: DMA list valid */
409 #define SRB_EDIF_CLEANUP_DELETE BIT_9
410
411 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
412 #define IS_PROT_IO(sp) (sp->flags & SRB_CRC_CTX_DSD_VALID)
413 #define ISP_REG16_DISCONNECT 0xFFFF
414
be_id_to_le(be_id_t id)415 static inline le_id_t be_id_to_le(be_id_t id)
416 {
417 le_id_t res;
418
419 res.domain = id.domain;
420 res.area = id.area;
421 res.al_pa = id.al_pa;
422
423 return res;
424 }
425
le_id_to_be(le_id_t id)426 static inline be_id_t le_id_to_be(le_id_t id)
427 {
428 be_id_t res;
429
430 res.domain = id.domain;
431 res.area = id.area;
432 res.al_pa = id.al_pa;
433
434 return res;
435 }
436
be_to_port_id(be_id_t id)437 static inline port_id_t be_to_port_id(be_id_t id)
438 {
439 port_id_t res;
440
441 res.b.domain = id.domain;
442 res.b.area = id.area;
443 res.b.al_pa = id.al_pa;
444 res.b.rsvd_1 = 0;
445
446 return res;
447 }
448
port_id_to_be_id(port_id_t port_id)449 static inline be_id_t port_id_to_be_id(port_id_t port_id)
450 {
451 be_id_t res;
452
453 res.domain = port_id.b.domain;
454 res.area = port_id.b.area;
455 res.al_pa = port_id.b.al_pa;
456
457 return res;
458 }
459
460 struct els_logo_payload {
461 uint8_t opcode;
462 uint8_t rsvd[3];
463 uint8_t s_id[3];
464 uint8_t rsvd1[1];
465 uint8_t wwpn[WWN_SIZE];
466 };
467
468 struct els_plogi_payload {
469 uint8_t opcode;
470 uint8_t rsvd[3];
471 __be32 data[112 / 4];
472 };
473
474 struct ct_arg {
475 void *iocb;
476 u16 nport_handle;
477 dma_addr_t req_dma;
478 dma_addr_t rsp_dma;
479 u32 req_size;
480 u32 rsp_size;
481 u32 req_allocated_size;
482 u32 rsp_allocated_size;
483 void *req;
484 void *rsp;
485 port_id_t id;
486 };
487
488 /*
489 * SRB extensions.
490 */
491 struct srb_iocb {
492 union {
493 struct {
494 uint16_t flags;
495 #define SRB_LOGIN_RETRIED BIT_0
496 #define SRB_LOGIN_COND_PLOGI BIT_1
497 #define SRB_LOGIN_SKIP_PRLI BIT_2
498 #define SRB_LOGIN_NVME_PRLI BIT_3
499 #define SRB_LOGIN_PRLI_ONLY BIT_4
500 #define SRB_LOGIN_FCSP BIT_5
501 uint16_t data[2];
502 u32 iop[2];
503 } logio;
504 struct {
505 #define ELS_DCMD_TIMEOUT 20
506 #define ELS_DCMD_LOGO 0x5
507 uint32_t flags;
508 uint32_t els_cmd;
509 struct completion comp;
510 struct els_logo_payload *els_logo_pyld;
511 dma_addr_t els_logo_pyld_dma;
512 } els_logo;
513 struct els_plogi {
514 #define ELS_DCMD_PLOGI 0x3
515 uint32_t flags;
516 uint32_t els_cmd;
517 struct completion comp;
518 struct els_plogi_payload *els_plogi_pyld;
519 struct els_plogi_payload *els_resp_pyld;
520 u32 tx_size;
521 u32 rx_size;
522 dma_addr_t els_plogi_pyld_dma;
523 dma_addr_t els_resp_pyld_dma;
524 __le32 fw_status[3];
525 __le16 comp_status;
526 __le16 len;
527 } els_plogi;
528 struct {
529 /*
530 * Values for flags field below are as
531 * defined in tsk_mgmt_entry struct
532 * for control_flags field in qla_fw.h.
533 */
534 uint64_t lun;
535 uint32_t flags;
536 uint32_t data;
537 struct completion comp;
538 __le16 comp_status;
539 } tmf;
540 struct {
541 #define SRB_FXDISC_REQ_DMA_VALID BIT_0
542 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
543 #define SRB_FXDISC_REQ_DWRD_VALID BIT_2
544 #define SRB_FXDISC_RSP_DWRD_VALID BIT_3
545 #define FXDISC_TIMEOUT 20
546 uint8_t flags;
547 uint32_t req_len;
548 uint32_t rsp_len;
549 void *req_addr;
550 void *rsp_addr;
551 dma_addr_t req_dma_handle;
552 dma_addr_t rsp_dma_handle;
553 __le32 adapter_id;
554 __le32 adapter_id_hi;
555 __le16 req_func_type;
556 __le32 req_data;
557 __le32 req_data_extra;
558 __le32 result;
559 __le32 seq_number;
560 __le16 fw_flags;
561 struct completion fxiocb_comp;
562 __le32 reserved_0;
563 uint8_t reserved_1;
564 } fxiocb;
565 struct {
566 uint32_t cmd_hndl;
567 __le16 comp_status;
568 __le16 req_que_no;
569 struct completion comp;
570 } abt;
571 struct ct_arg ctarg;
572 #define MAX_IOCB_MB_REG 28
573 #define SIZEOF_IOCB_MB_REG (MAX_IOCB_MB_REG * sizeof(uint16_t))
574 struct {
575 u16 in_mb[MAX_IOCB_MB_REG]; /* from FW */
576 u16 out_mb[MAX_IOCB_MB_REG]; /* to FW */
577 void *out, *in;
578 dma_addr_t out_dma, in_dma;
579 struct completion comp;
580 int rc;
581 } mbx;
582 struct {
583 struct imm_ntfy_from_isp *ntfy;
584 } nack;
585 struct {
586 __le16 comp_status;
587 __le16 rsp_pyld_len;
588 uint8_t aen_op;
589 void *desc;
590
591 /* These are only used with ls4 requests */
592 int cmd_len;
593 int rsp_len;
594 dma_addr_t cmd_dma;
595 dma_addr_t rsp_dma;
596 enum nvmefc_fcp_datadir dir;
597 uint32_t dl;
598 uint32_t timeout_sec;
599 struct list_head entry;
600 } nvme;
601 struct {
602 u16 cmd;
603 u16 vp_index;
604 } ctrlvp;
605 struct {
606 struct edif_sa_ctl *sa_ctl;
607 struct qla_sa_update_frame sa_frame;
608 } sa_update;
609 } u;
610
611 struct timer_list timer;
612 void (*timeout)(void *);
613 };
614
615 /* Values for srb_ctx type */
616 #define SRB_LOGIN_CMD 1
617 #define SRB_LOGOUT_CMD 2
618 #define SRB_ELS_CMD_RPT 3
619 #define SRB_ELS_CMD_HST 4
620 #define SRB_CT_CMD 5
621 #define SRB_ADISC_CMD 6
622 #define SRB_TM_CMD 7
623 #define SRB_SCSI_CMD 8
624 #define SRB_BIDI_CMD 9
625 #define SRB_FXIOCB_DCMD 10
626 #define SRB_FXIOCB_BCMD 11
627 #define SRB_ABT_CMD 12
628 #define SRB_ELS_DCMD 13
629 #define SRB_MB_IOCB 14
630 #define SRB_CT_PTHRU_CMD 15
631 #define SRB_NACK_PLOGI 16
632 #define SRB_NACK_PRLI 17
633 #define SRB_NACK_LOGO 18
634 #define SRB_NVME_CMD 19
635 #define SRB_NVME_LS 20
636 #define SRB_PRLI_CMD 21
637 #define SRB_CTRL_VP 22
638 #define SRB_PRLO_CMD 23
639 #define SRB_SA_UPDATE 25
640 #define SRB_ELS_CMD_HST_NOLOGIN 26
641 #define SRB_SA_REPLACE 27
642
643 struct qla_els_pt_arg {
644 u8 els_opcode;
645 u8 vp_idx;
646 __le16 nport_handle;
647 u16 control_flags, ox_id;
648 __le32 rx_xchg_address;
649 port_id_t did, sid;
650 u32 tx_len, tx_byte_count, rx_len, rx_byte_count;
651 dma_addr_t tx_addr, rx_addr;
652
653 };
654
655 enum {
656 TYPE_SRB,
657 TYPE_TGT_CMD,
658 TYPE_TGT_TMCMD, /* task management */
659 };
660
661 struct iocb_resource {
662 u8 res_type;
663 u8 pad;
664 u16 iocb_cnt;
665 };
666
667 struct bsg_cmd {
668 struct bsg_job *bsg_job;
669 union {
670 struct qla_els_pt_arg els_arg;
671 } u;
672 };
673
674 typedef struct srb {
675 /*
676 * Do not move cmd_type field, it needs to
677 * line up with qla_tgt_cmd->cmd_type
678 */
679 uint8_t cmd_type;
680 uint8_t pad[3];
681 struct iocb_resource iores;
682 struct kref cmd_kref; /* need to migrate ref_count over to this */
683 void *priv;
684 wait_queue_head_t nvme_ls_waitq;
685 struct fc_port *fcport;
686 struct scsi_qla_host *vha;
687 unsigned int start_timer:1;
688
689 uint32_t handle;
690 uint16_t flags;
691 uint16_t type;
692 const char *name;
693 int iocbs;
694 struct qla_qpair *qpair;
695 struct srb *cmd_sp;
696 struct list_head elem;
697 u32 gen1; /* scratch */
698 u32 gen2; /* scratch */
699 int rc;
700 int retry_count;
701 struct completion *comp;
702 union {
703 struct srb_iocb iocb_cmd;
704 struct bsg_job *bsg_job;
705 struct srb_cmd scmd;
706 struct bsg_cmd bsg_cmd;
707 } u;
708 struct {
709 bool remapped;
710 struct {
711 dma_addr_t dma;
712 void *buf;
713 uint len;
714 } req;
715 struct {
716 dma_addr_t dma;
717 void *buf;
718 uint len;
719 } rsp;
720 } remap;
721 /*
722 * Report completion status @res and call sp_put(@sp). @res is
723 * an NVMe status code, a SCSI result (e.g. DID_OK << 16) or a
724 * QLA_* status value.
725 */
726 void (*done)(struct srb *sp, int res);
727 /* Stop the timer and free @sp. Only used by the FCP code. */
728 void (*free)(struct srb *sp);
729 /*
730 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe
731 * code.
732 */
733 void (*put_fn)(struct kref *kref);
734
735 /*
736 * Report completion for asynchronous commands.
737 */
738 void (*async_done)(struct srb *sp, int res);
739 } srb_t;
740
741 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
742
743 #define GET_CMD_SENSE_LEN(sp) \
744 (sp->u.scmd.request_sense_length)
745 #define SET_CMD_SENSE_LEN(sp, len) \
746 (sp->u.scmd.request_sense_length = len)
747 #define GET_CMD_SENSE_PTR(sp) \
748 (sp->u.scmd.request_sense_ptr)
749 #define SET_CMD_SENSE_PTR(sp, ptr) \
750 (sp->u.scmd.request_sense_ptr = ptr)
751 #define GET_FW_SENSE_LEN(sp) \
752 (sp->u.scmd.fw_sense_length)
753 #define SET_FW_SENSE_LEN(sp, len) \
754 (sp->u.scmd.fw_sense_length = len)
755
756 struct msg_echo_lb {
757 dma_addr_t send_dma;
758 dma_addr_t rcv_dma;
759 uint16_t req_sg_cnt;
760 uint16_t rsp_sg_cnt;
761 uint16_t options;
762 uint32_t transfer_size;
763 uint32_t iteration_count;
764 };
765
766 /*
767 * ISP I/O Register Set structure definitions.
768 */
769 struct device_reg_2xxx {
770 __le16 flash_address; /* Flash BIOS address */
771 __le16 flash_data; /* Flash BIOS data */
772 __le16 unused_1[1]; /* Gap */
773 __le16 ctrl_status; /* Control/Status */
774 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
775 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
776 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
777
778 __le16 ictrl; /* Interrupt control */
779 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
780 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
781
782 __le16 istatus; /* Interrupt status */
783 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
784
785 __le16 semaphore; /* Semaphore */
786 __le16 nvram; /* NVRAM register. */
787 #define NVR_DESELECT 0
788 #define NVR_BUSY BIT_15
789 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
790 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
791 #define NVR_DATA_IN BIT_3
792 #define NVR_DATA_OUT BIT_2
793 #define NVR_SELECT BIT_1
794 #define NVR_CLOCK BIT_0
795
796 #define NVR_WAIT_CNT 20000
797
798 union {
799 struct {
800 __le16 mailbox0;
801 __le16 mailbox1;
802 __le16 mailbox2;
803 __le16 mailbox3;
804 __le16 mailbox4;
805 __le16 mailbox5;
806 __le16 mailbox6;
807 __le16 mailbox7;
808 __le16 unused_2[59]; /* Gap */
809 } __attribute__((packed)) isp2100;
810 struct {
811 /* Request Queue */
812 __le16 req_q_in; /* In-Pointer */
813 __le16 req_q_out; /* Out-Pointer */
814 /* Response Queue */
815 __le16 rsp_q_in; /* In-Pointer */
816 __le16 rsp_q_out; /* Out-Pointer */
817
818 /* RISC to Host Status */
819 __le32 host_status;
820 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
821 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
822
823 /* Host to Host Semaphore */
824 __le16 host_semaphore;
825 __le16 unused_3[17]; /* Gap */
826 __le16 mailbox0;
827 __le16 mailbox1;
828 __le16 mailbox2;
829 __le16 mailbox3;
830 __le16 mailbox4;
831 __le16 mailbox5;
832 __le16 mailbox6;
833 __le16 mailbox7;
834 __le16 mailbox8;
835 __le16 mailbox9;
836 __le16 mailbox10;
837 __le16 mailbox11;
838 __le16 mailbox12;
839 __le16 mailbox13;
840 __le16 mailbox14;
841 __le16 mailbox15;
842 __le16 mailbox16;
843 __le16 mailbox17;
844 __le16 mailbox18;
845 __le16 mailbox19;
846 __le16 mailbox20;
847 __le16 mailbox21;
848 __le16 mailbox22;
849 __le16 mailbox23;
850 __le16 mailbox24;
851 __le16 mailbox25;
852 __le16 mailbox26;
853 __le16 mailbox27;
854 __le16 mailbox28;
855 __le16 mailbox29;
856 __le16 mailbox30;
857 __le16 mailbox31;
858 __le16 fb_cmd;
859 __le16 unused_4[10]; /* Gap */
860 } __attribute__((packed)) isp2300;
861 } u;
862
863 __le16 fpm_diag_config;
864 __le16 unused_5[0x4]; /* Gap */
865 __le16 risc_hw;
866 __le16 unused_5_1; /* Gap */
867 __le16 pcr; /* Processor Control Register. */
868 __le16 unused_6[0x5]; /* Gap */
869 __le16 mctr; /* Memory Configuration and Timing. */
870 __le16 unused_7[0x3]; /* Gap */
871 __le16 fb_cmd_2100; /* Unused on 23XX */
872 __le16 unused_8[0x3]; /* Gap */
873 __le16 hccr; /* Host command & control register. */
874 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
875 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
876 /* HCCR commands */
877 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
878 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
879 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
880 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
881 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
882 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
883 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
884 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
885
886 __le16 unused_9[5]; /* Gap */
887 __le16 gpiod; /* GPIO Data register. */
888 __le16 gpioe; /* GPIO Enable register. */
889 #define GPIO_LED_MASK 0x00C0
890 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
891 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
892 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
893 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
894 #define GPIO_LED_ALL_OFF 0x0000
895 #define GPIO_LED_RED_ON_OTHER_OFF 0x0001 /* isp2322 */
896 #define GPIO_LED_RGA_ON 0x00C1 /* isp2322: red green amber */
897
898 union {
899 struct {
900 __le16 unused_10[8]; /* Gap */
901 __le16 mailbox8;
902 __le16 mailbox9;
903 __le16 mailbox10;
904 __le16 mailbox11;
905 __le16 mailbox12;
906 __le16 mailbox13;
907 __le16 mailbox14;
908 __le16 mailbox15;
909 __le16 mailbox16;
910 __le16 mailbox17;
911 __le16 mailbox18;
912 __le16 mailbox19;
913 __le16 mailbox20;
914 __le16 mailbox21;
915 __le16 mailbox22;
916 __le16 mailbox23; /* Also probe reg. */
917 } __attribute__((packed)) isp2200;
918 } u_end;
919 };
920
921 struct device_reg_25xxmq {
922 __le32 req_q_in;
923 __le32 req_q_out;
924 __le32 rsp_q_in;
925 __le32 rsp_q_out;
926 __le32 atio_q_in;
927 __le32 atio_q_out;
928 };
929
930
931 struct device_reg_fx00 {
932 __le32 mailbox0; /* 00 */
933 __le32 mailbox1; /* 04 */
934 __le32 mailbox2; /* 08 */
935 __le32 mailbox3; /* 0C */
936 __le32 mailbox4; /* 10 */
937 __le32 mailbox5; /* 14 */
938 __le32 mailbox6; /* 18 */
939 __le32 mailbox7; /* 1C */
940 __le32 mailbox8; /* 20 */
941 __le32 mailbox9; /* 24 */
942 __le32 mailbox10; /* 28 */
943 __le32 mailbox11;
944 __le32 mailbox12;
945 __le32 mailbox13;
946 __le32 mailbox14;
947 __le32 mailbox15;
948 __le32 mailbox16;
949 __le32 mailbox17;
950 __le32 mailbox18;
951 __le32 mailbox19;
952 __le32 mailbox20;
953 __le32 mailbox21;
954 __le32 mailbox22;
955 __le32 mailbox23;
956 __le32 mailbox24;
957 __le32 mailbox25;
958 __le32 mailbox26;
959 __le32 mailbox27;
960 __le32 mailbox28;
961 __le32 mailbox29;
962 __le32 mailbox30;
963 __le32 mailbox31;
964 __le32 aenmailbox0;
965 __le32 aenmailbox1;
966 __le32 aenmailbox2;
967 __le32 aenmailbox3;
968 __le32 aenmailbox4;
969 __le32 aenmailbox5;
970 __le32 aenmailbox6;
971 __le32 aenmailbox7;
972 /* Request Queue. */
973 __le32 req_q_in; /* A0 - Request Queue In-Pointer */
974 __le32 req_q_out; /* A4 - Request Queue Out-Pointer */
975 /* Response Queue. */
976 __le32 rsp_q_in; /* A8 - Response Queue In-Pointer */
977 __le32 rsp_q_out; /* AC - Response Queue Out-Pointer */
978 /* Init values shadowed on FW Up Event */
979 __le32 initval0; /* B0 */
980 __le32 initval1; /* B4 */
981 __le32 initval2; /* B8 */
982 __le32 initval3; /* BC */
983 __le32 initval4; /* C0 */
984 __le32 initval5; /* C4 */
985 __le32 initval6; /* C8 */
986 __le32 initval7; /* CC */
987 __le32 fwheartbeat; /* D0 */
988 __le32 pseudoaen; /* D4 */
989 };
990
991
992
993 typedef union {
994 struct device_reg_2xxx isp;
995 struct device_reg_24xx isp24;
996 struct device_reg_25xxmq isp25mq;
997 struct device_reg_82xx isp82;
998 struct device_reg_fx00 ispfx00;
999 } __iomem device_reg_t;
1000
1001 #define ISP_REQ_Q_IN(ha, reg) \
1002 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1003 &(reg)->u.isp2100.mailbox4 : \
1004 &(reg)->u.isp2300.req_q_in)
1005 #define ISP_REQ_Q_OUT(ha, reg) \
1006 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1007 &(reg)->u.isp2100.mailbox4 : \
1008 &(reg)->u.isp2300.req_q_out)
1009 #define ISP_RSP_Q_IN(ha, reg) \
1010 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1011 &(reg)->u.isp2100.mailbox5 : \
1012 &(reg)->u.isp2300.rsp_q_in)
1013 #define ISP_RSP_Q_OUT(ha, reg) \
1014 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1015 &(reg)->u.isp2100.mailbox5 : \
1016 &(reg)->u.isp2300.rsp_q_out)
1017
1018 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
1019 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
1020
1021 #define MAILBOX_REG(ha, reg, num) \
1022 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1023 (num < 8 ? \
1024 &(reg)->u.isp2100.mailbox0 + (num) : \
1025 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
1026 &(reg)->u.isp2300.mailbox0 + (num))
1027 #define RD_MAILBOX_REG(ha, reg, num) \
1028 rd_reg_word(MAILBOX_REG(ha, reg, num))
1029 #define WRT_MAILBOX_REG(ha, reg, num, data) \
1030 wrt_reg_word(MAILBOX_REG(ha, reg, num), data)
1031
1032 #define FB_CMD_REG(ha, reg) \
1033 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
1034 &(reg)->fb_cmd_2100 : \
1035 &(reg)->u.isp2300.fb_cmd)
1036 #define RD_FB_CMD_REG(ha, reg) \
1037 rd_reg_word(FB_CMD_REG(ha, reg))
1038 #define WRT_FB_CMD_REG(ha, reg, data) \
1039 wrt_reg_word(FB_CMD_REG(ha, reg), data)
1040
1041 typedef struct {
1042 uint32_t out_mb; /* outbound from driver */
1043 uint32_t in_mb; /* Incoming from RISC */
1044 uint16_t mb[MAILBOX_REGISTER_COUNT];
1045 long buf_size;
1046 void *bufp;
1047 uint32_t tov;
1048 uint8_t flags;
1049 #define MBX_DMA_IN BIT_0
1050 #define MBX_DMA_OUT BIT_1
1051 #define IOCTL_CMD BIT_2
1052 } mbx_cmd_t;
1053
1054 struct mbx_cmd_32 {
1055 uint32_t out_mb; /* outbound from driver */
1056 uint32_t in_mb; /* Incoming from RISC */
1057 uint32_t mb[MAILBOX_REGISTER_COUNT];
1058 long buf_size;
1059 void *bufp;
1060 uint32_t tov;
1061 uint8_t flags;
1062 #define MBX_DMA_IN BIT_0
1063 #define MBX_DMA_OUT BIT_1
1064 #define IOCTL_CMD BIT_2
1065 };
1066
1067
1068 #define MBX_TOV_SECONDS 30
1069
1070 /*
1071 * ISP product identification definitions in mailboxes after reset.
1072 */
1073 #define PROD_ID_1 0x4953
1074 #define PROD_ID_2 0x0000
1075 #define PROD_ID_2a 0x5020
1076 #define PROD_ID_3 0x2020
1077
1078 /*
1079 * ISP mailbox Self-Test status codes
1080 */
1081 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
1082 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
1083 #define MBS_BUSY 4 /* Busy. */
1084
1085 /*
1086 * ISP mailbox command complete status codes
1087 */
1088 #define MBS_COMMAND_COMPLETE 0x4000
1089 #define MBS_INVALID_COMMAND 0x4001
1090 #define MBS_HOST_INTERFACE_ERROR 0x4002
1091 #define MBS_TEST_FAILED 0x4003
1092 #define MBS_COMMAND_ERROR 0x4005
1093 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
1094 #define MBS_PORT_ID_USED 0x4007
1095 #define MBS_LOOP_ID_USED 0x4008
1096 #define MBS_ALL_IDS_IN_USE 0x4009
1097 #define MBS_NOT_LOGGED_IN 0x400A
1098 #define MBS_LINK_DOWN_ERROR 0x400B
1099 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1100
qla2xxx_is_valid_mbs(unsigned int mbs)1101 static inline bool qla2xxx_is_valid_mbs(unsigned int mbs)
1102 {
1103 return MBS_COMMAND_COMPLETE <= mbs && mbs <= MBS_DIAG_ECHO_TEST_ERROR;
1104 }
1105
1106 /*
1107 * ISP mailbox asynchronous event status codes
1108 */
1109 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
1110 #define MBA_RESET 0x8001 /* Reset Detected. */
1111 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
1112 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
1113 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
1114 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
1115 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
1116 /* occurred. */
1117 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
1118 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
1119 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
1120 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
1121 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
1122 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
1123 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
1124 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
1125 #define MBA_CONGN_NOTI_RECV 0x801e /* Congestion Notification Received */
1126 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
1127 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
1128 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
1129 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
1130 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
1131 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
1132 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
1133 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
1134 /* used. */
1135 #define MBA_TRACE_NOTIFICATION 0x8028 /* Trace/Diagnostic notification. */
1136 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
1137 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
1138 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
1139 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
1140 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
1141 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
1142 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
1143 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
1144 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
1145 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
1146 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
1147 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
1148 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
1149 #define MBA_FW_NOT_STARTED 0x8050 /* Firmware not started */
1150 #define MBA_FW_STARTING 0x8051 /* Firmware starting */
1151 #define MBA_FW_RESTART_CMPLT 0x8060 /* Firmware restart complete */
1152 #define MBA_INIT_REQUIRED 0x8061 /* Initialization required */
1153 #define MBA_SHUTDOWN_REQUESTED 0x8062 /* Shutdown Requested */
1154 #define MBA_TEMPERATURE_ALERT 0x8070 /* Temperature Alert */
1155 #define MBA_DPORT_DIAGNOSTICS 0x8080 /* D-port Diagnostics */
1156 #define MBA_TRANS_INSERT 0x8130 /* Transceiver Insertion */
1157 #define MBA_TRANS_REMOVE 0x8131 /* Transceiver Removal */
1158 #define MBA_FW_INIT_FAILURE 0x8401 /* Firmware initialization failure */
1159 #define MBA_MIRROR_LUN_CHANGE 0x8402 /* Mirror LUN State Change
1160 Notification */
1161 #define MBA_FW_POLL_STATE 0x8600 /* Firmware in poll diagnostic state */
1162 #define MBA_FW_RESET_FCT 0x8502 /* Firmware reset factory defaults */
1163 #define MBA_FW_INIT_INPROGRESS 0x8500 /* Firmware boot in progress */
1164 /* 83XX FCoE specific */
1165 #define MBA_IDC_AEN 0x8200 /* FCoE: NIC Core state change AEN */
1166
1167 /* Interrupt type codes */
1168 #define INTR_ROM_MB_SUCCESS 0x1
1169 #define INTR_ROM_MB_FAILED 0x2
1170 #define INTR_MB_SUCCESS 0x10
1171 #define INTR_MB_FAILED 0x11
1172 #define INTR_ASYNC_EVENT 0x12
1173 #define INTR_RSP_QUE_UPDATE 0x13
1174 #define INTR_RSP_QUE_UPDATE_83XX 0x14
1175 #define INTR_ATIO_QUE_UPDATE 0x1C
1176 #define INTR_ATIO_RSP_QUE_UPDATE 0x1D
1177 #define INTR_ATIO_QUE_UPDATE_27XX 0x1E
1178
1179 /* ISP mailbox loopback echo diagnostic error code */
1180 #define MBS_LB_RESET 0x17
1181
1182 /* AEN mailbox Port Diagnostics test */
1183 #define AEN_START_DIAG_TEST 0x0 /* start the diagnostics */
1184 #define AEN_DONE_DIAG_TEST_WITH_NOERR 0x1 /* Done with no errors */
1185 #define AEN_DONE_DIAG_TEST_WITH_ERR 0x2 /* Done with error.*/
1186
1187 /*
1188 * Firmware options 1, 2, 3.
1189 */
1190 #define FO1_AE_ON_LIPF8 BIT_0
1191 #define FO1_AE_ALL_LIP_RESET BIT_1
1192 #define FO1_CTIO_RETRY BIT_3
1193 #define FO1_DISABLE_LIP_F7_SW BIT_4
1194 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1195 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1196 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
1197 #define FO1_SET_EMPHASIS_SWING BIT_8
1198 #define FO1_AE_AUTO_BYPASS BIT_9
1199 #define FO1_ENABLE_PURE_IOCB BIT_10
1200 #define FO1_AE_PLOGI_RJT BIT_11
1201 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
1202 #define FO1_AE_QUEUE_FULL BIT_13
1203
1204 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
1205 #define FO2_REV_LOOPBACK BIT_1
1206
1207 #define FO3_ENABLE_EMERG_IOCB BIT_0
1208 #define FO3_AE_RND_ERROR BIT_1
1209
1210 /* 24XX additional firmware options */
1211 #define ADD_FO_COUNT 3
1212 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
1213 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
1214
1215 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1216
1217 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
1218
1219 /*
1220 * ISP mailbox commands
1221 */
1222 #define MBC_LOAD_RAM 1 /* Load RAM. */
1223 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
1224 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
1225 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
1226 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
1227 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
1228 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
1229 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
1230 #define MBC_SECURE_FLASH_UPDATE 0xa /* Secure Flash Update(28xx) */
1231 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
1232 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
1233 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
1234 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
1235 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
1236 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1237 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
1238 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
1239 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
1240 #define MBC_RESET 0x18 /* Reset. */
1241 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
1242 #define MBC_GET_SET_ZIO_THRESHOLD 0x21 /* Get/SET ZIO THRESHOLD. */
1243 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
1244 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
1245 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
1246 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
1247 #define MBC_GET_MEM_OFFLOAD_CNTRL_STAT 0x34 /* Memory Offload ctrl/Stat*/
1248 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
1249 #define MBC_SET_GET_FC_LED_CONFIG 0x3b /* Set/Get FC LED config */
1250 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
1251 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
1252 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
1253 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
1254 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
1255 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
1256 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
1257 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
1258 #define MBC_CONFIGURE_VF 0x4b /* Configure VFs */
1259 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
1260 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
1261 #define MBC_PORT_LOGOUT 0x56 /* Port Logout request */
1262 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
1263 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
1264 #define MBC_GET_RNID_PARAMS 0x5a /* Get RNID parameters */
1265 #define MBC_DATA_RATE 0x5d /* Data Rate */
1266 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
1267 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
1268 /* Initialization Procedure */
1269 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
1270 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
1271 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
1272 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
1273 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
1274 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
1275 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
1276 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
1277 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
1278 #define MBC_LIP_RESET 0x6c /* LIP reset. */
1279 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
1280 /* commandd. */
1281 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
1282 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
1283 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
1284 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
1285 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
1286 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
1287 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
1288 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
1289 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
1290 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
1291 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
1292
1293 /*
1294 * all the Mt. Rainier mailbox command codes that clash with FC/FCoE ones
1295 * should be defined with MBC_MR_*
1296 */
1297 #define MBC_MR_DRV_SHUTDOWN 0x6A
1298
1299 /*
1300 * ISP24xx mailbox commands
1301 */
1302 #define MBC_WRITE_SERDES 0x3 /* Write serdes word. */
1303 #define MBC_READ_SERDES 0x4 /* Read serdes word. */
1304 #define MBC_LOAD_DUMP_MPI_RAM 0x5 /* Load/Dump MPI RAM. */
1305 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
1306 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
1307 #define MBC_PORT_PARAMS 0x1A /* Port iDMA Parameters. */
1308 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
1309 #define MBC_TRACE_CONTROL 0x27 /* Trace control command. */
1310 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
1311 #define MBC_WRITE_SFP 0x30 /* Write SFP Data. */
1312 #define MBC_READ_SFP 0x31 /* Read SFP Data. */
1313 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
1314 #define MBC_DPORT_DIAGNOSTICS 0x47 /* D-Port Diagnostics */
1315 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
1316 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
1317 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
1318 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
1319 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
1320 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
1321 #define MBC_LINK_INITIALIZATION 0x72 /* Do link initialization. */
1322 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
1323 #define MBC_PORT_RESET 0x120 /* Port Reset */
1324 #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */
1325 #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */
1326
1327 /*
1328 * ISP81xx mailbox commands
1329 */
1330 #define MBC_WRITE_MPI_REGISTER 0x01 /* Write MPI Register. */
1331
1332 /*
1333 * ISP8044 mailbox commands
1334 */
1335 #define MBC_SET_GET_ETH_SERDES_REG 0x150
1336 #define HCS_WRITE_SERDES 0x3
1337 #define HCS_READ_SERDES 0x4
1338
1339 /* Firmware return data sizes */
1340 #define FCAL_MAP_SIZE 128
1341
1342 /* Mailbox bit definitions for out_mb and in_mb */
1343 #define MBX_31 BIT_31
1344 #define MBX_30 BIT_30
1345 #define MBX_29 BIT_29
1346 #define MBX_28 BIT_28
1347 #define MBX_27 BIT_27
1348 #define MBX_26 BIT_26
1349 #define MBX_25 BIT_25
1350 #define MBX_24 BIT_24
1351 #define MBX_23 BIT_23
1352 #define MBX_22 BIT_22
1353 #define MBX_21 BIT_21
1354 #define MBX_20 BIT_20
1355 #define MBX_19 BIT_19
1356 #define MBX_18 BIT_18
1357 #define MBX_17 BIT_17
1358 #define MBX_16 BIT_16
1359 #define MBX_15 BIT_15
1360 #define MBX_14 BIT_14
1361 #define MBX_13 BIT_13
1362 #define MBX_12 BIT_12
1363 #define MBX_11 BIT_11
1364 #define MBX_10 BIT_10
1365 #define MBX_9 BIT_9
1366 #define MBX_8 BIT_8
1367 #define MBX_7 BIT_7
1368 #define MBX_6 BIT_6
1369 #define MBX_5 BIT_5
1370 #define MBX_4 BIT_4
1371 #define MBX_3 BIT_3
1372 #define MBX_2 BIT_2
1373 #define MBX_1 BIT_1
1374 #define MBX_0 BIT_0
1375
1376 #define RNID_TYPE_ELS_CMD 0x5
1377 #define RNID_TYPE_PORT_LOGIN 0x7
1378 #define RNID_BUFFER_CREDITS 0x8
1379 #define RNID_TYPE_SET_VERSION 0x9
1380 #define RNID_TYPE_ASIC_TEMP 0xC
1381
1382 #define ELS_CMD_MAP_SIZE 32
1383
1384 /*
1385 * Firmware state codes from get firmware state mailbox command
1386 */
1387 #define FSTATE_CONFIG_WAIT 0
1388 #define FSTATE_WAIT_AL_PA 1
1389 #define FSTATE_WAIT_LOGIN 2
1390 #define FSTATE_READY 3
1391 #define FSTATE_LOSS_OF_SYNC 4
1392 #define FSTATE_ERROR 5
1393 #define FSTATE_REINIT 6
1394 #define FSTATE_NON_PART 7
1395
1396 #define FSTATE_CONFIG_CORRECT 0
1397 #define FSTATE_P2P_RCV_LIP 1
1398 #define FSTATE_P2P_CHOOSE_LOOP 2
1399 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
1400 #define FSTATE_FATAL_ERROR 4
1401 #define FSTATE_LOOP_BACK_CONN 5
1402
1403 #define QLA27XX_IMG_STATUS_VER_MAJOR 0x01
1404 #define QLA27XX_IMG_STATUS_VER_MINOR 0x00
1405 #define QLA27XX_IMG_STATUS_SIGN 0xFACEFADE
1406 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1407 #define QLA28XX_IMG_STATUS_SIGN 0xFACEFADF
1408 #define QLA28XX_AUX_IMG_STATUS_SIGN 0xFACEFAED
1409 #define QLA27XX_DEFAULT_IMAGE 0
1410 #define QLA27XX_PRIMARY_IMAGE 1
1411 #define QLA27XX_SECONDARY_IMAGE 2
1412
1413 /*
1414 * Port Database structure definition
1415 * Little endian except where noted.
1416 */
1417 #define PORT_DATABASE_SIZE 128 /* bytes */
1418 typedef struct {
1419 uint8_t options;
1420 uint8_t control;
1421 uint8_t master_state;
1422 uint8_t slave_state;
1423 uint8_t reserved[2];
1424 uint8_t hard_address;
1425 uint8_t reserved_1;
1426 uint8_t port_id[4];
1427 uint8_t node_name[WWN_SIZE];
1428 uint8_t port_name[WWN_SIZE];
1429 __le16 execution_throttle;
1430 uint16_t execution_count;
1431 uint8_t reset_count;
1432 uint8_t reserved_2;
1433 uint16_t resource_allocation;
1434 uint16_t current_allocation;
1435 uint16_t queue_head;
1436 uint16_t queue_tail;
1437 uint16_t transmit_execution_list_next;
1438 uint16_t transmit_execution_list_previous;
1439 uint16_t common_features;
1440 uint16_t total_concurrent_sequences;
1441 uint16_t RO_by_information_category;
1442 uint8_t recipient;
1443 uint8_t initiator;
1444 uint16_t receive_data_size;
1445 uint16_t concurrent_sequences;
1446 uint16_t open_sequences_per_exchange;
1447 uint16_t lun_abort_flags;
1448 uint16_t lun_stop_flags;
1449 uint16_t stop_queue_head;
1450 uint16_t stop_queue_tail;
1451 uint16_t port_retry_timer;
1452 uint16_t next_sequence_id;
1453 uint16_t frame_count;
1454 uint16_t PRLI_payload_length;
1455 uint8_t prli_svc_param_word_0[2]; /* Big endian */
1456 /* Bits 15-0 of word 0 */
1457 uint8_t prli_svc_param_word_3[2]; /* Big endian */
1458 /* Bits 15-0 of word 3 */
1459 uint16_t loop_id;
1460 uint16_t extended_lun_info_list_pointer;
1461 uint16_t extended_lun_stop_list_pointer;
1462 } port_database_t;
1463
1464 /*
1465 * Port database slave/master states
1466 */
1467 #define PD_STATE_DISCOVERY 0
1468 #define PD_STATE_WAIT_DISCOVERY_ACK 1
1469 #define PD_STATE_PORT_LOGIN 2
1470 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
1471 #define PD_STATE_PROCESS_LOGIN 4
1472 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
1473 #define PD_STATE_PORT_LOGGED_IN 6
1474 #define PD_STATE_PORT_UNAVAILABLE 7
1475 #define PD_STATE_PROCESS_LOGOUT 8
1476 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
1477 #define PD_STATE_PORT_LOGOUT 10
1478 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
1479
1480
1481 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
1482 #define QLA_ZIO_DISABLED 0
1483 #define QLA_ZIO_DEFAULT_TIMER 2
1484
1485 /*
1486 * ISP Initialization Control Block.
1487 * Little endian except where noted.
1488 */
1489 #define ICB_VERSION 1
1490 typedef struct {
1491 uint8_t version;
1492 uint8_t reserved_1;
1493
1494 /*
1495 * LSB BIT 0 = Enable Hard Loop Id
1496 * LSB BIT 1 = Enable Fairness
1497 * LSB BIT 2 = Enable Full-Duplex
1498 * LSB BIT 3 = Enable Fast Posting
1499 * LSB BIT 4 = Enable Target Mode
1500 * LSB BIT 5 = Disable Initiator Mode
1501 * LSB BIT 6 = Enable ADISC
1502 * LSB BIT 7 = Enable Target Inquiry Data
1503 *
1504 * MSB BIT 0 = Enable PDBC Notify
1505 * MSB BIT 1 = Non Participating LIP
1506 * MSB BIT 2 = Descending Loop ID Search
1507 * MSB BIT 3 = Acquire Loop ID in LIPA
1508 * MSB BIT 4 = Stop PortQ on Full Status
1509 * MSB BIT 5 = Full Login after LIP
1510 * MSB BIT 6 = Node Name Option
1511 * MSB BIT 7 = Ext IFWCB enable bit
1512 */
1513 uint8_t firmware_options[2];
1514
1515 __le16 frame_payload_size;
1516 __le16 max_iocb_allocation;
1517 __le16 execution_throttle;
1518 uint8_t retry_count;
1519 uint8_t retry_delay; /* unused */
1520 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1521 uint16_t hard_address;
1522 uint8_t inquiry_data;
1523 uint8_t login_timeout;
1524 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1525
1526 __le16 request_q_outpointer;
1527 __le16 response_q_inpointer;
1528 __le16 request_q_length;
1529 __le16 response_q_length;
1530 __le64 request_q_address __packed;
1531 __le64 response_q_address __packed;
1532
1533 __le16 lun_enables;
1534 uint8_t command_resource_count;
1535 uint8_t immediate_notify_resource_count;
1536 __le16 timeout;
1537 uint8_t reserved_2[2];
1538
1539 /*
1540 * LSB BIT 0 = Timer Operation mode bit 0
1541 * LSB BIT 1 = Timer Operation mode bit 1
1542 * LSB BIT 2 = Timer Operation mode bit 2
1543 * LSB BIT 3 = Timer Operation mode bit 3
1544 * LSB BIT 4 = Init Config Mode bit 0
1545 * LSB BIT 5 = Init Config Mode bit 1
1546 * LSB BIT 6 = Init Config Mode bit 2
1547 * LSB BIT 7 = Enable Non part on LIHA failure
1548 *
1549 * MSB BIT 0 = Enable class 2
1550 * MSB BIT 1 = Enable ACK0
1551 * MSB BIT 2 =
1552 * MSB BIT 3 =
1553 * MSB BIT 4 = FC Tape Enable
1554 * MSB BIT 5 = Enable FC Confirm
1555 * MSB BIT 6 = Enable command queuing in target mode
1556 * MSB BIT 7 = No Logo On Link Down
1557 */
1558 uint8_t add_firmware_options[2];
1559
1560 uint8_t response_accumulation_timer;
1561 uint8_t interrupt_delay_timer;
1562
1563 /*
1564 * LSB BIT 0 = Enable Read xfr_rdy
1565 * LSB BIT 1 = Soft ID only
1566 * LSB BIT 2 =
1567 * LSB BIT 3 =
1568 * LSB BIT 4 = FCP RSP Payload [0]
1569 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1570 * LSB BIT 6 = Enable Out-of-Order frame handling
1571 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1572 *
1573 * MSB BIT 0 = Sbus enable - 2300
1574 * MSB BIT 1 =
1575 * MSB BIT 2 =
1576 * MSB BIT 3 =
1577 * MSB BIT 4 = LED mode
1578 * MSB BIT 5 = enable 50 ohm termination
1579 * MSB BIT 6 = Data Rate (2300 only)
1580 * MSB BIT 7 = Data Rate (2300 only)
1581 */
1582 uint8_t special_options[2];
1583
1584 uint8_t reserved_3[26];
1585 } init_cb_t;
1586
1587 /* Special Features Control Block */
1588 struct init_sf_cb {
1589 uint8_t format;
1590 uint8_t reserved0;
1591 /*
1592 * BIT 15-14 = Reserved
1593 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled)
1594 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled)
1595 * BIT 11-0 = Reserved
1596 */
1597 __le16 flags;
1598 uint8_t reserved1[32];
1599 uint16_t discard_OHRB_timeout_value;
1600 uint16_t remote_write_opt_queue_num;
1601 uint8_t reserved2[40];
1602 uint8_t scm_related_parameter[16];
1603 uint8_t reserved3[32];
1604 };
1605
1606 /*
1607 * Get Link Status mailbox command return buffer.
1608 */
1609 #define GLSO_SEND_RPS BIT_0
1610 #define GLSO_USE_DID BIT_3
1611
1612 struct link_statistics {
1613 __le32 link_fail_cnt;
1614 __le32 loss_sync_cnt;
1615 __le32 loss_sig_cnt;
1616 __le32 prim_seq_err_cnt;
1617 __le32 inval_xmit_word_cnt;
1618 __le32 inval_crc_cnt;
1619 __le32 lip_cnt;
1620 __le32 link_up_cnt;
1621 __le32 link_down_loop_init_tmo;
1622 __le32 link_down_los;
1623 __le32 link_down_loss_rcv_clk;
1624 uint32_t reserved0[5];
1625 __le32 port_cfg_chg;
1626 uint32_t reserved1[11];
1627 __le32 rsp_q_full;
1628 __le32 atio_q_full;
1629 __le32 drop_ae;
1630 __le32 els_proto_err;
1631 __le32 reserved2;
1632 __le32 tx_frames;
1633 __le32 rx_frames;
1634 __le32 discarded_frames;
1635 __le32 dropped_frames;
1636 uint32_t reserved3;
1637 __le32 nos_rcvd;
1638 uint32_t reserved4[4];
1639 __le32 tx_prjt;
1640 __le32 rcv_exfail;
1641 __le32 rcv_abts;
1642 __le32 seq_frm_miss;
1643 __le32 corr_err;
1644 __le32 mb_rqst;
1645 __le32 nport_full;
1646 __le32 eofa;
1647 uint32_t reserved5;
1648 __le64 fpm_recv_word_cnt;
1649 __le64 fpm_disc_word_cnt;
1650 __le64 fpm_xmit_word_cnt;
1651 uint32_t reserved6[70];
1652 };
1653
1654 /*
1655 * NVRAM Command values.
1656 */
1657 #define NV_START_BIT BIT_2
1658 #define NV_WRITE_OP (BIT_26+BIT_24)
1659 #define NV_READ_OP (BIT_26+BIT_25)
1660 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
1661 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
1662 #define NV_DELAY_COUNT 10
1663
1664 /*
1665 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
1666 */
1667 typedef struct {
1668 /*
1669 * NVRAM header
1670 */
1671 uint8_t id[4];
1672 uint8_t nvram_version;
1673 uint8_t reserved_0;
1674
1675 /*
1676 * NVRAM RISC parameter block
1677 */
1678 uint8_t parameter_block_version;
1679 uint8_t reserved_1;
1680
1681 /*
1682 * LSB BIT 0 = Enable Hard Loop Id
1683 * LSB BIT 1 = Enable Fairness
1684 * LSB BIT 2 = Enable Full-Duplex
1685 * LSB BIT 3 = Enable Fast Posting
1686 * LSB BIT 4 = Enable Target Mode
1687 * LSB BIT 5 = Disable Initiator Mode
1688 * LSB BIT 6 = Enable ADISC
1689 * LSB BIT 7 = Enable Target Inquiry Data
1690 *
1691 * MSB BIT 0 = Enable PDBC Notify
1692 * MSB BIT 1 = Non Participating LIP
1693 * MSB BIT 2 = Descending Loop ID Search
1694 * MSB BIT 3 = Acquire Loop ID in LIPA
1695 * MSB BIT 4 = Stop PortQ on Full Status
1696 * MSB BIT 5 = Full Login after LIP
1697 * MSB BIT 6 = Node Name Option
1698 * MSB BIT 7 = Ext IFWCB enable bit
1699 */
1700 uint8_t firmware_options[2];
1701
1702 __le16 frame_payload_size;
1703 __le16 max_iocb_allocation;
1704 __le16 execution_throttle;
1705 uint8_t retry_count;
1706 uint8_t retry_delay; /* unused */
1707 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1708 uint16_t hard_address;
1709 uint8_t inquiry_data;
1710 uint8_t login_timeout;
1711 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1712
1713 /*
1714 * LSB BIT 0 = Timer Operation mode bit 0
1715 * LSB BIT 1 = Timer Operation mode bit 1
1716 * LSB BIT 2 = Timer Operation mode bit 2
1717 * LSB BIT 3 = Timer Operation mode bit 3
1718 * LSB BIT 4 = Init Config Mode bit 0
1719 * LSB BIT 5 = Init Config Mode bit 1
1720 * LSB BIT 6 = Init Config Mode bit 2
1721 * LSB BIT 7 = Enable Non part on LIHA failure
1722 *
1723 * MSB BIT 0 = Enable class 2
1724 * MSB BIT 1 = Enable ACK0
1725 * MSB BIT 2 =
1726 * MSB BIT 3 =
1727 * MSB BIT 4 = FC Tape Enable
1728 * MSB BIT 5 = Enable FC Confirm
1729 * MSB BIT 6 = Enable command queuing in target mode
1730 * MSB BIT 7 = No Logo On Link Down
1731 */
1732 uint8_t add_firmware_options[2];
1733
1734 uint8_t response_accumulation_timer;
1735 uint8_t interrupt_delay_timer;
1736
1737 /*
1738 * LSB BIT 0 = Enable Read xfr_rdy
1739 * LSB BIT 1 = Soft ID only
1740 * LSB BIT 2 =
1741 * LSB BIT 3 =
1742 * LSB BIT 4 = FCP RSP Payload [0]
1743 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1744 * LSB BIT 6 = Enable Out-of-Order frame handling
1745 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1746 *
1747 * MSB BIT 0 = Sbus enable - 2300
1748 * MSB BIT 1 =
1749 * MSB BIT 2 =
1750 * MSB BIT 3 =
1751 * MSB BIT 4 = LED mode
1752 * MSB BIT 5 = enable 50 ohm termination
1753 * MSB BIT 6 = Data Rate (2300 only)
1754 * MSB BIT 7 = Data Rate (2300 only)
1755 */
1756 uint8_t special_options[2];
1757
1758 /* Reserved for expanded RISC parameter block */
1759 uint8_t reserved_2[22];
1760
1761 /*
1762 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1763 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1764 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1765 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1766 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1767 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1768 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1769 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1770 *
1771 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1772 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1773 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1774 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1775 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1776 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1777 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1778 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1779 *
1780 * LSB BIT 0 = Output Swing 1G bit 0
1781 * LSB BIT 1 = Output Swing 1G bit 1
1782 * LSB BIT 2 = Output Swing 1G bit 2
1783 * LSB BIT 3 = Output Emphasis 1G bit 0
1784 * LSB BIT 4 = Output Emphasis 1G bit 1
1785 * LSB BIT 5 = Output Swing 2G bit 0
1786 * LSB BIT 6 = Output Swing 2G bit 1
1787 * LSB BIT 7 = Output Swing 2G bit 2
1788 *
1789 * MSB BIT 0 = Output Emphasis 2G bit 0
1790 * MSB BIT 1 = Output Emphasis 2G bit 1
1791 * MSB BIT 2 = Output Enable
1792 * MSB BIT 3 =
1793 * MSB BIT 4 =
1794 * MSB BIT 5 =
1795 * MSB BIT 6 =
1796 * MSB BIT 7 =
1797 */
1798 uint8_t seriallink_options[4];
1799
1800 /*
1801 * NVRAM host parameter block
1802 *
1803 * LSB BIT 0 = Enable spinup delay
1804 * LSB BIT 1 = Disable BIOS
1805 * LSB BIT 2 = Enable Memory Map BIOS
1806 * LSB BIT 3 = Enable Selectable Boot
1807 * LSB BIT 4 = Disable RISC code load
1808 * LSB BIT 5 = Set cache line size 1
1809 * LSB BIT 6 = PCI Parity Disable
1810 * LSB BIT 7 = Enable extended logging
1811 *
1812 * MSB BIT 0 = Enable 64bit addressing
1813 * MSB BIT 1 = Enable lip reset
1814 * MSB BIT 2 = Enable lip full login
1815 * MSB BIT 3 = Enable target reset
1816 * MSB BIT 4 = Enable database storage
1817 * MSB BIT 5 = Enable cache flush read
1818 * MSB BIT 6 = Enable database load
1819 * MSB BIT 7 = Enable alternate WWN
1820 */
1821 uint8_t host_p[2];
1822
1823 uint8_t boot_node_name[WWN_SIZE];
1824 uint8_t boot_lun_number;
1825 uint8_t reset_delay;
1826 uint8_t port_down_retry_count;
1827 uint8_t boot_id_number;
1828 __le16 max_luns_per_target;
1829 uint8_t fcode_boot_port_name[WWN_SIZE];
1830 uint8_t alternate_port_name[WWN_SIZE];
1831 uint8_t alternate_node_name[WWN_SIZE];
1832
1833 /*
1834 * BIT 0 = Selective Login
1835 * BIT 1 = Alt-Boot Enable
1836 * BIT 2 =
1837 * BIT 3 = Boot Order List
1838 * BIT 4 =
1839 * BIT 5 = Selective LUN
1840 * BIT 6 =
1841 * BIT 7 = unused
1842 */
1843 uint8_t efi_parameters;
1844
1845 uint8_t link_down_timeout;
1846
1847 uint8_t adapter_id[16];
1848
1849 uint8_t alt1_boot_node_name[WWN_SIZE];
1850 uint16_t alt1_boot_lun_number;
1851 uint8_t alt2_boot_node_name[WWN_SIZE];
1852 uint16_t alt2_boot_lun_number;
1853 uint8_t alt3_boot_node_name[WWN_SIZE];
1854 uint16_t alt3_boot_lun_number;
1855 uint8_t alt4_boot_node_name[WWN_SIZE];
1856 uint16_t alt4_boot_lun_number;
1857 uint8_t alt5_boot_node_name[WWN_SIZE];
1858 uint16_t alt5_boot_lun_number;
1859 uint8_t alt6_boot_node_name[WWN_SIZE];
1860 uint16_t alt6_boot_lun_number;
1861 uint8_t alt7_boot_node_name[WWN_SIZE];
1862 uint16_t alt7_boot_lun_number;
1863
1864 uint8_t reserved_3[2];
1865
1866 /* Offset 200-215 : Model Number */
1867 uint8_t model_number[16];
1868
1869 /* OEM related items */
1870 uint8_t oem_specific[16];
1871
1872 /*
1873 * NVRAM Adapter Features offset 232-239
1874 *
1875 * LSB BIT 0 = External GBIC
1876 * LSB BIT 1 = Risc RAM parity
1877 * LSB BIT 2 = Buffer Plus Module
1878 * LSB BIT 3 = Multi Chip Adapter
1879 * LSB BIT 4 = Internal connector
1880 * LSB BIT 5 =
1881 * LSB BIT 6 =
1882 * LSB BIT 7 =
1883 *
1884 * MSB BIT 0 =
1885 * MSB BIT 1 =
1886 * MSB BIT 2 =
1887 * MSB BIT 3 =
1888 * MSB BIT 4 =
1889 * MSB BIT 5 =
1890 * MSB BIT 6 =
1891 * MSB BIT 7 =
1892 */
1893 uint8_t adapter_features[2];
1894
1895 uint8_t reserved_4[16];
1896
1897 /* Subsystem vendor ID for ISP2200 */
1898 uint16_t subsystem_vendor_id_2200;
1899
1900 /* Subsystem device ID for ISP2200 */
1901 uint16_t subsystem_device_id_2200;
1902
1903 uint8_t reserved_5;
1904 uint8_t checksum;
1905 } nvram_t;
1906
1907 /*
1908 * ISP queue - response queue entry definition.
1909 */
1910 typedef struct {
1911 uint8_t entry_type; /* Entry type. */
1912 uint8_t entry_count; /* Entry count. */
1913 uint8_t sys_define; /* System defined. */
1914 uint8_t entry_status; /* Entry Status. */
1915 uint32_t handle; /* System defined handle */
1916 uint8_t data[52];
1917 uint32_t signature;
1918 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1919 } response_t;
1920
1921 /*
1922 * ISP queue - ATIO queue entry definition.
1923 */
1924 struct atio {
1925 uint8_t entry_type; /* Entry type. */
1926 uint8_t entry_count; /* Entry count. */
1927 __le16 attr_n_length;
1928 uint8_t data[56];
1929 uint32_t signature;
1930 #define ATIO_PROCESSED 0xDEADDEAD /* Signature */
1931 };
1932
1933 typedef union {
1934 __le16 extended;
1935 struct {
1936 uint8_t reserved;
1937 uint8_t standard;
1938 } id;
1939 } target_id_t;
1940
1941 #define SET_TARGET_ID(ha, to, from) \
1942 do { \
1943 if (HAS_EXTENDED_IDS(ha)) \
1944 to.extended = cpu_to_le16(from); \
1945 else \
1946 to.id.standard = (uint8_t)from; \
1947 } while (0)
1948
1949 /*
1950 * ISP queue - command entry structure definition.
1951 */
1952 #define COMMAND_TYPE 0x11 /* Command entry */
1953 typedef struct {
1954 uint8_t entry_type; /* Entry type. */
1955 uint8_t entry_count; /* Entry count. */
1956 uint8_t sys_define; /* System defined. */
1957 uint8_t entry_status; /* Entry Status. */
1958 uint32_t handle; /* System handle. */
1959 target_id_t target; /* SCSI ID */
1960 __le16 lun; /* SCSI LUN */
1961 __le16 control_flags; /* Control flags. */
1962 #define CF_WRITE BIT_6
1963 #define CF_READ BIT_5
1964 #define CF_SIMPLE_TAG BIT_3
1965 #define CF_ORDERED_TAG BIT_2
1966 #define CF_HEAD_TAG BIT_1
1967 uint16_t reserved_1;
1968 __le16 timeout; /* Command timeout. */
1969 __le16 dseg_count; /* Data segment count. */
1970 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1971 __le32 byte_count; /* Total byte count. */
1972 union {
1973 struct dsd32 dsd32[3];
1974 struct dsd64 dsd64[2];
1975 };
1976 } cmd_entry_t;
1977
1978 /*
1979 * ISP queue - 64-Bit addressing, command entry structure definition.
1980 */
1981 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1982 typedef struct {
1983 uint8_t entry_type; /* Entry type. */
1984 uint8_t entry_count; /* Entry count. */
1985 uint8_t sys_define; /* System defined. */
1986 uint8_t entry_status; /* Entry Status. */
1987 uint32_t handle; /* System handle. */
1988 target_id_t target; /* SCSI ID */
1989 __le16 lun; /* SCSI LUN */
1990 __le16 control_flags; /* Control flags. */
1991 uint16_t reserved_1;
1992 __le16 timeout; /* Command timeout. */
1993 __le16 dseg_count; /* Data segment count. */
1994 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1995 uint32_t byte_count; /* Total byte count. */
1996 struct dsd64 dsd[2];
1997 } cmd_a64_entry_t, request_t;
1998
1999 /*
2000 * ISP queue - continuation entry structure definition.
2001 */
2002 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
2003 typedef struct {
2004 uint8_t entry_type; /* Entry type. */
2005 uint8_t entry_count; /* Entry count. */
2006 uint8_t sys_define; /* System defined. */
2007 uint8_t entry_status; /* Entry Status. */
2008 uint32_t reserved;
2009 struct dsd32 dsd[7];
2010 } cont_entry_t;
2011
2012 /*
2013 * ISP queue - 64-Bit addressing, continuation entry structure definition.
2014 */
2015 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
2016 typedef struct {
2017 uint8_t entry_type; /* Entry type. */
2018 uint8_t entry_count; /* Entry count. */
2019 uint8_t sys_define; /* System defined. */
2020 uint8_t entry_status; /* Entry Status. */
2021 struct dsd64 dsd[5];
2022 } cont_a64_entry_t;
2023
2024 #define PO_MODE_DIF_INSERT 0
2025 #define PO_MODE_DIF_REMOVE 1
2026 #define PO_MODE_DIF_PASS 2
2027 #define PO_MODE_DIF_REPLACE 3
2028 #define PO_MODE_DIF_TCP_CKSUM 6
2029 #define PO_ENABLE_INCR_GUARD_SEED BIT_3
2030 #define PO_DISABLE_GUARD_CHECK BIT_4
2031 #define PO_DISABLE_INCR_REF_TAG BIT_5
2032 #define PO_DIS_HEADER_MODE BIT_7
2033 #define PO_ENABLE_DIF_BUNDLING BIT_8
2034 #define PO_DIS_FRAME_MODE BIT_9
2035 #define PO_DIS_VALD_APP_ESC BIT_10 /* Dis validation for escape tag/ffffh */
2036 #define PO_DIS_VALD_APP_REF_ESC BIT_11
2037
2038 #define PO_DIS_APP_TAG_REPL BIT_12 /* disable REG Tag replacement */
2039 #define PO_DIS_REF_TAG_REPL BIT_13
2040 #define PO_DIS_APP_TAG_VALD BIT_14 /* disable REF Tag validation */
2041 #define PO_DIS_REF_TAG_VALD BIT_15
2042
2043 /*
2044 * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
2045 */
2046 struct crc_context {
2047 uint32_t handle; /* System handle. */
2048 __le32 ref_tag;
2049 __le16 app_tag;
2050 uint8_t ref_tag_mask[4]; /* Validation/Replacement Mask*/
2051 uint8_t app_tag_mask[2]; /* Validation/Replacement Mask*/
2052 __le16 guard_seed; /* Initial Guard Seed */
2053 __le16 prot_opts; /* Requested Data Protection Mode */
2054 __le16 blk_size; /* Data size in bytes */
2055 __le16 runt_blk_guard; /* Guard value for runt block (tape
2056 * only) */
2057 __le32 byte_count; /* Total byte count/ total data
2058 * transfer count */
2059 union {
2060 struct {
2061 uint32_t reserved_1;
2062 uint16_t reserved_2;
2063 uint16_t reserved_3;
2064 uint32_t reserved_4;
2065 struct dsd64 data_dsd[1];
2066 uint32_t reserved_5[2];
2067 uint32_t reserved_6;
2068 } nobundling;
2069 struct {
2070 __le32 dif_byte_count; /* Total DIF byte
2071 * count */
2072 uint16_t reserved_1;
2073 __le16 dseg_count; /* Data segment count */
2074 uint32_t reserved_2;
2075 struct dsd64 data_dsd[1];
2076 struct dsd64 dif_dsd;
2077 } bundling;
2078 } u;
2079
2080 struct fcp_cmnd fcp_cmnd;
2081 dma_addr_t crc_ctx_dma;
2082 /* List of DMA context transfers */
2083 struct list_head dsd_list;
2084
2085 /* List of DIF Bundling context DMA address */
2086 struct list_head ldif_dsd_list;
2087 u8 no_ldif_dsd;
2088
2089 struct list_head ldif_dma_hndl_list;
2090 u32 dif_bundl_len;
2091 u8 no_dif_bundl;
2092 /* This structure should not exceed 512 bytes */
2093 };
2094
2095 #define CRC_CONTEXT_LEN_FW (offsetof(struct crc_context, fcp_cmnd.lun))
2096 #define CRC_CONTEXT_FCPCMND_OFF (offsetof(struct crc_context, fcp_cmnd.lun))
2097
2098 /*
2099 * ISP queue - status entry structure definition.
2100 */
2101 #define STATUS_TYPE 0x03 /* Status entry. */
2102 typedef struct {
2103 uint8_t entry_type; /* Entry type. */
2104 uint8_t entry_count; /* Entry count. */
2105 uint8_t sys_define; /* System defined. */
2106 uint8_t entry_status; /* Entry Status. */
2107 uint32_t handle; /* System handle. */
2108 __le16 scsi_status; /* SCSI status. */
2109 __le16 comp_status; /* Completion status. */
2110 __le16 state_flags; /* State flags. */
2111 __le16 status_flags; /* Status flags. */
2112 __le16 rsp_info_len; /* Response Info Length. */
2113 __le16 req_sense_length; /* Request sense data length. */
2114 __le32 residual_length; /* Residual transfer length. */
2115 uint8_t rsp_info[8]; /* FCP response information. */
2116 uint8_t req_sense_data[32]; /* Request sense data. */
2117 } sts_entry_t;
2118
2119 /*
2120 * Status entry entry status
2121 */
2122 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
2123 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
2124 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
2125 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
2126 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
2127 #define RF_BUSY BIT_1 /* Busy */
2128 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
2129 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
2130 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
2131 RF_INV_E_TYPE)
2132
2133 /*
2134 * Status entry SCSI status bit definitions.
2135 */
2136 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
2137 #define SS_RESIDUAL_UNDER BIT_11
2138 #define SS_RESIDUAL_OVER BIT_10
2139 #define SS_SENSE_LEN_VALID BIT_9
2140 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
2141 #define SS_SCSI_STATUS_BYTE 0xff
2142
2143 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
2144 #define SS_BUSY_CONDITION BIT_3
2145 #define SS_CONDITION_MET BIT_2
2146 #define SS_CHECK_CONDITION BIT_1
2147
2148 /*
2149 * Status entry completion status
2150 */
2151 #define CS_COMPLETE 0x0 /* No errors */
2152 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
2153 #define CS_DMA 0x2 /* A DMA direction error. */
2154 #define CS_TRANSPORT 0x3 /* Transport error. */
2155 #define CS_RESET 0x4 /* SCSI bus reset occurred */
2156 #define CS_ABORTED 0x5 /* System aborted command. */
2157 #define CS_TIMEOUT 0x6 /* Timeout error. */
2158 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
2159 #define CS_DIF_ERROR 0xC /* DIF error detected */
2160
2161 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
2162 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
2163 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
2164 /* (selection timeout) */
2165 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
2166 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
2167 #define CS_PORT_BUSY 0x2B /* Port Busy */
2168 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
2169 #define CS_IOCB_ERROR 0x31 /* Generic error for IOCB request
2170 failure */
2171 #define CS_REJECT_RECEIVED 0x4E /* Reject received */
2172 #define CS_EDIF_AUTH_ERROR 0x63 /* decrypt error */
2173 #define CS_EDIF_PAD_LEN_ERROR 0x65 /* pad > frame size, not 4byte align */
2174 #define CS_EDIF_INV_REQ 0x66 /* invalid request */
2175 #define CS_EDIF_SPI_ERROR 0x67 /* rx frame unable to locate sa */
2176 #define CS_EDIF_HDR_ERROR 0x69 /* data frame != expected len */
2177 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
2178 #define CS_UNKNOWN 0x81 /* Driver defined */
2179 #define CS_RETRY 0x82 /* Driver defined */
2180 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
2181
2182 #define CS_BIDIR_RD_OVERRUN 0x700
2183 #define CS_BIDIR_RD_WR_OVERRUN 0x707
2184 #define CS_BIDIR_RD_OVERRUN_WR_UNDERRUN 0x715
2185 #define CS_BIDIR_RD_UNDERRUN 0x1500
2186 #define CS_BIDIR_RD_UNDERRUN_WR_OVERRUN 0x1507
2187 #define CS_BIDIR_RD_WR_UNDERRUN 0x1515
2188 #define CS_BIDIR_DMA 0x200
2189 /*
2190 * Status entry status flags
2191 */
2192 #define SF_ABTS_TERMINATED BIT_10
2193 #define SF_LOGOUT_SENT BIT_13
2194
2195 /*
2196 * ISP queue - status continuation entry structure definition.
2197 */
2198 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
2199 typedef struct {
2200 uint8_t entry_type; /* Entry type. */
2201 uint8_t entry_count; /* Entry count. */
2202 uint8_t sys_define; /* System defined. */
2203 uint8_t entry_status; /* Entry Status. */
2204 uint8_t data[60]; /* data */
2205 } sts_cont_entry_t;
2206
2207 /*
2208 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
2209 * structure definition.
2210 */
2211 #define STATUS_TYPE_21 0x21 /* Status entry. */
2212 typedef struct {
2213 uint8_t entry_type; /* Entry type. */
2214 uint8_t entry_count; /* Entry count. */
2215 uint8_t handle_count; /* Handle count. */
2216 uint8_t entry_status; /* Entry Status. */
2217 uint32_t handle[15]; /* System handles. */
2218 } sts21_entry_t;
2219
2220 /*
2221 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
2222 * structure definition.
2223 */
2224 #define STATUS_TYPE_22 0x22 /* Status entry. */
2225 typedef struct {
2226 uint8_t entry_type; /* Entry type. */
2227 uint8_t entry_count; /* Entry count. */
2228 uint8_t handle_count; /* Handle count. */
2229 uint8_t entry_status; /* Entry Status. */
2230 uint16_t handle[30]; /* System handles. */
2231 } sts22_entry_t;
2232
2233 /*
2234 * ISP queue - marker entry structure definition.
2235 */
2236 #define MARKER_TYPE 0x04 /* Marker entry. */
2237 typedef struct {
2238 uint8_t entry_type; /* Entry type. */
2239 uint8_t entry_count; /* Entry count. */
2240 uint8_t handle_count; /* Handle count. */
2241 uint8_t entry_status; /* Entry Status. */
2242 uint32_t sys_define_2; /* System defined. */
2243 target_id_t target; /* SCSI ID */
2244 uint8_t modifier; /* Modifier (7-0). */
2245 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
2246 #define MK_SYNC_ID 1 /* Synchronize ID */
2247 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
2248 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
2249 /* clear port changed, */
2250 /* use sequence number. */
2251 uint8_t reserved_1;
2252 __le16 sequence_number; /* Sequence number of event */
2253 __le16 lun; /* SCSI LUN */
2254 uint8_t reserved_2[48];
2255 } mrk_entry_t;
2256
2257 /*
2258 * ISP queue - Management Server entry structure definition.
2259 */
2260 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
2261 typedef struct {
2262 uint8_t entry_type; /* Entry type. */
2263 uint8_t entry_count; /* Entry count. */
2264 uint8_t handle_count; /* Handle count. */
2265 uint8_t entry_status; /* Entry Status. */
2266 uint32_t handle1; /* System handle. */
2267 target_id_t loop_id;
2268 __le16 status;
2269 __le16 control_flags; /* Control flags. */
2270 uint16_t reserved2;
2271 __le16 timeout;
2272 __le16 cmd_dsd_count;
2273 __le16 total_dsd_count;
2274 uint8_t type;
2275 uint8_t r_ctl;
2276 __le16 rx_id;
2277 uint16_t reserved3;
2278 uint32_t handle2;
2279 __le32 rsp_bytecount;
2280 __le32 req_bytecount;
2281 struct dsd64 req_dsd;
2282 struct dsd64 rsp_dsd;
2283 } ms_iocb_entry_t;
2284
2285 #define SCM_EDC_ACC_RECEIVED BIT_6
2286 #define SCM_RDF_ACC_RECEIVED BIT_7
2287
2288 /*
2289 * ISP queue - Mailbox Command entry structure definition.
2290 */
2291 #define MBX_IOCB_TYPE 0x39
2292 struct mbx_entry {
2293 uint8_t entry_type;
2294 uint8_t entry_count;
2295 uint8_t sys_define1;
2296 /* Use sys_define1 for source type */
2297 #define SOURCE_SCSI 0x00
2298 #define SOURCE_IP 0x01
2299 #define SOURCE_VI 0x02
2300 #define SOURCE_SCTP 0x03
2301 #define SOURCE_MP 0x04
2302 #define SOURCE_MPIOCTL 0x05
2303 #define SOURCE_ASYNC_IOCB 0x07
2304
2305 uint8_t entry_status;
2306
2307 uint32_t handle;
2308 target_id_t loop_id;
2309
2310 __le16 status;
2311 __le16 state_flags;
2312 __le16 status_flags;
2313
2314 uint32_t sys_define2[2];
2315
2316 __le16 mb0;
2317 __le16 mb1;
2318 __le16 mb2;
2319 __le16 mb3;
2320 __le16 mb6;
2321 __le16 mb7;
2322 __le16 mb9;
2323 __le16 mb10;
2324 uint32_t reserved_2[2];
2325 uint8_t node_name[WWN_SIZE];
2326 uint8_t port_name[WWN_SIZE];
2327 };
2328
2329 #ifndef IMMED_NOTIFY_TYPE
2330 #define IMMED_NOTIFY_TYPE 0x0D /* Immediate notify entry. */
2331 /*
2332 * ISP queue - immediate notify entry structure definition.
2333 * This is sent by the ISP to the Target driver.
2334 * This IOCB would have report of events sent by the
2335 * initiator, that needs to be handled by the target
2336 * driver immediately.
2337 */
2338 struct imm_ntfy_from_isp {
2339 uint8_t entry_type; /* Entry type. */
2340 uint8_t entry_count; /* Entry count. */
2341 uint8_t sys_define; /* System defined. */
2342 uint8_t entry_status; /* Entry Status. */
2343 union {
2344 struct {
2345 __le32 sys_define_2; /* System defined. */
2346 target_id_t target;
2347 __le16 lun;
2348 uint8_t target_id;
2349 uint8_t reserved_1;
2350 __le16 status_modifier;
2351 __le16 status;
2352 __le16 task_flags;
2353 __le16 seq_id;
2354 __le16 srr_rx_id;
2355 __le32 srr_rel_offs;
2356 __le16 srr_ui;
2357 #define SRR_IU_DATA_IN 0x1
2358 #define SRR_IU_DATA_OUT 0x5
2359 #define SRR_IU_STATUS 0x7
2360 __le16 srr_ox_id;
2361 uint8_t reserved_2[28];
2362 } isp2x;
2363 struct {
2364 uint32_t reserved;
2365 __le16 nport_handle;
2366 uint16_t reserved_2;
2367 __le16 flags;
2368 #define NOTIFY24XX_FLAGS_FCSP BIT_5
2369 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
2370 #define NOTIFY24XX_FLAGS_PUREX_IOCB BIT_0
2371 __le16 srr_rx_id;
2372 __le16 status;
2373 uint8_t status_subcode;
2374 uint8_t fw_handle;
2375 __le32 exchange_address;
2376 __le32 srr_rel_offs;
2377 __le16 srr_ui;
2378 __le16 srr_ox_id;
2379 union {
2380 struct {
2381 uint8_t node_name[8];
2382 } plogi; /* PLOGI/ADISC/PDISC */
2383 struct {
2384 /* PRLI word 3 bit 0-15 */
2385 __le16 wd3_lo;
2386 uint8_t resv0[6];
2387 } prli;
2388 struct {
2389 uint8_t port_id[3];
2390 uint8_t resv1;
2391 __le16 nport_handle;
2392 uint16_t resv2;
2393 } req_els;
2394 } u;
2395 uint8_t port_name[8];
2396 uint8_t resv3[3];
2397 uint8_t vp_index;
2398 uint32_t reserved_5;
2399 uint8_t port_id[3];
2400 uint8_t reserved_6;
2401 } isp24;
2402 } u;
2403 uint16_t reserved_7;
2404 __le16 ox_id;
2405 } __packed;
2406 #endif
2407
2408 /*
2409 * ISP request and response queue entry sizes
2410 */
2411 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
2412 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
2413
2414
2415
2416 /*
2417 * Switch info gathering structure.
2418 */
2419 typedef struct {
2420 port_id_t d_id;
2421 uint8_t node_name[WWN_SIZE];
2422 uint8_t port_name[WWN_SIZE];
2423 uint8_t fabric_port_name[WWN_SIZE];
2424 uint16_t fp_speed;
2425 uint8_t fc4_type;
2426 uint8_t fc4_features;
2427 } sw_info_t;
2428
2429 /* FCP-4 types */
2430 #define FC4_TYPE_FCP_SCSI 0x08
2431 #define FC4_TYPE_NVME 0x28
2432 #define FC4_TYPE_OTHER 0x0
2433 #define FC4_TYPE_UNKNOWN 0xff
2434
2435 /* mailbox command 4G & above */
2436 struct mbx_24xx_entry {
2437 uint8_t entry_type;
2438 uint8_t entry_count;
2439 uint8_t sys_define1;
2440 uint8_t entry_status;
2441 uint32_t handle;
2442 uint16_t mb[28];
2443 };
2444
2445 #define IOCB_SIZE 64
2446
2447 /*
2448 * Fibre channel port type.
2449 */
2450 typedef enum {
2451 FCT_UNKNOWN,
2452 FCT_BROADCAST = 0x01,
2453 FCT_INITIATOR = 0x02,
2454 FCT_TARGET = 0x04,
2455 FCT_NVME_INITIATOR = 0x10,
2456 FCT_NVME_TARGET = 0x20,
2457 FCT_NVME_DISCOVERY = 0x40,
2458 FCT_NVME = 0xf0,
2459 } fc_port_type_t;
2460
2461 enum qla_sess_deletion {
2462 QLA_SESS_DELETION_NONE = 0,
2463 QLA_SESS_DELETION_IN_PROGRESS,
2464 QLA_SESS_DELETED,
2465 };
2466
2467 enum qlt_plogi_link_t {
2468 QLT_PLOGI_LINK_SAME_WWN,
2469 QLT_PLOGI_LINK_CONFLICT,
2470 QLT_PLOGI_LINK_MAX
2471 };
2472
2473 struct qlt_plogi_ack_t {
2474 struct list_head list;
2475 struct imm_ntfy_from_isp iocb;
2476 port_id_t id;
2477 int ref_count;
2478 void *fcport;
2479 };
2480
2481 struct ct_sns_desc {
2482 struct ct_sns_pkt *ct_sns;
2483 dma_addr_t ct_sns_dma;
2484 };
2485
2486 enum discovery_state {
2487 DSC_DELETED,
2488 DSC_GNN_ID,
2489 DSC_GNL,
2490 DSC_LOGIN_PEND,
2491 DSC_LOGIN_FAILED,
2492 DSC_GPDB,
2493 DSC_UPD_FCPORT,
2494 DSC_LOGIN_COMPLETE,
2495 DSC_ADISC,
2496 DSC_DELETE_PEND,
2497 DSC_LOGIN_AUTH_PEND,
2498 };
2499
2500 enum login_state { /* FW control Target side */
2501 DSC_LS_LLIOCB_SENT = 2,
2502 DSC_LS_PLOGI_PEND,
2503 DSC_LS_PLOGI_COMP,
2504 DSC_LS_PRLI_PEND,
2505 DSC_LS_PRLI_COMP,
2506 DSC_LS_PORT_UNAVAIL,
2507 DSC_LS_PRLO_PEND = 9,
2508 DSC_LS_LOGO_PEND,
2509 };
2510
2511 enum rscn_addr_format {
2512 RSCN_PORT_ADDR,
2513 RSCN_AREA_ADDR,
2514 RSCN_DOM_ADDR,
2515 RSCN_FAB_ADDR,
2516 };
2517
2518 /*
2519 * Fibre channel port structure.
2520 */
2521 typedef struct fc_port {
2522 struct list_head list;
2523 struct scsi_qla_host *vha;
2524
2525 unsigned int conf_compl_supported:1;
2526 unsigned int deleted:2;
2527 unsigned int free_pending:1;
2528 unsigned int local:1;
2529 unsigned int logout_on_delete:1;
2530 unsigned int logo_ack_needed:1;
2531 unsigned int keep_nport_handle:1;
2532 unsigned int send_els_logo:1;
2533 unsigned int login_pause:1;
2534 unsigned int login_succ:1;
2535 unsigned int query:1;
2536 unsigned int id_changed:1;
2537 unsigned int scan_needed:1;
2538 unsigned int n2n_flag:1;
2539 unsigned int explicit_logout:1;
2540 unsigned int prli_pend_timer:1;
2541 unsigned int do_prli_nvme:1;
2542
2543 uint8_t nvme_flag;
2544
2545 uint8_t node_name[WWN_SIZE];
2546 uint8_t port_name[WWN_SIZE];
2547 port_id_t d_id;
2548 uint16_t loop_id;
2549 uint16_t old_loop_id;
2550
2551 struct completion nvme_del_done;
2552 uint32_t nvme_prli_service_param;
2553 #define NVME_PRLI_SP_PI_CTRL BIT_9
2554 #define NVME_PRLI_SP_SLER BIT_8
2555 #define NVME_PRLI_SP_CONF BIT_7
2556 #define NVME_PRLI_SP_INITIATOR BIT_5
2557 #define NVME_PRLI_SP_TARGET BIT_4
2558 #define NVME_PRLI_SP_DISCOVERY BIT_3
2559 #define NVME_PRLI_SP_FIRST_BURST BIT_0
2560
2561 uint32_t nvme_first_burst_size;
2562 #define NVME_FLAG_REGISTERED 4
2563 #define NVME_FLAG_DELETING 2
2564 #define NVME_FLAG_RESETTING 1
2565
2566 struct fc_port *conflict;
2567 unsigned char logout_completed;
2568 int generation;
2569
2570 struct se_session *se_sess;
2571 struct list_head sess_cmd_list;
2572 spinlock_t sess_cmd_lock;
2573 struct kref sess_kref;
2574 struct qla_tgt *tgt;
2575 unsigned long expires;
2576 struct list_head del_list_entry;
2577 struct work_struct free_work;
2578 struct work_struct reg_work;
2579 uint64_t jiffies_at_registration;
2580 unsigned long prli_expired;
2581 struct qlt_plogi_ack_t *plogi_link[QLT_PLOGI_LINK_MAX];
2582
2583 uint16_t tgt_id;
2584 uint16_t old_tgt_id;
2585 uint16_t sec_since_registration;
2586
2587 uint8_t fcp_prio;
2588
2589 uint8_t fabric_port_name[WWN_SIZE];
2590 uint16_t fp_speed;
2591
2592 fc_port_type_t port_type;
2593
2594 atomic_t state;
2595 uint32_t flags;
2596
2597 int login_retry;
2598
2599 struct fc_rport *rport, *drport;
2600 u32 supported_classes;
2601
2602 uint8_t fc4_type;
2603 uint8_t fc4_features;
2604 uint8_t scan_state;
2605
2606 unsigned long last_queue_full;
2607 unsigned long last_ramp_up;
2608
2609 uint16_t port_id;
2610
2611 struct nvme_fc_remote_port *nvme_remote_port;
2612
2613 unsigned long retry_delay_timestamp;
2614 struct qla_tgt_sess *tgt_session;
2615 struct ct_sns_desc ct_desc;
2616 enum discovery_state disc_state;
2617 atomic_t shadow_disc_state;
2618 enum discovery_state next_disc_state;
2619 enum login_state fw_login_state;
2620 unsigned long dm_login_expire;
2621 unsigned long plogi_nack_done_deadline;
2622
2623 u32 login_gen, last_login_gen;
2624 u32 rscn_gen, last_rscn_gen;
2625 u32 chip_reset;
2626 struct list_head gnl_entry;
2627 struct work_struct del_work;
2628 u8 iocb[IOCB_SIZE];
2629 u8 current_login_state;
2630 u8 last_login_state;
2631 u16 n2n_link_reset_cnt;
2632 u16 n2n_chip_reset;
2633
2634 struct dentry *dfs_rport_dir;
2635
2636 u64 tgt_short_link_down_cnt;
2637 u64 tgt_link_down_time;
2638 u64 dev_loss_tmo;
2639 /*
2640 * EDIF parameters for encryption.
2641 */
2642 struct {
2643 uint32_t enable:1; /* device is edif enabled/req'd */
2644 uint32_t app_stop:2;
2645 uint32_t aes_gmac:1;
2646 uint32_t app_sess_online:1;
2647 uint32_t tx_sa_set:1;
2648 uint32_t rx_sa_set:1;
2649 uint32_t tx_sa_pending:1;
2650 uint32_t rx_sa_pending:1;
2651 uint32_t tx_rekey_cnt;
2652 uint32_t rx_rekey_cnt;
2653 uint64_t tx_bytes;
2654 uint64_t rx_bytes;
2655 uint8_t sess_down_acked;
2656 uint8_t auth_state;
2657 uint16_t authok:1;
2658 uint16_t rekey_cnt;
2659 struct list_head edif_indx_list;
2660 spinlock_t indx_list_lock;
2661
2662 struct list_head tx_sa_list;
2663 struct list_head rx_sa_list;
2664 spinlock_t sa_list_lock;
2665 } edif;
2666 } fc_port_t;
2667
2668 enum {
2669 FC4_PRIORITY_NVME = 1,
2670 FC4_PRIORITY_FCP = 2,
2671 };
2672
2673 #define QLA_FCPORT_SCAN 1
2674 #define QLA_FCPORT_FOUND 2
2675
2676 struct event_arg {
2677 fc_port_t *fcport;
2678 srb_t *sp;
2679 port_id_t id;
2680 u16 data[2], rc;
2681 u8 port_name[WWN_SIZE];
2682 u32 iop[2];
2683 };
2684
2685 #include "qla_mr.h"
2686
2687 /*
2688 * Fibre channel port/lun states.
2689 */
2690 enum {
2691 FCS_UNKNOWN,
2692 FCS_UNCONFIGURED,
2693 FCS_DEVICE_DEAD,
2694 FCS_DEVICE_LOST,
2695 FCS_ONLINE,
2696 };
2697
2698 extern const char *const port_state_str[5];
2699
2700 static const char *const port_dstate_str[] = {
2701 [DSC_DELETED] = "DELETED",
2702 [DSC_GNN_ID] = "GNN_ID",
2703 [DSC_GNL] = "GNL",
2704 [DSC_LOGIN_PEND] = "LOGIN_PEND",
2705 [DSC_LOGIN_FAILED] = "LOGIN_FAILED",
2706 [DSC_GPDB] = "GPDB",
2707 [DSC_UPD_FCPORT] = "UPD_FCPORT",
2708 [DSC_LOGIN_COMPLETE] = "LOGIN_COMPLETE",
2709 [DSC_ADISC] = "ADISC",
2710 [DSC_DELETE_PEND] = "DELETE_PEND",
2711 [DSC_LOGIN_AUTH_PEND] = "LOGIN_AUTH_PEND",
2712 };
2713
2714 /*
2715 * FC port flags.
2716 */
2717 #define FCF_FABRIC_DEVICE BIT_0
2718 #define FCF_LOGIN_NEEDED BIT_1
2719 #define FCF_FCP2_DEVICE BIT_2
2720 #define FCF_ASYNC_SENT BIT_3
2721 #define FCF_CONF_COMP_SUPPORTED BIT_4
2722 #define FCF_ASYNC_ACTIVE BIT_5
2723 #define FCF_FCSP_DEVICE BIT_6
2724 #define FCF_EDIF_DELETE BIT_7
2725
2726 /* No loop ID flag. */
2727 #define FC_NO_LOOP_ID 0x1000
2728
2729 /*
2730 * FC-CT interface
2731 *
2732 * NOTE: All structures are big-endian in form.
2733 */
2734
2735 #define CT_REJECT_RESPONSE 0x8001
2736 #define CT_ACCEPT_RESPONSE 0x8002
2737 #define CT_REASON_INVALID_COMMAND_CODE 0x01
2738 #define CT_REASON_CANNOT_PERFORM 0x09
2739 #define CT_REASON_COMMAND_UNSUPPORTED 0x0b
2740 #define CT_EXPL_ALREADY_REGISTERED 0x10
2741 #define CT_EXPL_HBA_ATTR_NOT_REGISTERED 0x11
2742 #define CT_EXPL_MULTIPLE_HBA_ATTR 0x12
2743 #define CT_EXPL_INVALID_HBA_BLOCK_LENGTH 0x13
2744 #define CT_EXPL_MISSING_REQ_HBA_ATTR 0x14
2745 #define CT_EXPL_PORT_NOT_REGISTERED_ 0x15
2746 #define CT_EXPL_MISSING_HBA_ID_PORT_LIST 0x16
2747 #define CT_EXPL_HBA_NOT_REGISTERED 0x17
2748 #define CT_EXPL_PORT_ATTR_NOT_REGISTERED 0x20
2749 #define CT_EXPL_PORT_NOT_REGISTERED 0x21
2750 #define CT_EXPL_MULTIPLE_PORT_ATTR 0x22
2751 #define CT_EXPL_INVALID_PORT_BLOCK_LENGTH 0x23
2752
2753 #define NS_N_PORT_TYPE 0x01
2754 #define NS_NL_PORT_TYPE 0x02
2755 #define NS_NX_PORT_TYPE 0x7F
2756
2757 #define GA_NXT_CMD 0x100
2758 #define GA_NXT_REQ_SIZE (16 + 4)
2759 #define GA_NXT_RSP_SIZE (16 + 620)
2760
2761 #define GPN_FT_CMD 0x172
2762 #define GPN_FT_REQ_SIZE (16 + 4)
2763 #define GNN_FT_CMD 0x173
2764 #define GNN_FT_REQ_SIZE (16 + 4)
2765
2766 #define GID_PT_CMD 0x1A1
2767 #define GID_PT_REQ_SIZE (16 + 4)
2768
2769 #define GPN_ID_CMD 0x112
2770 #define GPN_ID_REQ_SIZE (16 + 4)
2771 #define GPN_ID_RSP_SIZE (16 + 8)
2772
2773 #define GNN_ID_CMD 0x113
2774 #define GNN_ID_REQ_SIZE (16 + 4)
2775 #define GNN_ID_RSP_SIZE (16 + 8)
2776
2777 #define GFT_ID_CMD 0x117
2778 #define GFT_ID_REQ_SIZE (16 + 4)
2779 #define GFT_ID_RSP_SIZE (16 + 32)
2780
2781 #define GID_PN_CMD 0x121
2782 #define GID_PN_REQ_SIZE (16 + 8)
2783 #define GID_PN_RSP_SIZE (16 + 4)
2784
2785 #define RFT_ID_CMD 0x217
2786 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
2787 #define RFT_ID_RSP_SIZE 16
2788
2789 #define RFF_ID_CMD 0x21F
2790 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
2791 #define RFF_ID_RSP_SIZE 16
2792
2793 #define RNN_ID_CMD 0x213
2794 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
2795 #define RNN_ID_RSP_SIZE 16
2796
2797 #define RSNN_NN_CMD 0x239
2798 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
2799 #define RSNN_NN_RSP_SIZE 16
2800
2801 #define GFPN_ID_CMD 0x11C
2802 #define GFPN_ID_REQ_SIZE (16 + 4)
2803 #define GFPN_ID_RSP_SIZE (16 + 8)
2804
2805 #define GPSC_CMD 0x127
2806 #define GPSC_REQ_SIZE (16 + 8)
2807 #define GPSC_RSP_SIZE (16 + 2 + 2)
2808
2809 #define GFF_ID_CMD 0x011F
2810 #define GFF_ID_REQ_SIZE (16 + 4)
2811 #define GFF_ID_RSP_SIZE (16 + 128)
2812
2813 /*
2814 * FDMI HBA attribute types.
2815 */
2816 #define FDMI1_HBA_ATTR_COUNT 10
2817 #define FDMI2_HBA_ATTR_COUNT 17
2818
2819 #define FDMI_HBA_NODE_NAME 0x1
2820 #define FDMI_HBA_MANUFACTURER 0x2
2821 #define FDMI_HBA_SERIAL_NUMBER 0x3
2822 #define FDMI_HBA_MODEL 0x4
2823 #define FDMI_HBA_MODEL_DESCRIPTION 0x5
2824 #define FDMI_HBA_HARDWARE_VERSION 0x6
2825 #define FDMI_HBA_DRIVER_VERSION 0x7
2826 #define FDMI_HBA_OPTION_ROM_VERSION 0x8
2827 #define FDMI_HBA_FIRMWARE_VERSION 0x9
2828 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
2829 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
2830
2831 #define FDMI_HBA_NODE_SYMBOLIC_NAME 0xc
2832 #define FDMI_HBA_VENDOR_SPECIFIC_INFO 0xd
2833 #define FDMI_HBA_NUM_PORTS 0xe
2834 #define FDMI_HBA_FABRIC_NAME 0xf
2835 #define FDMI_HBA_BOOT_BIOS_NAME 0x10
2836 #define FDMI_HBA_VENDOR_IDENTIFIER 0xe0
2837
2838 struct ct_fdmi_hba_attr {
2839 __be16 type;
2840 __be16 len;
2841 union {
2842 uint8_t node_name[WWN_SIZE];
2843 uint8_t manufacturer[64];
2844 uint8_t serial_num[32];
2845 uint8_t model[16+1];
2846 uint8_t model_desc[80];
2847 uint8_t hw_version[32];
2848 uint8_t driver_version[32];
2849 uint8_t orom_version[16];
2850 uint8_t fw_version[32];
2851 uint8_t os_version[128];
2852 __be32 max_ct_len;
2853
2854 uint8_t sym_name[256];
2855 __be32 vendor_specific_info;
2856 __be32 num_ports;
2857 uint8_t fabric_name[WWN_SIZE];
2858 uint8_t bios_name[32];
2859 uint8_t vendor_identifier[8];
2860 } a;
2861 };
2862
2863 struct ct_fdmi1_hba_attributes {
2864 __be32 count;
2865 struct ct_fdmi_hba_attr entry[FDMI1_HBA_ATTR_COUNT];
2866 };
2867
2868 struct ct_fdmi2_hba_attributes {
2869 __be32 count;
2870 struct ct_fdmi_hba_attr entry[FDMI2_HBA_ATTR_COUNT];
2871 };
2872
2873 /*
2874 * FDMI Port attribute types.
2875 */
2876 #define FDMI1_PORT_ATTR_COUNT 6
2877 #define FDMI2_PORT_ATTR_COUNT 16
2878 #define FDMI2_SMARTSAN_PORT_ATTR_COUNT 23
2879
2880 #define FDMI_PORT_FC4_TYPES 0x1
2881 #define FDMI_PORT_SUPPORT_SPEED 0x2
2882 #define FDMI_PORT_CURRENT_SPEED 0x3
2883 #define FDMI_PORT_MAX_FRAME_SIZE 0x4
2884 #define FDMI_PORT_OS_DEVICE_NAME 0x5
2885 #define FDMI_PORT_HOST_NAME 0x6
2886
2887 #define FDMI_PORT_NODE_NAME 0x7
2888 #define FDMI_PORT_NAME 0x8
2889 #define FDMI_PORT_SYM_NAME 0x9
2890 #define FDMI_PORT_TYPE 0xa
2891 #define FDMI_PORT_SUPP_COS 0xb
2892 #define FDMI_PORT_FABRIC_NAME 0xc
2893 #define FDMI_PORT_FC4_TYPE 0xd
2894 #define FDMI_PORT_STATE 0x101
2895 #define FDMI_PORT_COUNT 0x102
2896 #define FDMI_PORT_IDENTIFIER 0x103
2897
2898 #define FDMI_SMARTSAN_SERVICE 0xF100
2899 #define FDMI_SMARTSAN_GUID 0xF101
2900 #define FDMI_SMARTSAN_VERSION 0xF102
2901 #define FDMI_SMARTSAN_PROD_NAME 0xF103
2902 #define FDMI_SMARTSAN_PORT_INFO 0xF104
2903 #define FDMI_SMARTSAN_QOS_SUPPORT 0xF105
2904 #define FDMI_SMARTSAN_SECURITY_SUPPORT 0xF106
2905
2906 #define FDMI_PORT_SPEED_1GB 0x1
2907 #define FDMI_PORT_SPEED_2GB 0x2
2908 #define FDMI_PORT_SPEED_10GB 0x4
2909 #define FDMI_PORT_SPEED_4GB 0x8
2910 #define FDMI_PORT_SPEED_8GB 0x10
2911 #define FDMI_PORT_SPEED_16GB 0x20
2912 #define FDMI_PORT_SPEED_32GB 0x40
2913 #define FDMI_PORT_SPEED_20GB 0x80
2914 #define FDMI_PORT_SPEED_40GB 0x100
2915 #define FDMI_PORT_SPEED_128GB 0x200
2916 #define FDMI_PORT_SPEED_64GB 0x400
2917 #define FDMI_PORT_SPEED_256GB 0x800
2918 #define FDMI_PORT_SPEED_UNKNOWN 0x8000
2919
2920 #define FC_CLASS_2 0x04
2921 #define FC_CLASS_3 0x08
2922 #define FC_CLASS_2_3 0x0C
2923
2924 struct ct_fdmi_port_attr {
2925 __be16 type;
2926 __be16 len;
2927 union {
2928 uint8_t fc4_types[32];
2929 __be32 sup_speed;
2930 __be32 cur_speed;
2931 __be32 max_frame_size;
2932 uint8_t os_dev_name[32];
2933 uint8_t host_name[256];
2934
2935 uint8_t node_name[WWN_SIZE];
2936 uint8_t port_name[WWN_SIZE];
2937 uint8_t port_sym_name[128];
2938 __be32 port_type;
2939 __be32 port_supported_cos;
2940 uint8_t fabric_name[WWN_SIZE];
2941 uint8_t port_fc4_type[32];
2942 __be32 port_state;
2943 __be32 num_ports;
2944 __be32 port_id;
2945
2946 uint8_t smartsan_service[24];
2947 uint8_t smartsan_guid[16];
2948 uint8_t smartsan_version[24];
2949 uint8_t smartsan_prod_name[16];
2950 __be32 smartsan_port_info;
2951 __be32 smartsan_qos_support;
2952 __be32 smartsan_security_support;
2953 } a;
2954 };
2955
2956 struct ct_fdmi1_port_attributes {
2957 __be32 count;
2958 struct ct_fdmi_port_attr entry[FDMI1_PORT_ATTR_COUNT];
2959 };
2960
2961 struct ct_fdmi2_port_attributes {
2962 __be32 count;
2963 struct ct_fdmi_port_attr entry[FDMI2_PORT_ATTR_COUNT];
2964 };
2965
2966 #define FDMI_ATTR_TYPELEN(obj) \
2967 (sizeof((obj)->type) + sizeof((obj)->len))
2968
2969 #define FDMI_ATTR_ALIGNMENT(len) \
2970 (4 - ((len) & 3))
2971
2972 /* FDMI register call options */
2973 #define CALLOPT_FDMI1 0
2974 #define CALLOPT_FDMI2 1
2975 #define CALLOPT_FDMI2_SMARTSAN 2
2976
2977 /* FDMI definitions. */
2978 #define GRHL_CMD 0x100
2979 #define GHAT_CMD 0x101
2980 #define GRPL_CMD 0x102
2981 #define GPAT_CMD 0x110
2982
2983 #define RHBA_CMD 0x200
2984 #define RHBA_RSP_SIZE 16
2985
2986 #define RHAT_CMD 0x201
2987
2988 #define RPRT_CMD 0x210
2989 #define RPRT_RSP_SIZE 24
2990
2991 #define RPA_CMD 0x211
2992 #define RPA_RSP_SIZE 16
2993 #define SMARTSAN_RPA_RSP_SIZE 24
2994
2995 #define DHBA_CMD 0x300
2996 #define DHBA_REQ_SIZE (16 + 8)
2997 #define DHBA_RSP_SIZE 16
2998
2999 #define DHAT_CMD 0x301
3000 #define DPRT_CMD 0x310
3001 #define DPA_CMD 0x311
3002
3003 /* CT command header -- request/response common fields */
3004 struct ct_cmd_hdr {
3005 uint8_t revision;
3006 uint8_t in_id[3];
3007 uint8_t gs_type;
3008 uint8_t gs_subtype;
3009 uint8_t options;
3010 uint8_t reserved;
3011 };
3012
3013 /* CT command request */
3014 struct ct_sns_req {
3015 struct ct_cmd_hdr header;
3016 __be16 command;
3017 __be16 max_rsp_size;
3018 uint8_t fragment_id;
3019 uint8_t reserved[3];
3020
3021 union {
3022 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID, GFPN_ID */
3023 struct {
3024 uint8_t reserved;
3025 be_id_t port_id;
3026 } port_id;
3027
3028 struct {
3029 uint8_t reserved;
3030 uint8_t domain;
3031 uint8_t area;
3032 uint8_t port_type;
3033 } gpn_ft;
3034
3035 struct {
3036 uint8_t port_type;
3037 uint8_t domain;
3038 uint8_t area;
3039 uint8_t reserved;
3040 } gid_pt;
3041
3042 struct {
3043 uint8_t reserved;
3044 be_id_t port_id;
3045 uint8_t fc4_types[32];
3046 } rft_id;
3047
3048 struct {
3049 uint8_t reserved;
3050 be_id_t port_id;
3051 uint16_t reserved2;
3052 uint8_t fc4_feature;
3053 uint8_t fc4_type;
3054 } rff_id;
3055
3056 struct {
3057 uint8_t reserved;
3058 be_id_t port_id;
3059 uint8_t node_name[8];
3060 } rnn_id;
3061
3062 struct {
3063 uint8_t node_name[8];
3064 uint8_t name_len;
3065 uint8_t sym_node_name[255];
3066 } rsnn_nn;
3067
3068 struct {
3069 uint8_t hba_identifier[8];
3070 } ghat;
3071
3072 struct {
3073 uint8_t hba_identifier[8];
3074 __be32 entry_count;
3075 uint8_t port_name[8];
3076 struct ct_fdmi2_hba_attributes attrs;
3077 } rhba;
3078
3079 struct {
3080 uint8_t hba_identifier[8];
3081 struct ct_fdmi1_hba_attributes attrs;
3082 } rhat;
3083
3084 struct {
3085 uint8_t port_name[8];
3086 struct ct_fdmi2_port_attributes attrs;
3087 } rpa;
3088
3089 struct {
3090 uint8_t hba_identifier[8];
3091 uint8_t port_name[8];
3092 struct ct_fdmi2_port_attributes attrs;
3093 } rprt;
3094
3095 struct {
3096 uint8_t port_name[8];
3097 } dhba;
3098
3099 struct {
3100 uint8_t port_name[8];
3101 } dhat;
3102
3103 struct {
3104 uint8_t port_name[8];
3105 } dprt;
3106
3107 struct {
3108 uint8_t port_name[8];
3109 } dpa;
3110
3111 struct {
3112 uint8_t port_name[8];
3113 } gpsc;
3114
3115 struct {
3116 uint8_t reserved;
3117 uint8_t port_id[3];
3118 } gff_id;
3119
3120 struct {
3121 uint8_t port_name[8];
3122 } gid_pn;
3123 } req;
3124 };
3125
3126 /* CT command response header */
3127 struct ct_rsp_hdr {
3128 struct ct_cmd_hdr header;
3129 __be16 response;
3130 uint16_t residual;
3131 uint8_t fragment_id;
3132 uint8_t reason_code;
3133 uint8_t explanation_code;
3134 uint8_t vendor_unique;
3135 };
3136
3137 struct ct_sns_gid_pt_data {
3138 uint8_t control_byte;
3139 be_id_t port_id;
3140 };
3141
3142 /* It's the same for both GPN_FT and GNN_FT */
3143 struct ct_sns_gpnft_rsp {
3144 struct {
3145 struct ct_cmd_hdr header;
3146 uint16_t response;
3147 uint16_t residual;
3148 uint8_t fragment_id;
3149 uint8_t reason_code;
3150 uint8_t explanation_code;
3151 uint8_t vendor_unique;
3152 };
3153 /* Assume the largest number of targets for the union */
3154 struct ct_sns_gpn_ft_data {
3155 u8 control_byte;
3156 u8 port_id[3];
3157 u32 reserved;
3158 u8 port_name[8];
3159 } entries[1];
3160 };
3161
3162 /* CT command response */
3163 struct ct_sns_rsp {
3164 struct ct_rsp_hdr header;
3165
3166 union {
3167 struct {
3168 uint8_t port_type;
3169 be_id_t port_id;
3170 uint8_t port_name[8];
3171 uint8_t sym_port_name_len;
3172 uint8_t sym_port_name[255];
3173 uint8_t node_name[8];
3174 uint8_t sym_node_name_len;
3175 uint8_t sym_node_name[255];
3176 uint8_t init_proc_assoc[8];
3177 uint8_t node_ip_addr[16];
3178 uint8_t class_of_service[4];
3179 uint8_t fc4_types[32];
3180 uint8_t ip_address[16];
3181 uint8_t fabric_port_name[8];
3182 uint8_t reserved;
3183 uint8_t hard_address[3];
3184 } ga_nxt;
3185
3186 struct {
3187 /* Assume the largest number of targets for the union */
3188 struct ct_sns_gid_pt_data
3189 entries[MAX_FIBRE_DEVICES_MAX];
3190 } gid_pt;
3191
3192 struct {
3193 uint8_t port_name[8];
3194 } gpn_id;
3195
3196 struct {
3197 uint8_t node_name[8];
3198 } gnn_id;
3199
3200 struct {
3201 uint8_t fc4_types[32];
3202 } gft_id;
3203
3204 struct {
3205 uint32_t entry_count;
3206 uint8_t port_name[8];
3207 struct ct_fdmi1_hba_attributes attrs;
3208 } ghat;
3209
3210 struct {
3211 uint8_t port_name[8];
3212 } gfpn_id;
3213
3214 struct {
3215 __be16 speeds;
3216 __be16 speed;
3217 } gpsc;
3218
3219 #define GFF_FCP_SCSI_OFFSET 7
3220 #define GFF_NVME_OFFSET 23 /* type = 28h */
3221 struct {
3222 uint8_t fc4_features[128];
3223 #define FC4_FF_TARGET BIT_0
3224 #define FC4_FF_INITIATOR BIT_1
3225 } gff_id;
3226 struct {
3227 uint8_t reserved;
3228 uint8_t port_id[3];
3229 } gid_pn;
3230 } rsp;
3231 };
3232
3233 struct ct_sns_pkt {
3234 union {
3235 struct ct_sns_req req;
3236 struct ct_sns_rsp rsp;
3237 } p;
3238 };
3239
3240 struct ct_sns_gpnft_pkt {
3241 union {
3242 struct ct_sns_req req;
3243 struct ct_sns_gpnft_rsp rsp;
3244 } p;
3245 };
3246
3247 enum scan_flags_t {
3248 SF_SCANNING = BIT_0,
3249 SF_QUEUED = BIT_1,
3250 };
3251
3252 enum fc4type_t {
3253 FS_FC4TYPE_FCP = BIT_0,
3254 FS_FC4TYPE_NVME = BIT_1,
3255 FS_FCP_IS_N2N = BIT_7,
3256 };
3257
3258 struct fab_scan_rp {
3259 port_id_t id;
3260 enum fc4type_t fc4type;
3261 u8 port_name[8];
3262 u8 node_name[8];
3263 };
3264
3265 struct fab_scan {
3266 struct fab_scan_rp *l;
3267 u32 size;
3268 u16 scan_retry;
3269 #define MAX_SCAN_RETRIES 5
3270 enum scan_flags_t scan_flags;
3271 struct delayed_work scan_work;
3272 };
3273
3274 /*
3275 * SNS command structures -- for 2200 compatibility.
3276 */
3277 #define RFT_ID_SNS_SCMD_LEN 22
3278 #define RFT_ID_SNS_CMD_SIZE 60
3279 #define RFT_ID_SNS_DATA_SIZE 16
3280
3281 #define RNN_ID_SNS_SCMD_LEN 10
3282 #define RNN_ID_SNS_CMD_SIZE 36
3283 #define RNN_ID_SNS_DATA_SIZE 16
3284
3285 #define GA_NXT_SNS_SCMD_LEN 6
3286 #define GA_NXT_SNS_CMD_SIZE 28
3287 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
3288
3289 #define GID_PT_SNS_SCMD_LEN 6
3290 #define GID_PT_SNS_CMD_SIZE 28
3291 /*
3292 * Assume MAX_FIBRE_DEVICES_2100 as these defines are only used with older
3293 * adapters.
3294 */
3295 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES_2100 * 4 + 16)
3296
3297 #define GPN_ID_SNS_SCMD_LEN 6
3298 #define GPN_ID_SNS_CMD_SIZE 28
3299 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
3300
3301 #define GNN_ID_SNS_SCMD_LEN 6
3302 #define GNN_ID_SNS_CMD_SIZE 28
3303 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
3304
3305 struct sns_cmd_pkt {
3306 union {
3307 struct {
3308 __le16 buffer_length;
3309 __le16 reserved_1;
3310 __le64 buffer_address __packed;
3311 __le16 subcommand_length;
3312 __le16 reserved_2;
3313 __le16 subcommand;
3314 __le16 size;
3315 uint32_t reserved_3;
3316 uint8_t param[36];
3317 } cmd;
3318
3319 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
3320 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
3321 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
3322 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
3323 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
3324 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
3325 } p;
3326 };
3327
3328 struct fw_blob {
3329 char *name;
3330 uint32_t segs[4];
3331 const struct firmware *fw;
3332 };
3333
3334 /* Return data from MBC_GET_ID_LIST call. */
3335 struct gid_list_info {
3336 uint8_t al_pa;
3337 uint8_t area;
3338 uint8_t domain;
3339 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
3340 __le16 loop_id; /* ISP23XX -- 6 bytes. */
3341 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
3342 };
3343
3344 /* NPIV */
3345 typedef struct vport_info {
3346 uint8_t port_name[WWN_SIZE];
3347 uint8_t node_name[WWN_SIZE];
3348 int vp_id;
3349 uint16_t loop_id;
3350 unsigned long host_no;
3351 uint8_t port_id[3];
3352 int loop_state;
3353 } vport_info_t;
3354
3355 typedef struct vport_params {
3356 uint8_t port_name[WWN_SIZE];
3357 uint8_t node_name[WWN_SIZE];
3358 uint32_t options;
3359 #define VP_OPTS_RETRY_ENABLE BIT_0
3360 #define VP_OPTS_VP_DISABLE BIT_1
3361 } vport_params_t;
3362
3363 /* NPIV - return codes of VP create and modify */
3364 #define VP_RET_CODE_OK 0
3365 #define VP_RET_CODE_FATAL 1
3366 #define VP_RET_CODE_WRONG_ID 2
3367 #define VP_RET_CODE_WWPN 3
3368 #define VP_RET_CODE_RESOURCES 4
3369 #define VP_RET_CODE_NO_MEM 5
3370 #define VP_RET_CODE_NOT_FOUND 6
3371
3372 struct qla_hw_data;
3373 struct rsp_que;
3374 /*
3375 * ISP operations
3376 */
3377 struct isp_operations {
3378
3379 int (*pci_config) (struct scsi_qla_host *);
3380 int (*reset_chip)(struct scsi_qla_host *);
3381 int (*chip_diag) (struct scsi_qla_host *);
3382 void (*config_rings) (struct scsi_qla_host *);
3383 int (*reset_adapter)(struct scsi_qla_host *);
3384 int (*nvram_config) (struct scsi_qla_host *);
3385 void (*update_fw_options) (struct scsi_qla_host *);
3386 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
3387
3388 char * (*pci_info_str)(struct scsi_qla_host *, char *, size_t);
3389 char * (*fw_version_str)(struct scsi_qla_host *, char *, size_t);
3390
3391 irq_handler_t intr_handler;
3392 void (*enable_intrs) (struct qla_hw_data *);
3393 void (*disable_intrs) (struct qla_hw_data *);
3394
3395 int (*abort_command) (srb_t *);
3396 int (*target_reset) (struct fc_port *, uint64_t, int);
3397 int (*lun_reset) (struct fc_port *, uint64_t, int);
3398 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
3399 uint8_t, uint8_t, uint16_t *, uint8_t);
3400 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
3401 uint8_t, uint8_t);
3402
3403 uint16_t (*calc_req_entries) (uint16_t);
3404 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
3405 void *(*prep_ms_iocb) (struct scsi_qla_host *, struct ct_arg *);
3406 void *(*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
3407 uint32_t);
3408
3409 uint8_t *(*read_nvram)(struct scsi_qla_host *, void *,
3410 uint32_t, uint32_t);
3411 int (*write_nvram)(struct scsi_qla_host *, void *, uint32_t,
3412 uint32_t);
3413
3414 void (*fw_dump)(struct scsi_qla_host *vha);
3415 void (*mpi_fw_dump)(struct scsi_qla_host *, int);
3416
3417 /* Context: task, might sleep */
3418 int (*beacon_on) (struct scsi_qla_host *);
3419 int (*beacon_off) (struct scsi_qla_host *);
3420
3421 void (*beacon_blink) (struct scsi_qla_host *);
3422
3423 void *(*read_optrom)(struct scsi_qla_host *, void *,
3424 uint32_t, uint32_t);
3425 int (*write_optrom)(struct scsi_qla_host *, void *, uint32_t,
3426 uint32_t);
3427
3428 int (*get_flash_version) (struct scsi_qla_host *, void *);
3429 int (*start_scsi) (srb_t *);
3430 int (*start_scsi_mq) (srb_t *);
3431
3432 /* Context: task, might sleep */
3433 int (*abort_isp) (struct scsi_qla_host *);
3434
3435 int (*iospace_config)(struct qla_hw_data *);
3436 int (*initialize_adapter)(struct scsi_qla_host *);
3437 };
3438
3439 /* MSI-X Support *************************************************************/
3440
3441 #define QLA_MSIX_CHIP_REV_24XX 3
3442 #define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
3443 #define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
3444
3445 #define QLA_BASE_VECTORS 2 /* default + RSP */
3446 #define QLA_MSIX_RSP_Q 0x01
3447 #define QLA_ATIO_VECTOR 0x02
3448 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q 0x03
3449 #define QLA_MSIX_QPAIR_MULTIQ_RSP_Q_HS 0x04
3450
3451 #define QLA_MIDX_DEFAULT 0
3452 #define QLA_MIDX_RSP_Q 1
3453 #define QLA_PCI_MSIX_CONTROL 0xa2
3454 #define QLA_83XX_PCI_MSIX_CONTROL 0x92
3455
3456 struct scsi_qla_host;
3457
3458
3459 #define QLA83XX_RSPQ_MSIX_ENTRY_NUMBER 1 /* refer to qla83xx_msix_entries */
3460
3461 struct qla_msix_entry {
3462 int have_irq;
3463 int in_use;
3464 uint32_t vector;
3465 uint16_t entry;
3466 char name[30];
3467 void *handle;
3468 int cpuid;
3469 };
3470
3471 #define WATCH_INTERVAL 1 /* number of seconds */
3472
3473 /* Work events. */
3474 enum qla_work_type {
3475 QLA_EVT_AEN,
3476 QLA_EVT_IDC_ACK,
3477 QLA_EVT_ASYNC_LOGIN,
3478 QLA_EVT_ASYNC_LOGOUT,
3479 QLA_EVT_ASYNC_ADISC,
3480 QLA_EVT_UEVENT,
3481 QLA_EVT_AENFX,
3482 QLA_EVT_GPNID,
3483 QLA_EVT_UNMAP,
3484 QLA_EVT_NEW_SESS,
3485 QLA_EVT_GPDB,
3486 QLA_EVT_PRLI,
3487 QLA_EVT_GPSC,
3488 QLA_EVT_GNL,
3489 QLA_EVT_NACK,
3490 QLA_EVT_RELOGIN,
3491 QLA_EVT_ASYNC_PRLO,
3492 QLA_EVT_ASYNC_PRLO_DONE,
3493 QLA_EVT_GPNFT,
3494 QLA_EVT_GPNFT_DONE,
3495 QLA_EVT_GNNFT_DONE,
3496 QLA_EVT_GNNID,
3497 QLA_EVT_GFPNID,
3498 QLA_EVT_SP_RETRY,
3499 QLA_EVT_IIDMA,
3500 QLA_EVT_ELS_PLOGI,
3501 QLA_EVT_SA_REPLACE,
3502 };
3503
3504
3505 struct qla_work_evt {
3506 struct list_head list;
3507 enum qla_work_type type;
3508 u32 flags;
3509 #define QLA_EVT_FLAG_FREE 0x1
3510
3511 union {
3512 struct {
3513 enum fc_host_event_code code;
3514 u32 data;
3515 } aen;
3516 struct {
3517 #define QLA_IDC_ACK_REGS 7
3518 uint16_t mb[QLA_IDC_ACK_REGS];
3519 } idc_ack;
3520 struct {
3521 struct fc_port *fcport;
3522 #define QLA_LOGIO_LOGIN_RETRIED BIT_0
3523 u16 data[2];
3524 } logio;
3525 struct {
3526 u32 code;
3527 #define QLA_UEVENT_CODE_FW_DUMP 0
3528 } uevent;
3529 struct {
3530 uint32_t evtcode;
3531 uint32_t mbx[8];
3532 uint32_t count;
3533 } aenfx;
3534 struct {
3535 srb_t *sp;
3536 } iosb;
3537 struct {
3538 port_id_t id;
3539 } gpnid;
3540 struct {
3541 port_id_t id;
3542 u8 port_name[8];
3543 u8 node_name[8];
3544 void *pla;
3545 u8 fc4_type;
3546 } new_sess;
3547 struct { /*Get PDB, Get Speed, update fcport, gnl, gidpn */
3548 fc_port_t *fcport;
3549 u8 opt;
3550 } fcport;
3551 struct {
3552 fc_port_t *fcport;
3553 u8 iocb[IOCB_SIZE];
3554 int type;
3555 } nack;
3556 struct {
3557 u8 fc4_type;
3558 srb_t *sp;
3559 } gpnft;
3560 struct {
3561 struct edif_sa_ctl *sa_ctl;
3562 fc_port_t *fcport;
3563 uint16_t nport_handle;
3564 } sa_update;
3565 } u;
3566 };
3567
3568 struct qla_chip_state_84xx {
3569 struct list_head list;
3570 struct kref kref;
3571
3572 void *bus;
3573 spinlock_t access_lock;
3574 struct mutex fw_update_mutex;
3575 uint32_t fw_update;
3576 uint32_t op_fw_version;
3577 uint32_t op_fw_size;
3578 uint32_t op_fw_seq_size;
3579 uint32_t diag_fw_version;
3580 uint32_t gold_fw_version;
3581 };
3582
3583 struct qla_dif_statistics {
3584 uint64_t dif_input_bytes;
3585 uint64_t dif_output_bytes;
3586 uint64_t dif_input_requests;
3587 uint64_t dif_output_requests;
3588 uint32_t dif_guard_err;
3589 uint32_t dif_ref_tag_err;
3590 uint32_t dif_app_tag_err;
3591 };
3592
3593 struct qla_statistics {
3594 uint32_t total_isp_aborts;
3595 uint64_t input_bytes;
3596 uint64_t output_bytes;
3597 uint64_t input_requests;
3598 uint64_t output_requests;
3599 uint32_t control_requests;
3600
3601 uint64_t jiffies_at_last_reset;
3602 uint32_t stat_max_pend_cmds;
3603 uint32_t stat_max_qfull_cmds_alloc;
3604 uint32_t stat_max_qfull_cmds_dropped;
3605
3606 struct qla_dif_statistics qla_dif_stats;
3607 };
3608
3609 struct bidi_statistics {
3610 unsigned long long io_count;
3611 unsigned long long transfer_bytes;
3612 };
3613
3614 struct qla_tc_param {
3615 struct scsi_qla_host *vha;
3616 uint32_t blk_sz;
3617 uint32_t bufflen;
3618 struct scatterlist *sg;
3619 struct scatterlist *prot_sg;
3620 struct crc_context *ctx;
3621 uint8_t *ctx_dsd_alloced;
3622 };
3623
3624 /* Multi queue support */
3625 #define MBC_INITIALIZE_MULTIQ 0x1f
3626 #define QLA_QUE_PAGE 0X1000
3627 #define QLA_MQ_SIZE 32
3628 #define QLA_MAX_QUEUES 256
3629 #define ISP_QUE_REG(ha, id) \
3630 ((ha->mqenable || IS_QLA83XX(ha) || \
3631 IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? \
3632 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3633 ((void __iomem *)ha->iobase))
3634 #define QLA_REQ_QUE_ID(tag) \
3635 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
3636 #define QLA_DEFAULT_QUE_QOS 5
3637 #define QLA_PRECONFIG_VPORTS 32
3638 #define QLA_MAX_VPORTS_QLA24XX 128
3639 #define QLA_MAX_VPORTS_QLA25XX 256
3640
3641 struct qla_tgt_counters {
3642 uint64_t qla_core_sbt_cmd;
3643 uint64_t core_qla_que_buf;
3644 uint64_t qla_core_ret_ctio;
3645 uint64_t core_qla_snd_status;
3646 uint64_t qla_core_ret_sta_ctio;
3647 uint64_t core_qla_free_cmd;
3648 uint64_t num_q_full_sent;
3649 uint64_t num_alloc_iocb_failed;
3650 uint64_t num_term_xchg_sent;
3651 };
3652
3653 struct qla_counters {
3654 uint64_t input_bytes;
3655 uint64_t input_requests;
3656 uint64_t output_bytes;
3657 uint64_t output_requests;
3658
3659 };
3660
3661 struct qla_qpair;
3662
3663 /* Response queue data structure */
3664 struct rsp_que {
3665 dma_addr_t dma;
3666 response_t *ring;
3667 response_t *ring_ptr;
3668 __le32 __iomem *rsp_q_in; /* FWI2-capable only. */
3669 __le32 __iomem *rsp_q_out;
3670 uint16_t ring_index;
3671 uint16_t out_ptr;
3672 uint16_t *in_ptr; /* queue shadow in index */
3673 uint16_t length;
3674 uint16_t options;
3675 uint16_t rid;
3676 uint16_t id;
3677 uint16_t vp_idx;
3678 struct qla_hw_data *hw;
3679 struct qla_msix_entry *msix;
3680 struct req_que *req;
3681 srb_t *status_srb; /* status continuation entry */
3682 struct qla_qpair *qpair;
3683
3684 dma_addr_t dma_fx00;
3685 response_t *ring_fx00;
3686 uint16_t length_fx00;
3687 uint8_t rsp_pkt[REQUEST_ENTRY_SIZE];
3688 };
3689
3690 /* Request queue data structure */
3691 struct req_que {
3692 dma_addr_t dma;
3693 request_t *ring;
3694 request_t *ring_ptr;
3695 __le32 __iomem *req_q_in; /* FWI2-capable only. */
3696 __le32 __iomem *req_q_out;
3697 uint16_t ring_index;
3698 uint16_t in_ptr;
3699 uint16_t *out_ptr; /* queue shadow out index */
3700 uint16_t cnt;
3701 uint16_t length;
3702 uint16_t options;
3703 uint16_t rid;
3704 uint16_t id;
3705 uint16_t qos;
3706 uint16_t vp_idx;
3707 struct rsp_que *rsp;
3708 srb_t **outstanding_cmds;
3709 uint32_t current_outstanding_cmd;
3710 uint16_t num_outstanding_cmds;
3711 int max_q_depth;
3712
3713 dma_addr_t dma_fx00;
3714 request_t *ring_fx00;
3715 uint16_t length_fx00;
3716 uint8_t req_pkt[REQUEST_ENTRY_SIZE];
3717 };
3718
3719 struct qla_fw_resources {
3720 u16 iocbs_total;
3721 u16 iocbs_limit;
3722 u16 iocbs_qp_limit;
3723 u16 iocbs_used;
3724 };
3725
3726 #define QLA_IOCB_PCT_LIMIT 95
3727
3728 /*Queue pair data structure */
3729 struct qla_qpair {
3730 spinlock_t qp_lock;
3731 atomic_t ref_count;
3732 uint32_t lun_cnt;
3733 /*
3734 * For qpair 0, qp_lock_ptr will point at hardware_lock due to
3735 * legacy code. For other Qpair(s), it will point at qp_lock.
3736 */
3737 spinlock_t *qp_lock_ptr;
3738 struct scsi_qla_host *vha;
3739 u32 chip_reset;
3740
3741 /* distill these fields down to 'online=0/1'
3742 * ha->flags.eeh_busy
3743 * ha->flags.pci_channel_io_perm_failure
3744 * base_vha->loop_state
3745 */
3746 uint32_t online:1;
3747 /* move vha->flags.difdix_supported here */
3748 uint32_t difdix_supported:1;
3749 uint32_t delete_in_progress:1;
3750 uint32_t fw_started:1;
3751 uint32_t enable_class_2:1;
3752 uint32_t enable_explicit_conf:1;
3753 uint32_t use_shadow_reg:1;
3754 uint32_t rcv_intr:1;
3755
3756 uint16_t id; /* qp number used with FW */
3757 uint16_t vp_idx; /* vport ID */
3758 mempool_t *srb_mempool;
3759
3760 struct pci_dev *pdev;
3761 void (*reqq_start_iocbs)(struct qla_qpair *);
3762
3763 /* to do: New driver: move queues to here instead of pointers */
3764 struct req_que *req;
3765 struct rsp_que *rsp;
3766 struct atio_que *atio;
3767 struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3768 struct qla_hw_data *hw;
3769 struct work_struct q_work;
3770 struct qla_counters counters;
3771
3772 struct list_head qp_list_elem; /* vha->qp_list */
3773 struct list_head hints_list;
3774
3775 uint16_t retry_term_cnt;
3776 __le32 retry_term_exchg_addr;
3777 uint64_t retry_term_jiff;
3778 struct qla_tgt_counters tgt_counters;
3779 uint16_t cpuid;
3780 struct qla_fw_resources fwres ____cacheline_aligned;
3781 u32 cmd_cnt;
3782 u32 cmd_completion_cnt;
3783 u32 prev_completion_cnt;
3784 };
3785
3786 /* Place holder for FW buffer parameters */
3787 struct qlfc_fw {
3788 void *fw_buf;
3789 dma_addr_t fw_dma;
3790 uint32_t len;
3791 };
3792
3793 struct rdp_req_payload {
3794 uint32_t els_request;
3795 uint32_t desc_list_len;
3796
3797 /* NPIV descriptor */
3798 struct {
3799 uint32_t desc_tag;
3800 uint32_t desc_len;
3801 uint8_t reserved;
3802 uint8_t nport_id[3];
3803 } npiv_desc;
3804 };
3805
3806 struct rdp_rsp_payload {
3807 struct {
3808 __be32 cmd;
3809 __be32 len;
3810 } hdr;
3811
3812 /* LS Request Info descriptor */
3813 struct {
3814 __be32 desc_tag;
3815 __be32 desc_len;
3816 __be32 req_payload_word_0;
3817 } ls_req_info_desc;
3818
3819 /* LS Request Info descriptor */
3820 struct {
3821 __be32 desc_tag;
3822 __be32 desc_len;
3823 __be32 req_payload_word_0;
3824 } ls_req_info_desc2;
3825
3826 /* SFP diagnostic param descriptor */
3827 struct {
3828 __be32 desc_tag;
3829 __be32 desc_len;
3830 __be16 temperature;
3831 __be16 vcc;
3832 __be16 tx_bias;
3833 __be16 tx_power;
3834 __be16 rx_power;
3835 __be16 sfp_flags;
3836 } sfp_diag_desc;
3837
3838 /* Port Speed Descriptor */
3839 struct {
3840 __be32 desc_tag;
3841 __be32 desc_len;
3842 __be16 speed_capab;
3843 __be16 operating_speed;
3844 } port_speed_desc;
3845
3846 /* Link Error Status Descriptor */
3847 struct {
3848 __be32 desc_tag;
3849 __be32 desc_len;
3850 __be32 link_fail_cnt;
3851 __be32 loss_sync_cnt;
3852 __be32 loss_sig_cnt;
3853 __be32 prim_seq_err_cnt;
3854 __be32 inval_xmit_word_cnt;
3855 __be32 inval_crc_cnt;
3856 uint8_t pn_port_phy_type;
3857 uint8_t reserved[3];
3858 } ls_err_desc;
3859
3860 /* Port name description with diag param */
3861 struct {
3862 __be32 desc_tag;
3863 __be32 desc_len;
3864 uint8_t WWNN[WWN_SIZE];
3865 uint8_t WWPN[WWN_SIZE];
3866 } port_name_diag_desc;
3867
3868 /* Port Name desc for Direct attached Fx_Port or Nx_Port */
3869 struct {
3870 __be32 desc_tag;
3871 __be32 desc_len;
3872 uint8_t WWNN[WWN_SIZE];
3873 uint8_t WWPN[WWN_SIZE];
3874 } port_name_direct_desc;
3875
3876 /* Buffer Credit descriptor */
3877 struct {
3878 __be32 desc_tag;
3879 __be32 desc_len;
3880 __be32 fcport_b2b;
3881 __be32 attached_fcport_b2b;
3882 __be32 fcport_rtt;
3883 } buffer_credit_desc;
3884
3885 /* Optical Element Data Descriptor */
3886 struct {
3887 __be32 desc_tag;
3888 __be32 desc_len;
3889 __be16 high_alarm;
3890 __be16 low_alarm;
3891 __be16 high_warn;
3892 __be16 low_warn;
3893 __be32 element_flags;
3894 } optical_elmt_desc[5];
3895
3896 /* Optical Product Data Descriptor */
3897 struct {
3898 __be32 desc_tag;
3899 __be32 desc_len;
3900 uint8_t vendor_name[16];
3901 uint8_t part_number[16];
3902 uint8_t serial_number[16];
3903 uint8_t revision[4];
3904 uint8_t date[8];
3905 } optical_prod_desc;
3906 };
3907
3908 #define RDP_DESC_LEN(obj) \
3909 (sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len))
3910
3911 #define RDP_PORT_SPEED_1GB BIT_15
3912 #define RDP_PORT_SPEED_2GB BIT_14
3913 #define RDP_PORT_SPEED_4GB BIT_13
3914 #define RDP_PORT_SPEED_10GB BIT_12
3915 #define RDP_PORT_SPEED_8GB BIT_11
3916 #define RDP_PORT_SPEED_16GB BIT_10
3917 #define RDP_PORT_SPEED_32GB BIT_9
3918 #define RDP_PORT_SPEED_64GB BIT_8
3919 #define RDP_PORT_SPEED_UNKNOWN BIT_0
3920
3921 struct scsi_qlt_host {
3922 void *target_lport_ptr;
3923 struct mutex tgt_mutex;
3924 struct mutex tgt_host_action_mutex;
3925 struct qla_tgt *qla_tgt;
3926 };
3927
3928 struct qlt_hw_data {
3929 /* Protected by hw lock */
3930 uint32_t node_name_set:1;
3931
3932 dma_addr_t atio_dma; /* Physical address. */
3933 struct atio *atio_ring; /* Base virtual address */
3934 struct atio *atio_ring_ptr; /* Current address. */
3935 uint16_t atio_ring_index; /* Current index. */
3936 uint16_t atio_q_length;
3937 __le32 __iomem *atio_q_in;
3938 __le32 __iomem *atio_q_out;
3939
3940 const struct qla_tgt_func_tmpl *tgt_ops;
3941 struct qla_tgt_vp_map *tgt_vp_map;
3942
3943 int saved_set;
3944 __le16 saved_exchange_count;
3945 __le32 saved_firmware_options_1;
3946 __le32 saved_firmware_options_2;
3947 __le32 saved_firmware_options_3;
3948 uint8_t saved_firmware_options[2];
3949 uint8_t saved_add_firmware_options[2];
3950
3951 uint8_t tgt_node_name[WWN_SIZE];
3952
3953 struct dentry *dfs_tgt_sess;
3954 struct dentry *dfs_tgt_port_database;
3955 struct dentry *dfs_naqp;
3956
3957 struct list_head q_full_list;
3958 uint32_t num_pend_cmds;
3959 uint32_t num_qfull_cmds_alloc;
3960 uint32_t num_qfull_cmds_dropped;
3961 spinlock_t q_full_lock;
3962 uint32_t leak_exchg_thresh_hold;
3963 spinlock_t sess_lock;
3964 int num_act_qpairs;
3965 #define DEFAULT_NAQP 2
3966 spinlock_t atio_lock ____cacheline_aligned;
3967 };
3968
3969 #define MAX_QFULL_CMDS_ALLOC 8192
3970 #define Q_FULL_THRESH_HOLD_PERCENT 90
3971 #define Q_FULL_THRESH_HOLD(ha) \
3972 ((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
3973
3974 #define LEAK_EXCHG_THRESH_HOLD_PERCENT 75 /* 75 percent */
3975
3976 struct qla_hw_data_stat {
3977 u32 num_fw_dump;
3978 u32 num_mpi_reset;
3979 };
3980
3981 /* refer to pcie_do_recovery reference */
3982 typedef enum {
3983 QLA_PCI_RESUME,
3984 QLA_PCI_ERR_DETECTED,
3985 QLA_PCI_MMIO_ENABLED,
3986 QLA_PCI_SLOT_RESET,
3987 } pci_error_state_t;
3988 /*
3989 * Qlogic host adapter specific data structure.
3990 */
3991 struct qla_hw_data {
3992 struct pci_dev *pdev;
3993 /* SRB cache. */
3994 #define SRB_MIN_REQ 128
3995 mempool_t *srb_mempool;
3996 u8 port_name[WWN_SIZE];
3997
3998 volatile struct {
3999 uint32_t mbox_int :1;
4000 uint32_t mbox_busy :1;
4001 uint32_t disable_risc_code_load :1;
4002 uint32_t enable_64bit_addressing :1;
4003 uint32_t enable_lip_reset :1;
4004 uint32_t enable_target_reset :1;
4005 uint32_t enable_lip_full_login :1;
4006 uint32_t enable_led_scheme :1;
4007
4008 uint32_t msi_enabled :1;
4009 uint32_t msix_enabled :1;
4010 uint32_t disable_serdes :1;
4011 uint32_t gpsc_supported :1;
4012 uint32_t npiv_supported :1;
4013 uint32_t pci_channel_io_perm_failure :1;
4014 uint32_t fce_enabled :1;
4015 uint32_t fac_supported :1;
4016
4017 uint32_t chip_reset_done :1;
4018 uint32_t running_gold_fw :1;
4019 uint32_t eeh_busy :1;
4020 uint32_t disable_msix_handshake :1;
4021 uint32_t fcp_prio_enabled :1;
4022 uint32_t isp82xx_fw_hung:1;
4023 uint32_t nic_core_hung:1;
4024
4025 uint32_t quiesce_owner:1;
4026 uint32_t nic_core_reset_hdlr_active:1;
4027 uint32_t nic_core_reset_owner:1;
4028 uint32_t isp82xx_no_md_cap:1;
4029 uint32_t host_shutting_down:1;
4030 uint32_t idc_compl_status:1;
4031 uint32_t mr_reset_hdlr_active:1;
4032 uint32_t mr_intr_valid:1;
4033
4034 uint32_t dport_enabled:1;
4035 uint32_t fawwpn_enabled:1;
4036 uint32_t exlogins_enabled:1;
4037 uint32_t exchoffld_enabled:1;
4038
4039 uint32_t lip_ae:1;
4040 uint32_t n2n_ae:1;
4041 uint32_t fw_started:1;
4042 uint32_t fw_init_done:1;
4043
4044 uint32_t lr_detected:1;
4045
4046 uint32_t rida_fmt2:1;
4047 uint32_t purge_mbox:1;
4048 uint32_t n2n_bigger:1;
4049 uint32_t secure_adapter:1;
4050 uint32_t secure_fw:1;
4051 /* Supported by Adapter */
4052 uint32_t scm_supported_a:1;
4053 /* Supported by Firmware */
4054 uint32_t scm_supported_f:1;
4055 /* Enabled in Driver */
4056 uint32_t scm_enabled:1;
4057 uint32_t edif_hw:1;
4058 uint32_t edif_enabled:1;
4059 uint32_t n2n_fw_acc_sec:1;
4060 uint32_t plogi_template_valid:1;
4061 uint32_t port_isolated:1;
4062 uint32_t eeh_flush:2;
4063 #define EEH_FLUSH_RDY 1
4064 #define EEH_FLUSH_DONE 2
4065 } flags;
4066
4067 uint16_t max_exchg;
4068 uint16_t lr_distance; /* 32G & above */
4069 #define LR_DISTANCE_5K 1
4070 #define LR_DISTANCE_10K 0
4071
4072 /* This spinlock is used to protect "io transactions", you must
4073 * acquire it before doing any IO to the card, eg with RD_REG*() and
4074 * WRT_REG*() for the duration of your entire commandtransaction.
4075 *
4076 * This spinlock is of lower priority than the io request lock.
4077 */
4078
4079 spinlock_t hardware_lock ____cacheline_aligned;
4080 int bars;
4081 int mem_only;
4082 device_reg_t *iobase; /* Base I/O address */
4083 resource_size_t pio_address;
4084
4085 #define MIN_IOBASE_LEN 0x100
4086 dma_addr_t bar0_hdl;
4087
4088 void __iomem *cregbase;
4089 dma_addr_t bar2_hdl;
4090 #define BAR0_LEN_FX00 (1024 * 1024)
4091 #define BAR2_LEN_FX00 (128 * 1024)
4092
4093 uint32_t rqstq_intr_code;
4094 uint32_t mbx_intr_code;
4095 uint32_t req_que_len;
4096 uint32_t rsp_que_len;
4097 uint32_t req_que_off;
4098 uint32_t rsp_que_off;
4099 unsigned long eeh_jif;
4100
4101 /* Multi queue data structs */
4102 device_reg_t *mqiobase;
4103 device_reg_t *msixbase;
4104 uint16_t msix_count;
4105 uint8_t mqenable;
4106 struct req_que **req_q_map;
4107 struct rsp_que **rsp_q_map;
4108 struct qla_qpair **queue_pair_map;
4109 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
4110 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
4111 unsigned long qpair_qid_map[(QLA_MAX_QUEUES / 8)
4112 / sizeof(unsigned long)];
4113 uint8_t max_req_queues;
4114 uint8_t max_rsp_queues;
4115 uint8_t max_qpairs;
4116 uint8_t num_qpairs;
4117 struct qla_qpair *base_qpair;
4118 struct qla_npiv_entry *npiv_info;
4119 uint16_t nvram_npiv_size;
4120
4121 uint16_t switch_cap;
4122 #define FLOGI_SEQ_DEL BIT_8
4123 #define FLOGI_MID_SUPPORT BIT_10
4124 #define FLOGI_VSAN_SUPPORT BIT_12
4125 #define FLOGI_SP_SUPPORT BIT_13
4126
4127 uint8_t port_no; /* Physical port of adapter */
4128 uint8_t exch_starvation;
4129
4130 /* Timeout timers. */
4131 uint8_t loop_down_abort_time; /* port down timer */
4132 atomic_t loop_down_timer; /* loop down timer */
4133 uint8_t link_down_timeout; /* link down timeout */
4134 uint16_t max_loop_id;
4135 uint16_t max_fibre_devices; /* Maximum number of targets */
4136
4137 uint16_t fb_rev;
4138 uint16_t min_external_loopid; /* First external loop Id */
4139
4140 #define PORT_SPEED_UNKNOWN 0xFFFF
4141 #define PORT_SPEED_1GB 0x00
4142 #define PORT_SPEED_2GB 0x01
4143 #define PORT_SPEED_AUTO 0x02
4144 #define PORT_SPEED_4GB 0x03
4145 #define PORT_SPEED_8GB 0x04
4146 #define PORT_SPEED_16GB 0x05
4147 #define PORT_SPEED_32GB 0x06
4148 #define PORT_SPEED_64GB 0x07
4149 #define PORT_SPEED_10GB 0x13
4150 uint16_t link_data_rate; /* F/W operating speed */
4151 uint16_t set_data_rate; /* Set by user */
4152
4153 uint8_t current_topology;
4154 uint8_t prev_topology;
4155 #define ISP_CFG_NL 1
4156 #define ISP_CFG_N 2
4157 #define ISP_CFG_FL 4
4158 #define ISP_CFG_F 8
4159
4160 uint8_t operating_mode; /* F/W operating mode */
4161 #define LOOP 0
4162 #define P2P 1
4163 #define LOOP_P2P 2
4164 #define P2P_LOOP 3
4165 uint8_t interrupts_on;
4166 uint32_t isp_abort_cnt;
4167 #define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
4168 #define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
4169 #define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
4170 #define PCI_DEVICE_ID_QLOGIC_ISP8031 0x8031
4171 #define PCI_DEVICE_ID_QLOGIC_ISP2031 0x2031
4172 #define PCI_DEVICE_ID_QLOGIC_ISP2071 0x2071
4173 #define PCI_DEVICE_ID_QLOGIC_ISP2271 0x2271
4174 #define PCI_DEVICE_ID_QLOGIC_ISP2261 0x2261
4175 #define PCI_DEVICE_ID_QLOGIC_ISP2061 0x2061
4176 #define PCI_DEVICE_ID_QLOGIC_ISP2081 0x2081
4177 #define PCI_DEVICE_ID_QLOGIC_ISP2089 0x2089
4178 #define PCI_DEVICE_ID_QLOGIC_ISP2281 0x2281
4179 #define PCI_DEVICE_ID_QLOGIC_ISP2289 0x2289
4180
4181 uint32_t isp_type;
4182 #define DT_ISP2100 BIT_0
4183 #define DT_ISP2200 BIT_1
4184 #define DT_ISP2300 BIT_2
4185 #define DT_ISP2312 BIT_3
4186 #define DT_ISP2322 BIT_4
4187 #define DT_ISP6312 BIT_5
4188 #define DT_ISP6322 BIT_6
4189 #define DT_ISP2422 BIT_7
4190 #define DT_ISP2432 BIT_8
4191 #define DT_ISP5422 BIT_9
4192 #define DT_ISP5432 BIT_10
4193 #define DT_ISP2532 BIT_11
4194 #define DT_ISP8432 BIT_12
4195 #define DT_ISP8001 BIT_13
4196 #define DT_ISP8021 BIT_14
4197 #define DT_ISP2031 BIT_15
4198 #define DT_ISP8031 BIT_16
4199 #define DT_ISPFX00 BIT_17
4200 #define DT_ISP8044 BIT_18
4201 #define DT_ISP2071 BIT_19
4202 #define DT_ISP2271 BIT_20
4203 #define DT_ISP2261 BIT_21
4204 #define DT_ISP2061 BIT_22
4205 #define DT_ISP2081 BIT_23
4206 #define DT_ISP2089 BIT_24
4207 #define DT_ISP2281 BIT_25
4208 #define DT_ISP2289 BIT_26
4209 #define DT_ISP_LAST (DT_ISP2289 << 1)
4210
4211 uint32_t device_type;
4212 #define DT_T10_PI BIT_25
4213 #define DT_IIDMA BIT_26
4214 #define DT_FWI2 BIT_27
4215 #define DT_ZIO_SUPPORTED BIT_28
4216 #define DT_OEM_001 BIT_29
4217 #define DT_ISP2200A BIT_30
4218 #define DT_EXTENDED_IDS BIT_31
4219
4220 #define DT_MASK(ha) ((ha)->isp_type & (DT_ISP_LAST - 1))
4221 #define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
4222 #define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
4223 #define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
4224 #define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
4225 #define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
4226 #define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
4227 #define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
4228 #define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
4229 #define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
4230 #define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
4231 #define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
4232 #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
4233 #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
4234 #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
4235 #define IS_QLA81XX(ha) (IS_QLA8001(ha))
4236 #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021)
4237 #define IS_QLA8044(ha) (DT_MASK(ha) & DT_ISP8044)
4238 #define IS_QLA2031(ha) (DT_MASK(ha) & DT_ISP2031)
4239 #define IS_QLA8031(ha) (DT_MASK(ha) & DT_ISP8031)
4240 #define IS_QLAFX00(ha) (DT_MASK(ha) & DT_ISPFX00)
4241 #define IS_QLA2071(ha) (DT_MASK(ha) & DT_ISP2071)
4242 #define IS_QLA2271(ha) (DT_MASK(ha) & DT_ISP2271)
4243 #define IS_QLA2261(ha) (DT_MASK(ha) & DT_ISP2261)
4244 #define IS_QLA2081(ha) (DT_MASK(ha) & DT_ISP2081)
4245 #define IS_QLA2281(ha) (DT_MASK(ha) & DT_ISP2281)
4246
4247 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
4248 IS_QLA6312(ha) || IS_QLA6322(ha))
4249 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
4250 #define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
4251 #define IS_QLA25XX(ha) (IS_QLA2532(ha))
4252 #define IS_QLA83XX(ha) (IS_QLA2031(ha) || IS_QLA8031(ha))
4253 #define IS_QLA84XX(ha) (IS_QLA8432(ha))
4254 #define IS_QLA27XX(ha) (IS_QLA2071(ha) || IS_QLA2271(ha) || IS_QLA2261(ha))
4255 #define IS_QLA28XX(ha) (IS_QLA2081(ha) || IS_QLA2281(ha))
4256 #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
4257 IS_QLA84XX(ha))
4258 #define IS_CNA_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha) || \
4259 IS_QLA8031(ha) || IS_QLA8044(ha))
4260 #define IS_P3P_TYPE(ha) (IS_QLA82XX(ha) || IS_QLA8044(ha))
4261 #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
4262 IS_QLA25XX(ha) || IS_QLA81XX(ha) || \
4263 IS_QLA82XX(ha) || IS_QLA83XX(ha) || \
4264 IS_QLA8044(ha) || IS_QLA27XX(ha) || \
4265 IS_QLA28XX(ha))
4266 #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4267 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4268 #define IS_NOPOLLING_TYPE(ha) (IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
4269 #define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4270 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4271 #define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4272 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4273 #define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
4274
4275 #define IS_T10_PI_CAPABLE(ha) ((ha)->device_type & DT_T10_PI)
4276 #define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
4277 #define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
4278 #define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
4279 #define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
4280 #define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
4281 #define IS_CT6_SUPPORTED(ha) ((ha)->device_type & DT_CT6_SUPPORTED)
4282 #define IS_MQUE_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4283 IS_QLA28XX(ha))
4284 #define IS_BIDI_CAPABLE(ha) \
4285 (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4286 /* Bit 21 of fw_attributes decides the MCTP capabilities */
4287 #define IS_MCTP_CAPABLE(ha) (IS_QLA2031(ha) && \
4288 ((ha)->fw_attributes_ext[0] & BIT_0))
4289 #define QLA_ABTS_FW_ENABLED(_ha) ((_ha)->fw_attributes_ext[0] & BIT_14)
4290 #define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS)
4291 #define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD)
4292 #define QLA_NVME_IOS(_sp) (QLA_SRB_NVME_CMD(_sp) || QLA_SRB_NVME_LS(_sp))
4293 #define QLA_LS_ABTS_WAIT_ENABLED(_sp) \
4294 (QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4295 #define QLA_CMD_ABTS_WAIT_ENABLED(_sp) \
4296 (QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4297 #define QLA_ABTS_WAIT_ENABLED(_sp) \
4298 (QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4299
4300 #define IS_PI_UNINIT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4301 IS_QLA28XX(ha))
4302 #define IS_PI_IPGUARD_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4303 IS_QLA28XX(ha))
4304 #define IS_PI_DIFB_DIX0_CAPABLE(ha) (0)
4305 #define IS_PI_SPLIT_DET_CAPABLE_HBA(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4306 IS_QLA28XX(ha))
4307 #define IS_PI_SPLIT_DET_CAPABLE(ha) (IS_PI_SPLIT_DET_CAPABLE_HBA(ha) && \
4308 (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
4309 #define IS_ATIO_MSIX_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4310 IS_QLA28XX(ha))
4311 #define IS_TGT_MODE_CAPABLE(ha) (ha->tgt.atio_q_length)
4312 #define IS_SHADOW_REG_CAPABLE(ha) (IS_QLA27XX(ha) || IS_QLA28XX(ha))
4313 #define IS_DPORT_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4314 IS_QLA28XX(ha))
4315 #define IS_FAWWN_CAPABLE(ha) (IS_QLA83XX(ha) || IS_QLA27XX(ha) || \
4316 IS_QLA28XX(ha))
4317 #define IS_EXCHG_OFFLD_CAPABLE(ha) \
4318 (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4319 #define IS_EXLOGIN_OFFLD_CAPABLE(ha) \
4320 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
4321 IS_QLA27XX(ha) || IS_QLA28XX(ha))
4322 #define USE_ASYNC_SCAN(ha) (IS_QLA25XX(ha) || IS_QLA81XX(ha) ||\
4323 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
4324
4325 #define IS_ZIO_THRESHOLD_CAPABLE(ha) \
4326 ((IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) &&\
4327 (ha->zio_mode == QLA_ZIO_MODE_6))
4328
4329 /* HBA serial number */
4330 uint8_t serial0;
4331 uint8_t serial1;
4332 uint8_t serial2;
4333
4334 /* NVRAM configuration data */
4335 #define MAX_NVRAM_SIZE 4096
4336 #define VPD_OFFSET (MAX_NVRAM_SIZE / 2)
4337 uint16_t nvram_size;
4338 uint16_t nvram_base;
4339 void *nvram;
4340 uint16_t vpd_size;
4341 uint16_t vpd_base;
4342 void *vpd;
4343
4344 uint16_t loop_reset_delay;
4345 uint8_t retry_count;
4346 uint8_t login_timeout;
4347 uint16_t r_a_tov;
4348 int port_down_retry_count;
4349 uint8_t mbx_count;
4350 uint8_t aen_mbx_count;
4351 atomic_t num_pend_mbx_stage1;
4352 atomic_t num_pend_mbx_stage2;
4353 atomic_t num_pend_mbx_stage3;
4354 uint16_t frame_payload_size;
4355
4356 uint32_t login_retry_count;
4357 /* SNS command interfaces. */
4358 ms_iocb_entry_t *ms_iocb;
4359 dma_addr_t ms_iocb_dma;
4360 struct ct_sns_pkt *ct_sns;
4361 dma_addr_t ct_sns_dma;
4362 /* SNS command interfaces for 2200. */
4363 struct sns_cmd_pkt *sns_cmd;
4364 dma_addr_t sns_cmd_dma;
4365
4366 #define SFP_DEV_SIZE 512
4367 #define SFP_BLOCK_SIZE 64
4368 #define SFP_RTDI_LEN SFP_BLOCK_SIZE
4369
4370 void *sfp_data;
4371 dma_addr_t sfp_data_dma;
4372
4373 struct qla_flt_header *flt;
4374 dma_addr_t flt_dma;
4375
4376 #define XGMAC_DATA_SIZE 4096
4377 void *xgmac_data;
4378 dma_addr_t xgmac_data_dma;
4379
4380 #define DCBX_TLV_DATA_SIZE 4096
4381 void *dcbx_tlv;
4382 dma_addr_t dcbx_tlv_dma;
4383
4384 struct task_struct *dpc_thread;
4385 uint8_t dpc_active; /* DPC routine is active */
4386
4387 dma_addr_t gid_list_dma;
4388 struct gid_list_info *gid_list;
4389 int gid_list_info_size;
4390
4391 /* Small DMA pool allocations -- maximum 256 bytes in length. */
4392 #define DMA_POOL_SIZE 256
4393 struct dma_pool *s_dma_pool;
4394
4395 dma_addr_t init_cb_dma;
4396 init_cb_t *init_cb;
4397 int init_cb_size;
4398 dma_addr_t ex_init_cb_dma;
4399 struct ex_init_cb_81xx *ex_init_cb;
4400 dma_addr_t sf_init_cb_dma;
4401 struct init_sf_cb *sf_init_cb;
4402
4403 void *scm_fpin_els_buff;
4404 uint64_t scm_fpin_els_buff_size;
4405 bool scm_fpin_valid;
4406 bool scm_fpin_payload_size;
4407
4408 void *async_pd;
4409 dma_addr_t async_pd_dma;
4410
4411 #define ENABLE_EXTENDED_LOGIN BIT_7
4412
4413 /* Extended Logins */
4414 void *exlogin_buf;
4415 dma_addr_t exlogin_buf_dma;
4416 uint32_t exlogin_size;
4417
4418 #define ENABLE_EXCHANGE_OFFLD BIT_2
4419
4420 /* Exchange Offload */
4421 void *exchoffld_buf;
4422 dma_addr_t exchoffld_buf_dma;
4423 int exchoffld_size;
4424 int exchoffld_count;
4425
4426 /* n2n */
4427 struct fc_els_flogi plogi_els_payld;
4428 #define LOGIN_TEMPLATE_SIZE (sizeof(struct fc_els_flogi) - 4)
4429
4430 void *swl;
4431
4432 /* These are used by mailbox operations. */
4433 uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
4434 uint32_t mailbox_out32[MAILBOX_REGISTER_COUNT];
4435 uint32_t aenmb[AEN_MAILBOX_REGISTER_COUNT_FX00];
4436
4437 mbx_cmd_t *mcp;
4438 struct mbx_cmd_32 *mcp32;
4439
4440 unsigned long mbx_cmd_flags;
4441 #define MBX_INTERRUPT 1
4442 #define MBX_INTR_WAIT 2
4443 #define MBX_UPDATE_FLASH_ACTIVE 3
4444
4445 struct mutex vport_lock; /* Virtual port synchronization */
4446 spinlock_t vport_slock; /* order is hardware_lock, then vport_slock */
4447 struct mutex mq_lock; /* multi-queue synchronization */
4448 struct completion mbx_cmd_comp; /* Serialize mbx access */
4449 struct completion mbx_intr_comp; /* Used for completion notification */
4450 struct completion dcbx_comp; /* For set port config notification */
4451 struct completion lb_portup_comp; /* Used to wait for link up during
4452 * loopback */
4453 #define DCBX_COMP_TIMEOUT 20
4454 #define LB_PORTUP_COMP_TIMEOUT 10
4455
4456 int notify_dcbx_comp;
4457 int notify_lb_portup_comp;
4458 struct mutex selflogin_lock;
4459
4460 /* Basic firmware related information. */
4461 uint16_t fw_major_version;
4462 uint16_t fw_minor_version;
4463 uint16_t fw_subminor_version;
4464 uint16_t fw_attributes;
4465 uint16_t fw_attributes_h;
4466 #define FW_ATTR_H_NVME_FBURST BIT_1
4467 #define FW_ATTR_H_NVME BIT_10
4468 #define FW_ATTR_H_NVME_UPDATED BIT_14
4469
4470 /* About firmware SCM support */
4471 #define FW_ATTR_EXT0_SCM_SUPPORTED BIT_12
4472 /* Brocade fabric attached */
4473 #define FW_ATTR_EXT0_SCM_BROCADE 0x00001000
4474 /* Cisco fabric attached */
4475 #define FW_ATTR_EXT0_SCM_CISCO 0x00002000
4476 #define FW_ATTR_EXT0_NVME2 BIT_13
4477 #define FW_ATTR_EXT0_EDIF BIT_5
4478 uint16_t fw_attributes_ext[2];
4479 uint32_t fw_memory_size;
4480 uint32_t fw_transfer_size;
4481 uint32_t fw_srisc_address;
4482 #define RISC_START_ADDRESS_2100 0x1000
4483 #define RISC_START_ADDRESS_2300 0x800
4484 #define RISC_START_ADDRESS_2400 0x100000
4485
4486 uint16_t orig_fw_tgt_xcb_count;
4487 uint16_t cur_fw_tgt_xcb_count;
4488 uint16_t orig_fw_xcb_count;
4489 uint16_t cur_fw_xcb_count;
4490 uint16_t orig_fw_iocb_count;
4491 uint16_t cur_fw_iocb_count;
4492 uint16_t fw_max_fcf_count;
4493
4494 uint32_t fw_shared_ram_start;
4495 uint32_t fw_shared_ram_end;
4496 uint32_t fw_ddr_ram_start;
4497 uint32_t fw_ddr_ram_end;
4498
4499 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
4500 uint8_t fw_seriallink_options[4];
4501 __le16 fw_seriallink_options24[4];
4502
4503 uint8_t serdes_version[3];
4504 uint8_t mpi_version[3];
4505 uint32_t mpi_capabilities;
4506 uint8_t phy_version[3];
4507 uint8_t pep_version[3];
4508
4509 /* Firmware dump template */
4510 struct fwdt {
4511 void *template;
4512 ulong length;
4513 ulong dump_size;
4514 } fwdt[2];
4515 struct qla2xxx_fw_dump *fw_dump;
4516 uint32_t fw_dump_len;
4517 u32 fw_dump_alloc_len;
4518 bool fw_dumped;
4519 unsigned long fw_dump_cap_flags;
4520 #define RISC_PAUSE_CMPL 0
4521 #define DMA_SHUTDOWN_CMPL 1
4522 #define ISP_RESET_CMPL 2
4523 #define RISC_RDY_AFT_RESET 3
4524 #define RISC_SRAM_DUMP_CMPL 4
4525 #define RISC_EXT_MEM_DUMP_CMPL 5
4526 #define ISP_MBX_RDY 6
4527 #define ISP_SOFT_RESET_CMPL 7
4528 int fw_dump_reading;
4529 void *mpi_fw_dump;
4530 u32 mpi_fw_dump_len;
4531 unsigned int mpi_fw_dump_reading:1;
4532 unsigned int mpi_fw_dumped:1;
4533 int prev_minidump_failed;
4534 dma_addr_t eft_dma;
4535 void *eft;
4536 /* Current size of mctp dump is 0x086064 bytes */
4537 #define MCTP_DUMP_SIZE 0x086064
4538 dma_addr_t mctp_dump_dma;
4539 void *mctp_dump;
4540 int mctp_dumped;
4541 int mctp_dump_reading;
4542 uint32_t chain_offset;
4543 struct dentry *dfs_dir;
4544 struct dentry *dfs_fce;
4545 struct dentry *dfs_tgt_counters;
4546 struct dentry *dfs_fw_resource_cnt;
4547
4548 dma_addr_t fce_dma;
4549 void *fce;
4550 uint32_t fce_bufs;
4551 uint16_t fce_mb[8];
4552 uint64_t fce_wr, fce_rd;
4553 struct mutex fce_mutex;
4554
4555 uint32_t pci_attr;
4556 uint16_t chip_revision;
4557
4558 uint16_t product_id[4];
4559
4560 uint8_t model_number[16+1];
4561 char model_desc[80];
4562 uint8_t adapter_id[16+1];
4563
4564 /* Option ROM information. */
4565 char *optrom_buffer;
4566 uint32_t optrom_size;
4567 int optrom_state;
4568 #define QLA_SWAITING 0
4569 #define QLA_SREADING 1
4570 #define QLA_SWRITING 2
4571 uint32_t optrom_region_start;
4572 uint32_t optrom_region_size;
4573 struct mutex optrom_mutex;
4574
4575 /* PCI expansion ROM image information. */
4576 #define ROM_CODE_TYPE_BIOS 0
4577 #define ROM_CODE_TYPE_FCODE 1
4578 #define ROM_CODE_TYPE_EFI 3
4579 uint8_t bios_revision[2];
4580 uint8_t efi_revision[2];
4581 uint8_t fcode_revision[16];
4582 uint32_t fw_revision[4];
4583
4584 uint32_t gold_fw_version[4];
4585
4586 /* Offsets for flash/nvram access (set to ~0 if not used). */
4587 uint32_t flash_conf_off;
4588 uint32_t flash_data_off;
4589 uint32_t nvram_conf_off;
4590 uint32_t nvram_data_off;
4591
4592 uint32_t fdt_wrt_disable;
4593 uint32_t fdt_wrt_enable;
4594 uint32_t fdt_erase_cmd;
4595 uint32_t fdt_block_size;
4596 uint32_t fdt_unprotect_sec_cmd;
4597 uint32_t fdt_protect_sec_cmd;
4598 uint32_t fdt_wrt_sts_reg_cmd;
4599
4600 struct {
4601 uint32_t flt_region_flt;
4602 uint32_t flt_region_fdt;
4603 uint32_t flt_region_boot;
4604 uint32_t flt_region_boot_sec;
4605 uint32_t flt_region_fw;
4606 uint32_t flt_region_fw_sec;
4607 uint32_t flt_region_vpd_nvram;
4608 uint32_t flt_region_vpd_nvram_sec;
4609 uint32_t flt_region_vpd;
4610 uint32_t flt_region_vpd_sec;
4611 uint32_t flt_region_nvram;
4612 uint32_t flt_region_nvram_sec;
4613 uint32_t flt_region_npiv_conf;
4614 uint32_t flt_region_gold_fw;
4615 uint32_t flt_region_fcp_prio;
4616 uint32_t flt_region_bootload;
4617 uint32_t flt_region_img_status_pri;
4618 uint32_t flt_region_img_status_sec;
4619 uint32_t flt_region_aux_img_status_pri;
4620 uint32_t flt_region_aux_img_status_sec;
4621 };
4622 uint8_t active_image;
4623
4624 /* Needed for BEACON */
4625 uint16_t beacon_blink_led;
4626 uint8_t beacon_color_state;
4627 #define QLA_LED_GRN_ON 0x01
4628 #define QLA_LED_YLW_ON 0x02
4629 #define QLA_LED_ABR_ON 0x04
4630 #define QLA_LED_ALL_ON 0x07 /* yellow, green, amber. */
4631 /* ISP2322: red, green, amber. */
4632 uint16_t zio_mode;
4633 uint16_t zio_timer;
4634
4635 struct qla_msix_entry *msix_entries;
4636
4637 struct list_head vp_list; /* list of VP */
4638 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
4639 sizeof(unsigned long)];
4640 uint16_t num_vhosts; /* number of vports created */
4641 uint16_t num_vsans; /* number of vsan created */
4642 uint16_t max_npiv_vports; /* 63 or 125 per topoloty */
4643 int cur_vport_count;
4644
4645 struct qla_chip_state_84xx *cs84xx;
4646 struct isp_operations *isp_ops;
4647 struct workqueue_struct *wq;
4648 struct work_struct heartbeat_work;
4649 struct qlfc_fw fw_buf;
4650 unsigned long last_heartbeat_run_jiffies;
4651
4652 /* FCP_CMND priority support */
4653 struct qla_fcp_prio_cfg *fcp_prio_cfg;
4654
4655 struct dma_pool *dl_dma_pool;
4656 #define DSD_LIST_DMA_POOL_SIZE 512
4657
4658 struct dma_pool *fcp_cmnd_dma_pool;
4659 mempool_t *ctx_mempool;
4660 #define FCP_CMND_DMA_POOL_SIZE 512
4661
4662 void __iomem *nx_pcibase; /* Base I/O address */
4663 void __iomem *nxdb_rd_ptr; /* Doorbell read pointer */
4664 void __iomem *nxdb_wr_ptr; /* Door bell write pointer */
4665
4666 uint32_t crb_win;
4667 uint32_t curr_window;
4668 uint32_t ddr_mn_window;
4669 unsigned long mn_win_crb;
4670 unsigned long ms_win_crb;
4671 int qdr_sn_window;
4672 uint32_t fcoe_dev_init_timeout;
4673 uint32_t fcoe_reset_timeout;
4674 rwlock_t hw_lock;
4675 uint16_t portnum; /* port number */
4676 int link_width;
4677 struct fw_blob *hablob;
4678 struct qla82xx_legacy_intr_set nx_legacy_intr;
4679
4680 uint16_t gbl_dsd_inuse;
4681 uint16_t gbl_dsd_avail;
4682 struct list_head gbl_dsd_list;
4683 #define NUM_DSD_CHAIN 4096
4684
4685 uint8_t fw_type;
4686 uint32_t file_prd_off; /* File firmware product offset */
4687
4688 uint32_t md_template_size;
4689 void *md_tmplt_hdr;
4690 dma_addr_t md_tmplt_hdr_dma;
4691 void *md_dump;
4692 uint32_t md_dump_size;
4693
4694 void *loop_id_map;
4695
4696 /* QLA83XX IDC specific fields */
4697 uint32_t idc_audit_ts;
4698 uint32_t idc_extend_tmo;
4699
4700 /* DPC low-priority workqueue */
4701 struct workqueue_struct *dpc_lp_wq;
4702 struct work_struct idc_aen;
4703 /* DPC high-priority workqueue */
4704 struct workqueue_struct *dpc_hp_wq;
4705 struct work_struct nic_core_reset;
4706 struct work_struct idc_state_handler;
4707 struct work_struct nic_core_unrecoverable;
4708 struct work_struct board_disable;
4709
4710 struct mr_data_fx00 mr;
4711 uint32_t chip_reset;
4712
4713 struct qlt_hw_data tgt;
4714 int allow_cna_fw_dump;
4715 uint32_t fw_ability_mask;
4716 uint16_t min_supported_speed;
4717 uint16_t max_supported_speed;
4718
4719 /* DMA pool for the DIF bundling buffers */
4720 struct dma_pool *dif_bundl_pool;
4721 #define DIF_BUNDLING_DMA_POOL_SIZE 1024
4722 struct {
4723 struct {
4724 struct list_head head;
4725 uint count;
4726 } good;
4727 struct {
4728 struct list_head head;
4729 uint count;
4730 } unusable;
4731 } pool;
4732
4733 unsigned long long dif_bundle_crossed_pages;
4734 unsigned long long dif_bundle_reads;
4735 unsigned long long dif_bundle_writes;
4736 unsigned long long dif_bundle_kallocs;
4737 unsigned long long dif_bundle_dma_allocs;
4738
4739 atomic_t nvme_active_aen_cnt;
4740 uint16_t nvme_last_rptd_aen; /* Last recorded aen count */
4741
4742 uint8_t fc4_type_priority;
4743
4744 atomic_t zio_threshold;
4745 uint16_t last_zio_threshold;
4746
4747 #define DEFAULT_ZIO_THRESHOLD 5
4748
4749 struct qla_hw_data_stat stat;
4750 pci_error_state_t pci_error_state;
4751 struct dma_pool *purex_dma_pool;
4752 struct btree_head32 host_map;
4753
4754 #define EDIF_NUM_SA_INDEX 512
4755 #define EDIF_TX_SA_INDEX_BASE EDIF_NUM_SA_INDEX
4756 void *edif_rx_sa_id_map;
4757 void *edif_tx_sa_id_map;
4758 spinlock_t sadb_fp_lock;
4759
4760 struct list_head sadb_tx_index_list;
4761 struct list_head sadb_rx_index_list;
4762 spinlock_t sadb_lock; /* protects list */
4763 struct els_reject elsrej;
4764 u8 edif_post_stop_cnt_down;
4765 };
4766
4767 #define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES))
4768
4769 struct active_regions {
4770 uint8_t global;
4771 struct {
4772 uint8_t board_config;
4773 uint8_t vpd_nvram;
4774 uint8_t npiv_config_0_1;
4775 uint8_t npiv_config_2_3;
4776 uint8_t nvme_params;
4777 } aux;
4778 };
4779
4780 #define FW_ABILITY_MAX_SPEED_MASK 0xFUL
4781 #define FW_ABILITY_MAX_SPEED_16G 0x0
4782 #define FW_ABILITY_MAX_SPEED_32G 0x1
4783 #define FW_ABILITY_MAX_SPEED(ha) \
4784 (ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
4785
4786 #define QLA_GET_DATA_RATE 0
4787 #define QLA_SET_DATA_RATE_NOLR 1
4788 #define QLA_SET_DATA_RATE_LR 2 /* Set speed and initiate LR */
4789
4790 #define QLA_DEFAULT_PAYLOAD_SIZE 64
4791 /*
4792 * This item might be allocated with a size > sizeof(struct purex_item).
4793 * The "size" variable gives the size of the payload (which
4794 * is variable) starting at "iocb".
4795 */
4796 struct purex_item {
4797 struct list_head list;
4798 struct scsi_qla_host *vha;
4799 void (*process_item)(struct scsi_qla_host *vha,
4800 struct purex_item *pkt);
4801 atomic_t in_use;
4802 uint16_t size;
4803 struct {
4804 uint8_t iocb[64];
4805 } iocb;
4806 };
4807
4808 #include "qla_edif.h"
4809
4810 #define SCM_FLAG_RDF_REJECT 0x00
4811 #define SCM_FLAG_RDF_COMPLETED 0x01
4812
4813 #define QLA_CON_PRIMITIVE_RECEIVED 0x1
4814 #define QLA_CONGESTION_ARB_WARNING 0x1
4815 #define QLA_CONGESTION_ARB_ALARM 0X2
4816
4817 /*
4818 * Qlogic scsi host structure
4819 */
4820 typedef struct scsi_qla_host {
4821 struct list_head list;
4822 struct list_head vp_fcports; /* list of fcports */
4823 struct list_head work_list;
4824 spinlock_t work_lock;
4825 struct work_struct iocb_work;
4826
4827 /* Commonly used flags and state information. */
4828 struct Scsi_Host *host;
4829 unsigned long host_no;
4830 uint8_t host_str[16];
4831
4832 volatile struct {
4833 uint32_t init_done :1;
4834 uint32_t online :1;
4835 uint32_t reset_active :1;
4836
4837 uint32_t management_server_logged_in :1;
4838 uint32_t process_response_queue :1;
4839 uint32_t difdix_supported:1;
4840 uint32_t delete_progress:1;
4841
4842 uint32_t fw_tgt_reported:1;
4843 uint32_t bbcr_enable:1;
4844 uint32_t qpairs_available:1;
4845 uint32_t qpairs_req_created:1;
4846 uint32_t qpairs_rsp_created:1;
4847 uint32_t nvme_enabled:1;
4848 uint32_t nvme_first_burst:1;
4849 uint32_t nvme2_enabled:1;
4850 } flags;
4851
4852 atomic_t loop_state;
4853 #define LOOP_TIMEOUT 1
4854 #define LOOP_DOWN 2
4855 #define LOOP_UP 3
4856 #define LOOP_UPDATE 4
4857 #define LOOP_READY 5
4858 #define LOOP_DEAD 6
4859
4860 unsigned long relogin_jif;
4861 unsigned long dpc_flags;
4862 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
4863 #define RESET_ACTIVE 1
4864 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
4865 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
4866 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
4867 #define LOOP_RESYNC_ACTIVE 5
4868 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
4869 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
4870 #define RELOGIN_NEEDED 8
4871 #define REGISTER_FC4_NEEDED 9 /* SNS FC4 registration required. */
4872 #define ISP_ABORT_RETRY 10 /* ISP aborted. */
4873 #define BEACON_BLINK_NEEDED 11
4874 #define REGISTER_FDMI_NEEDED 12
4875 #define FCPORT_UPDATE_NEEDED 13
4876 #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */
4877 #define UNLOADING 15
4878 #define NPIV_CONFIG_NEEDED 16
4879 #define ISP_UNRECOVERABLE 17
4880 #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */
4881 #define MPI_RESET_NEEDED 19 /* Initiate MPI FW reset */
4882 #define ISP_QUIESCE_NEEDED 20 /* Driver need some quiescence */
4883 #define N2N_LINK_RESET 21
4884 #define PORT_UPDATE_NEEDED 22
4885 #define FX00_RESET_RECOVERY 23
4886 #define FX00_TARGET_SCAN 24
4887 #define FX00_CRITEMP_RECOVERY 25
4888 #define FX00_HOST_INFO_RESEND 26
4889 #define QPAIR_ONLINE_CHECK_NEEDED 27
4890 #define DO_EEH_RECOVERY 28
4891 #define DETECT_SFP_CHANGE 29
4892 #define N2N_LOGIN_NEEDED 30
4893 #define IOCB_WORK_ACTIVE 31
4894 #define SET_ZIO_THRESHOLD_NEEDED 32
4895 #define ISP_ABORT_TO_ROM 33
4896 #define VPORT_DELETE 34
4897
4898 #define PROCESS_PUREX_IOCB 63
4899
4900 unsigned long pci_flags;
4901 #define PFLG_DISCONNECTED 0 /* PCI device removed */
4902 #define PFLG_DRIVER_REMOVING 1 /* PCI driver .remove */
4903 #define PFLG_DRIVER_PROBING 2 /* PCI driver .probe */
4904
4905 uint32_t device_flags;
4906 #define SWITCH_FOUND BIT_0
4907 #define DFLG_NO_CABLE BIT_1
4908 #define DFLG_DEV_FAILED BIT_5
4909
4910 /* ISP configuration data. */
4911 uint16_t loop_id; /* Host adapter loop id */
4912 uint16_t self_login_loop_id; /* host adapter loop id
4913 * get it on self login
4914 */
4915 fc_port_t bidir_fcport; /* fcport used for bidir cmnds
4916 * no need of allocating it for
4917 * each command
4918 */
4919
4920 port_id_t d_id; /* Host adapter port id */
4921 uint8_t marker_needed;
4922 uint16_t mgmt_svr_loop_id;
4923
4924
4925
4926 /* Timeout timers. */
4927 uint8_t loop_down_abort_time; /* port down timer */
4928 atomic_t loop_down_timer; /* loop down timer */
4929 uint8_t link_down_timeout; /* link down timeout */
4930
4931 uint32_t timer_active;
4932 struct timer_list timer;
4933
4934 uint8_t node_name[WWN_SIZE];
4935 uint8_t port_name[WWN_SIZE];
4936 uint8_t fabric_node_name[WWN_SIZE];
4937 uint8_t fabric_port_name[WWN_SIZE];
4938
4939 struct nvme_fc_local_port *nvme_local_port;
4940 struct completion nvme_del_done;
4941
4942 uint16_t fcoe_vlan_id;
4943 uint16_t fcoe_fcf_idx;
4944 uint8_t fcoe_vn_port_mac[6];
4945
4946 /* list of commands waiting on workqueue */
4947 struct list_head qla_cmd_list;
4948 struct list_head unknown_atio_list;
4949 spinlock_t cmd_list_lock;
4950 struct delayed_work unknown_atio_work;
4951
4952 /* Counter to detect races between ELS and RSCN events */
4953 atomic_t generation_tick;
4954 /* Time when global fcport update has been scheduled */
4955 int total_fcport_update_gen;
4956 /* List of pending LOGOs, protected by tgt_mutex */
4957 struct list_head logo_list;
4958 /* List of pending PLOGI acks, protected by hw lock */
4959 struct list_head plogi_ack_list;
4960
4961 struct list_head qp_list;
4962
4963 uint32_t vp_abort_cnt;
4964
4965 struct fc_vport *fc_vport; /* holds fc_vport * for each vport */
4966 uint16_t vp_idx; /* vport ID */
4967 struct qla_qpair *qpair; /* base qpair */
4968
4969 unsigned long vp_flags;
4970 #define VP_IDX_ACQUIRED 0 /* bit no 0 */
4971 #define VP_CREATE_NEEDED 1
4972 #define VP_BIND_NEEDED 2
4973 #define VP_DELETE_NEEDED 3
4974 #define VP_SCR_NEEDED 4 /* State Change Request registration */
4975 #define VP_CONFIG_OK 5 /* Flag to cfg VP, if FW is ready */
4976 atomic_t vp_state;
4977 #define VP_OFFLINE 0
4978 #define VP_ACTIVE 1
4979 #define VP_FAILED 2
4980 // #define VP_DISABLE 3
4981 uint16_t vp_err_state;
4982 uint16_t vp_prev_err_state;
4983 #define VP_ERR_UNKWN 0
4984 #define VP_ERR_PORTDWN 1
4985 #define VP_ERR_FAB_UNSUPPORTED 2
4986 #define VP_ERR_FAB_NORESOURCES 3
4987 #define VP_ERR_FAB_LOGOUT 4
4988 #define VP_ERR_ADAP_NORESOURCES 5
4989 struct qla_hw_data *hw;
4990 struct scsi_qlt_host vha_tgt;
4991 struct req_que *req;
4992 int fw_heartbeat_counter;
4993 int seconds_since_last_heartbeat;
4994 struct fc_host_statistics fc_host_stat;
4995 struct qla_statistics qla_stats;
4996 struct bidi_statistics bidi_stats;
4997 atomic_t vref_count;
4998 struct qla8044_reset_template reset_tmplt;
4999 uint16_t bbcr;
5000
5001 uint16_t u_ql2xexchoffld;
5002 uint16_t u_ql2xiniexchg;
5003 uint16_t qlini_mode;
5004 uint16_t ql2xexchoffld;
5005 uint16_t ql2xiniexchg;
5006
5007 struct dentry *dfs_rport_root;
5008
5009 struct purex_list {
5010 struct list_head head;
5011 spinlock_t lock;
5012 } purex_list;
5013 struct purex_item default_item;
5014
5015 struct name_list_extended gnl;
5016 /* Count of active session/fcport */
5017 int fcport_count;
5018 wait_queue_head_t fcport_waitQ;
5019 wait_queue_head_t vref_waitq;
5020 uint8_t min_supported_speed;
5021 uint8_t n2n_node_name[WWN_SIZE];
5022 uint8_t n2n_port_name[WWN_SIZE];
5023 uint16_t n2n_id;
5024 __le16 dport_data[4];
5025 struct list_head gpnid_list;
5026 struct fab_scan scan;
5027 uint8_t scm_fabric_connection_flags;
5028
5029 unsigned int irq_offset;
5030
5031 u64 hw_err_cnt;
5032 u64 interface_err_cnt;
5033 u64 cmd_timeout_cnt;
5034 u64 reset_cmd_err_cnt;
5035 u64 link_down_time;
5036 u64 short_link_down_cnt;
5037 struct edif_dbell e_dbell;
5038 struct pur_core pur_cinfo;
5039
5040 #define DPORT_DIAG_IN_PROGRESS BIT_0
5041 #define DPORT_DIAG_CHIP_RESET_IN_PROGRESS BIT_1
5042 uint16_t dport_status;
5043 } scsi_qla_host_t;
5044
5045 struct qla27xx_image_status {
5046 uint8_t image_status_mask;
5047 __le16 generation;
5048 uint8_t ver_major;
5049 uint8_t ver_minor;
5050 uint8_t bitmap; /* 28xx only */
5051 uint8_t reserved[2];
5052 __le32 checksum;
5053 __le32 signature;
5054 } __packed;
5055
5056 /* 28xx aux image status bimap values */
5057 #define QLA28XX_AUX_IMG_BOARD_CONFIG BIT_0
5058 #define QLA28XX_AUX_IMG_VPD_NVRAM BIT_1
5059 #define QLA28XX_AUX_IMG_NPIV_CONFIG_0_1 BIT_2
5060 #define QLA28XX_AUX_IMG_NPIV_CONFIG_2_3 BIT_3
5061 #define QLA28XX_AUX_IMG_NVME_PARAMS BIT_4
5062
5063 #define SET_VP_IDX 1
5064 #define SET_AL_PA 2
5065 #define RESET_VP_IDX 3
5066 #define RESET_AL_PA 4
5067 struct qla_tgt_vp_map {
5068 uint8_t idx;
5069 scsi_qla_host_t *vha;
5070 };
5071
5072 struct qla2_sgx {
5073 dma_addr_t dma_addr; /* OUT */
5074 uint32_t dma_len; /* OUT */
5075
5076 uint32_t tot_bytes; /* IN */
5077 struct scatterlist *cur_sg; /* IN */
5078
5079 /* for book keeping, bzero on initial invocation */
5080 uint32_t bytes_consumed;
5081 uint32_t num_bytes;
5082 uint32_t tot_partial;
5083
5084 /* for debugging */
5085 uint32_t num_sg;
5086 srb_t *sp;
5087 };
5088
5089 #define QLA_FW_STARTED(_ha) { \
5090 int i; \
5091 _ha->flags.fw_started = 1; \
5092 _ha->base_qpair->fw_started = 1; \
5093 for (i = 0; i < _ha->max_qpairs; i++) { \
5094 if (_ha->queue_pair_map[i]) \
5095 _ha->queue_pair_map[i]->fw_started = 1; \
5096 } \
5097 }
5098
5099 #define QLA_FW_STOPPED(_ha) { \
5100 int i; \
5101 _ha->flags.fw_started = 0; \
5102 _ha->base_qpair->fw_started = 0; \
5103 for (i = 0; i < _ha->max_qpairs; i++) { \
5104 if (_ha->queue_pair_map[i]) \
5105 _ha->queue_pair_map[i]->fw_started = 0; \
5106 } \
5107 }
5108
5109
5110 #define SFUB_CHECKSUM_SIZE 4
5111
5112 struct secure_flash_update_block {
5113 uint32_t block_info;
5114 uint32_t signature_lo;
5115 uint32_t signature_hi;
5116 uint32_t signature_upper[0x3e];
5117 };
5118
5119 struct secure_flash_update_block_pk {
5120 uint32_t block_info;
5121 uint32_t signature_lo;
5122 uint32_t signature_hi;
5123 uint32_t signature_upper[0x3e];
5124 uint32_t public_key[0x41];
5125 };
5126
5127 /*
5128 * Macros to help code, maintain, etc.
5129 */
5130 #define LOOP_TRANSITION(ha) \
5131 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
5132 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
5133 atomic_read(&ha->loop_state) == LOOP_DOWN)
5134
5135 #define STATE_TRANSITION(ha) \
5136 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
5137 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
5138
5139 #define QLA_VHA_MARK_BUSY(__vha, __bail) do { \
5140 atomic_inc(&__vha->vref_count); \
5141 mb(); \
5142 if (__vha->flags.delete_progress) { \
5143 atomic_dec(&__vha->vref_count); \
5144 wake_up(&__vha->vref_waitq); \
5145 __bail = 1; \
5146 } else { \
5147 __bail = 0; \
5148 } \
5149 } while (0)
5150
5151 #define QLA_VHA_MARK_NOT_BUSY(__vha) do { \
5152 atomic_dec(&__vha->vref_count); \
5153 wake_up(&__vha->vref_waitq); \
5154 } while (0) \
5155
5156 #define QLA_QPAIR_MARK_BUSY(__qpair, __bail) do { \
5157 atomic_inc(&__qpair->ref_count); \
5158 mb(); \
5159 if (__qpair->delete_in_progress) { \
5160 atomic_dec(&__qpair->ref_count); \
5161 __bail = 1; \
5162 } else { \
5163 __bail = 0; \
5164 } \
5165 } while (0)
5166
5167 #define QLA_QPAIR_MARK_NOT_BUSY(__qpair) \
5168 atomic_dec(&__qpair->ref_count)
5169
5170 #define QLA_ENA_CONF(_ha) {\
5171 int i;\
5172 _ha->base_qpair->enable_explicit_conf = 1; \
5173 for (i = 0; i < _ha->max_qpairs; i++) { \
5174 if (_ha->queue_pair_map[i]) \
5175 _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
5176 } \
5177 }
5178
5179 #define QLA_DIS_CONF(_ha) {\
5180 int i;\
5181 _ha->base_qpair->enable_explicit_conf = 0; \
5182 for (i = 0; i < _ha->max_qpairs; i++) { \
5183 if (_ha->queue_pair_map[i]) \
5184 _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
5185 } \
5186 }
5187
5188 /*
5189 * qla2x00 local function return status codes
5190 */
5191 #define MBS_MASK 0x3fff
5192
5193 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
5194 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
5195 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
5196 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
5197 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
5198 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
5199 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
5200 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
5201 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
5202 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
5203
5204 #define QLA_FUNCTION_TIMEOUT 0x100
5205 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
5206 #define QLA_FUNCTION_FAILED 0x102
5207 #define QLA_MEMORY_ALLOC_FAILED 0x103
5208 #define QLA_LOCK_TIMEOUT 0x104
5209 #define QLA_ABORTED 0x105
5210 #define QLA_SUSPENDED 0x106
5211 #define QLA_BUSY 0x107
5212 #define QLA_ALREADY_REGISTERED 0x109
5213 #define QLA_OS_TIMER_EXPIRED 0x10a
5214 #define QLA_ERR_NO_QPAIR 0x10b
5215 #define QLA_ERR_NOT_FOUND 0x10c
5216 #define QLA_ERR_FROM_FW 0x10d
5217
5218 #define NVRAM_DELAY() udelay(10)
5219
5220 /*
5221 * Flash support definitions
5222 */
5223 #define OPTROM_SIZE_2300 0x20000
5224 #define OPTROM_SIZE_2322 0x100000
5225 #define OPTROM_SIZE_24XX 0x100000
5226 #define OPTROM_SIZE_25XX 0x200000
5227 #define OPTROM_SIZE_81XX 0x400000
5228 #define OPTROM_SIZE_82XX 0x800000
5229 #define OPTROM_SIZE_83XX 0x1000000
5230 #define OPTROM_SIZE_28XX 0x2000000
5231
5232 #define OPTROM_BURST_SIZE 0x1000
5233 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
5234
5235 #define QLA_DSDS_PER_IOCB 37
5236
5237 #define QLA_SG_ALL 1024
5238
5239 enum nexus_wait_type {
5240 WAIT_HOST = 0,
5241 WAIT_TARGET,
5242 WAIT_LUN,
5243 };
5244
5245 #define INVALID_EDIF_SA_INDEX 0xffff
5246 #define RX_DELETE_NO_EDIF_SA_INDEX 0xfffe
5247
5248 #define QLA_SKIP_HANDLE QLA_TGT_SKIP_HANDLE
5249
5250 /* edif hash element */
5251 struct edif_list_entry {
5252 uint16_t handle; /* nport_handle */
5253 uint32_t update_sa_index;
5254 uint32_t delete_sa_index;
5255 uint32_t count; /* counter for filtering sa_index */
5256 #define EDIF_ENTRY_FLAGS_CLEANUP 0x01 /* this index is being cleaned up */
5257 uint32_t flags; /* used by sadb cleanup code */
5258 fc_port_t *fcport; /* needed by rx delay timer function */
5259 struct timer_list timer; /* rx delay timer */
5260 struct list_head next;
5261 };
5262
5263 #define EDIF_TX_INDX_BASE 512
5264 #define EDIF_RX_INDX_BASE 0
5265 #define EDIF_RX_DELETE_FILTER_COUNT 3 /* delay queuing rx delete until this many */
5266
5267 /* entry in the sa_index free pool */
5268
5269 struct sa_index_pair {
5270 uint16_t sa_index;
5271 uint32_t spi;
5272 };
5273
5274 /* edif sa_index data structure */
5275 struct edif_sa_index_entry {
5276 struct sa_index_pair sa_pair[2];
5277 fc_port_t *fcport;
5278 uint16_t handle;
5279 struct list_head next;
5280 };
5281
5282 /* Refer to SNIA SFF 8247 */
5283 struct sff_8247_a0 {
5284 u8 txid; /* transceiver id */
5285 u8 ext_txid;
5286 u8 connector;
5287 /* compliance code */
5288 u8 eth_infi_cc3; /* ethernet, inifiband */
5289 u8 sonet_cc4[2];
5290 u8 eth_cc6;
5291 /* link length */
5292 #define FC_LL_VL BIT_7 /* very long */
5293 #define FC_LL_S BIT_6 /* Short */
5294 #define FC_LL_I BIT_5 /* Intermidiate*/
5295 #define FC_LL_L BIT_4 /* Long */
5296 #define FC_LL_M BIT_3 /* Medium */
5297 #define FC_LL_SA BIT_2 /* ShortWave laser */
5298 #define FC_LL_LC BIT_1 /* LongWave laser */
5299 #define FC_LL_EL BIT_0 /* Electrical inter enclosure */
5300 u8 fc_ll_cc7;
5301 /* FC technology */
5302 #define FC_TEC_EL BIT_7 /* Electrical inter enclosure */
5303 #define FC_TEC_SN BIT_6 /* short wave w/o OFC */
5304 #define FC_TEC_SL BIT_5 /* short wave with OFC */
5305 #define FC_TEC_LL BIT_4 /* Longwave Laser */
5306 #define FC_TEC_ACT BIT_3 /* Active cable */
5307 #define FC_TEC_PAS BIT_2 /* Passive cable */
5308 u8 fc_tec_cc8;
5309 /* Transmission Media */
5310 #define FC_MED_TW BIT_7 /* Twin Ax */
5311 #define FC_MED_TP BIT_6 /* Twited Pair */
5312 #define FC_MED_MI BIT_5 /* Min Coax */
5313 #define FC_MED_TV BIT_4 /* Video Coax */
5314 #define FC_MED_M6 BIT_3 /* Multimode, 62.5um */
5315 #define FC_MED_M5 BIT_2 /* Multimode, 50um */
5316 #define FC_MED_SM BIT_0 /* Single Mode */
5317 u8 fc_med_cc9;
5318 /* speed FC_SP_12: 12*100M = 1200 MB/s */
5319 #define FC_SP_12 BIT_7
5320 #define FC_SP_8 BIT_6
5321 #define FC_SP_16 BIT_5
5322 #define FC_SP_4 BIT_4
5323 #define FC_SP_32 BIT_3
5324 #define FC_SP_2 BIT_2
5325 #define FC_SP_1 BIT_0
5326 u8 fc_sp_cc10;
5327 u8 encode;
5328 u8 bitrate;
5329 u8 rate_id;
5330 u8 length_km; /* offset 14/eh */
5331 u8 length_100m;
5332 u8 length_50um_10m;
5333 u8 length_62um_10m;
5334 u8 length_om4_10m;
5335 u8 length_om3_10m;
5336 #define SFF_VEN_NAME_LEN 16
5337 u8 vendor_name[SFF_VEN_NAME_LEN]; /* offset 20/14h */
5338 u8 tx_compat;
5339 u8 vendor_oui[3];
5340 #define SFF_PART_NAME_LEN 16
5341 u8 vendor_pn[SFF_PART_NAME_LEN]; /* part number */
5342 u8 vendor_rev[4];
5343 u8 wavelength[2];
5344 u8 resv;
5345 u8 cc_base;
5346 u8 options[2]; /* offset 64 */
5347 u8 br_max;
5348 u8 br_min;
5349 u8 vendor_sn[16];
5350 u8 date_code[8];
5351 u8 diag;
5352 u8 enh_options;
5353 u8 sff_revision;
5354 u8 cc_ext;
5355 u8 vendor_specific[32];
5356 u8 resv2[128];
5357 };
5358
5359 /* BPM -- Buffer Plus Management support. */
5360 #define IS_BPM_CAPABLE(ha) \
5361 (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || \
5362 IS_QLA27XX(ha) || IS_QLA28XX(ha))
5363 #define IS_BPM_RANGE_CAPABLE(ha) \
5364 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
5365 #define IS_BPM_ENABLED(vha) \
5366 (ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw))
5367
5368 #define FLASH_SEMAPHORE_REGISTER_ADDR 0x00101016
5369
5370 #define USER_CTRL_IRQ(_ha) (ql2xuctrlirq && QLA_TGT_MODE_ENABLED() && \
5371 (IS_QLA27XX(_ha) || IS_QLA28XX(_ha) || IS_QLA83XX(_ha)))
5372
5373 #define SAVE_TOPO(_ha) { \
5374 if (_ha->current_topology) \
5375 _ha->prev_topology = _ha->current_topology; \
5376 }
5377
5378 #define N2N_TOPO(ha) \
5379 ((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
5380 ha->current_topology == ISP_CFG_N || \
5381 !ha->current_topology)
5382
5383 #define QLA_N2N_WAIT_TIME 5 /* 2 * ra_tov(n2n) + 1 */
5384
5385 #define NVME_TYPE(fcport) \
5386 (fcport->fc4_type & FS_FC4TYPE_NVME) \
5387
5388 #define FCP_TYPE(fcport) \
5389 (fcport->fc4_type & FS_FC4TYPE_FCP) \
5390
5391 #define NVME_ONLY_TARGET(fcport) \
5392 (NVME_TYPE(fcport) && !FCP_TYPE(fcport)) \
5393
5394 #define NVME_FCP_TARGET(fcport) \
5395 (FCP_TYPE(fcport) && NVME_TYPE(fcport)) \
5396
5397 #define NVME_PRIORITY(ha, fcport) \
5398 (NVME_FCP_TARGET(fcport) && \
5399 (ha->fc4_type_priority == FC4_PRIORITY_NVME))
5400
5401 #define NVME_TARGET(ha, fcport) \
5402 (fcport->do_prli_nvme || \
5403 NVME_ONLY_TARGET(fcport)) \
5404
5405 #define PRLI_PHASE(_cls) \
5406 ((_cls == DSC_LS_PRLI_PEND) || (_cls == DSC_LS_PRLI_COMP))
5407
5408 enum ql_vnd_host_stat_action {
5409 QLA_STOP = 0,
5410 QLA_START,
5411 QLA_CLEAR,
5412 };
5413
5414 struct ql_vnd_mng_host_stats_param {
5415 u32 stat_type;
5416 enum ql_vnd_host_stat_action action;
5417 } __packed;
5418
5419 struct ql_vnd_mng_host_stats_resp {
5420 u32 status;
5421 } __packed;
5422
5423 struct ql_vnd_stats_param {
5424 u32 stat_type;
5425 } __packed;
5426
5427 struct ql_vnd_tgt_stats_param {
5428 s32 tgt_id;
5429 u32 stat_type;
5430 } __packed;
5431
5432 enum ql_vnd_host_port_action {
5433 QLA_ENABLE = 0,
5434 QLA_DISABLE,
5435 };
5436
5437 struct ql_vnd_mng_host_port_param {
5438 enum ql_vnd_host_port_action action;
5439 } __packed;
5440
5441 struct ql_vnd_mng_host_port_resp {
5442 u32 status;
5443 } __packed;
5444
5445 struct ql_vnd_stat_entry {
5446 u32 stat_type; /* Failure type */
5447 u32 tgt_num; /* Target Num */
5448 u64 cnt; /* Counter value */
5449 } __packed;
5450
5451 struct ql_vnd_stats {
5452 u64 entry_count; /* Num of entries */
5453 u64 rservd;
5454 struct ql_vnd_stat_entry entry[]; /* Place holder of entries */
5455 } __packed;
5456
5457 struct ql_vnd_host_stats_resp {
5458 u32 status;
5459 struct ql_vnd_stats stats;
5460 } __packed;
5461
5462 struct ql_vnd_tgt_stats_resp {
5463 u32 status;
5464 struct ql_vnd_stats stats;
5465 } __packed;
5466
5467 #include "qla_target.h"
5468 #include "qla_gbl.h"
5469 #include "qla_dbg.h"
5470 #include "qla_inline.h"
5471
5472 #define IS_SESSION_DELETED(_fcport) (_fcport->disc_state == DSC_DELETE_PEND || \
5473 _fcport->disc_state == DSC_DELETED)
5474
5475 #define DBG_FCPORT_PRFMT(_fp, _fmt, _args...) \
5476 "%s: %8phC: " _fmt " (state=%d disc_state=%d scan_state=%d loopid=0x%x deleted=%d flags=0x%x)\n", \
5477 __func__, _fp->port_name, ##_args, atomic_read(&_fp->state), \
5478 _fp->disc_state, _fp->scan_state, _fp->loop_id, _fp->deleted, \
5479 _fp->flags
5480
5481 #endif
5482