1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h 4 * 5 * Register definitions for IXP4xx chipset. This file contains 6 * register location and bit definitions only. Platform specific 7 * definitions and helper function declarations are in platform.h 8 * and machine-name.h. 9 * 10 * Copyright (C) 2002 Intel Corporation. 11 * Copyright (C) 2003-2004 MontaVista Software, Inc. 12 */ 13 14 #ifndef _ASM_ARM_IXP4XX_H_ 15 #define _ASM_ARM_IXP4XX_H_ 16 17 /* 18 * IXP4xx Linux Memory Map: 19 * 20 * Phy Size Virt Description 21 * ========================================================================= 22 * 23 * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM 24 * 25 * 0x48000000 0x04000000 ioremap'd PCI Memory Space 26 * 27 * 0x50000000 0x10000000 ioremap'd EXP BUS 28 * 29 * 0xC8000000 0x00013000 0xFEF00000 On-Chip Peripherals 30 * 31 * 0xC0000000 0x00001000 0xFEF13000 PCI CFG 32 * 33 * 0xC4000000 0x00001000 0xFEF14000 EXP CFG 34 * 35 * 0x60000000 0x00004000 0xFEF15000 QMgr 36 */ 37 38 /* 39 * Queue Manager 40 */ 41 #define IXP4XX_QMGR_BASE_PHYS 0x60000000 42 43 /* 44 * Peripheral space, including debug UART. Must be section-aligned so that 45 * it can be used with the low-level debug code. 46 */ 47 #define IXP4XX_PERIPHERAL_BASE_PHYS 0xC8000000 48 #define IXP4XX_PERIPHERAL_BASE_VIRT IOMEM(0xFEF00000) 49 #define IXP4XX_PERIPHERAL_REGION_SIZE 0x00013000 50 51 /* 52 * PCI Config registers 53 */ 54 #define IXP4XX_PCI_CFG_BASE_PHYS 0xC0000000 55 #define IXP4XX_PCI_CFG_BASE_VIRT IOMEM(0xFEF13000) 56 #define IXP4XX_PCI_CFG_REGION_SIZE 0x00001000 57 58 /* 59 * Expansion BUS Configuration registers 60 */ 61 #define IXP4XX_EXP_CFG_BASE_PHYS 0xC4000000 62 #define IXP4XX_EXP_CFG_BASE_VIRT 0xFEF14000 63 #define IXP4XX_EXP_CFG_REGION_SIZE 0x00001000 64 65 #define IXP4XX_EXP_CS0_OFFSET 0x00 66 #define IXP4XX_EXP_CS1_OFFSET 0x04 67 #define IXP4XX_EXP_CS2_OFFSET 0x08 68 #define IXP4XX_EXP_CS3_OFFSET 0x0C 69 #define IXP4XX_EXP_CS4_OFFSET 0x10 70 #define IXP4XX_EXP_CS5_OFFSET 0x14 71 #define IXP4XX_EXP_CS6_OFFSET 0x18 72 #define IXP4XX_EXP_CS7_OFFSET 0x1C 73 #define IXP4XX_EXP_CFG0_OFFSET 0x20 74 #define IXP4XX_EXP_CFG1_OFFSET 0x24 75 #define IXP4XX_EXP_CFG2_OFFSET 0x28 76 #define IXP4XX_EXP_CFG3_OFFSET 0x2C 77 78 /* 79 * Expansion Bus Controller registers. 80 */ 81 #define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x))) 82 83 #define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET) 84 #define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET) 85 #define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) 86 #define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET) 87 #define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET) 88 #define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET) 89 #define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET) 90 #define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET) 91 92 #define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) 93 #define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) 94 #define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) 95 #define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET) 96 97 98 /* 99 * Peripheral Space Register Region Base Addresses 100 */ 101 #define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000) 102 #define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000) 103 #define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000) 104 #define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000) 105 #define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000) 106 #define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000) 107 #define IXP4XX_NPEA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x6000) 108 #define IXP4XX_NPEB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x7000) 109 #define IXP4XX_NPEC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x8000) 110 #define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000) 111 #define IXP4XX_EthC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000) 112 #define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000) 113 /* ixp46X only */ 114 #define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xC000) 115 #define IXP4XX_EthB1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xD000) 116 #define IXP4XX_EthB2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xE000) 117 #define IXP4XX_EthB3_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xF000) 118 #define IXP4XX_TIMESYNC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x10000) 119 #define IXP4XX_I2C_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x11000) 120 #define IXP4XX_SSP_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x12000) 121 122 123 #define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000) 124 #define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000) 125 #define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000) 126 #define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000) 127 #define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000) 128 #define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000) 129 #define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000) 130 #define IXP4XX_EthC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000) 131 #define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000) 132 /* ixp46X only */ 133 #define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xC000) 134 #define IXP4XX_EthB1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xD000) 135 #define IXP4XX_EthB2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xE000) 136 #define IXP4XX_EthB3_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xF000) 137 #define IXP4XX_TIMESYNC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x10000) 138 #define IXP4XX_I2C_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x11000) 139 #define IXP4XX_SSP_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x12000) 140 141 /* 142 * Constants to make it easy to access Timer Control/Status registers 143 */ 144 #define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */ 145 #define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ 146 #define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ 147 #define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ 148 #define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ 149 #define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */ 150 #define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */ 151 #define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */ 152 #define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */ 153 154 /* 155 * Operating System Timer Register Definitions. 156 */ 157 158 #define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x))) 159 160 #define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET) 161 #define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET) 162 #define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET) 163 #define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET) 164 #define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET) 165 #define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET) 166 #define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET) 167 #define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET) 168 #define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET) 169 170 /* 171 * Timer register values and bit definitions 172 */ 173 #define IXP4XX_OST_ENABLE 0x00000001 174 #define IXP4XX_OST_ONE_SHOT 0x00000002 175 /* Low order bits of reload value ignored */ 176 #define IXP4XX_OST_RELOAD_MASK 0x00000003 177 #define IXP4XX_OST_DISABLED 0x00000000 178 #define IXP4XX_OSST_TIMER_1_PEND 0x00000001 179 #define IXP4XX_OSST_TIMER_2_PEND 0x00000002 180 #define IXP4XX_OSST_TIMER_TS_PEND 0x00000004 181 #define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008 182 #define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010 183 184 #define IXP4XX_WDT_KEY 0x0000482E 185 186 #define IXP4XX_WDT_RESET_ENABLE 0x00000001 187 #define IXP4XX_WDT_IRQ_ENABLE 0x00000002 188 #define IXP4XX_WDT_COUNT_ENABLE 0x00000004 189 190 191 /* 192 * Constants to make it easy to access PCI Control/Status registers 193 */ 194 #define PCI_NP_AD_OFFSET 0x00 195 #define PCI_NP_CBE_OFFSET 0x04 196 #define PCI_NP_WDATA_OFFSET 0x08 197 #define PCI_NP_RDATA_OFFSET 0x0c 198 #define PCI_CRP_AD_CBE_OFFSET 0x10 199 #define PCI_CRP_WDATA_OFFSET 0x14 200 #define PCI_CRP_RDATA_OFFSET 0x18 201 #define PCI_CSR_OFFSET 0x1c 202 #define PCI_ISR_OFFSET 0x20 203 #define PCI_INTEN_OFFSET 0x24 204 #define PCI_DMACTRL_OFFSET 0x28 205 #define PCI_AHBMEMBASE_OFFSET 0x2c 206 #define PCI_AHBIOBASE_OFFSET 0x30 207 #define PCI_PCIMEMBASE_OFFSET 0x34 208 #define PCI_AHBDOORBELL_OFFSET 0x38 209 #define PCI_PCIDOORBELL_OFFSET 0x3C 210 #define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 211 #define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 212 #define PCI_ATPDMA0_LENADDR_OFFSET 0x48 213 #define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C 214 #define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 215 #define PCI_ATPDMA1_LENADDR_OFFSET 0x54 216 217 /* 218 * PCI Control/Status Registers 219 */ 220 #define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x))) 221 222 #define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET) 223 #define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET) 224 #define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET) 225 #define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET) 226 #define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) 227 #define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET) 228 #define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET) 229 #define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 230 #define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET) 231 #define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET) 232 #define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET) 233 #define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET) 234 #define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET) 235 #define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET) 236 #define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET) 237 #define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET) 238 #define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) 239 #define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) 240 #define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) 241 #define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) 242 #define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) 243 #define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) 244 245 /* 246 * PCI register values and bit definitions 247 */ 248 249 /* CSR bit definitions */ 250 #define PCI_CSR_HOST 0x00000001 251 #define PCI_CSR_ARBEN 0x00000002 252 #define PCI_CSR_ADS 0x00000004 253 #define PCI_CSR_PDS 0x00000008 254 #define PCI_CSR_ABE 0x00000010 255 #define PCI_CSR_DBT 0x00000020 256 #define PCI_CSR_ASE 0x00000100 257 #define PCI_CSR_IC 0x00008000 258 259 /* ISR (Interrupt status) Register bit definitions */ 260 #define PCI_ISR_PSE 0x00000001 261 #define PCI_ISR_PFE 0x00000002 262 #define PCI_ISR_PPE 0x00000004 263 #define PCI_ISR_AHBE 0x00000008 264 #define PCI_ISR_APDC 0x00000010 265 #define PCI_ISR_PADC 0x00000020 266 #define PCI_ISR_ADB 0x00000040 267 #define PCI_ISR_PDB 0x00000080 268 269 /* INTEN (Interrupt Enable) Register bit definitions */ 270 #define PCI_INTEN_PSE 0x00000001 271 #define PCI_INTEN_PFE 0x00000002 272 #define PCI_INTEN_PPE 0x00000004 273 #define PCI_INTEN_AHBE 0x00000008 274 #define PCI_INTEN_APDC 0x00000010 275 #define PCI_INTEN_PADC 0x00000020 276 #define PCI_INTEN_ADB 0x00000040 277 #define PCI_INTEN_PDB 0x00000080 278 279 /* 280 * Shift value for byte enable on NP cmd/byte enable register 281 */ 282 #define IXP4XX_PCI_NP_CBE_BESL 4 283 284 /* 285 * PCI commands supported by NP access unit 286 */ 287 #define NP_CMD_IOREAD 0x2 288 #define NP_CMD_IOWRITE 0x3 289 #define NP_CMD_CONFIGREAD 0xa 290 #define NP_CMD_CONFIGWRITE 0xb 291 #define NP_CMD_MEMREAD 0x6 292 #define NP_CMD_MEMWRITE 0x7 293 294 /* 295 * Constants for CRP access into local config space 296 */ 297 #define CRP_AD_CBE_BESL 20 298 #define CRP_AD_CBE_WRITE 0x00010000 299 300 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ 301 302 /* "fuse" bits of IXP_EXP_CFG2 */ 303 /* All IXP4xx CPUs */ 304 #define IXP4XX_FEATURE_RCOMP (1 << 0) 305 #define IXP4XX_FEATURE_USB_DEVICE (1 << 1) 306 #define IXP4XX_FEATURE_HASH (1 << 2) 307 #define IXP4XX_FEATURE_AES (1 << 3) 308 #define IXP4XX_FEATURE_DES (1 << 4) 309 #define IXP4XX_FEATURE_HDLC (1 << 5) 310 #define IXP4XX_FEATURE_AAL (1 << 6) 311 #define IXP4XX_FEATURE_HSS (1 << 7) 312 #define IXP4XX_FEATURE_UTOPIA (1 << 8) 313 #define IXP4XX_FEATURE_NPEB_ETH0 (1 << 9) 314 #define IXP4XX_FEATURE_NPEC_ETH (1 << 10) 315 #define IXP4XX_FEATURE_RESET_NPEA (1 << 11) 316 #define IXP4XX_FEATURE_RESET_NPEB (1 << 12) 317 #define IXP4XX_FEATURE_RESET_NPEC (1 << 13) 318 #define IXP4XX_FEATURE_PCI (1 << 14) 319 #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) 320 #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) 321 #define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \ 322 IXP4XX_FEATURE_USB_DEVICE | \ 323 IXP4XX_FEATURE_HASH | \ 324 IXP4XX_FEATURE_AES | \ 325 IXP4XX_FEATURE_DES | \ 326 IXP4XX_FEATURE_HDLC | \ 327 IXP4XX_FEATURE_AAL | \ 328 IXP4XX_FEATURE_HSS | \ 329 IXP4XX_FEATURE_UTOPIA | \ 330 IXP4XX_FEATURE_NPEB_ETH0 | \ 331 IXP4XX_FEATURE_NPEC_ETH | \ 332 IXP4XX_FEATURE_RESET_NPEA | \ 333 IXP4XX_FEATURE_RESET_NPEB | \ 334 IXP4XX_FEATURE_RESET_NPEC | \ 335 IXP4XX_FEATURE_PCI | \ 336 IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \ 337 IXP4XX_FEATURE_XSCALE_MAX_FREQ) 338 339 340 /* IXP43x/46x CPUs */ 341 #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) 342 #define IXP4XX_FEATURE_USB_HOST (1 << 18) 343 #define IXP4XX_FEATURE_NPEA_ETH (1 << 19) 344 #define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \ 345 IXP4XX_FEATURE_ECC_TIMESYNC | \ 346 IXP4XX_FEATURE_USB_HOST | \ 347 IXP4XX_FEATURE_NPEA_ETH) 348 349 /* IXP46x CPU (including IXP455) only */ 350 #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) 351 #define IXP4XX_FEATURE_RSA (1 << 21) 352 #define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \ 353 IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ 354 IXP4XX_FEATURE_RSA) 355 356 #endif 357
