1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _IXGBEVF_DEFINES_H_ 5 #define _IXGBEVF_DEFINES_H_ 6 7 /* Device IDs */ 8 #define IXGBE_DEV_ID_82599_VF 0x10ED 9 #define IXGBE_DEV_ID_X540_VF 0x1515 10 #define IXGBE_DEV_ID_X550_VF 0x1565 11 #define IXGBE_DEV_ID_X550EM_X_VF 0x15A8 12 #define IXGBE_DEV_ID_X550EM_A_VF 0x15C5 13 14 #define IXGBE_DEV_ID_82599_VF_HV 0x152E 15 #define IXGBE_DEV_ID_X540_VF_HV 0x1530 16 #define IXGBE_DEV_ID_X550_VF_HV 0x1564 17 #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9 18 19 #define IXGBE_VF_IRQ_CLEAR_MASK 7 20 #define IXGBE_VF_MAX_TX_QUEUES 8 21 #define IXGBE_VF_MAX_RX_QUEUES 8 22 23 /* DCB define */ 24 #define IXGBE_VF_MAX_TRAFFIC_CLASS 8 25 26 /* Link speed */ 27 typedef u32 ixgbe_link_speed; 28 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020 29 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080 30 #define IXGBE_LINK_SPEED_100_FULL 0x0008 31 32 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 33 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 34 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */ 35 #define IXGBE_LINKS_UP 0x40000000 36 #define IXGBE_LINKS_SPEED_82599 0x30000000 37 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000 38 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000 39 #define IXGBE_LINKS_SPEED_100_82599 0x10000000 40 41 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 42 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 43 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 44 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 45 46 /* Interrupt Vector Allocation Registers */ 47 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 48 49 #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 50 51 /* Receive Config masks */ 52 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 53 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */ 54 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */ 55 #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 56 #define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* Only supported on the X540 */ 57 #define IXGBE_RXDCTL_RLPML_EN 0x00008000 58 59 /* DCA Control */ 60 #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */ 61 62 /* PSRTYPE bit definitions */ 63 #define IXGBE_PSRTYPE_TCPHDR 0x00000010 64 #define IXGBE_PSRTYPE_UDPHDR 0x00000020 65 #define IXGBE_PSRTYPE_IPV4HDR 0x00000100 66 #define IXGBE_PSRTYPE_IPV6HDR 0x00000200 67 #define IXGBE_PSRTYPE_L2HDR 0x00001000 68 69 /* SRRCTL bit definitions */ 70 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 71 #define IXGBE_SRRCTL_RDMTS_SHIFT 22 72 #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 73 #define IXGBE_SRRCTL_DROP_EN 0x10000000 74 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 75 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 76 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 77 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 78 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 79 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 80 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 81 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 82 83 /* Receive Descriptor bit definitions */ 84 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 85 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 86 #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 87 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 88 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 89 #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 90 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 91 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 92 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 93 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 94 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 95 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 96 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 97 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 98 #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 99 #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 100 #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 101 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 102 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 103 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 104 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 105 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 106 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 107 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 108 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 109 #define IXGBE_RXDADV_ERR_MASK 0xFFF00000 /* RDESC.ERRORS mask */ 110 #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 111 #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 112 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 113 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 114 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 115 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 116 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 117 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 118 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 119 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 120 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 121 #define IXGBE_RXD_PRI_SHIFT 13 122 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 123 #define IXGBE_RXD_CFI_SHIFT 12 124 125 #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 126 #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 127 #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 128 #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 129 #define IXGBE_RXDADV_STAT_MASK 0x000FFFFF /* Stat/NEXTP: bit 0-19 */ 130 #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 131 #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 132 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 133 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 134 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 135 #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 136 #define IXGBE_RXDADV_STAT_SECP 0x00020000 /* IPsec/MACsec pkt found */ 137 138 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 139 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 140 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 141 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 142 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 143 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 144 #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 145 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 146 #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 147 #define IXGBE_RXDADV_RSCCNT_SHIFT 17 148 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 149 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 150 #define IXGBE_RXDADV_SPH 0x8000 151 152 /* RSS Hash results */ 153 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 154 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 155 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 156 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 157 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 158 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 159 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 160 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 161 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 162 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 163 164 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 165 IXGBE_RXD_ERR_CE | \ 166 IXGBE_RXD_ERR_LE | \ 167 IXGBE_RXD_ERR_PE | \ 168 IXGBE_RXD_ERR_OSE | \ 169 IXGBE_RXD_ERR_USE) 170 171 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 172 IXGBE_RXDADV_ERR_CE | \ 173 IXGBE_RXDADV_ERR_LE | \ 174 IXGBE_RXDADV_ERR_PE | \ 175 IXGBE_RXDADV_ERR_OSE | \ 176 IXGBE_RXDADV_ERR_USE) 177 178 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 179 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 180 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 181 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 182 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 183 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 184 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor ext (0 = legacy) */ 185 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 186 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 187 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS) 188 189 /* Transmit Descriptor - Advanced */ 190 union ixgbe_adv_tx_desc { 191 struct { 192 __le64 buffer_addr; /* Address of descriptor's data buf */ 193 __le32 cmd_type_len; 194 __le32 olinfo_status; 195 } read; 196 struct { 197 __le64 rsvd; /* Reserved */ 198 __le32 nxtseq_seed; 199 __le32 status; 200 } wb; 201 }; 202 203 /* Receive Descriptor - Advanced */ 204 union ixgbe_adv_rx_desc { 205 struct { 206 __le64 pkt_addr; /* Packet buffer address */ 207 __le64 hdr_addr; /* Header buffer address */ 208 } read; 209 struct { 210 struct { 211 union { 212 __le32 data; 213 struct { 214 __le16 pkt_info; /* RSS, Pkt type */ 215 __le16 hdr_info; /* Splithdr, hdrlen */ 216 } hs_rss; 217 } lo_dword; 218 union { 219 __le32 rss; /* RSS Hash */ 220 struct { 221 __le16 ip_id; /* IP id */ 222 __le16 csum; /* Packet Checksum */ 223 } csum_ip; 224 } hi_dword; 225 } lower; 226 struct { 227 __le32 status_error; /* ext status/error */ 228 __le16 length; /* Packet length */ 229 __le16 vlan; /* VLAN tag */ 230 } upper; 231 } wb; /* writeback */ 232 }; 233 234 /* Context descriptors */ 235 struct ixgbe_adv_tx_context_desc { 236 __le32 vlan_macip_lens; 237 __le32 fceof_saidx; 238 __le32 type_tucmd_mlhl; 239 __le32 mss_l4len_idx; 240 }; 241 242 /* Adv Transmit Descriptor Config Masks */ 243 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 244 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */ 245 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 246 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 247 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 248 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 249 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */ 250 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 251 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 252 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 253 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 254 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 255 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 256 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 257 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 258 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 259 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 /* ESP Encrypt Enable */ 260 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 261 #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 262 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 263 #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 264 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 265 IXGBE_ADVTXD_POPTS_SHIFT) 266 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 267 IXGBE_ADVTXD_POPTS_SHIFT) 268 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 269 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 270 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 271 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 272 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 273 274 /* Interrupt register bitmasks */ 275 276 #define IXGBE_EITR_CNT_WDIS 0x80000000 277 #define IXGBE_MAX_EITR 0x00000FF8 278 #define IXGBE_MIN_EITR 8 279 280 /* Error Codes */ 281 #define IXGBE_ERR_INVALID_MAC_ADDR -1 282 #define IXGBE_ERR_RESET_FAILED -2 283 #define IXGBE_ERR_INVALID_ARGUMENT -3 284 285 /* Transmit Config masks */ 286 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */ 287 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ 288 #define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 289 290 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* Rx Desc enable */ 291 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* Rx Desc header ena */ 292 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* Rx Desc payload ena */ 293 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* Rx rd Desc Relax Order */ 294 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN BIT(13) /* Rx wr data Relax Order */ 295 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN BIT(15) /* Rx wr header RO */ 296 297 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */ 298 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */ 299 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN BIT(11) /* Tx Desc writeback RO bit */ 300 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */ 301 302 #endif /* _IXGBEVF_DEFINES_H_ */ 303
