1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2012-2014, 2018-2020 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_fw_api_rx_h__ 8 #define __iwl_fw_api_rx_h__ 9 10 /* API for pre-9000 hardware */ 11 12 #define IWL_RX_INFO_PHY_CNT 8 13 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1 14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff 15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00 16 #define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000 17 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0 18 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8 19 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16 20 21 enum iwl_mac_context_info { 22 MAC_CONTEXT_INFO_NONE, 23 MAC_CONTEXT_INFO_GSCAN, 24 }; 25 26 /** 27 * struct iwl_rx_phy_info - phy info 28 * (REPLY_RX_PHY_CMD = 0xc0) 29 * @non_cfg_phy_cnt: non configurable DSP phy data byte count 30 * @cfg_phy_cnt: configurable DSP phy data byte count 31 * @stat_id: configurable DSP phy data set ID 32 * @reserved1: reserved 33 * @system_timestamp: GP2 at on air rise 34 * @timestamp: TSF at on air rise 35 * @beacon_time_stamp: beacon at on-air rise 36 * @phy_flags: general phy flags: band, modulation, ... 37 * @channel: channel number 38 * @non_cfg_phy: for various implementations of non_cfg_phy 39 * @rate_n_flags: RATE_MCS_* 40 * @byte_count: frame's byte-count 41 * @frame_time: frame's time on the air, based on byte count and frame rate 42 * calculation 43 * @mac_active_msk: what MACs were active when the frame was received 44 * @mac_context_info: additional info on the context in which the frame was 45 * received as defined in &enum iwl_mac_context_info 46 * 47 * Before each Rx, the device sends this data. It contains PHY information 48 * about the reception of the packet. 49 */ 50 struct iwl_rx_phy_info { 51 u8 non_cfg_phy_cnt; 52 u8 cfg_phy_cnt; 53 u8 stat_id; 54 u8 reserved1; 55 __le32 system_timestamp; 56 __le64 timestamp; 57 __le32 beacon_time_stamp; 58 __le16 phy_flags; 59 __le16 channel; 60 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT]; 61 __le32 rate_n_flags; 62 __le32 byte_count; 63 u8 mac_active_msk; 64 u8 mac_context_info; 65 __le16 frame_time; 66 } __packed; 67 68 /* 69 * TCP offload Rx assist info 70 * 71 * bits 0:3 - reserved 72 * bits 4:7 - MIC CRC length 73 * bits 8:12 - MAC header length 74 * bit 13 - Padding indication 75 * bit 14 - A-AMSDU indication 76 * bit 15 - Offload enabled 77 */ 78 enum iwl_csum_rx_assist_info { 79 CSUM_RXA_RESERVED_MASK = 0x000f, 80 CSUM_RXA_MICSIZE_MASK = 0x00f0, 81 CSUM_RXA_HEADERLEN_MASK = 0x1f00, 82 CSUM_RXA_PADD = BIT(13), 83 CSUM_RXA_AMSDU = BIT(14), 84 CSUM_RXA_ENA = BIT(15) 85 }; 86 87 /** 88 * struct iwl_rx_mpdu_res_start - phy info 89 * @byte_count: byte count of the frame 90 * @assist: see &enum iwl_csum_rx_assist_info 91 */ 92 struct iwl_rx_mpdu_res_start { 93 __le16 byte_count; 94 __le16 assist; 95 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */ 96 97 /** 98 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags 99 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band 100 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK 101 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short 102 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive 103 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received 104 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position 105 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU 106 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame 107 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble 108 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame 109 */ 110 enum iwl_rx_phy_flags { 111 RX_RES_PHY_FLAGS_BAND_24 = BIT(0), 112 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1), 113 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2), 114 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3), 115 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4), 116 RX_RES_PHY_FLAGS_ANTENNA_POS = 4, 117 RX_RES_PHY_FLAGS_AGG = BIT(7), 118 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8), 119 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9), 120 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10), 121 }; 122 123 /** 124 * enum iwl_mvm_rx_status - written by fw for each Rx packet 125 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine 126 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow 127 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found 128 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid 129 * @RX_MPDU_RES_STATUS_KEY_PARAM_OK: key parameters were usable 130 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed 131 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked 132 * in the driver. 133 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine 134 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or 135 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if 136 * %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set. 137 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted 138 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP 139 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM 140 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP 141 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension 142 * algorithm 143 * @RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC: this frame is protected using 144 * CMAC or GMAC 145 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted 146 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm 147 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted 148 * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: extended IV (set with TKIP) 149 * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: key ID comparison done 150 * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame 151 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw 152 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors 153 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask 154 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift 155 */ 156 enum iwl_mvm_rx_status { 157 RX_MPDU_RES_STATUS_CRC_OK = BIT(0), 158 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1), 159 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2), 160 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3), 161 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4), 162 RX_MPDU_RES_STATUS_ICV_OK = BIT(5), 163 RX_MPDU_RES_STATUS_MIC_OK = BIT(6), 164 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 165 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7), 166 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8), 167 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8), 168 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8), 169 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8), 170 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8), 171 RX_MPDU_RES_STATUS_SEC_CMAC_GMAC_ENC = (6 << 8), 172 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8), 173 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8), 174 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11), 175 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13), 176 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14), 177 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15), 178 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16), 179 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17), 180 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24, 181 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT, 182 }; 183 184 /* 9000 series API */ 185 enum iwl_rx_mpdu_mac_flags1 { 186 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03, 187 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0, 188 /* shift should be 4, but the length is measured in 2-byte 189 * words, so shifting only by 3 gives a byte result 190 */ 191 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3, 192 }; 193 194 enum iwl_rx_mpdu_mac_flags2 { 195 /* in 2-byte words */ 196 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f, 197 IWL_RX_MPDU_MFLG2_PAD = 0x20, 198 IWL_RX_MPDU_MFLG2_AMSDU = 0x40, 199 }; 200 201 enum iwl_rx_mpdu_amsdu_info { 202 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f, 203 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80, 204 }; 205 206 #define RX_MPDU_BAND_POS 6 207 #define RX_MPDU_BAND_MASK 0xC0 208 #define BAND_IN_RX_STATUS(_val) \ 209 (((_val) & RX_MPDU_BAND_MASK) >> RX_MPDU_BAND_POS) 210 211 enum iwl_rx_l3_proto_values { 212 IWL_RX_L3_TYPE_NONE, 213 IWL_RX_L3_TYPE_IPV4, 214 IWL_RX_L3_TYPE_IPV4_FRAG, 215 IWL_RX_L3_TYPE_IPV6_FRAG, 216 IWL_RX_L3_TYPE_IPV6, 217 IWL_RX_L3_TYPE_IPV6_IN_IPV4, 218 IWL_RX_L3_TYPE_ARP, 219 IWL_RX_L3_TYPE_EAPOL, 220 }; 221 222 #define IWL_RX_L3_PROTO_POS 4 223 224 enum iwl_rx_l3l4_flags { 225 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0), 226 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1), 227 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2), 228 IWL_RX_L3L4_TCP_ACK = BIT(3), 229 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS, 230 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8, 231 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12, 232 }; 233 234 enum iwl_rx_mpdu_status { 235 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0), 236 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1), 237 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2), 238 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3), 239 IWL_RX_MPDU_STATUS_KEY_PARAM_OK = BIT(4), 240 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5), 241 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6), 242 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7), 243 /* overlayed since IWL_UCODE_TLV_API_DEPRECATE_TTAK */ 244 IWL_RX_MPDU_STATUS_REPLAY_ERROR = BIT(7), 245 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8, 246 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK, 247 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8, 248 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8, 249 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8, 250 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8, 251 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8, 252 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8, 253 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11), 254 IWL_RX_MPDU_STATUS_WEP_MATCH = BIT(12), 255 IWL_RX_MPDU_STATUS_EXT_IV_MATCH = BIT(13), 256 IWL_RX_MPDU_STATUS_KEY_ID_MATCH = BIT(14), 257 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15), 258 259 IWL_RX_MPDU_STATUS_KEY = 0x3f0000, 260 IWL_RX_MPDU_STATUS_DUPLICATE = BIT(22), 261 262 IWL_RX_MPDU_STATUS_STA_ID = 0x1f000000, 263 }; 264 265 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f 266 267 enum iwl_rx_mpdu_reorder_data { 268 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff, 269 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000, 270 IWL_RX_MPDU_REORDER_SN_SHIFT = 12, 271 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000, 272 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24, 273 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000, 274 }; 275 276 enum iwl_rx_mpdu_phy_info { 277 IWL_RX_MPDU_PHY_AMPDU = BIT(5), 278 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6), 279 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7), 280 /* short preamble is only for CCK, for non-CCK overridden by this */ 281 IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7), 282 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8), 283 }; 284 285 enum iwl_rx_mpdu_mac_info { 286 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f, 287 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0, 288 }; 289 290 /* TSF overload low dword */ 291 enum iwl_rx_phy_data0 { 292 /* info type: HE any */ 293 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001, 294 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002, 295 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc, 296 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00, 297 /* 1 bit reserved */ 298 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000, 299 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000, 300 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000, 301 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000, 302 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000, 303 /* 6 bits reserved */ 304 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000, 305 }; 306 307 enum iwl_rx_phy_info_type { 308 IWL_RX_PHY_INFO_TYPE_NONE = 0, 309 IWL_RX_PHY_INFO_TYPE_CCK = 1, 310 IWL_RX_PHY_INFO_TYPE_OFDM_LGCY = 2, 311 IWL_RX_PHY_INFO_TYPE_HT = 3, 312 IWL_RX_PHY_INFO_TYPE_VHT_SU = 4, 313 IWL_RX_PHY_INFO_TYPE_VHT_MU = 5, 314 IWL_RX_PHY_INFO_TYPE_HE_SU = 6, 315 IWL_RX_PHY_INFO_TYPE_HE_MU = 7, 316 IWL_RX_PHY_INFO_TYPE_HE_TB = 8, 317 IWL_RX_PHY_INFO_TYPE_HE_MU_EXT = 9, 318 IWL_RX_PHY_INFO_TYPE_HE_TB_EXT = 10, 319 }; 320 321 /* TSF overload high dword */ 322 enum iwl_rx_phy_data1 { 323 /* 324 * check this first - if TSF overload is set, 325 * see &enum iwl_rx_phy_info_type 326 */ 327 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000, 328 329 /* info type: HT/VHT/HE any */ 330 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000, 331 332 /* info type: HE MU/MU-EXT */ 333 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001, 334 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e, 335 336 /* info type: HE any */ 337 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0, 338 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100, 339 /* trigger encoded */ 340 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00, 341 342 /* info type: HE TB/TX-EXT */ 343 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001, 344 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e, 345 }; 346 347 /* goes into Metadata DW 7 */ 348 enum iwl_rx_phy_data2 { 349 /* info type: HE MU-EXT */ 350 /* the a1/a2/... is what the PHY/firmware calls the values */ 351 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */ 352 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */ 353 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */ 354 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */ 355 356 /* info type: HE TB-EXT */ 357 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f, 358 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0, 359 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00, 360 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000, 361 }; 362 363 /* goes into Metadata DW 8 */ 364 enum iwl_rx_phy_data3 { 365 /* info type: HE MU-EXT */ 366 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */ 367 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */ 368 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */ 369 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */ 370 }; 371 372 /* goes into Metadata DW 4 high 16 bits */ 373 enum iwl_rx_phy_data4 { 374 /* info type: HE MU-EXT */ 375 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001, 376 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002, 377 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004, 378 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008, 379 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0, 380 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100, 381 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600, 382 }; 383 384 /** 385 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor 386 */ 387 struct iwl_rx_mpdu_desc_v1 { 388 /* DW7 - carries rss_hash only when rpa_en == 1 */ 389 union { 390 /** 391 * @rss_hash: RSS hash value 392 */ 393 __le32 rss_hash; 394 395 /** 396 * @phy_data2: depends on info type (see @phy_data1) 397 */ 398 __le32 phy_data2; 399 }; 400 401 /* DW8 - carries filter_match only when rpa_en == 1 */ 402 union { 403 /** 404 * @filter_match: filter match value 405 */ 406 __le32 filter_match; 407 408 /** 409 * @phy_data3: depends on info type (see @phy_data1) 410 */ 411 __le32 phy_data3; 412 }; 413 414 /* DW9 */ 415 /** 416 * @rate_n_flags: RX rate/flags encoding 417 */ 418 __le32 rate_n_flags; 419 /* DW10 */ 420 /** 421 * @energy_a: energy chain A 422 */ 423 u8 energy_a; 424 /** 425 * @energy_b: energy chain B 426 */ 427 u8 energy_b; 428 /** 429 * @channel: channel number 430 */ 431 u8 channel; 432 /** 433 * @mac_context: MAC context mask 434 */ 435 u8 mac_context; 436 /* DW11 */ 437 /** 438 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 439 */ 440 __le32 gp2_on_air_rise; 441 /* DW12 & DW13 */ 442 union { 443 /** 444 * @tsf_on_air_rise: 445 * TSF value on air rise (INA), only valid if 446 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 447 */ 448 __le64 tsf_on_air_rise; 449 450 struct { 451 /** 452 * @phy_data0: depends on info_type, see @phy_data1 453 */ 454 __le32 phy_data0; 455 /** 456 * @phy_data1: valid only if 457 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 458 * see &enum iwl_rx_phy_data1. 459 */ 460 __le32 phy_data1; 461 }; 462 }; 463 } __packed; 464 465 /** 466 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor 467 */ 468 struct iwl_rx_mpdu_desc_v3 { 469 /* DW7 - carries filter_match only when rpa_en == 1 */ 470 union { 471 /** 472 * @filter_match: filter match value 473 */ 474 __le32 filter_match; 475 476 /** 477 * @phy_data3: depends on info type (see @phy_data1) 478 */ 479 __le32 phy_data3; 480 }; 481 482 /* DW8 - carries rss_hash only when rpa_en == 1 */ 483 union { 484 /** 485 * @rss_hash: RSS hash value 486 */ 487 __le32 rss_hash; 488 489 /** 490 * @phy_data2: depends on info type (see @phy_data1) 491 */ 492 __le32 phy_data2; 493 }; 494 /* DW9 */ 495 /** 496 * @partial_hash: 31:0 ip/tcp header hash 497 * w/o some fields (such as IP SRC addr) 498 */ 499 __le32 partial_hash; 500 /* DW10 */ 501 /** 502 * @raw_xsum: raw xsum value 503 */ 504 __be16 raw_xsum; 505 /** 506 * @reserved_xsum: reserved high bits in the raw checksum 507 */ 508 __le16 reserved_xsum; 509 /* DW11 */ 510 /** 511 * @rate_n_flags: RX rate/flags encoding 512 */ 513 __le32 rate_n_flags; 514 /* DW12 */ 515 /** 516 * @energy_a: energy chain A 517 */ 518 u8 energy_a; 519 /** 520 * @energy_b: energy chain B 521 */ 522 u8 energy_b; 523 /** 524 * @channel: channel number 525 */ 526 u8 channel; 527 /** 528 * @mac_context: MAC context mask 529 */ 530 u8 mac_context; 531 /* DW13 */ 532 /** 533 * @gp2_on_air_rise: GP2 timer value on air rise (INA) 534 */ 535 __le32 gp2_on_air_rise; 536 /* DW14 & DW15 */ 537 union { 538 /** 539 * @tsf_on_air_rise: 540 * TSF value on air rise (INA), only valid if 541 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set 542 */ 543 __le64 tsf_on_air_rise; 544 545 struct { 546 /** 547 * @phy_data0: depends on info_type, see @phy_data1 548 */ 549 __le32 phy_data0; 550 /** 551 * @phy_data1: valid only if 552 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set, 553 * see &enum iwl_rx_phy_data1. 554 */ 555 __le32 phy_data1; 556 }; 557 }; 558 /* DW16 & DW17 */ 559 /** 560 * @reserved: reserved 561 */ 562 __le32 reserved[2]; 563 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */ 564 565 /** 566 * struct iwl_rx_mpdu_desc - RX MPDU descriptor 567 */ 568 struct iwl_rx_mpdu_desc { 569 /* DW2 */ 570 /** 571 * @mpdu_len: MPDU length 572 */ 573 __le16 mpdu_len; 574 /** 575 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1 576 */ 577 u8 mac_flags1; 578 /** 579 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2 580 */ 581 u8 mac_flags2; 582 /* DW3 */ 583 /** 584 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info 585 */ 586 u8 amsdu_info; 587 /** 588 * @phy_info: &enum iwl_rx_mpdu_phy_info 589 */ 590 __le16 phy_info; 591 /** 592 * @mac_phy_idx: MAC/PHY index 593 */ 594 u8 mac_phy_idx; 595 /* DW4 - carries csum data only when rpa_en == 1 */ 596 /** 597 * @raw_csum: raw checksum (alledgedly unreliable) 598 */ 599 __le16 raw_csum; 600 601 union { 602 /** 603 * @l3l4_flags: &enum iwl_rx_l3l4_flags 604 */ 605 __le16 l3l4_flags; 606 607 /** 608 * @phy_data4: depends on info type, see phy_data1 609 */ 610 __le16 phy_data4; 611 }; 612 /* DW5 */ 613 /** 614 * @status: &enum iwl_rx_mpdu_status 615 */ 616 __le32 status; 617 618 /* DW6 */ 619 /** 620 * @reorder_data: &enum iwl_rx_mpdu_reorder_data 621 */ 622 __le32 reorder_data; 623 624 union { 625 struct iwl_rx_mpdu_desc_v1 v1; 626 struct iwl_rx_mpdu_desc_v3 v3; 627 }; 628 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */ 629 630 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1) 631 632 #define RX_NO_DATA_CHAIN_A_POS 0 633 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS) 634 #define RX_NO_DATA_CHAIN_B_POS 8 635 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS) 636 #define RX_NO_DATA_CHANNEL_POS 16 637 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS) 638 639 #define RX_NO_DATA_INFO_TYPE_POS 0 640 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS) 641 #define RX_NO_DATA_INFO_TYPE_NONE 0 642 #define RX_NO_DATA_INFO_TYPE_RX_ERR 1 643 #define RX_NO_DATA_INFO_TYPE_NDP 2 644 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED 3 645 #define RX_NO_DATA_INFO_TYPE_HE_TB_UNMATCHED 4 646 647 #define RX_NO_DATA_INFO_ERR_POS 8 648 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS) 649 #define RX_NO_DATA_INFO_ERR_NONE 0 650 #define RX_NO_DATA_INFO_ERR_BAD_PLCP 1 651 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE 2 652 #define RX_NO_DATA_INFO_ERR_NO_DELIM 3 653 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4 654 655 #define RX_NO_DATA_FRAME_TIME_POS 0 656 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS) 657 658 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000 659 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000 660 661 /** 662 * struct iwl_rx_no_data - RX no data descriptor 663 * @info: 7:0 frame type, 15:8 RX error type 664 * @rssi: 7:0 energy chain-A, 665 * 15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel 666 * @on_air_rise_time: GP2 during on air rise 667 * @fr_time: frame time 668 * @rate: rate/mcs of frame 669 * @phy_info: &enum iwl_rx_phy_data0 and &enum iwl_rx_phy_info_type 670 * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type. 671 * for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT 672 * for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT 673 */ 674 struct iwl_rx_no_data { 675 __le32 info; 676 __le32 rssi; 677 __le32 on_air_rise_time; 678 __le32 fr_time; 679 __le32 rate; 680 __le32 phy_info[2]; 681 __le32 rx_vec[2]; 682 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1 */ 683 684 struct iwl_frame_release { 685 u8 baid; 686 u8 reserved; 687 __le16 nssn; 688 }; 689 690 /** 691 * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release 692 * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask 693 * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask 694 */ 695 enum iwl_bar_frame_release_sta_tid { 696 IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f, 697 IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0, 698 }; 699 700 /** 701 * enum iwl_bar_frame_release_ba_info - BA information for BAR release 702 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask 703 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver) 704 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask 705 */ 706 enum iwl_bar_frame_release_ba_info { 707 IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff, 708 IWL_BAR_FRAME_RELEASE_SN_MASK = 0x00fff000, 709 IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000, 710 }; 711 712 /** 713 * struct iwl_bar_frame_release - frame release from BAR info 714 * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid. 715 * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info. 716 */ 717 struct iwl_bar_frame_release { 718 __le32 sta_tid; 719 __le32 ba_info; 720 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */ 721 722 enum iwl_rss_hash_func_en { 723 IWL_RSS_HASH_TYPE_IPV4_TCP, 724 IWL_RSS_HASH_TYPE_IPV4_UDP, 725 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD, 726 IWL_RSS_HASH_TYPE_IPV6_TCP, 727 IWL_RSS_HASH_TYPE_IPV6_UDP, 728 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD, 729 }; 730 731 #define IWL_RSS_HASH_KEY_CNT 10 732 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128 733 #define IWL_RSS_ENABLE 1 734 735 /** 736 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration 737 * 738 * @flags: 1 - enable, 0 - disable 739 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en 740 * @reserved: reserved 741 * @secret_key: 320 bit input of random key configuration from driver 742 * @indirection_table: indirection table 743 */ 744 struct iwl_rss_config_cmd { 745 __le32 flags; 746 u8 hash_mask; 747 u8 reserved[3]; 748 __le32 secret_key[IWL_RSS_HASH_KEY_CNT]; 749 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE]; 750 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */ 751 752 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0 753 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf 754 755 /** 756 * struct iwl_rxq_sync_cmd - RXQ notification trigger 757 * 758 * @flags: flags of the notification. bit 0:3 are the sender queue 759 * @rxq_mask: rx queues to send the notification on 760 * @count: number of bytes in payload, should be DWORD aligned 761 * @payload: data to send to rx queues 762 */ 763 struct iwl_rxq_sync_cmd { 764 __le32 flags; 765 __le32 rxq_mask; 766 __le32 count; 767 u8 payload[]; 768 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 769 770 /** 771 * struct iwl_rxq_sync_notification - Notification triggered by RXQ 772 * sync command 773 * 774 * @count: number of bytes in payload 775 * @payload: data to send to rx queues 776 */ 777 struct iwl_rxq_sync_notification { 778 __le32 count; 779 u8 payload[]; 780 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */ 781 782 /** 783 * enum iwl_mvm_pm_event - type of station PM event 784 * @IWL_MVM_PM_EVENT_AWAKE: station woke up 785 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep 786 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger 787 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll 788 */ 789 enum iwl_mvm_pm_event { 790 IWL_MVM_PM_EVENT_AWAKE, 791 IWL_MVM_PM_EVENT_ASLEEP, 792 IWL_MVM_PM_EVENT_UAPSD, 793 IWL_MVM_PM_EVENT_PS_POLL, 794 }; /* PEER_PM_NTFY_API_E_VER_1 */ 795 796 /** 797 * struct iwl_mvm_pm_state_notification - station PM state notification 798 * @sta_id: station ID of the station changing state 799 * @type: the new powersave state, see &enum iwl_mvm_pm_event 800 */ 801 struct iwl_mvm_pm_state_notification { 802 u8 sta_id; 803 u8 type; 804 /* private: */ 805 __le16 reserved; 806 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */ 807 808 #define BA_WINDOW_STREAMS_MAX 16 809 #define BA_WINDOW_STATUS_TID_MSK 0x000F 810 #define BA_WINDOW_STATUS_STA_ID_POS 4 811 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0 812 #define BA_WINDOW_STATUS_VALID_MSK BIT(9) 813 814 /** 815 * struct iwl_ba_window_status_notif - reordering window's status notification 816 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63] 817 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid 818 * @start_seq_num: the start sequence number of the bitmap 819 * @mpdu_rx_count: the number of received MPDUs since entering D0i3 820 */ 821 struct iwl_ba_window_status_notif { 822 __le64 bitmap[BA_WINDOW_STREAMS_MAX]; 823 __le16 ra_tid[BA_WINDOW_STREAMS_MAX]; 824 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX]; 825 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX]; 826 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */ 827 828 /** 829 * struct iwl_rfh_queue_config - RX queue configuration 830 * @q_num: Q num 831 * @enable: enable queue 832 * @reserved: alignment 833 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 834 * @fr_bd_cb: DMA address of freeRB table 835 * @ur_bd_cb: DMA address of used RB table 836 * @fr_bd_wid: Initial index of the free table 837 */ 838 struct iwl_rfh_queue_data { 839 u8 q_num; 840 u8 enable; 841 __le16 reserved; 842 __le64 urbd_stts_wrptr; 843 __le64 fr_bd_cb; 844 __le64 ur_bd_cb; 845 __le32 fr_bd_wid; 846 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */ 847 848 /** 849 * struct iwl_rfh_queue_config - RX queue configuration 850 * @num_queues: number of queues configured 851 * @reserved: alignment 852 * @data: DMA addresses per-queue 853 */ 854 struct iwl_rfh_queue_config { 855 u8 num_queues; 856 u8 reserved[3]; 857 struct iwl_rfh_queue_data data[]; 858 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */ 859 860 #endif /* __iwl_fw_api_rx_h__ */ 861
