1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13 #ifndef _DPU_HW_CATALOG_H
14 #define _DPU_HW_CATALOG_H
15
16 #include <linux/kernel.h>
17 #include <linux/bug.h>
18 #include <linux/bitmap.h>
19 #include <linux/err.h>
20 #include <drm/drmP.h>
21
22 /**
23 * Max hardware block count: For ex: max 12 SSPP pipes or
24 * 5 ctl paths. In all cases, it can have max 12 hardware blocks
25 * based on current design
26 */
27 #define MAX_BLOCKS 12
28
29 #define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\
30 ((MINOR & 0xFFF) << 16) |\
31 (STEP & 0xFFFF))
32
33 #define DPU_HW_MAJOR(rev) ((rev) >> 28)
34 #define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF)
35 #define DPU_HW_STEP(rev) ((rev) & 0xFFFF)
36 #define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16)
37
38 #define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \
39 (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2)))
40
41 #define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */
42 #define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */
43 #define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */
44 #define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */
45 #define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */
46 #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */
47 #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */
48 #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */
49 #define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sdm855 v1.0 */
50
51
52 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
53 #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300)
54 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400)
55 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410)
56 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500)
57
58
59 #define DPU_HW_BLK_NAME_LEN 16
60
61 #define MAX_IMG_WIDTH 0x3fff
62 #define MAX_IMG_HEIGHT 0x3fff
63
64 #define CRTC_DUAL_MIXERS 2
65
66 #define MAX_XIN_COUNT 16
67
68 /**
69 * Supported UBWC feature versions
70 */
71 enum {
72 DPU_HW_UBWC_VER_10 = 0x100,
73 DPU_HW_UBWC_VER_20 = 0x200,
74 DPU_HW_UBWC_VER_30 = 0x300,
75 };
76
77 #define IS_UBWC_20_SUPPORTED(rev) ((rev) >= DPU_HW_UBWC_VER_20)
78
79 /**
80 * MDP TOP BLOCK features
81 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe
82 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats
83 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression.
84 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth
85 * compression initial revision
86 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5
87 * @DPU_MDP_MAX Maximum value
88
89 */
90 enum {
91 DPU_MDP_PANIC_PER_PIPE = 0x1,
92 DPU_MDP_10BIT_SUPPORT,
93 DPU_MDP_BWC,
94 DPU_MDP_UBWC_1_0,
95 DPU_MDP_UBWC_1_5,
96 DPU_MDP_MAX
97 };
98
99 /**
100 * SSPP sub-blocks/features
101 * @DPU_SSPP_SRC Src and fetch part of the pipes,
102 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support
103 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support
104 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes
105 * @DPU_SSPP_CSC, Support of Color space converion
106 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion
107 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer
108 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq
109 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control
110 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect
111 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support
112 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support
113 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper
114 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec
115 * @DPU_SSPP_CDP Supports client driven prefetch
116 * @DPU_SSPP_MAX maximum value
117 */
118 enum {
119 DPU_SSPP_SRC = 0x1,
120 DPU_SSPP_SCALER_QSEED2,
121 DPU_SSPP_SCALER_QSEED3,
122 DPU_SSPP_SCALER_RGB,
123 DPU_SSPP_CSC,
124 DPU_SSPP_CSC_10BIT,
125 DPU_SSPP_CURSOR,
126 DPU_SSPP_QOS,
127 DPU_SSPP_QOS_8LVL,
128 DPU_SSPP_EXCL_RECT,
129 DPU_SSPP_SMART_DMA_V1,
130 DPU_SSPP_SMART_DMA_V2,
131 DPU_SSPP_TS_PREFILL,
132 DPU_SSPP_TS_PREFILL_REC1,
133 DPU_SSPP_CDP,
134 DPU_SSPP_MAX
135 };
136
137 /*
138 * MIXER sub-blocks/features
139 * @DPU_MIXER_LAYER Layer mixer layer blend configuration,
140 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration
141 * @DPU_MIXER_GC Gamma correction block
142 * @DPU_DIM_LAYER Layer mixer supports dim layer
143 * @DPU_MIXER_MAX maximum value
144 */
145 enum {
146 DPU_MIXER_LAYER = 0x1,
147 DPU_MIXER_SOURCESPLIT,
148 DPU_MIXER_GC,
149 DPU_DIM_LAYER,
150 DPU_MIXER_MAX
151 };
152
153 /**
154 * PINGPONG sub-blocks
155 * @DPU_PINGPONG_TE Tear check block
156 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes
157 * @DPU_PINGPONG_SPLIT PP block supports split fifo
158 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo
159 * @DPU_PINGPONG_DITHER, Dither blocks
160 * @DPU_PINGPONG_MAX
161 */
162 enum {
163 DPU_PINGPONG_TE = 0x1,
164 DPU_PINGPONG_TE2,
165 DPU_PINGPONG_SPLIT,
166 DPU_PINGPONG_SLAVE,
167 DPU_PINGPONG_DITHER,
168 DPU_PINGPONG_MAX
169 };
170
171 /**
172 * CTL sub-blocks
173 * @DPU_CTL_SPLIT_DISPLAY CTL supports video mode split display
174 * @DPU_CTL_MAX
175 */
176 enum {
177 DPU_CTL_SPLIT_DISPLAY = 0x1,
178 DPU_CTL_MAX
179 };
180
181 /**
182 * VBIF sub-blocks and features
183 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit
184 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap
185 * @DPU_VBIF_MAX maximum value
186 */
187 enum {
188 DPU_VBIF_QOS_OTLIM = 0x1,
189 DPU_VBIF_QOS_REMAP,
190 DPU_VBIF_MAX
191 };
192
193 /**
194 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU
195 * @name: string name for debug purposes
196 * @id: enum identifying this block
197 * @base: register base offset to mdss
198 * @len: length of hardware block
199 * @features bit mask identifying sub-blocks/features
200 */
201 #define DPU_HW_BLK_INFO \
202 char name[DPU_HW_BLK_NAME_LEN]; \
203 u32 id; \
204 u32 base; \
205 u32 len; \
206 unsigned long features
207
208 /**
209 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU
210 * @name: string name for debug purposes
211 * @id: enum identifying this sub-block
212 * @base: offset of this sub-block relative to the block
213 * offset
214 * @len register block length of this sub-block
215 */
216 #define DPU_HW_SUBBLK_INFO \
217 char name[DPU_HW_BLK_NAME_LEN]; \
218 u32 id; \
219 u32 base; \
220 u32 len
221
222 /**
223 * struct dpu_src_blk: SSPP part of the source pipes
224 * @info: HW register and features supported by this sub-blk
225 */
226 struct dpu_src_blk {
227 DPU_HW_SUBBLK_INFO;
228 };
229
230 /**
231 * struct dpu_scaler_blk: Scaler information
232 * @info: HW register and features supported by this sub-blk
233 * @version: qseed block revision
234 */
235 struct dpu_scaler_blk {
236 DPU_HW_SUBBLK_INFO;
237 u32 version;
238 };
239
240 struct dpu_csc_blk {
241 DPU_HW_SUBBLK_INFO;
242 };
243
244 /**
245 * struct dpu_pp_blk : Pixel processing sub-blk information
246 * @info: HW register and features supported by this sub-blk
247 * @version: HW Algorithm version
248 */
249 struct dpu_pp_blk {
250 DPU_HW_SUBBLK_INFO;
251 u32 version;
252 };
253
254 /**
255 * struct dpu_format_extended - define dpu specific pixel format+modifier
256 * @fourcc_format: Base FOURCC pixel format code
257 * @modifier: 64-bit drm format modifier, same modifier must be applied to all
258 * framebuffer planes
259 */
260 struct dpu_format_extended {
261 uint32_t fourcc_format;
262 uint64_t modifier;
263 };
264
265 /**
266 * enum dpu_qos_lut_usage - define QoS LUT use cases
267 */
268 enum dpu_qos_lut_usage {
269 DPU_QOS_LUT_USAGE_LINEAR,
270 DPU_QOS_LUT_USAGE_MACROTILE,
271 DPU_QOS_LUT_USAGE_NRT,
272 DPU_QOS_LUT_USAGE_MAX,
273 };
274
275 /**
276 * struct dpu_qos_lut_entry - define QoS LUT table entry
277 * @fl: fill level, or zero on last entry to indicate default lut
278 * @lut: lut to use if equal to or less than fill level
279 */
280 struct dpu_qos_lut_entry {
281 u32 fl;
282 u64 lut;
283 };
284
285 /**
286 * struct dpu_qos_lut_tbl - define QoS LUT table
287 * @nentry: number of entry in this table
288 * @entries: Pointer to table entries
289 */
290 struct dpu_qos_lut_tbl {
291 u32 nentry;
292 struct dpu_qos_lut_entry *entries;
293 };
294
295 /**
296 * struct dpu_caps - define DPU capabilities
297 * @max_mixer_width max layer mixer line width support.
298 * @max_mixer_blendstages max layer mixer blend stages or
299 * supported z order
300 * @qseed_type qseed2 or qseed3 support.
301 * @smart_dma_rev Supported version of SmartDMA feature.
302 * @ubwc_version UBWC feature version (0x0 for not supported)
303 * @has_src_split source split feature status
304 * @has_dim_layer dim layer feature status
305 * @has_idle_pc indicate if idle power collapse feature is supported
306 */
307 struct dpu_caps {
308 u32 max_mixer_width;
309 u32 max_mixer_blendstages;
310 u32 qseed_type;
311 u32 smart_dma_rev;
312 u32 ubwc_version;
313 bool has_src_split;
314 bool has_dim_layer;
315 bool has_idle_pc;
316 };
317
318 /**
319 * struct dpu_sspp_blks_common : SSPP sub-blocks common configuration
320 * @maxwidth: max pixelwidth supported by this pipe
321 * @pixel_ram_size: size of latency hiding and de-tiling buffer in bytes
322 * @maxhdeciexp: max horizontal decimation supported by this pipe
323 * (max is 2^value)
324 * @maxvdeciexp: max vertical decimation supported by this pipe
325 * (max is 2^value)
326 */
327 struct dpu_sspp_blks_common {
328 u32 maxlinewidth;
329 u32 pixel_ram_size;
330 u32 maxhdeciexp;
331 u32 maxvdeciexp;
332 };
333
334 /**
335 * struct dpu_sspp_sub_blks : SSPP sub-blocks
336 * common: Pointer to common configurations shared by sub blocks
337 * @creq_vblank: creq priority during vertical blanking
338 * @danger_vblank: danger priority during vertical blanking
339 * @maxdwnscale: max downscale ratio supported(without DECIMATION)
340 * @maxupscale: maxupscale ratio supported
341 * @smart_dma_priority: hw priority of rect1 of multirect pipe
342 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps
343 * @src_blk:
344 * @scaler_blk:
345 * @csc_blk:
346 * @hsic:
347 * @memcolor:
348 * @pcc_blk:
349 * @igc_blk:
350 * @format_list: Pointer to list of supported formats
351 * @virt_format_list: Pointer to list of supported formats for virtual planes
352 */
353 struct dpu_sspp_sub_blks {
354 const struct dpu_sspp_blks_common *common;
355 u32 creq_vblank;
356 u32 danger_vblank;
357 u32 maxdwnscale;
358 u32 maxupscale;
359 u32 smart_dma_priority;
360 u32 max_per_pipe_bw;
361 struct dpu_src_blk src_blk;
362 struct dpu_scaler_blk scaler_blk;
363 struct dpu_pp_blk csc_blk;
364 struct dpu_pp_blk hsic_blk;
365 struct dpu_pp_blk memcolor_blk;
366 struct dpu_pp_blk pcc_blk;
367 struct dpu_pp_blk igc_blk;
368
369 const struct dpu_format_extended *format_list;
370 const struct dpu_format_extended *virt_format_list;
371 };
372
373 /**
374 * struct dpu_lm_sub_blks: information of mixer block
375 * @maxwidth: Max pixel width supported by this mixer
376 * @maxblendstages: Max number of blend-stages supported
377 * @blendstage_base: Blend-stage register base offset
378 * @gc: gamma correction block
379 */
380 struct dpu_lm_sub_blks {
381 u32 maxwidth;
382 u32 maxblendstages;
383 u32 blendstage_base[MAX_BLOCKS];
384 struct dpu_pp_blk gc;
385 };
386
387 struct dpu_pingpong_sub_blks {
388 struct dpu_pp_blk te;
389 struct dpu_pp_blk te2;
390 struct dpu_pp_blk dither;
391 };
392
393 /**
394 * dpu_clk_ctrl_type - Defines top level clock control signals
395 */
396 enum dpu_clk_ctrl_type {
397 DPU_CLK_CTRL_NONE,
398 DPU_CLK_CTRL_VIG0,
399 DPU_CLK_CTRL_VIG1,
400 DPU_CLK_CTRL_VIG2,
401 DPU_CLK_CTRL_VIG3,
402 DPU_CLK_CTRL_VIG4,
403 DPU_CLK_CTRL_RGB0,
404 DPU_CLK_CTRL_RGB1,
405 DPU_CLK_CTRL_RGB2,
406 DPU_CLK_CTRL_RGB3,
407 DPU_CLK_CTRL_DMA0,
408 DPU_CLK_CTRL_DMA1,
409 DPU_CLK_CTRL_CURSOR0,
410 DPU_CLK_CTRL_CURSOR1,
411 DPU_CLK_CTRL_INLINE_ROT0_SSPP,
412 DPU_CLK_CTRL_MAX,
413 };
414
415 /* struct dpu_clk_ctrl_reg : Clock control register
416 * @reg_off: register offset
417 * @bit_off: bit offset
418 */
419 struct dpu_clk_ctrl_reg {
420 u32 reg_off;
421 u32 bit_off;
422 };
423
424 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info
425 * @id: index identifying this block
426 * @base: register base offset to mdss
427 * @features bit mask identifying sub-blocks/features
428 * @highest_bank_bit: UBWC parameter
429 * @ubwc_static: ubwc static configuration
430 * @ubwc_swizzle: ubwc default swizzle setting
431 * @has_dest_scaler: indicates support of destination scaler
432 * @clk_ctrls clock control register definition
433 */
434 struct dpu_mdp_cfg {
435 DPU_HW_BLK_INFO;
436 u32 highest_bank_bit;
437 u32 ubwc_static;
438 u32 ubwc_swizzle;
439 bool has_dest_scaler;
440 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX];
441 };
442
443 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info
444 * @id: index identifying this block
445 * @base: register base offset to mdss
446 * @features bit mask identifying sub-blocks/features
447 */
448 struct dpu_ctl_cfg {
449 DPU_HW_BLK_INFO;
450 };
451
452 /**
453 * struct dpu_sspp_cfg - information of source pipes
454 * @id: index identifying this block
455 * @base register offset of this block
456 * @features bit mask identifying sub-blocks/features
457 * @sblk: SSPP sub-blocks information
458 * @xin_id: bus client identifier
459 * @clk_ctrl clock control identifier
460 * @type sspp type identifier
461 */
462 struct dpu_sspp_cfg {
463 DPU_HW_BLK_INFO;
464 const struct dpu_sspp_sub_blks *sblk;
465 u32 xin_id;
466 enum dpu_clk_ctrl_type clk_ctrl;
467 u32 type;
468 };
469
470 /**
471 * struct dpu_lm_cfg - information of layer mixer blocks
472 * @id: index identifying this block
473 * @base register offset of this block
474 * @features bit mask identifying sub-blocks/features
475 * @sblk: LM Sub-blocks information
476 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported
477 * @ds: ID of connected DS, DS_MAX if unsupported
478 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL
479 */
480 struct dpu_lm_cfg {
481 DPU_HW_BLK_INFO;
482 const struct dpu_lm_sub_blks *sblk;
483 u32 pingpong;
484 u32 ds;
485 unsigned long lm_pair_mask;
486 };
487
488 /**
489 * struct dpu_ds_top_cfg - information of dest scaler top
490 * @id enum identifying this block
491 * @base register offset of this block
492 * @features bit mask identifying features
493 * @version hw version of dest scaler
494 * @maxinputwidth maximum input line width
495 * @maxoutputwidth maximum output line width
496 * @maxupscale maximum upscale ratio
497 */
498 struct dpu_ds_top_cfg {
499 DPU_HW_BLK_INFO;
500 u32 version;
501 u32 maxinputwidth;
502 u32 maxoutputwidth;
503 u32 maxupscale;
504 };
505
506 /**
507 * struct dpu_ds_cfg - information of dest scaler blocks
508 * @id enum identifying this block
509 * @base register offset wrt DS top offset
510 * @features bit mask identifying features
511 * @version hw version of the qseed block
512 * @top DS top information
513 */
514 struct dpu_ds_cfg {
515 DPU_HW_BLK_INFO;
516 u32 version;
517 const struct dpu_ds_top_cfg *top;
518 };
519
520 /**
521 * struct dpu_pingpong_cfg - information of PING-PONG blocks
522 * @id enum identifying this block
523 * @base register offset of this block
524 * @features bit mask identifying sub-blocks/features
525 * @sblk sub-blocks information
526 */
527 struct dpu_pingpong_cfg {
528 DPU_HW_BLK_INFO;
529 const struct dpu_pingpong_sub_blks *sblk;
530 };
531
532 /**
533 * struct dpu_cdm_cfg - information of chroma down blocks
534 * @id enum identifying this block
535 * @base register offset of this block
536 * @features bit mask identifying sub-blocks/features
537 * @intf_connect Bitmask of INTF IDs this CDM can connect to
538 */
539 struct dpu_cdm_cfg {
540 DPU_HW_BLK_INFO;
541 unsigned long intf_connect;
542 };
543
544 /**
545 * struct dpu_intf_cfg - information of timing engine blocks
546 * @id enum identifying this block
547 * @base register offset of this block
548 * @features bit mask identifying sub-blocks/features
549 * @type: Interface type(DSI, DP, HDMI)
550 * @controller_id: Controller Instance ID in case of multiple of intf type
551 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch
552 */
553 struct dpu_intf_cfg {
554 DPU_HW_BLK_INFO;
555 u32 type; /* interface type*/
556 u32 controller_id;
557 u32 prog_fetch_lines_worst_case;
558 };
559
560 /**
561 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting
562 * @pps pixel per seconds
563 * @ot_limit OT limit to use up to specified pixel per second
564 */
565 struct dpu_vbif_dynamic_ot_cfg {
566 u64 pps;
567 u32 ot_limit;
568 };
569
570 /**
571 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table
572 * @count length of cfg
573 * @cfg pointer to array of configuration settings with
574 * ascending requirements
575 */
576 struct dpu_vbif_dynamic_ot_tbl {
577 u32 count;
578 struct dpu_vbif_dynamic_ot_cfg *cfg;
579 };
580
581 /**
582 * struct dpu_vbif_qos_tbl - QoS priority table
583 * @npriority_lvl num of priority level
584 * @priority_lvl pointer to array of priority level in ascending order
585 */
586 struct dpu_vbif_qos_tbl {
587 u32 npriority_lvl;
588 u32 *priority_lvl;
589 };
590
591 /**
592 * struct dpu_vbif_cfg - information of VBIF blocks
593 * @id enum identifying this block
594 * @base register offset of this block
595 * @features bit mask identifying sub-blocks/features
596 * @ot_rd_limit default OT read limit
597 * @ot_wr_limit default OT write limit
598 * @xin_halt_timeout maximum time (in usec) for xin to halt
599 * @dynamic_ot_rd_tbl dynamic OT read configuration table
600 * @dynamic_ot_wr_tbl dynamic OT write configuration table
601 * @qos_rt_tbl real-time QoS priority table
602 * @qos_nrt_tbl non-real-time QoS priority table
603 * @memtype_count number of defined memtypes
604 * @memtype array of xin memtype definitions
605 */
606 struct dpu_vbif_cfg {
607 DPU_HW_BLK_INFO;
608 u32 default_ot_rd_limit;
609 u32 default_ot_wr_limit;
610 u32 xin_halt_timeout;
611 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl;
612 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl;
613 struct dpu_vbif_qos_tbl qos_rt_tbl;
614 struct dpu_vbif_qos_tbl qos_nrt_tbl;
615 u32 memtype_count;
616 u32 memtype[MAX_XIN_COUNT];
617 };
618 /**
619 * struct dpu_reg_dma_cfg - information of lut dma blocks
620 * @id enum identifying this block
621 * @base register offset of this block
622 * @features bit mask identifying sub-blocks/features
623 * @version version of lutdma hw block
624 * @trigger_sel_off offset to trigger select registers of lutdma
625 */
626 struct dpu_reg_dma_cfg {
627 DPU_HW_BLK_INFO;
628 u32 version;
629 u32 trigger_sel_off;
630 };
631
632 /**
633 * Define CDP use cases
634 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases
635 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD
636 */
637 enum {
638 DPU_PERF_CDP_USAGE_RT,
639 DPU_PERF_CDP_USAGE_NRT,
640 DPU_PERF_CDP_USAGE_MAX
641 };
642
643 /**
644 * struct dpu_perf_cdp_cfg - define CDP use case configuration
645 * @rd_enable: true if read pipe CDP is enabled
646 * @wr_enable: true if write pipe CDP is enabled
647 */
648 struct dpu_perf_cdp_cfg {
649 bool rd_enable;
650 bool wr_enable;
651 };
652
653 /**
654 * struct dpu_perf_cfg - performance control settings
655 * @max_bw_low low threshold of maximum bandwidth (kbps)
656 * @max_bw_high high threshold of maximum bandwidth (kbps)
657 * @min_core_ib minimum bandwidth for core (kbps)
658 * @min_core_ib minimum mnoc ib vote in kbps
659 * @min_llcc_ib minimum llcc ib vote in kbps
660 * @min_dram_ib minimum dram ib vote in kbps
661 * @core_ib_ff core instantaneous bandwidth fudge factor
662 * @core_clk_ff core clock fudge factor
663 * @comp_ratio_rt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio>
664 * @comp_ratio_nrt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio>
665 * @undersized_prefill_lines undersized prefill in lines
666 * @xtra_prefill_lines extra prefill latency in lines
667 * @dest_scale_prefill_lines destination scaler latency in lines
668 * @macrotile_perfill_lines macrotile latency in lines
669 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines
670 * @linear_prefill_lines linear latency in lines
671 * @downscaling_prefill_lines downscaling latency in lines
672 * @amortizable_theshold minimum y position for traffic shaping prefill
673 * @min_prefill_lines minimum pipeline latency in lines
674 * @safe_lut_tbl: LUT tables for safe signals
675 * @danger_lut_tbl: LUT tables for danger signals
676 * @qos_lut_tbl: LUT tables for QoS signals
677 * @cdp_cfg cdp use case configurations
678 */
679 struct dpu_perf_cfg {
680 u32 max_bw_low;
681 u32 max_bw_high;
682 u32 min_core_ib;
683 u32 min_llcc_ib;
684 u32 min_dram_ib;
685 const char *core_ib_ff;
686 const char *core_clk_ff;
687 const char *comp_ratio_rt;
688 const char *comp_ratio_nrt;
689 u32 undersized_prefill_lines;
690 u32 xtra_prefill_lines;
691 u32 dest_scale_prefill_lines;
692 u32 macrotile_prefill_lines;
693 u32 yuv_nv12_prefill_lines;
694 u32 linear_prefill_lines;
695 u32 downscaling_prefill_lines;
696 u32 amortizable_threshold;
697 u32 min_prefill_lines;
698 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
699 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
700 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX];
701 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX];
702 };
703
704 /**
705 * struct dpu_mdss_cfg - information of MDSS HW
706 * This is the main catalog data structure representing
707 * this HW version. Contains number of instances,
708 * register offsets, capabilities of the all MDSS HW sub-blocks.
709 *
710 * @dma_formats Supported formats for dma pipe
711 * @cursor_formats Supported formats for cursor pipe
712 * @vig_formats Supported formats for vig pipe
713 */
714 struct dpu_mdss_cfg {
715 u32 hwversion;
716
717 const struct dpu_caps *caps;
718
719 u32 mdp_count;
720 struct dpu_mdp_cfg *mdp;
721
722 u32 ctl_count;
723 struct dpu_ctl_cfg *ctl;
724
725 u32 sspp_count;
726 struct dpu_sspp_cfg *sspp;
727
728 u32 mixer_count;
729 struct dpu_lm_cfg *mixer;
730
731 u32 ds_count;
732 struct dpu_ds_cfg *ds;
733
734 u32 pingpong_count;
735 struct dpu_pingpong_cfg *pingpong;
736
737 u32 cdm_count;
738 struct dpu_cdm_cfg *cdm;
739
740 u32 intf_count;
741 struct dpu_intf_cfg *intf;
742
743 u32 vbif_count;
744 struct dpu_vbif_cfg *vbif;
745
746 u32 reg_dma_count;
747 struct dpu_reg_dma_cfg dma_cfg;
748
749 u32 ad_count;
750
751 /* Add additional block data structures here */
752
753 struct dpu_perf_cfg perf;
754 struct dpu_format_extended *dma_formats;
755 struct dpu_format_extended *cursor_formats;
756 struct dpu_format_extended *vig_formats;
757 };
758
759 struct dpu_mdss_hw_cfg_handler {
760 u32 hw_rev;
761 void (*cfg_init)(struct dpu_mdss_cfg *dpu_cfg);
762 };
763
764 /*
765 * Access Macros
766 */
767 #define BLK_MDP(s) ((s)->mdp)
768 #define BLK_CTL(s) ((s)->ctl)
769 #define BLK_VIG(s) ((s)->vig)
770 #define BLK_RGB(s) ((s)->rgb)
771 #define BLK_DMA(s) ((s)->dma)
772 #define BLK_CURSOR(s) ((s)->cursor)
773 #define BLK_MIXER(s) ((s)->mixer)
774 #define BLK_DS(s) ((s)->ds)
775 #define BLK_PINGPONG(s) ((s)->pingpong)
776 #define BLK_CDM(s) ((s)->cdm)
777 #define BLK_INTF(s) ((s)->intf)
778 #define BLK_AD(s) ((s)->ad)
779
780 /**
781 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves
782 * hardcoded target specific catalog information in config structure
783 * @hw_rev: caller needs provide the hardware revision.
784 *
785 * Return: dpu config structure
786 */
787 struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev);
788
789 /**
790 * dpu_hw_catalog_deinit - dpu hardware catalog cleanup
791 * @dpu_cfg: pointer returned from init function
792 */
793 void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg);
794
795 /**
796 * dpu_hw_sspp_multirect_enabled - check multirect enabled for the sspp
797 * @cfg: pointer to sspp cfg
798 */
dpu_hw_sspp_multirect_enabled(const struct dpu_sspp_cfg * cfg)799 static inline bool dpu_hw_sspp_multirect_enabled(const struct dpu_sspp_cfg *cfg)
800 {
801 return test_bit(DPU_SSPP_SMART_DMA_V1, &cfg->features) ||
802 test_bit(DPU_SSPP_SMART_DMA_V2, &cfg->features);
803 }
804 #endif /* _DPU_HW_CATALOG_H */
805
