1 /* 2 * arch/arm/mach-pxa/include/mach/irqs.h 3 * 4 * Author: Nicolas Pitre 5 * Created: Jun 15, 2001 6 * Copyright: MontaVista Software Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 #ifndef __ASM_MACH_IRQS_H 13 #define __ASM_MACH_IRQS_H 14 15 #include <asm/irq.h> 16 17 #define PXA_ISA_IRQ(x) (x) 18 #define PXA_IRQ(x) (NR_IRQS_LEGACY + (x)) 19 20 #define IRQ_SSP3 PXA_IRQ(0) /* SSP3 service request */ 21 #define IRQ_MSL PXA_IRQ(1) /* MSL Interface interrupt */ 22 #define IRQ_USBH2 PXA_IRQ(2) /* USB Host interrupt 1 (OHCI,PXA27x) */ 23 #define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */ 24 #define IRQ_KEYPAD PXA_IRQ(4) /* Key pad controller */ 25 #define IRQ_MEMSTK PXA_IRQ(5) /* Memory Stick interrupt (PXA27x) */ 26 #define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */ 27 #define IRQ_PWRI2C PXA_IRQ(6) /* Power I2C interrupt */ 28 #define IRQ_HWUART PXA_IRQ(7) /* HWUART Transmit/Receive/Error (PXA26x) */ 29 #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */ 30 #define IRQ_GPIO0 PXA_IRQ(8) /* GPIO0 Edge Detect */ 31 #define IRQ_GPIO1 PXA_IRQ(9) /* GPIO1 Edge Detect */ 32 #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */ 33 #define IRQ_USB PXA_IRQ(11) /* USB Service */ 34 #define IRQ_PMU PXA_IRQ(12) /* Performance Monitoring Unit */ 35 #define IRQ_I2S PXA_IRQ(13) /* I2S Interrupt (PXA27x) */ 36 #define IRQ_SSP4 PXA_IRQ(13) /* SSP4 service request (PXA3xx) */ 37 #define IRQ_AC97 PXA_IRQ(14) /* AC97 Interrupt */ 38 #define IRQ_ASSP PXA_IRQ(15) /* Audio SSP Service Request (PXA25x) */ 39 #define IRQ_USIM PXA_IRQ(15) /* Smart Card interface interrupt (PXA27x) */ 40 #define IRQ_NSSP PXA_IRQ(16) /* Network SSP Service Request (PXA25x) */ 41 #define IRQ_SSP2 PXA_IRQ(16) /* SSP2 interrupt (PXA27x) */ 42 #define IRQ_LCD PXA_IRQ(17) /* LCD Controller Service Request */ 43 #define IRQ_I2C PXA_IRQ(18) /* I2C Service Request */ 44 #define IRQ_ICP PXA_IRQ(19) /* ICP Transmit/Receive/Error */ 45 #define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */ 46 #define IRQ_STUART PXA_IRQ(20) /* STUART Transmit/Receive/Error */ 47 #define IRQ_BTUART PXA_IRQ(21) /* BTUART Transmit/Receive/Error */ 48 #define IRQ_FFUART PXA_IRQ(22) /* FFUART Transmit/Receive/Error*/ 49 #define IRQ_MMC PXA_IRQ(23) /* MMC Status/Error Detection */ 50 #define IRQ_SSP PXA_IRQ(24) /* SSP Service Request */ 51 #define IRQ_DMA PXA_IRQ(25) /* DMA Channel Service Request */ 52 #define IRQ_OST0 PXA_IRQ(26) /* OS Timer match 0 */ 53 #define IRQ_OST1 PXA_IRQ(27) /* OS Timer match 1 */ 54 #define IRQ_OST2 PXA_IRQ(28) /* OS Timer match 2 */ 55 #define IRQ_OST3 PXA_IRQ(29) /* OS Timer match 3 */ 56 #define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */ 57 #define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */ 58 59 #define IRQ_TPM PXA_IRQ(32) /* TPM interrupt */ 60 #define IRQ_CAMERA PXA_IRQ(33) /* Camera Interface */ 61 #define IRQ_CIR PXA_IRQ(34) /* Consumer IR */ 62 #define IRQ_COMM_WDT PXA_IRQ(35) /* Comm WDT interrupt */ 63 #define IRQ_TSI PXA_IRQ(36) /* Touch Screen Interface (PXA320) */ 64 #define IRQ_ENHROT PXA_IRQ(37) /* Enhanced Rotary (PXA930) */ 65 #define IRQ_USIM2 PXA_IRQ(38) /* USIM2 Controller */ 66 #define IRQ_GCU PXA_IRQ(39) /* Graphics Controller (PXA3xx) */ 67 #define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */ 68 #define IRQ_MMC2 PXA_IRQ(41) /* MMC2 Controller */ 69 #define IRQ_TRKBALL PXA_IRQ(43) /* Track Ball (PXA930) */ 70 #define IRQ_1WIRE PXA_IRQ(44) /* 1-Wire Controller */ 71 #define IRQ_NAND PXA_IRQ(45) /* NAND Controller */ 72 #define IRQ_USB2 PXA_IRQ(46) /* USB 2.0 Device Controller */ 73 #define IRQ_WAKEUP0 PXA_IRQ(49) /* EXT_WAKEUP0 */ 74 #define IRQ_WAKEUP1 PXA_IRQ(50) /* EXT_WAKEUP1 */ 75 #define IRQ_DMEMC PXA_IRQ(51) /* Dynamic Memory Controller */ 76 #define IRQ_MMC3 PXA_IRQ(55) /* MMC3 Controller (PXA310) */ 77 78 #define IRQ_U2O PXA_IRQ(64) /* USB OTG 2.0 Controller (PXA935) */ 79 #define IRQ_U2H PXA_IRQ(65) /* USB Host 2.0 Controller (PXA935) */ 80 #define IRQ_PXA935_MMC0 PXA_IRQ(72) /* MMC0 Controller (PXA935) */ 81 #define IRQ_PXA935_MMC1 PXA_IRQ(73) /* MMC1 Controller (PXA935) */ 82 #define IRQ_PXA935_MMC2 PXA_IRQ(74) /* MMC2 Controller (PXA935) */ 83 #define IRQ_U2P PXA_IRQ(93) /* USB PHY D+/D- Lines (PXA935) */ 84 85 #define PXA_GPIO_IRQ_BASE PXA_IRQ(96) 86 #define PXA_NR_BUILTIN_GPIO (192) 87 #define PXA_GPIO_TO_IRQ(x) (PXA_GPIO_IRQ_BASE + (x)) 88 89 /* 90 * The following interrupts are for board specific purposes. Since 91 * the kernel can only run on one machine at a time, we can re-use 92 * these. 93 * By default, no board IRQ is reserved. It should be finished in 94 * custom board since sparse IRQ is already enabled. 95 */ 96 #define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_NR_BUILTIN_GPIO) 97 98 #define PXA_NR_IRQS (IRQ_BOARD_START) 99 100 #ifndef __ASSEMBLY__ 101 struct irq_data; 102 struct pt_regs; 103 104 void pxa_mask_irq(struct irq_data *); 105 void pxa_unmask_irq(struct irq_data *); 106 void icip_handle_irq(struct pt_regs *); 107 void ichp_handle_irq(struct pt_regs *); 108 109 void pxa_init_irq(int irq_nr, int (*set_wake)(struct irq_data *, unsigned int)); 110 #endif 111 112 #endif /* __ASM_MACH_IRQS_H */ 113
