1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */
2 /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */
3
4 #ifndef _IONIC_IF_H_
5 #define _IONIC_IF_H_
6
7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */
8 #define IONIC_DEV_INFO_VERSION 1
9 #define IONIC_IFNAMSIZ 16
10
11 /**
12 * enum ionic_cmd_opcode - Device commands
13 */
14 enum ionic_cmd_opcode {
15 IONIC_CMD_NOP = 0,
16
17 /* Device commands */
18 IONIC_CMD_IDENTIFY = 1,
19 IONIC_CMD_INIT = 2,
20 IONIC_CMD_RESET = 3,
21 IONIC_CMD_GETATTR = 4,
22 IONIC_CMD_SETATTR = 5,
23
24 /* Port commands */
25 IONIC_CMD_PORT_IDENTIFY = 10,
26 IONIC_CMD_PORT_INIT = 11,
27 IONIC_CMD_PORT_RESET = 12,
28 IONIC_CMD_PORT_GETATTR = 13,
29 IONIC_CMD_PORT_SETATTR = 14,
30
31 /* LIF commands */
32 IONIC_CMD_LIF_IDENTIFY = 20,
33 IONIC_CMD_LIF_INIT = 21,
34 IONIC_CMD_LIF_RESET = 22,
35 IONIC_CMD_LIF_GETATTR = 23,
36 IONIC_CMD_LIF_SETATTR = 24,
37
38 IONIC_CMD_RX_MODE_SET = 30,
39 IONIC_CMD_RX_FILTER_ADD = 31,
40 IONIC_CMD_RX_FILTER_DEL = 32,
41
42 /* Queue commands */
43 IONIC_CMD_Q_IDENTIFY = 39,
44 IONIC_CMD_Q_INIT = 40,
45 IONIC_CMD_Q_CONTROL = 41,
46
47 /* RDMA commands */
48 IONIC_CMD_RDMA_RESET_LIF = 50,
49 IONIC_CMD_RDMA_CREATE_EQ = 51,
50 IONIC_CMD_RDMA_CREATE_CQ = 52,
51 IONIC_CMD_RDMA_CREATE_ADMINQ = 53,
52
53 /* SR/IOV commands */
54 IONIC_CMD_VF_GETATTR = 60,
55 IONIC_CMD_VF_SETATTR = 61,
56
57 /* QoS commands */
58 IONIC_CMD_QOS_CLASS_IDENTIFY = 240,
59 IONIC_CMD_QOS_CLASS_INIT = 241,
60 IONIC_CMD_QOS_CLASS_RESET = 242,
61 IONIC_CMD_QOS_CLASS_UPDATE = 243,
62 IONIC_CMD_QOS_CLEAR_STATS = 244,
63 IONIC_CMD_QOS_RESET = 245,
64
65 /* Firmware commands */
66 IONIC_CMD_FW_DOWNLOAD = 252,
67 IONIC_CMD_FW_CONTROL = 253,
68 IONIC_CMD_FW_DOWNLOAD_V1 = 254,
69 IONIC_CMD_FW_CONTROL_V1 = 255,
70 };
71
72 /**
73 * enum ionic_status_code - Device command return codes
74 */
75 enum ionic_status_code {
76 IONIC_RC_SUCCESS = 0, /* Success */
77 IONIC_RC_EVERSION = 1, /* Incorrect version for request */
78 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */
79 IONIC_RC_EIO = 3, /* I/O error */
80 IONIC_RC_EPERM = 4, /* Permission denied */
81 IONIC_RC_EQID = 5, /* Bad qid */
82 IONIC_RC_EQTYPE = 6, /* Bad qtype */
83 IONIC_RC_ENOENT = 7, /* No such element */
84 IONIC_RC_EINTR = 8, /* operation interrupted */
85 IONIC_RC_EAGAIN = 9, /* Try again */
86 IONIC_RC_ENOMEM = 10, /* Out of memory */
87 IONIC_RC_EFAULT = 11, /* Bad address */
88 IONIC_RC_EBUSY = 12, /* Device or resource busy */
89 IONIC_RC_EEXIST = 13, /* object already exists */
90 IONIC_RC_EINVAL = 14, /* Invalid argument */
91 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */
92 IONIC_RC_ERANGE = 16, /* Parameter out of range */
93 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */
94 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */
95 IONIC_RC_ENOSUPP = 19, /* Operation not supported */
96 IONIC_RC_ERROR = 29, /* Generic error */
97 IONIC_RC_ERDMA = 30, /* Generic RDMA error */
98 IONIC_RC_EVFID = 31, /* VF ID does not exist */
99 IONIC_RC_EBAD_FW = 32, /* FW file is invalid or corrupted */
100 };
101
102 enum ionic_notifyq_opcode {
103 IONIC_EVENT_LINK_CHANGE = 1,
104 IONIC_EVENT_RESET = 2,
105 IONIC_EVENT_HEARTBEAT = 3,
106 IONIC_EVENT_LOG = 4,
107 IONIC_EVENT_XCVR = 5,
108 };
109
110 /**
111 * struct ionic_admin_cmd - General admin command format
112 * @opcode: Opcode for the command
113 * @lif_index: LIF index
114 * @cmd_data: Opcode-specific command bytes
115 */
116 struct ionic_admin_cmd {
117 u8 opcode;
118 u8 rsvd;
119 __le16 lif_index;
120 u8 cmd_data[60];
121 };
122
123 /**
124 * struct ionic_admin_comp - General admin command completion format
125 * @status: Status of the command (enum ionic_status_code)
126 * @comp_index: Index in the descriptor ring for which this is the completion
127 * @cmd_data: Command-specific bytes
128 * @color: Color bit (Always 0 for commands issued to the
129 * Device Cmd Registers)
130 */
131 struct ionic_admin_comp {
132 u8 status;
133 u8 rsvd;
134 __le16 comp_index;
135 u8 cmd_data[11];
136 u8 color;
137 #define IONIC_COMP_COLOR_MASK 0x80
138 };
139
color_match(u8 color,u8 done_color)140 static inline u8 color_match(u8 color, u8 done_color)
141 {
142 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color;
143 }
144
145 /**
146 * struct ionic_nop_cmd - NOP command
147 * @opcode: opcode
148 */
149 struct ionic_nop_cmd {
150 u8 opcode;
151 u8 rsvd[63];
152 };
153
154 /**
155 * struct ionic_nop_comp - NOP command completion
156 * @status: Status of the command (enum ionic_status_code)
157 */
158 struct ionic_nop_comp {
159 u8 status;
160 u8 rsvd[15];
161 };
162
163 /**
164 * struct ionic_dev_init_cmd - Device init command
165 * @opcode: opcode
166 * @type: Device type
167 */
168 struct ionic_dev_init_cmd {
169 u8 opcode;
170 u8 type;
171 u8 rsvd[62];
172 };
173
174 /**
175 * struct ionic_dev_init_comp - Device init command completion
176 * @status: Status of the command (enum ionic_status_code)
177 */
178 struct ionic_dev_init_comp {
179 u8 status;
180 u8 rsvd[15];
181 };
182
183 /**
184 * struct ionic_dev_reset_cmd - Device reset command
185 * @opcode: opcode
186 */
187 struct ionic_dev_reset_cmd {
188 u8 opcode;
189 u8 rsvd[63];
190 };
191
192 /**
193 * struct ionic_dev_reset_comp - Reset command completion
194 * @status: Status of the command (enum ionic_status_code)
195 */
196 struct ionic_dev_reset_comp {
197 u8 status;
198 u8 rsvd[15];
199 };
200
201 #define IONIC_IDENTITY_VERSION_1 1
202
203 /**
204 * struct ionic_dev_identify_cmd - Driver/device identify command
205 * @opcode: opcode
206 * @ver: Highest version of identify supported by driver
207 */
208 struct ionic_dev_identify_cmd {
209 u8 opcode;
210 u8 ver;
211 u8 rsvd[62];
212 };
213
214 /**
215 * struct ionic_dev_identify_comp - Driver/device identify command completion
216 * @status: Status of the command (enum ionic_status_code)
217 * @ver: Version of identify returned by device
218 */
219 struct ionic_dev_identify_comp {
220 u8 status;
221 u8 ver;
222 u8 rsvd[14];
223 };
224
225 enum ionic_os_type {
226 IONIC_OS_TYPE_LINUX = 1,
227 IONIC_OS_TYPE_WIN = 2,
228 IONIC_OS_TYPE_DPDK = 3,
229 IONIC_OS_TYPE_FREEBSD = 4,
230 IONIC_OS_TYPE_IPXE = 5,
231 IONIC_OS_TYPE_ESXI = 6,
232 };
233
234 /**
235 * union ionic_drv_identity - driver identity information
236 * @os_type: OS type (see enum ionic_os_type)
237 * @os_dist: OS distribution, numeric format
238 * @os_dist_str: OS distribution, string format
239 * @kernel_ver: Kernel version, numeric format
240 * @kernel_ver_str: Kernel version, string format
241 * @driver_ver_str: Driver version, string format
242 */
243 union ionic_drv_identity {
244 struct {
245 __le32 os_type;
246 __le32 os_dist;
247 char os_dist_str[128];
248 __le32 kernel_ver;
249 char kernel_ver_str[32];
250 char driver_ver_str[32];
251 };
252 __le32 words[478];
253 };
254
255 /**
256 * union ionic_dev_identity - device identity information
257 * @version: Version of device identify
258 * @type: Identify type (0 for now)
259 * @nports: Number of ports provisioned
260 * @nlifs: Number of LIFs provisioned
261 * @nintrs: Number of interrupts provisioned
262 * @ndbpgs_per_lif: Number of doorbell pages per LIF
263 * @intr_coal_mult: Interrupt coalescing multiplication factor
264 * Scale user-supplied interrupt coalescing
265 * value in usecs to device units using:
266 * device units = usecs * mult / div
267 * @intr_coal_div: Interrupt coalescing division factor
268 * Scale user-supplied interrupt coalescing
269 * value in usecs to device units using:
270 * device units = usecs * mult / div
271 * @eq_count: Number of shared event queues
272 */
273 union ionic_dev_identity {
274 struct {
275 u8 version;
276 u8 type;
277 u8 rsvd[2];
278 u8 nports;
279 u8 rsvd2[3];
280 __le32 nlifs;
281 __le32 nintrs;
282 __le32 ndbpgs_per_lif;
283 __le32 intr_coal_mult;
284 __le32 intr_coal_div;
285 __le32 eq_count;
286 };
287 __le32 words[478];
288 };
289
290 enum ionic_lif_type {
291 IONIC_LIF_TYPE_CLASSIC = 0,
292 IONIC_LIF_TYPE_MACVLAN = 1,
293 IONIC_LIF_TYPE_NETQUEUE = 2,
294 };
295
296 /**
297 * struct ionic_lif_identify_cmd - LIF identify command
298 * @opcode: opcode
299 * @type: LIF type (enum ionic_lif_type)
300 * @ver: Version of identify returned by device
301 */
302 struct ionic_lif_identify_cmd {
303 u8 opcode;
304 u8 type;
305 u8 ver;
306 u8 rsvd[61];
307 };
308
309 /**
310 * struct ionic_lif_identify_comp - LIF identify command completion
311 * @status: Status of the command (enum ionic_status_code)
312 * @ver: Version of identify returned by device
313 */
314 struct ionic_lif_identify_comp {
315 u8 status;
316 u8 ver;
317 u8 rsvd2[14];
318 };
319
320 /**
321 * enum ionic_lif_capability - LIF capabilities
322 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet
323 * @IONIC_LIF_CAP_RDMA: LIF support RDMA
324 */
325 enum ionic_lif_capability {
326 IONIC_LIF_CAP_ETH = BIT(0),
327 IONIC_LIF_CAP_RDMA = BIT(1),
328 };
329
330 /**
331 * enum ionic_logical_qtype - Logical Queue Types
332 * @IONIC_QTYPE_ADMINQ: Administrative Queue
333 * @IONIC_QTYPE_NOTIFYQ: Notify Queue
334 * @IONIC_QTYPE_RXQ: Receive Queue
335 * @IONIC_QTYPE_TXQ: Transmit Queue
336 * @IONIC_QTYPE_EQ: Event Queue
337 * @IONIC_QTYPE_MAX: Max queue type supported
338 */
339 enum ionic_logical_qtype {
340 IONIC_QTYPE_ADMINQ = 0,
341 IONIC_QTYPE_NOTIFYQ = 1,
342 IONIC_QTYPE_RXQ = 2,
343 IONIC_QTYPE_TXQ = 3,
344 IONIC_QTYPE_EQ = 4,
345 IONIC_QTYPE_MAX = 16,
346 };
347
348 /**
349 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type
350 * @qtype: Hardware Queue Type
351 * @qid_count: Number of Queue IDs of the logical type
352 * @qid_base: Minimum Queue ID of the logical type
353 */
354 struct ionic_lif_logical_qtype {
355 u8 qtype;
356 u8 rsvd[3];
357 __le32 qid_count;
358 __le32 qid_base;
359 };
360
361 /**
362 * enum ionic_lif_state - LIF state
363 * @IONIC_LIF_DISABLE: LIF disabled
364 * @IONIC_LIF_ENABLE: LIF enabled
365 * @IONIC_LIF_QUIESCE: LIF Quiesced
366 */
367 enum ionic_lif_state {
368 IONIC_LIF_QUIESCE = 0,
369 IONIC_LIF_ENABLE = 1,
370 IONIC_LIF_DISABLE = 2,
371 };
372
373 /**
374 * union ionic_lif_config - LIF configuration
375 * @state: LIF state (enum ionic_lif_state)
376 * @name: LIF name
377 * @mtu: MTU
378 * @mac: Station MAC address
379 * @vlan: Default Vlan ID
380 * @features: Features (enum ionic_eth_hw_features)
381 * @queue_count: Queue counts per queue-type
382 */
383 union ionic_lif_config {
384 struct {
385 u8 state;
386 u8 rsvd[3];
387 char name[IONIC_IFNAMSIZ];
388 __le32 mtu;
389 u8 mac[6];
390 __le16 vlan;
391 __le64 features;
392 __le32 queue_count[IONIC_QTYPE_MAX];
393 } __packed;
394 __le32 words[64];
395 };
396
397 /**
398 * struct ionic_lif_identity - LIF identity information (type-specific)
399 *
400 * @capabilities: LIF capabilities
401 *
402 * @eth: Ethernet identify structure
403 * @version: Ethernet identify structure version
404 * @max_ucast_filters: Number of perfect unicast addresses supported
405 * @max_mcast_filters: Number of perfect multicast addresses supported
406 * @min_frame_size: Minimum size of frames to be sent
407 * @max_frame_size: Maximim size of frames to be sent
408 * @config: LIF config struct with features, mtu, mac, q counts
409 *
410 * @rdma: RDMA identify structure
411 * @version: RDMA version of opcodes and queue descriptors
412 * @qp_opcodes: Number of RDMA queue pair opcodes supported
413 * @admin_opcodes: Number of RDMA admin opcodes supported
414 * @npts_per_lif: Page table size per LIF
415 * @nmrs_per_lif: Number of memory regions per LIF
416 * @nahs_per_lif: Number of address handles per LIF
417 * @max_stride: Max work request stride
418 * @cl_stride: Cache line stride
419 * @pte_stride: Page table entry stride
420 * @rrq_stride: Remote RQ work request stride
421 * @rsq_stride: Remote SQ work request stride
422 * @dcqcn_profiles: Number of DCQCN profiles
423 * @aq_qtype: RDMA Admin Qtype
424 * @sq_qtype: RDMA Send Qtype
425 * @rq_qtype: RDMA Receive Qtype
426 * @cq_qtype: RDMA Completion Qtype
427 * @eq_qtype: RDMA Event Qtype
428 */
429 union ionic_lif_identity {
430 struct {
431 __le64 capabilities;
432
433 struct {
434 u8 version;
435 u8 rsvd[3];
436 __le32 max_ucast_filters;
437 __le32 max_mcast_filters;
438 __le16 rss_ind_tbl_sz;
439 __le32 min_frame_size;
440 __le32 max_frame_size;
441 u8 rsvd2[106];
442 union ionic_lif_config config;
443 } __packed eth;
444
445 struct {
446 u8 version;
447 u8 qp_opcodes;
448 u8 admin_opcodes;
449 u8 rsvd;
450 __le32 npts_per_lif;
451 __le32 nmrs_per_lif;
452 __le32 nahs_per_lif;
453 u8 max_stride;
454 u8 cl_stride;
455 u8 pte_stride;
456 u8 rrq_stride;
457 u8 rsq_stride;
458 u8 dcqcn_profiles;
459 u8 rsvd_dimensions[10];
460 struct ionic_lif_logical_qtype aq_qtype;
461 struct ionic_lif_logical_qtype sq_qtype;
462 struct ionic_lif_logical_qtype rq_qtype;
463 struct ionic_lif_logical_qtype cq_qtype;
464 struct ionic_lif_logical_qtype eq_qtype;
465 } __packed rdma;
466 } __packed;
467 __le32 words[478];
468 };
469
470 /**
471 * struct ionic_lif_init_cmd - LIF init command
472 * @opcode: Opcode
473 * @type: LIF type (enum ionic_lif_type)
474 * @index: LIF index
475 * @info_pa: Destination address for LIF info (struct ionic_lif_info)
476 */
477 struct ionic_lif_init_cmd {
478 u8 opcode;
479 u8 type;
480 __le16 index;
481 __le32 rsvd;
482 __le64 info_pa;
483 u8 rsvd2[48];
484 };
485
486 /**
487 * struct ionic_lif_init_comp - LIF init command completion
488 * @status: Status of the command (enum ionic_status_code)
489 * @hw_index: Hardware index of the initialized LIF
490 */
491 struct ionic_lif_init_comp {
492 u8 status;
493 u8 rsvd;
494 __le16 hw_index;
495 u8 rsvd2[12];
496 };
497
498 /**
499 * struct ionic_q_identify_cmd - queue identify command
500 * @opcode: opcode
501 * @lif_type: LIF type (enum ionic_lif_type)
502 * @type: Logical queue type (enum ionic_logical_qtype)
503 * @ver: Highest queue type version that the driver supports
504 */
505 struct ionic_q_identify_cmd {
506 u8 opcode;
507 u8 rsvd;
508 __le16 lif_type;
509 u8 type;
510 u8 ver;
511 u8 rsvd2[58];
512 };
513
514 /**
515 * struct ionic_q_identify_comp - queue identify command completion
516 * @status: Status of the command (enum ionic_status_code)
517 * @comp_index: Index in the descriptor ring for which this is the completion
518 * @ver: Queue type version that can be used with FW
519 */
520 struct ionic_q_identify_comp {
521 u8 status;
522 u8 rsvd;
523 __le16 comp_index;
524 u8 ver;
525 u8 rsvd2[11];
526 };
527
528 /**
529 * union ionic_q_identity - queue identity information
530 * @version: Queue type version that can be used with FW
531 * @supported: Bitfield of queue versions, first bit = ver 0
532 * @features: Queue features
533 * @desc_sz: Descriptor size
534 * @comp_sz: Completion descriptor size
535 * @sg_desc_sz: Scatter/Gather descriptor size
536 * @max_sg_elems: Maximum number of Scatter/Gather elements
537 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor
538 */
539 union ionic_q_identity {
540 struct {
541 u8 version;
542 u8 supported;
543 u8 rsvd[6];
544 #define IONIC_QIDENT_F_CQ 0x01 /* queue has completion ring */
545 #define IONIC_QIDENT_F_SG 0x02 /* queue has scatter/gather ring */
546 #define IONIC_QIDENT_F_EQ 0x04 /* queue can use event queue */
547 #define IONIC_QIDENT_F_CMB 0x08 /* queue is in cmb bar */
548 __le64 features;
549 __le16 desc_sz;
550 __le16 comp_sz;
551 __le16 sg_desc_sz;
552 __le16 max_sg_elems;
553 __le16 sg_desc_stride;
554 };
555 __le32 words[478];
556 };
557
558 /**
559 * struct ionic_q_init_cmd - Queue init command
560 * @opcode: opcode
561 * @type: Logical queue type
562 * @ver: Queue type version
563 * @lif_index: LIF index
564 * @index: (LIF, qtype) relative admin queue index
565 * @intr_index: Interrupt control register index, or Event queue index
566 * @pid: Process ID
567 * @flags:
568 * IRQ: Interrupt requested on completion
569 * ENA: Enable the queue. If ENA=0 the queue is initialized
570 * but remains disabled, to be later enabled with the
571 * Queue Enable command. If ENA=1, then queue is
572 * initialized and then enabled.
573 * SG: Enable Scatter-Gather on the queue.
574 * in number of descs. The actual ring size is
575 * (1 << ring_size). For example, to
576 * select a ring size of 64 descriptors write
577 * ring_size = 6. The minimum ring_size value is 2
578 * for a ring size of 4 descriptors. The maximum
579 * ring_size value is 16 for a ring size of 64k
580 * descriptors. Values of ring_size <2 and >16 are
581 * reserved.
582 * EQ: Enable the Event Queue
583 * @cos: Class of service for this queue
584 * @ring_size: Queue ring size, encoded as a log2(size)
585 * @ring_base: Queue ring base address
586 * @cq_ring_base: Completion queue ring base address
587 * @sg_ring_base: Scatter/Gather ring base address
588 */
589 struct ionic_q_init_cmd {
590 u8 opcode;
591 u8 rsvd;
592 __le16 lif_index;
593 u8 type;
594 u8 ver;
595 u8 rsvd1[2];
596 __le32 index;
597 __le16 pid;
598 __le16 intr_index;
599 __le16 flags;
600 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */
601 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */
602 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */
603 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */
604 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */
605 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */
606 u8 cos;
607 u8 ring_size;
608 __le64 ring_base;
609 __le64 cq_ring_base;
610 __le64 sg_ring_base;
611 u8 rsvd2[20];
612 } __packed;
613
614 /**
615 * struct ionic_q_init_comp - Queue init command completion
616 * @status: Status of the command (enum ionic_status_code)
617 * @comp_index: Index in the descriptor ring for which this is the completion
618 * @hw_index: Hardware Queue ID
619 * @hw_type: Hardware Queue type
620 * @color: Color
621 */
622 struct ionic_q_init_comp {
623 u8 status;
624 u8 rsvd;
625 __le16 comp_index;
626 __le32 hw_index;
627 u8 hw_type;
628 u8 rsvd2[6];
629 u8 color;
630 };
631
632 /* the device's internal addressing uses up to 52 bits */
633 #define IONIC_ADDR_LEN 52
634 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
635
636 enum ionic_txq_desc_opcode {
637 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0,
638 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1,
639 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2,
640 IONIC_TXQ_DESC_OPCODE_TSO = 3,
641 };
642
643 /**
644 * struct ionic_txq_desc - Ethernet Tx queue descriptor format
645 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*:
646 *
647 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE:
648 * Non-offload send. No segmentation,
649 * fragmentation or checksum calc/insertion is
650 * performed by device; packet is prepared
651 * to send by software stack and requires
652 * no further manipulation from device.
653 *
654 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL:
655 * Offload 16-bit L4 checksum
656 * calculation/insertion. The device will
657 * calculate the L4 checksum value and
658 * insert the result in the packet's L4
659 * header checksum field. The L4 checksum
660 * is calculated starting at @csum_start bytes
661 * into the packet to the end of the packet.
662 * The checksum insertion position is given
663 * in @csum_offset, which is the offset from
664 * @csum_start to the checksum field in the L4
665 * header. This feature is only applicable to
666 * protocols such as TCP, UDP and ICMP where a
667 * standard (i.e. the 'IP-style' checksum)
668 * one's complement 16-bit checksum is used,
669 * using an IP pseudo-header to seed the
670 * calculation. Software will preload the L4
671 * checksum field with the IP pseudo-header
672 * checksum.
673 *
674 * For tunnel encapsulation, @csum_start and
675 * @csum_offset refer to the inner L4
676 * header. Supported tunnels encapsulations
677 * are: IPIP, GRE, and UDP. If the @encap
678 * is clear, no further processing by the
679 * device is required; software will
680 * calculate the outer header checksums. If
681 * the @encap is set, the device will
682 * offload the outer header checksums using
683 * LCO (local checksum offload) (see
684 * Documentation/networking/checksum-offloads.rst
685 * for more info).
686 *
687 * IONIC_TXQ_DESC_OPCODE_CSUM_HW:
688 * Offload 16-bit checksum computation to hardware.
689 * If @csum_l3 is set then the packet's L3 checksum is
690 * updated. Similarly, if @csum_l4 is set the the L4
691 * checksum is updated. If @encap is set then encap header
692 * checksums are also updated.
693 *
694 * IONIC_TXQ_DESC_OPCODE_TSO:
695 * Device preforms TCP segmentation offload
696 * (TSO). @hdr_len is the number of bytes
697 * to the end of TCP header (the offset to
698 * the TCP payload). @mss is the desired
699 * MSS, the TCP payload length for each
700 * segment. The device will calculate/
701 * insert IP (IPv4 only) and TCP checksums
702 * for each segment. In the first data
703 * buffer containing the header template,
704 * the driver will set IPv4 checksum to 0
705 * and preload TCP checksum with the IP
706 * pseudo header calculated with IP length = 0.
707 *
708 * Supported tunnel encapsulations are IPIP,
709 * layer-3 GRE, and UDP. @hdr_len includes
710 * both outer and inner headers. The driver
711 * will set IPv4 checksum to zero and
712 * preload TCP checksum with IP pseudo
713 * header on the inner header.
714 *
715 * TCP ECN offload is supported. The device
716 * will set CWR flag in the first segment if
717 * CWR is set in the template header, and
718 * clear CWR in remaining segments.
719 * @flags:
720 * vlan:
721 * Insert an L2 VLAN header using @vlan_tci
722 * encap:
723 * Calculate encap header checksum
724 * csum_l3:
725 * Compute L3 header checksum
726 * csum_l4:
727 * Compute L4 header checksum
728 * tso_sot:
729 * TSO start
730 * tso_eot:
731 * TSO end
732 * @num_sg_elems: Number of scatter-gather elements in SG
733 * descriptor
734 * @addr: First data buffer's DMA address
735 * (Subsequent data buffers are on txq_sg_desc)
736 * @len: First data buffer's length, in bytes
737 * @vlan_tci: VLAN tag to insert in the packet (if requested
738 * by @V-bit). Includes .1p and .1q tags
739 * @hdr_len: Length of packet headers, including
740 * encapsulating outer header, if applicable
741 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and
742 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for
743 * all other modes. For
744 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length
745 * of headers up to inner-most L4 header. For
746 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to
747 * inner-most L4 payload, so inclusive of
748 * inner-most L4 header.
749 * @mss: Desired MSS value for TSO; only applicable for
750 * IONIC_TXQ_DESC_OPCODE_TSO
751 * @csum_start: Offset from packet to first byte checked in L4 checksum
752 * @csum_offset: Offset from csum_start to L4 checksum field
753 */
754 struct ionic_txq_desc {
755 __le64 cmd;
756 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf
757 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4
758 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf
759 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0
760 #define IONIC_TXQ_DESC_NSGE_MASK 0xf
761 #define IONIC_TXQ_DESC_NSGE_SHIFT 8
762 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1)
763 #define IONIC_TXQ_DESC_ADDR_SHIFT 12
764
765 /* common flags */
766 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1
767 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2
768
769 /* flags for csum_hw opcode */
770 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4
771 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8
772
773 /* flags for tso opcode */
774 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4
775 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8
776
777 __le16 len;
778 union {
779 __le16 vlan_tci;
780 __le16 hword0;
781 };
782 union {
783 __le16 csum_start;
784 __le16 hdr_len;
785 __le16 hword1;
786 };
787 union {
788 __le16 csum_offset;
789 __le16 mss;
790 __le16 hword2;
791 };
792 };
793
encode_txq_desc_cmd(u8 opcode,u8 flags,u8 nsge,u64 addr)794 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags,
795 u8 nsge, u64 addr)
796 {
797 u64 cmd;
798
799 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT;
800 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT;
801 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT;
802 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT;
803
804 return cmd;
805 };
806
decode_txq_desc_cmd(u64 cmd,u8 * opcode,u8 * flags,u8 * nsge,u64 * addr)807 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags,
808 u8 *nsge, u64 *addr)
809 {
810 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK;
811 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK;
812 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK;
813 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK;
814 };
815
816 /**
817 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element
818 * @addr: DMA address of SG element data buffer
819 * @len: Length of SG element data buffer, in bytes
820 */
821 struct ionic_txq_sg_elem {
822 __le64 addr;
823 __le16 len;
824 __le16 rsvd[3];
825 };
826
827 /**
828 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list
829 * @elems: Scatter-gather elements
830 */
831 struct ionic_txq_sg_desc {
832 #define IONIC_TX_MAX_SG_ELEMS 8
833 #define IONIC_TX_SG_DESC_STRIDE 8
834 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS];
835 };
836
837 struct ionic_txq_sg_desc_v1 {
838 #define IONIC_TX_MAX_SG_ELEMS_V1 15
839 #define IONIC_TX_SG_DESC_STRIDE_V1 16
840 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1];
841 };
842
843 /**
844 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor
845 * @status: Status of the command (enum ionic_status_code)
846 * @comp_index: Index in the descriptor ring for which this is the completion
847 * @color: Color bit
848 */
849 struct ionic_txq_comp {
850 u8 status;
851 u8 rsvd;
852 __le16 comp_index;
853 u8 rsvd2[11];
854 u8 color;
855 };
856
857 enum ionic_rxq_desc_opcode {
858 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0,
859 IONIC_RXQ_DESC_OPCODE_SG = 1,
860 };
861
862 /**
863 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format
864 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*:
865 *
866 * IONIC_RXQ_DESC_OPCODE_SIMPLE:
867 * Receive full packet into data buffer
868 * starting at @addr. Results of
869 * receive, including actual bytes received,
870 * are recorded in Rx completion descriptor.
871 *
872 * @len: Data buffer's length, in bytes
873 * @addr: Data buffer's DMA address
874 */
875 struct ionic_rxq_desc {
876 u8 opcode;
877 u8 rsvd[5];
878 __le16 len;
879 __le64 addr;
880 };
881
882 /**
883 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element
884 * @addr: DMA address of SG element data buffer
885 * @len: Length of SG element data buffer, in bytes
886 */
887 struct ionic_rxq_sg_elem {
888 __le64 addr;
889 __le16 len;
890 __le16 rsvd[3];
891 };
892
893 /**
894 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list
895 * @elems: Scatter-gather elements
896 */
897 struct ionic_rxq_sg_desc {
898 #define IONIC_RX_MAX_SG_ELEMS 8
899 #define IONIC_RX_SG_DESC_STRIDE 8
900 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE];
901 };
902
903 /**
904 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor
905 * @status: Status of the command (enum ionic_status_code)
906 * @num_sg_elems: Number of SG elements used by this descriptor
907 * @comp_index: Index in the descriptor ring for which this is the completion
908 * @rss_hash: 32-bit RSS hash
909 * @csum: 16-bit sum of the packet's L2 payload
910 * If the packet's L2 payload is odd length, an extra
911 * zero-value byte is included in the @csum calculation but
912 * not included in @len.
913 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is
914 * set. Includes .1p and .1q tags.
915 * @len: Received packet length, in bytes. Excludes FCS.
916 * @csum_calc L2 payload checksum is computed or not
917 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*:
918 *
919 * IONIC_RXQ_COMP_CSUM_F_TCP_OK:
920 * The TCP checksum calculated by the device
921 * matched the checksum in the receive packet's
922 * TCP header.
923 *
924 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD:
925 * The TCP checksum calculated by the device did
926 * not match the checksum in the receive packet's
927 * TCP header.
928 *
929 * IONIC_RXQ_COMP_CSUM_F_UDP_OK:
930 * The UDP checksum calculated by the device
931 * matched the checksum in the receive packet's
932 * UDP header
933 *
934 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD:
935 * The UDP checksum calculated by the device did
936 * not match the checksum in the receive packet's
937 * UDP header.
938 *
939 * IONIC_RXQ_COMP_CSUM_F_IP_OK:
940 * The IPv4 checksum calculated by the device
941 * matched the checksum in the receive packet's
942 * first IPv4 header. If the receive packet
943 * contains both a tunnel IPv4 header and a
944 * transport IPv4 header, the device validates the
945 * checksum for the both IPv4 headers.
946 *
947 * IONIC_RXQ_COMP_CSUM_F_IP_BAD:
948 * The IPv4 checksum calculated by the device did
949 * not match the checksum in the receive packet's
950 * first IPv4 header. If the receive packet
951 * contains both a tunnel IPv4 header and a
952 * transport IPv4 header, the device validates the
953 * checksum for both IP headers.
954 *
955 * IONIC_RXQ_COMP_CSUM_F_VLAN:
956 * The VLAN header was stripped and placed in @vlan_tci.
957 *
958 * IONIC_RXQ_COMP_CSUM_F_CALC:
959 * The checksum was calculated by the device.
960 *
961 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK
962 */
963 struct ionic_rxq_comp {
964 u8 status;
965 u8 num_sg_elems;
966 __le16 comp_index;
967 __le32 rss_hash;
968 __le16 csum;
969 __le16 vlan_tci;
970 __le16 len;
971 u8 csum_flags;
972 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01
973 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02
974 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04
975 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08
976 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10
977 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20
978 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40
979 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80
980 u8 pkt_type_color;
981 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f
982 };
983
984 enum ionic_pkt_type {
985 IONIC_PKT_TYPE_NON_IP = 0x000,
986 IONIC_PKT_TYPE_IPV4 = 0x001,
987 IONIC_PKT_TYPE_IPV4_TCP = 0x003,
988 IONIC_PKT_TYPE_IPV4_UDP = 0x005,
989 IONIC_PKT_TYPE_IPV6 = 0x008,
990 IONIC_PKT_TYPE_IPV6_TCP = 0x018,
991 IONIC_PKT_TYPE_IPV6_UDP = 0x028,
992 /* below types are only used if encap offloads are enabled on lif */
993 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40,
994 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41,
995 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43,
996 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45,
997 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48,
998 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58,
999 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68,
1000 };
1001
1002 enum ionic_eth_hw_features {
1003 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0),
1004 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1),
1005 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2),
1006 IONIC_ETH_HW_RX_HASH = BIT(3),
1007 IONIC_ETH_HW_RX_CSUM = BIT(4),
1008 IONIC_ETH_HW_TX_SG = BIT(5),
1009 IONIC_ETH_HW_RX_SG = BIT(6),
1010 IONIC_ETH_HW_TX_CSUM = BIT(7),
1011 IONIC_ETH_HW_TSO = BIT(8),
1012 IONIC_ETH_HW_TSO_IPV6 = BIT(9),
1013 IONIC_ETH_HW_TSO_ECN = BIT(10),
1014 IONIC_ETH_HW_TSO_GRE = BIT(11),
1015 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12),
1016 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13),
1017 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14),
1018 IONIC_ETH_HW_TSO_UDP = BIT(15),
1019 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16),
1020 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17),
1021 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18),
1022 IONIC_ETH_HW_TSO_GENEVE = BIT(19)
1023 };
1024
1025 /**
1026 * struct ionic_q_control_cmd - Queue control command
1027 * @opcode: opcode
1028 * @type: Queue type
1029 * @lif_index: LIF index
1030 * @index: Queue index
1031 * @oper: Operation (enum ionic_q_control_oper)
1032 */
1033 struct ionic_q_control_cmd {
1034 u8 opcode;
1035 u8 type;
1036 __le16 lif_index;
1037 __le32 index;
1038 u8 oper;
1039 u8 rsvd[55];
1040 };
1041
1042 typedef struct ionic_admin_comp ionic_q_control_comp;
1043
1044 enum q_control_oper {
1045 IONIC_Q_DISABLE = 0,
1046 IONIC_Q_ENABLE = 1,
1047 IONIC_Q_HANG_RESET = 2,
1048 };
1049
1050 /**
1051 * enum ionic_phy_type - Physical connection type
1052 * @IONIC_PHY_TYPE_NONE: No PHY installed
1053 * @IONIC_PHY_TYPE_COPPER: Copper PHY
1054 * @IONIC_PHY_TYPE_FIBER: Fiber PHY
1055 */
1056 enum ionic_phy_type {
1057 IONIC_PHY_TYPE_NONE = 0,
1058 IONIC_PHY_TYPE_COPPER = 1,
1059 IONIC_PHY_TYPE_FIBER = 2,
1060 };
1061
1062 /**
1063 * enum ionic_xcvr_state - Transceiver status
1064 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed
1065 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted
1066 * @IONIC_XCVR_STATE_PENDING: Transceiver pending
1067 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read
1068 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error
1069 */
1070 enum ionic_xcvr_state {
1071 IONIC_XCVR_STATE_REMOVED = 0,
1072 IONIC_XCVR_STATE_INSERTED = 1,
1073 IONIC_XCVR_STATE_PENDING = 2,
1074 IONIC_XCVR_STATE_SPROM_READ = 3,
1075 IONIC_XCVR_STATE_SPROM_READ_ERR = 4,
1076 };
1077
1078 /**
1079 * enum ionic_xcvr_pid - Supported link modes
1080 */
1081 enum ionic_xcvr_pid {
1082 IONIC_XCVR_PID_UNKNOWN = 0,
1083
1084 /* CU */
1085 IONIC_XCVR_PID_QSFP_100G_CR4 = 1,
1086 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2,
1087 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3,
1088 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4,
1089 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5,
1090
1091 /* Fiber */
1092 IONIC_XCVR_PID_QSFP_100G_AOC = 50,
1093 IONIC_XCVR_PID_QSFP_100G_ACC = 51,
1094 IONIC_XCVR_PID_QSFP_100G_SR4 = 52,
1095 IONIC_XCVR_PID_QSFP_100G_LR4 = 53,
1096 IONIC_XCVR_PID_QSFP_100G_ER4 = 54,
1097 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55,
1098 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56,
1099 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57,
1100 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58,
1101 IONIC_XCVR_PID_SFP_25GBASE_SR = 59,
1102 IONIC_XCVR_PID_SFP_25GBASE_LR = 60,
1103 IONIC_XCVR_PID_SFP_25GBASE_ER = 61,
1104 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62,
1105 IONIC_XCVR_PID_SFP_10GBASE_SR = 63,
1106 IONIC_XCVR_PID_SFP_10GBASE_LR = 64,
1107 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65,
1108 IONIC_XCVR_PID_SFP_10GBASE_ER = 66,
1109 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67,
1110 IONIC_XCVR_PID_SFP_10GBASE_CU = 68,
1111 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69,
1112 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70,
1113 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71,
1114 };
1115
1116 /**
1117 * enum ionic_port_type - Port types
1118 * @IONIC_PORT_TYPE_NONE: Port type not configured
1119 * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband)
1120 * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band)
1121 */
1122 enum ionic_port_type {
1123 IONIC_PORT_TYPE_NONE = 0,
1124 IONIC_PORT_TYPE_ETH = 1,
1125 IONIC_PORT_TYPE_MGMT = 2,
1126 };
1127
1128 /**
1129 * enum ionic_port_admin_state - Port config state
1130 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured
1131 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled
1132 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled
1133 */
1134 enum ionic_port_admin_state {
1135 IONIC_PORT_ADMIN_STATE_NONE = 0,
1136 IONIC_PORT_ADMIN_STATE_DOWN = 1,
1137 IONIC_PORT_ADMIN_STATE_UP = 2,
1138 };
1139
1140 /**
1141 * enum ionic_port_oper_status - Port operational status
1142 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled
1143 * @IONIC_PORT_OPER_STATUS_UP: Port link status up
1144 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down
1145 */
1146 enum ionic_port_oper_status {
1147 IONIC_PORT_OPER_STATUS_NONE = 0,
1148 IONIC_PORT_OPER_STATUS_UP = 1,
1149 IONIC_PORT_OPER_STATUS_DOWN = 2,
1150 };
1151
1152 /**
1153 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes
1154 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled
1155 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC
1156 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC
1157 */
1158 enum ionic_port_fec_type {
1159 IONIC_PORT_FEC_TYPE_NONE = 0,
1160 IONIC_PORT_FEC_TYPE_FC = 1,
1161 IONIC_PORT_FEC_TYPE_RS = 2,
1162 };
1163
1164 /**
1165 * enum ionic_port_pause_type - Ethernet pause (flow control) modes
1166 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause
1167 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause
1168 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control
1169 */
1170 enum ionic_port_pause_type {
1171 IONIC_PORT_PAUSE_TYPE_NONE = 0,
1172 IONIC_PORT_PAUSE_TYPE_LINK = 1,
1173 IONIC_PORT_PAUSE_TYPE_PFC = 2,
1174 };
1175
1176 /**
1177 * enum ionic_port_loopback_mode - Loopback modes
1178 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback
1179 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback
1180 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback
1181 */
1182 enum ionic_port_loopback_mode {
1183 IONIC_PORT_LOOPBACK_MODE_NONE = 0,
1184 IONIC_PORT_LOOPBACK_MODE_MAC = 1,
1185 IONIC_PORT_LOOPBACK_MODE_PHY = 2,
1186 };
1187
1188 /**
1189 * struct ionic_xcvr_status - Transceiver Status information
1190 * @state: Transceiver status (enum ionic_xcvr_state)
1191 * @phy: Physical connection type (enum ionic_phy_type)
1192 * @pid: Transceiver link mode (enum ionic_xcvr_pid)
1193 * @sprom: Transceiver sprom contents
1194 */
1195 struct ionic_xcvr_status {
1196 u8 state;
1197 u8 phy;
1198 __le16 pid;
1199 u8 sprom[256];
1200 };
1201
1202 /**
1203 * union ionic_port_config - Port configuration
1204 * @speed: port speed (in Mbps)
1205 * @mtu: mtu
1206 * @state: port admin state (enum ionic_port_admin_state)
1207 * @an_enable: autoneg enable
1208 * @fec_type: fec type (enum ionic_port_fec_type)
1209 * @pause_type: pause type (enum ionic_port_pause_type)
1210 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode)
1211 */
1212 union ionic_port_config {
1213 struct {
1214 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */
1215 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */
1216 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */
1217 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */
1218 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */
1219 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */
1220 __le32 speed;
1221 __le32 mtu;
1222 u8 state;
1223 u8 an_enable;
1224 u8 fec_type;
1225 #define IONIC_PAUSE_TYPE_MASK 0x0f
1226 #define IONIC_PAUSE_FLAGS_MASK 0xf0
1227 #define IONIC_PAUSE_F_TX 0x10
1228 #define IONIC_PAUSE_F_RX 0x20
1229 u8 pause_type;
1230 u8 loopback_mode;
1231 };
1232 __le32 words[64];
1233 };
1234
1235 /**
1236 * struct ionic_port_status - Port Status information
1237 * @status: link status (enum ionic_port_oper_status)
1238 * @id: port id
1239 * @speed: link speed (in Mbps)
1240 * @link_down_count: number of times link went from from up to down
1241 * @fec_type: fec type (enum ionic_port_fec_type)
1242 * @xcvr: tranceiver status
1243 */
1244 struct ionic_port_status {
1245 __le32 id;
1246 __le32 speed;
1247 u8 status;
1248 __le16 link_down_count;
1249 u8 fec_type;
1250 u8 rsvd[48];
1251 struct ionic_xcvr_status xcvr;
1252 } __packed;
1253
1254 /**
1255 * struct ionic_port_identify_cmd - Port identify command
1256 * @opcode: opcode
1257 * @index: port index
1258 * @ver: Highest version of identify supported by driver
1259 */
1260 struct ionic_port_identify_cmd {
1261 u8 opcode;
1262 u8 index;
1263 u8 ver;
1264 u8 rsvd[61];
1265 };
1266
1267 /**
1268 * struct ionic_port_identify_comp - Port identify command completion
1269 * @status: Status of the command (enum ionic_status_code)
1270 * @ver: Version of identify returned by device
1271 */
1272 struct ionic_port_identify_comp {
1273 u8 status;
1274 u8 ver;
1275 u8 rsvd[14];
1276 };
1277
1278 /**
1279 * struct ionic_port_init_cmd - Port initialization command
1280 * @opcode: opcode
1281 * @index: port index
1282 * @info_pa: destination address for port info (struct ionic_port_info)
1283 */
1284 struct ionic_port_init_cmd {
1285 u8 opcode;
1286 u8 index;
1287 u8 rsvd[6];
1288 __le64 info_pa;
1289 u8 rsvd2[48];
1290 };
1291
1292 /**
1293 * struct ionic_port_init_comp - Port initialization command completion
1294 * @status: Status of the command (enum ionic_status_code)
1295 */
1296 struct ionic_port_init_comp {
1297 u8 status;
1298 u8 rsvd[15];
1299 };
1300
1301 /**
1302 * struct ionic_port_reset_cmd - Port reset command
1303 * @opcode: opcode
1304 * @index: port index
1305 */
1306 struct ionic_port_reset_cmd {
1307 u8 opcode;
1308 u8 index;
1309 u8 rsvd[62];
1310 };
1311
1312 /**
1313 * struct ionic_port_reset_comp - Port reset command completion
1314 * @status: Status of the command (enum ionic_status_code)
1315 */
1316 struct ionic_port_reset_comp {
1317 u8 status;
1318 u8 rsvd[15];
1319 };
1320
1321 /**
1322 * enum ionic_stats_ctl_cmd - List of commands for stats control
1323 * @IONIC_STATS_CTL_RESET: Reset statistics
1324 */
1325 enum ionic_stats_ctl_cmd {
1326 IONIC_STATS_CTL_RESET = 0,
1327 };
1328
1329 /**
1330 * enum ionic_port_attr - List of device attributes
1331 * @IONIC_PORT_ATTR_STATE: Port state attribute
1332 * @IONIC_PORT_ATTR_SPEED: Port speed attribute
1333 * @IONIC_PORT_ATTR_MTU: Port MTU attribute
1334 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotation attribute
1335 * @IONIC_PORT_ATTR_FEC: Port FEC attribute
1336 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute
1337 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute
1338 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute
1339 */
1340 enum ionic_port_attr {
1341 IONIC_PORT_ATTR_STATE = 0,
1342 IONIC_PORT_ATTR_SPEED = 1,
1343 IONIC_PORT_ATTR_MTU = 2,
1344 IONIC_PORT_ATTR_AUTONEG = 3,
1345 IONIC_PORT_ATTR_FEC = 4,
1346 IONIC_PORT_ATTR_PAUSE = 5,
1347 IONIC_PORT_ATTR_LOOPBACK = 6,
1348 IONIC_PORT_ATTR_STATS_CTRL = 7,
1349 };
1350
1351 /**
1352 * struct ionic_port_setattr_cmd - Set port attributes on the NIC
1353 * @opcode: Opcode
1354 * @index: Port index
1355 * @attr: Attribute type (enum ionic_port_attr)
1356 * @state: Port state
1357 * @speed: Port speed
1358 * @mtu: Port MTU
1359 * @an_enable: Port autonegotiation setting
1360 * @fec_type: Port FEC type setting
1361 * @pause_type: Port pause type setting
1362 * @loopback_mode: Port loopback mode
1363 * @stats_ctl: Port stats setting
1364 */
1365 struct ionic_port_setattr_cmd {
1366 u8 opcode;
1367 u8 index;
1368 u8 attr;
1369 u8 rsvd;
1370 union {
1371 u8 state;
1372 __le32 speed;
1373 __le32 mtu;
1374 u8 an_enable;
1375 u8 fec_type;
1376 u8 pause_type;
1377 u8 loopback_mode;
1378 u8 stats_ctl;
1379 u8 rsvd2[60];
1380 };
1381 };
1382
1383 /**
1384 * struct ionic_port_setattr_comp - Port set attr command completion
1385 * @status: Status of the command (enum ionic_status_code)
1386 * @color: Color bit
1387 */
1388 struct ionic_port_setattr_comp {
1389 u8 status;
1390 u8 rsvd[14];
1391 u8 color;
1392 };
1393
1394 /**
1395 * struct ionic_port_getattr_cmd - Get port attributes from the NIC
1396 * @opcode: Opcode
1397 * @index: port index
1398 * @attr: Attribute type (enum ionic_port_attr)
1399 */
1400 struct ionic_port_getattr_cmd {
1401 u8 opcode;
1402 u8 index;
1403 u8 attr;
1404 u8 rsvd[61];
1405 };
1406
1407 /**
1408 * struct ionic_port_getattr_comp - Port get attr command completion
1409 * @status: Status of the command (enum ionic_status_code)
1410 * @state: Port state
1411 * @speed: Port speed
1412 * @mtu: Port MTU
1413 * @an_enable: Port autonegotiation setting
1414 * @fec_type: Port FEC type setting
1415 * @pause_type: Port pause type setting
1416 * @loopback_mode: Port loopback mode
1417 * @color: Color bit
1418 */
1419 struct ionic_port_getattr_comp {
1420 u8 status;
1421 u8 rsvd[3];
1422 union {
1423 u8 state;
1424 __le32 speed;
1425 __le32 mtu;
1426 u8 an_enable;
1427 u8 fec_type;
1428 u8 pause_type;
1429 u8 loopback_mode;
1430 u8 rsvd2[11];
1431 } __packed;
1432 u8 color;
1433 };
1434
1435 /**
1436 * struct ionic_lif_status - LIF status register
1437 * @eid: most recent NotifyQ event id
1438 * @port_num: port the LIF is connected to
1439 * @link_status: port status (enum ionic_port_oper_status)
1440 * @link_speed: speed of link in Mbps
1441 * @link_down_count: number of times link went from up to down
1442 */
1443 struct ionic_lif_status {
1444 __le64 eid;
1445 u8 port_num;
1446 u8 rsvd;
1447 __le16 link_status;
1448 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */
1449 __le16 link_down_count;
1450 u8 rsvd2[46];
1451 };
1452
1453 /**
1454 * struct ionic_lif_reset_cmd - LIF reset command
1455 * @opcode: opcode
1456 * @index: LIF index
1457 */
1458 struct ionic_lif_reset_cmd {
1459 u8 opcode;
1460 u8 rsvd;
1461 __le16 index;
1462 __le32 rsvd2[15];
1463 };
1464
1465 typedef struct ionic_admin_comp ionic_lif_reset_comp;
1466
1467 enum ionic_dev_state {
1468 IONIC_DEV_DISABLE = 0,
1469 IONIC_DEV_ENABLE = 1,
1470 IONIC_DEV_HANG_RESET = 2,
1471 };
1472
1473 /**
1474 * enum ionic_dev_attr - List of device attributes
1475 * @IONIC_DEV_ATTR_STATE: Device state attribute
1476 * @IONIC_DEV_ATTR_NAME: Device name attribute
1477 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes
1478 */
1479 enum ionic_dev_attr {
1480 IONIC_DEV_ATTR_STATE = 0,
1481 IONIC_DEV_ATTR_NAME = 1,
1482 IONIC_DEV_ATTR_FEATURES = 2,
1483 };
1484
1485 /**
1486 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC
1487 * @opcode: Opcode
1488 * @attr: Attribute type (enum ionic_dev_attr)
1489 * @state: Device state (enum ionic_dev_state)
1490 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated
1491 * @features: Device features
1492 */
1493 struct ionic_dev_setattr_cmd {
1494 u8 opcode;
1495 u8 attr;
1496 __le16 rsvd;
1497 union {
1498 u8 state;
1499 char name[IONIC_IFNAMSIZ];
1500 __le64 features;
1501 u8 rsvd2[60];
1502 } __packed;
1503 };
1504
1505 /**
1506 * struct ionic_dev_setattr_comp - Device set attr command completion
1507 * @status: Status of the command (enum ionic_status_code)
1508 * @features: Device features
1509 * @color: Color bit
1510 */
1511 struct ionic_dev_setattr_comp {
1512 u8 status;
1513 u8 rsvd[3];
1514 union {
1515 __le64 features;
1516 u8 rsvd2[11];
1517 } __packed;
1518 u8 color;
1519 };
1520
1521 /**
1522 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC
1523 * @opcode: opcode
1524 * @attr: Attribute type (enum ionic_dev_attr)
1525 */
1526 struct ionic_dev_getattr_cmd {
1527 u8 opcode;
1528 u8 attr;
1529 u8 rsvd[62];
1530 };
1531
1532 /**
1533 * struct ionic_dev_setattr_comp - Device set attr command completion
1534 * @status: Status of the command (enum ionic_status_code)
1535 * @features: Device features
1536 * @color: Color bit
1537 */
1538 struct ionic_dev_getattr_comp {
1539 u8 status;
1540 u8 rsvd[3];
1541 union {
1542 __le64 features;
1543 u8 rsvd2[11];
1544 } __packed;
1545 u8 color;
1546 };
1547
1548 /**
1549 * RSS parameters
1550 */
1551 #define IONIC_RSS_HASH_KEY_SIZE 40
1552
1553 enum ionic_rss_hash_types {
1554 IONIC_RSS_TYPE_IPV4 = BIT(0),
1555 IONIC_RSS_TYPE_IPV4_TCP = BIT(1),
1556 IONIC_RSS_TYPE_IPV4_UDP = BIT(2),
1557 IONIC_RSS_TYPE_IPV6 = BIT(3),
1558 IONIC_RSS_TYPE_IPV6_TCP = BIT(4),
1559 IONIC_RSS_TYPE_IPV6_UDP = BIT(5),
1560 };
1561
1562 /**
1563 * enum ionic_lif_attr - List of LIF attributes
1564 * @IONIC_LIF_ATTR_STATE: LIF state attribute
1565 * @IONIC_LIF_ATTR_NAME: LIF name attribute
1566 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute
1567 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute
1568 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute
1569 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute
1570 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute
1571 */
1572 enum ionic_lif_attr {
1573 IONIC_LIF_ATTR_STATE = 0,
1574 IONIC_LIF_ATTR_NAME = 1,
1575 IONIC_LIF_ATTR_MTU = 2,
1576 IONIC_LIF_ATTR_MAC = 3,
1577 IONIC_LIF_ATTR_FEATURES = 4,
1578 IONIC_LIF_ATTR_RSS = 5,
1579 IONIC_LIF_ATTR_STATS_CTRL = 6,
1580 };
1581
1582 /**
1583 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC
1584 * @opcode: Opcode
1585 * @attr: Attribute type (enum ionic_lif_attr)
1586 * @index: LIF index
1587 * @state: LIF state (enum ionic_lif_state)
1588 * @name: The netdev name string, 0 terminated
1589 * @mtu: Mtu
1590 * @mac: Station mac
1591 * @features: Features (enum ionic_eth_hw_features)
1592 * @rss: RSS properties
1593 * @types: The hash types to enable (see rss_hash_types)
1594 * @key: The hash secret key
1595 * @addr: Address for the indirection table shared memory
1596 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd)
1597 */
1598 struct ionic_lif_setattr_cmd {
1599 u8 opcode;
1600 u8 attr;
1601 __le16 index;
1602 union {
1603 u8 state;
1604 char name[IONIC_IFNAMSIZ];
1605 __le32 mtu;
1606 u8 mac[6];
1607 __le64 features;
1608 struct {
1609 __le16 types;
1610 u8 key[IONIC_RSS_HASH_KEY_SIZE];
1611 u8 rsvd[6];
1612 __le64 addr;
1613 } rss;
1614 u8 stats_ctl;
1615 u8 rsvd[60];
1616 } __packed;
1617 };
1618
1619 /**
1620 * struct ionic_lif_setattr_comp - LIF set attr command completion
1621 * @status: Status of the command (enum ionic_status_code)
1622 * @comp_index: Index in the descriptor ring for which this is the completion
1623 * @features: features (enum ionic_eth_hw_features)
1624 * @color: Color bit
1625 */
1626 struct ionic_lif_setattr_comp {
1627 u8 status;
1628 u8 rsvd;
1629 __le16 comp_index;
1630 union {
1631 __le64 features;
1632 u8 rsvd2[11];
1633 } __packed;
1634 u8 color;
1635 };
1636
1637 /**
1638 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC
1639 * @opcode: Opcode
1640 * @attr: Attribute type (enum ionic_lif_attr)
1641 * @index: LIF index
1642 */
1643 struct ionic_lif_getattr_cmd {
1644 u8 opcode;
1645 u8 attr;
1646 __le16 index;
1647 u8 rsvd[60];
1648 };
1649
1650 /**
1651 * struct ionic_lif_getattr_comp - LIF get attr command completion
1652 * @status: Status of the command (enum ionic_status_code)
1653 * @comp_index: Index in the descriptor ring for which this is the completion
1654 * @state: LIF state (enum ionic_lif_state)
1655 * @name: The netdev name string, 0 terminated
1656 * @mtu: Mtu
1657 * @mac: Station mac
1658 * @features: Features (enum ionic_eth_hw_features)
1659 * @color: Color bit
1660 */
1661 struct ionic_lif_getattr_comp {
1662 u8 status;
1663 u8 rsvd;
1664 __le16 comp_index;
1665 union {
1666 u8 state;
1667 __le32 mtu;
1668 u8 mac[6];
1669 __le64 features;
1670 u8 rsvd2[11];
1671 } __packed;
1672 u8 color;
1673 };
1674
1675 enum ionic_rx_mode {
1676 IONIC_RX_MODE_F_UNICAST = BIT(0),
1677 IONIC_RX_MODE_F_MULTICAST = BIT(1),
1678 IONIC_RX_MODE_F_BROADCAST = BIT(2),
1679 IONIC_RX_MODE_F_PROMISC = BIT(3),
1680 IONIC_RX_MODE_F_ALLMULTI = BIT(4),
1681 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5),
1682 };
1683
1684 /**
1685 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command
1686 * @opcode: opcode
1687 * @lif_index: LIF index
1688 * @rx_mode: Rx mode flags:
1689 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets
1690 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets
1691 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets
1692 * IONIC_RX_MODE_F_PROMISC: Accept any packets
1693 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets
1694 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets
1695 */
1696 struct ionic_rx_mode_set_cmd {
1697 u8 opcode;
1698 u8 rsvd;
1699 __le16 lif_index;
1700 __le16 rx_mode;
1701 __le16 rsvd2[29];
1702 };
1703
1704 typedef struct ionic_admin_comp ionic_rx_mode_set_comp;
1705
1706 enum ionic_rx_filter_match_type {
1707 IONIC_RX_FILTER_MATCH_VLAN = 0,
1708 IONIC_RX_FILTER_MATCH_MAC,
1709 IONIC_RX_FILTER_MATCH_MAC_VLAN,
1710 };
1711
1712 /**
1713 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command
1714 * @opcode: opcode
1715 * @qtype: Queue type
1716 * @lif_index: LIF index
1717 * @qid: Queue ID
1718 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx)
1719 * @vlan: VLAN filter
1720 * @vlan: VLAN ID
1721 * @mac: MAC filter
1722 * @addr: MAC address (network-byte order)
1723 * @mac_vlan: MACVLAN filter
1724 * @vlan: VLAN ID
1725 * @addr: MAC address (network-byte order)
1726 */
1727 struct ionic_rx_filter_add_cmd {
1728 u8 opcode;
1729 u8 qtype;
1730 __le16 lif_index;
1731 __le32 qid;
1732 __le16 match;
1733 union {
1734 struct {
1735 __le16 vlan;
1736 } vlan;
1737 struct {
1738 u8 addr[6];
1739 } mac;
1740 struct {
1741 __le16 vlan;
1742 u8 addr[6];
1743 } mac_vlan;
1744 u8 rsvd[54];
1745 };
1746 };
1747
1748 /**
1749 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion
1750 * @status: Status of the command (enum ionic_status_code)
1751 * @comp_index: Index in the descriptor ring for which this is the completion
1752 * @filter_id: Filter ID
1753 * @color: Color bit
1754 */
1755 struct ionic_rx_filter_add_comp {
1756 u8 status;
1757 u8 rsvd;
1758 __le16 comp_index;
1759 __le32 filter_id;
1760 u8 rsvd2[7];
1761 u8 color;
1762 };
1763
1764 /**
1765 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command
1766 * @opcode: opcode
1767 * @lif_index: LIF index
1768 * @filter_id: Filter ID
1769 */
1770 struct ionic_rx_filter_del_cmd {
1771 u8 opcode;
1772 u8 rsvd;
1773 __le16 lif_index;
1774 __le32 filter_id;
1775 u8 rsvd2[56];
1776 };
1777
1778 typedef struct ionic_admin_comp ionic_rx_filter_del_comp;
1779
1780 enum ionic_vf_attr {
1781 IONIC_VF_ATTR_SPOOFCHK = 1,
1782 IONIC_VF_ATTR_TRUST = 2,
1783 IONIC_VF_ATTR_MAC = 3,
1784 IONIC_VF_ATTR_LINKSTATE = 4,
1785 IONIC_VF_ATTR_VLAN = 5,
1786 IONIC_VF_ATTR_RATE = 6,
1787 IONIC_VF_ATTR_STATSADDR = 7,
1788 };
1789
1790 /**
1791 * enum ionic_vf_link_status - Virtual Function link status
1792 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink
1793 * @IONIC_VF_LINK_STATUS_UP: Link always up
1794 * @IONIC_VF_LINK_STATUS_DOWN: Link always down
1795 */
1796 enum ionic_vf_link_status {
1797 IONIC_VF_LINK_STATUS_AUTO = 0,
1798 IONIC_VF_LINK_STATUS_UP = 1,
1799 IONIC_VF_LINK_STATUS_DOWN = 2,
1800 };
1801
1802 /**
1803 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC
1804 * @opcode: Opcode
1805 * @attr: Attribute type (enum ionic_vf_attr)
1806 * @vf_index: VF index
1807 * @macaddr: mac address
1808 * @vlanid: vlan ID
1809 * @maxrate: max Tx rate in Mbps
1810 * @spoofchk: enable address spoof checking
1811 * @trust: enable VF trust
1812 * @linkstate: set link up or down
1813 * @stats_pa: set DMA address for VF stats
1814 */
1815 struct ionic_vf_setattr_cmd {
1816 u8 opcode;
1817 u8 attr;
1818 __le16 vf_index;
1819 union {
1820 u8 macaddr[6];
1821 __le16 vlanid;
1822 __le32 maxrate;
1823 u8 spoofchk;
1824 u8 trust;
1825 u8 linkstate;
1826 __le64 stats_pa;
1827 u8 pad[60];
1828 } __packed;
1829 };
1830
1831 struct ionic_vf_setattr_comp {
1832 u8 status;
1833 u8 attr;
1834 __le16 vf_index;
1835 __le16 comp_index;
1836 u8 rsvd[9];
1837 u8 color;
1838 };
1839
1840 /**
1841 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC
1842 * @opcode: Opcode
1843 * @attr: Attribute type (enum ionic_vf_attr)
1844 * @vf_index: VF index
1845 */
1846 struct ionic_vf_getattr_cmd {
1847 u8 opcode;
1848 u8 attr;
1849 __le16 vf_index;
1850 u8 rsvd[60];
1851 };
1852
1853 struct ionic_vf_getattr_comp {
1854 u8 status;
1855 u8 attr;
1856 __le16 vf_index;
1857 union {
1858 u8 macaddr[6];
1859 __le16 vlanid;
1860 __le32 maxrate;
1861 u8 spoofchk;
1862 u8 trust;
1863 u8 linkstate;
1864 __le64 stats_pa;
1865 u8 pad[11];
1866 } __packed;
1867 u8 color;
1868 };
1869
1870 /**
1871 * struct ionic_qos_identify_cmd - QoS identify command
1872 * @opcode: opcode
1873 * @ver: Highest version of identify supported by driver
1874 *
1875 */
1876 struct ionic_qos_identify_cmd {
1877 u8 opcode;
1878 u8 ver;
1879 u8 rsvd[62];
1880 };
1881
1882 /**
1883 * struct ionic_qos_identify_comp - QoS identify command completion
1884 * @status: Status of the command (enum ionic_status_code)
1885 * @ver: Version of identify returned by device
1886 */
1887 struct ionic_qos_identify_comp {
1888 u8 status;
1889 u8 ver;
1890 u8 rsvd[14];
1891 };
1892
1893 #define IONIC_QOS_TC_MAX 8
1894 #define IONIC_QOS_ALL_TC 0xFF
1895 /* Capri max supported, should be renamed. */
1896 #define IONIC_QOS_CLASS_MAX 7
1897 #define IONIC_QOS_PCP_MAX 8
1898 #define IONIC_QOS_CLASS_NAME_SZ 32
1899 #define IONIC_QOS_DSCP_MAX 64
1900 #define IONIC_QOS_ALL_PCP 0xFF
1901 #define IONIC_DSCP_BLOCK_SIZE 8
1902
1903 /**
1904 * enum ionic_qos_class
1905 */
1906 enum ionic_qos_class {
1907 IONIC_QOS_CLASS_DEFAULT = 0,
1908 IONIC_QOS_CLASS_USER_DEFINED_1 = 1,
1909 IONIC_QOS_CLASS_USER_DEFINED_2 = 2,
1910 IONIC_QOS_CLASS_USER_DEFINED_3 = 3,
1911 IONIC_QOS_CLASS_USER_DEFINED_4 = 4,
1912 IONIC_QOS_CLASS_USER_DEFINED_5 = 5,
1913 IONIC_QOS_CLASS_USER_DEFINED_6 = 6,
1914 };
1915
1916 /**
1917 * enum ionic_qos_class_type - Traffic classification criteria
1918 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS
1919 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP
1920 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP
1921 */
1922 enum ionic_qos_class_type {
1923 IONIC_QOS_CLASS_TYPE_NONE = 0,
1924 IONIC_QOS_CLASS_TYPE_PCP = 1,
1925 IONIC_QOS_CLASS_TYPE_DSCP = 2,
1926 };
1927
1928 /**
1929 * enum ionic_qos_sched_type - QoS class scheduling type
1930 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority
1931 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin
1932 */
1933 enum ionic_qos_sched_type {
1934 IONIC_QOS_SCHED_TYPE_STRICT = 0,
1935 IONIC_QOS_SCHED_TYPE_DWRR = 1,
1936 };
1937
1938 /**
1939 * union ionic_qos_config - QoS configuration structure
1940 * @flags: Configuration flags
1941 * IONIC_QOS_CONFIG_F_ENABLE enable
1942 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop
1943 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite
1944 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite
1945 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update
1946 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type)
1947 * @class_type: QoS class type (enum ionic_qos_class_type)
1948 * @pause_type: QoS pause type (enum ionic_qos_pause_type)
1949 * @name: QoS class name
1950 * @mtu: MTU of the class
1951 * @pfc_cos: Priority-Flow Control class of service
1952 * @dwrr_weight: QoS class scheduling weight
1953 * @strict_rlmt: Rate limit for strict priority scheduling
1954 * @rw_dot1q_pcp: Rewrite dot1q pcp to this value (valid iff F_RW_DOT1Q_PCP)
1955 * @rw_ip_dscp: Rewrite ip dscp to this value (valid iff F_RW_IP_DSCP)
1956 * @dot1q_pcp: Dot1q pcp value
1957 * @ndscp: Number of valid dscp values in the ip_dscp field
1958 * @ip_dscp: IP dscp values
1959 */
1960 union ionic_qos_config {
1961 struct {
1962 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0)
1963 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1)
1964 /* Used to rewrite PCP or DSCP value. */
1965 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2)
1966 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3)
1967 /* Non-disruptive TC update */
1968 #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4)
1969 u8 flags;
1970 u8 sched_type;
1971 u8 class_type;
1972 u8 pause_type;
1973 char name[IONIC_QOS_CLASS_NAME_SZ];
1974 __le32 mtu;
1975 /* flow control */
1976 u8 pfc_cos;
1977 /* scheduler */
1978 union {
1979 u8 dwrr_weight;
1980 __le64 strict_rlmt;
1981 };
1982 /* marking */
1983 /* Used to rewrite PCP or DSCP value. */
1984 union {
1985 u8 rw_dot1q_pcp;
1986 u8 rw_ip_dscp;
1987 };
1988 /* classification */
1989 union {
1990 u8 dot1q_pcp;
1991 struct {
1992 u8 ndscp;
1993 u8 ip_dscp[IONIC_QOS_DSCP_MAX];
1994 };
1995 };
1996 };
1997 __le32 words[64];
1998 };
1999
2000 /**
2001 * union ionic_qos_identity - QoS identity structure
2002 * @version: Version of the identify structure
2003 * @type: QoS system type
2004 * @nclasses: Number of usable QoS classes
2005 * @config: Current configuration of classes
2006 */
2007 union ionic_qos_identity {
2008 struct {
2009 u8 version;
2010 u8 type;
2011 u8 rsvd[62];
2012 union ionic_qos_config config[IONIC_QOS_CLASS_MAX];
2013 };
2014 __le32 words[478];
2015 };
2016
2017 /**
2018 * struct ionic_qos_init_cmd - QoS config init command
2019 * @opcode: Opcode
2020 * @group: QoS class id
2021 * @info_pa: destination address for qos info
2022 */
2023 struct ionic_qos_init_cmd {
2024 u8 opcode;
2025 u8 group;
2026 u8 rsvd[6];
2027 __le64 info_pa;
2028 u8 rsvd1[48];
2029 };
2030
2031 typedef struct ionic_admin_comp ionic_qos_init_comp;
2032
2033 /**
2034 * struct ionic_qos_reset_cmd - QoS config reset command
2035 * @opcode: Opcode
2036 * @group: QoS class id
2037 */
2038 struct ionic_qos_reset_cmd {
2039 u8 opcode;
2040 u8 group;
2041 u8 rsvd[62];
2042 };
2043
2044 /**
2045 * struct ionic_qos_clear_port_stats_cmd - Qos config reset command
2046 * @opcode: Opcode
2047 */
2048 struct ionic_qos_clear_stats_cmd {
2049 u8 opcode;
2050 u8 group_bitmap;
2051 u8 rsvd[62];
2052 };
2053
2054 typedef struct ionic_admin_comp ionic_qos_reset_comp;
2055
2056 /**
2057 * struct ionic_fw_download_cmd - Firmware download command
2058 * @opcode: opcode
2059 * @addr: dma address of the firmware buffer
2060 * @offset: offset of the firmware buffer within the full image
2061 * @length: number of valid bytes in the firmware buffer
2062 */
2063 struct ionic_fw_download_cmd {
2064 u8 opcode;
2065 u8 rsvd[3];
2066 __le32 offset;
2067 __le64 addr;
2068 __le32 length;
2069 };
2070
2071 typedef struct ionic_admin_comp ionic_fw_download_comp;
2072
2073 /**
2074 * enum ionic_fw_control_oper - FW control operations
2075 * @IONIC_FW_RESET: Reset firmware
2076 * @IONIC_FW_INSTALL: Install firmware
2077 * @IONIC_FW_ACTIVATE: Activate firmware
2078 * @IONIC_FW_INSTALL_ASYNC: Install firmware asynchronously
2079 * @IONIC_FW_INSTALL_STATUS: Firmware installation status
2080 * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously
2081 * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status
2082 */
2083 enum ionic_fw_control_oper {
2084 IONIC_FW_RESET = 0,
2085 IONIC_FW_INSTALL = 1,
2086 IONIC_FW_ACTIVATE = 2,
2087 IONIC_FW_INSTALL_ASYNC = 3,
2088 IONIC_FW_INSTALL_STATUS = 4,
2089 IONIC_FW_ACTIVATE_ASYNC = 5,
2090 IONIC_FW_ACTIVATE_STATUS = 6,
2091 IONIC_FW_UPDATE_CLEANUP = 7,
2092 };
2093
2094 /**
2095 * struct ionic_fw_control_cmd - Firmware control command
2096 * @opcode: opcode
2097 * @oper: firmware control operation (enum ionic_fw_control_oper)
2098 * @slot: slot to activate
2099 */
2100 struct ionic_fw_control_cmd {
2101 u8 opcode;
2102 u8 rsvd[3];
2103 u8 oper;
2104 u8 slot;
2105 u8 rsvd1[58];
2106 };
2107
2108 /**
2109 * struct ionic_fw_control_comp - Firmware control copletion
2110 * @status: Status of the command (enum ionic_status_code)
2111 * @comp_index: Index in the descriptor ring for which this is the completion
2112 * @slot: Slot where the firmware was installed
2113 * @color: Color bit
2114 */
2115 struct ionic_fw_control_comp {
2116 u8 status;
2117 u8 rsvd;
2118 __le16 comp_index;
2119 u8 slot;
2120 u8 rsvd1[10];
2121 u8 color;
2122 };
2123
2124 /******************************************************************
2125 ******************* RDMA Commands ********************************
2126 ******************************************************************/
2127
2128 /**
2129 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd
2130 * @opcode: opcode
2131 * @lif_index: LIF index
2132 *
2133 * There is no RDMA specific dev command completion struct. Completion uses
2134 * the common struct ionic_admin_comp. Only the status is indicated.
2135 * Nonzero status means the LIF does not support RDMA.
2136 **/
2137 struct ionic_rdma_reset_cmd {
2138 u8 opcode;
2139 u8 rsvd;
2140 __le16 lif_index;
2141 u8 rsvd2[60];
2142 };
2143
2144 /**
2145 * struct ionic_rdma_queue_cmd - Create RDMA Queue command
2146 * @opcode: opcode, 52, 53
2147 * @lif_index: LIF index
2148 * @qid_ver: (qid | (RDMA version << 24))
2149 * @cid: intr, eq_id, or cq_id
2150 * @dbid: doorbell page id
2151 * @depth_log2: log base two of queue depth
2152 * @stride_log2: log base two of queue stride
2153 * @dma_addr: address of the queue memory
2154 *
2155 * The same command struct is used to create an RDMA event queue, completion
2156 * queue, or RDMA admin queue. The cid is an interrupt number for an event
2157 * queue, an event queue id for a completion queue, or a completion queue id
2158 * for an RDMA admin queue.
2159 *
2160 * The queue created via a dev command must be contiguous in dma space.
2161 *
2162 * The dev commands are intended only to be used during driver initialization,
2163 * to create queues supporting the RDMA admin queue. Other queues, and other
2164 * types of RDMA resources like memory regions, will be created and registered
2165 * via the RDMA admin queue, and will support a more complete interface
2166 * providing scatter gather lists for larger, scattered queue buffers and
2167 * memory registration.
2168 *
2169 * There is no RDMA specific dev command completion struct. Completion uses
2170 * the common struct ionic_admin_comp. Only the status is indicated.
2171 **/
2172 struct ionic_rdma_queue_cmd {
2173 u8 opcode;
2174 u8 rsvd;
2175 __le16 lif_index;
2176 __le32 qid_ver;
2177 __le32 cid;
2178 __le16 dbid;
2179 u8 depth_log2;
2180 u8 stride_log2;
2181 __le64 dma_addr;
2182 u8 rsvd2[40];
2183 };
2184
2185 /******************************************************************
2186 ******************* Notify Events ********************************
2187 ******************************************************************/
2188
2189 /**
2190 * struct ionic_notifyq_event - Generic event reporting structure
2191 * @eid: event number
2192 * @ecode: event code
2193 * @data: unspecified data about the event
2194 *
2195 * This is the generic event report struct from which the other
2196 * actual events will be formed.
2197 */
2198 struct ionic_notifyq_event {
2199 __le64 eid;
2200 __le16 ecode;
2201 u8 data[54];
2202 };
2203
2204 /**
2205 * struct ionic_link_change_event - Link change event notification
2206 * @eid: event number
2207 * @ecode: event code = IONIC_EVENT_LINK_CHANGE
2208 * @link_status: link up/down, with error bits (enum ionic_port_status)
2209 * @link_speed: speed of the network link
2210 *
2211 * Sent when the network link state changes between UP and DOWN
2212 */
2213 struct ionic_link_change_event {
2214 __le64 eid;
2215 __le16 ecode;
2216 __le16 link_status;
2217 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */
2218 u8 rsvd[48];
2219 };
2220
2221 /**
2222 * struct ionic_reset_event - Reset event notification
2223 * @eid: event number
2224 * @ecode: event code = IONIC_EVENT_RESET
2225 * @reset_code: reset type
2226 * @state: 0=pending, 1=complete, 2=error
2227 *
2228 * Sent when the NIC or some subsystem is going to be or
2229 * has been reset.
2230 */
2231 struct ionic_reset_event {
2232 __le64 eid;
2233 __le16 ecode;
2234 u8 reset_code;
2235 u8 state;
2236 u8 rsvd[52];
2237 };
2238
2239 /**
2240 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health
2241 * @eid: event number
2242 * @ecode: event code = IONIC_EVENT_HEARTBEAT
2243 */
2244 struct ionic_heartbeat_event {
2245 __le64 eid;
2246 __le16 ecode;
2247 u8 rsvd[54];
2248 };
2249
2250 /**
2251 * struct ionic_log_event - Sent to notify the driver of an internal error
2252 * @eid: event number
2253 * @ecode: event code = IONIC_EVENT_LOG
2254 * @data: log data
2255 */
2256 struct ionic_log_event {
2257 __le64 eid;
2258 __le16 ecode;
2259 u8 data[54];
2260 };
2261
2262 /**
2263 * struct ionic_xcvr_event - Transceiver change event
2264 * @eid: event number
2265 * @ecode: event code = IONIC_EVENT_XCVR
2266 */
2267 struct ionic_xcvr_event {
2268 __le64 eid;
2269 __le16 ecode;
2270 u8 rsvd[54];
2271 };
2272
2273 /**
2274 * struct ionic_port_stats - Port statistics structure
2275 */
2276 struct ionic_port_stats {
2277 __le64 frames_rx_ok;
2278 __le64 frames_rx_all;
2279 __le64 frames_rx_bad_fcs;
2280 __le64 frames_rx_bad_all;
2281 __le64 octets_rx_ok;
2282 __le64 octets_rx_all;
2283 __le64 frames_rx_unicast;
2284 __le64 frames_rx_multicast;
2285 __le64 frames_rx_broadcast;
2286 __le64 frames_rx_pause;
2287 __le64 frames_rx_bad_length;
2288 __le64 frames_rx_undersized;
2289 __le64 frames_rx_oversized;
2290 __le64 frames_rx_fragments;
2291 __le64 frames_rx_jabber;
2292 __le64 frames_rx_pripause;
2293 __le64 frames_rx_stomped_crc;
2294 __le64 frames_rx_too_long;
2295 __le64 frames_rx_vlan_good;
2296 __le64 frames_rx_dropped;
2297 __le64 frames_rx_less_than_64b;
2298 __le64 frames_rx_64b;
2299 __le64 frames_rx_65b_127b;
2300 __le64 frames_rx_128b_255b;
2301 __le64 frames_rx_256b_511b;
2302 __le64 frames_rx_512b_1023b;
2303 __le64 frames_rx_1024b_1518b;
2304 __le64 frames_rx_1519b_2047b;
2305 __le64 frames_rx_2048b_4095b;
2306 __le64 frames_rx_4096b_8191b;
2307 __le64 frames_rx_8192b_9215b;
2308 __le64 frames_rx_other;
2309 __le64 frames_tx_ok;
2310 __le64 frames_tx_all;
2311 __le64 frames_tx_bad;
2312 __le64 octets_tx_ok;
2313 __le64 octets_tx_total;
2314 __le64 frames_tx_unicast;
2315 __le64 frames_tx_multicast;
2316 __le64 frames_tx_broadcast;
2317 __le64 frames_tx_pause;
2318 __le64 frames_tx_pripause;
2319 __le64 frames_tx_vlan;
2320 __le64 frames_tx_less_than_64b;
2321 __le64 frames_tx_64b;
2322 __le64 frames_tx_65b_127b;
2323 __le64 frames_tx_128b_255b;
2324 __le64 frames_tx_256b_511b;
2325 __le64 frames_tx_512b_1023b;
2326 __le64 frames_tx_1024b_1518b;
2327 __le64 frames_tx_1519b_2047b;
2328 __le64 frames_tx_2048b_4095b;
2329 __le64 frames_tx_4096b_8191b;
2330 __le64 frames_tx_8192b_9215b;
2331 __le64 frames_tx_other;
2332 __le64 frames_tx_pri_0;
2333 __le64 frames_tx_pri_1;
2334 __le64 frames_tx_pri_2;
2335 __le64 frames_tx_pri_3;
2336 __le64 frames_tx_pri_4;
2337 __le64 frames_tx_pri_5;
2338 __le64 frames_tx_pri_6;
2339 __le64 frames_tx_pri_7;
2340 __le64 frames_rx_pri_0;
2341 __le64 frames_rx_pri_1;
2342 __le64 frames_rx_pri_2;
2343 __le64 frames_rx_pri_3;
2344 __le64 frames_rx_pri_4;
2345 __le64 frames_rx_pri_5;
2346 __le64 frames_rx_pri_6;
2347 __le64 frames_rx_pri_7;
2348 __le64 tx_pripause_0_1us_count;
2349 __le64 tx_pripause_1_1us_count;
2350 __le64 tx_pripause_2_1us_count;
2351 __le64 tx_pripause_3_1us_count;
2352 __le64 tx_pripause_4_1us_count;
2353 __le64 tx_pripause_5_1us_count;
2354 __le64 tx_pripause_6_1us_count;
2355 __le64 tx_pripause_7_1us_count;
2356 __le64 rx_pripause_0_1us_count;
2357 __le64 rx_pripause_1_1us_count;
2358 __le64 rx_pripause_2_1us_count;
2359 __le64 rx_pripause_3_1us_count;
2360 __le64 rx_pripause_4_1us_count;
2361 __le64 rx_pripause_5_1us_count;
2362 __le64 rx_pripause_6_1us_count;
2363 __le64 rx_pripause_7_1us_count;
2364 __le64 rx_pause_1us_count;
2365 __le64 frames_tx_truncated;
2366 };
2367
2368 struct ionic_mgmt_port_stats {
2369 __le64 frames_rx_ok;
2370 __le64 frames_rx_all;
2371 __le64 frames_rx_bad_fcs;
2372 __le64 frames_rx_bad_all;
2373 __le64 octets_rx_ok;
2374 __le64 octets_rx_all;
2375 __le64 frames_rx_unicast;
2376 __le64 frames_rx_multicast;
2377 __le64 frames_rx_broadcast;
2378 __le64 frames_rx_pause;
2379 __le64 frames_rx_bad_length;
2380 __le64 frames_rx_undersized;
2381 __le64 frames_rx_oversized;
2382 __le64 frames_rx_fragments;
2383 __le64 frames_rx_jabber;
2384 __le64 frames_rx_64b;
2385 __le64 frames_rx_65b_127b;
2386 __le64 frames_rx_128b_255b;
2387 __le64 frames_rx_256b_511b;
2388 __le64 frames_rx_512b_1023b;
2389 __le64 frames_rx_1024b_1518b;
2390 __le64 frames_rx_gt_1518b;
2391 __le64 frames_rx_fifo_full;
2392 __le64 frames_tx_ok;
2393 __le64 frames_tx_all;
2394 __le64 frames_tx_bad;
2395 __le64 octets_tx_ok;
2396 __le64 octets_tx_total;
2397 __le64 frames_tx_unicast;
2398 __le64 frames_tx_multicast;
2399 __le64 frames_tx_broadcast;
2400 __le64 frames_tx_pause;
2401 };
2402
2403 enum ionic_pb_buffer_drop_stats {
2404 IONIC_BUFFER_INTRINSIC_DROP = 0,
2405 IONIC_BUFFER_DISCARDED,
2406 IONIC_BUFFER_ADMITTED,
2407 IONIC_BUFFER_OUT_OF_CELLS_DROP,
2408 IONIC_BUFFER_OUT_OF_CELLS_DROP_2,
2409 IONIC_BUFFER_OUT_OF_CREDIT_DROP,
2410 IONIC_BUFFER_TRUNCATION_DROP,
2411 IONIC_BUFFER_PORT_DISABLED_DROP,
2412 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP,
2413 IONIC_BUFFER_SPAN_TAIL_DROP,
2414 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP,
2415 IONIC_BUFFER_ENQUEUE_ERROR_DROP,
2416 IONIC_BUFFER_INVALID_PORT_DROP,
2417 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP,
2418 IONIC_BUFFER_DROP_MAX,
2419 };
2420
2421 enum ionic_oflow_drop_stats {
2422 IONIC_OFLOW_OCCUPANCY_DROP,
2423 IONIC_OFLOW_EMERGENCY_STOP_DROP,
2424 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP,
2425 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP,
2426 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP,
2427 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP,
2428 IONIC_OFLOW_DROP_MAX,
2429 };
2430
2431 /**
2432 * struct port_pb_stats - packet buffers system stats
2433 * uses ionic_pb_buffer_drop_stats for drop_counts[]
2434 */
2435 struct ionic_port_pb_stats {
2436 __le64 sop_count_in;
2437 __le64 eop_count_in;
2438 __le64 sop_count_out;
2439 __le64 eop_count_out;
2440 __le64 drop_counts[IONIC_BUFFER_DROP_MAX];
2441 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2442 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX];
2443 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX];
2444 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX];
2445 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX];
2446 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX];
2447 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX];
2448 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX];
2449 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX];
2450 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX];
2451 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX];
2452 };
2453
2454 /**
2455 * struct ionic_port_identity - port identity structure
2456 * @version: identity structure version
2457 * @type: type of port (enum ionic_port_type)
2458 * @num_lanes: number of lanes for the port
2459 * @autoneg: autoneg supported
2460 * @min_frame_size: minimum frame size supported
2461 * @max_frame_size: maximum frame size supported
2462 * @fec_type: supported fec types
2463 * @pause_type: supported pause types
2464 * @loopback_mode: supported loopback mode
2465 * @speeds: supported speeds
2466 * @config: current port configuration
2467 */
2468 union ionic_port_identity {
2469 struct {
2470 u8 version;
2471 u8 type;
2472 u8 num_lanes;
2473 u8 autoneg;
2474 __le32 min_frame_size;
2475 __le32 max_frame_size;
2476 u8 fec_type[4];
2477 u8 pause_type[2];
2478 u8 loopback_mode[2];
2479 __le32 speeds[16];
2480 u8 rsvd2[44];
2481 union ionic_port_config config;
2482 };
2483 __le32 words[478];
2484 };
2485
2486 /**
2487 * struct ionic_port_info - port info structure
2488 * @config: Port configuration data
2489 * @status: Port status data
2490 * @stats: Port statistics data
2491 * @mgmt_stats: Port management statistics data
2492 * @port_pb_drop_stats: uplink pb drop stats
2493 */
2494 struct ionic_port_info {
2495 union ionic_port_config config;
2496 struct ionic_port_status status;
2497 union {
2498 struct ionic_port_stats stats;
2499 struct ionic_mgmt_port_stats mgmt_stats;
2500 };
2501 /* room for pb_stats to start at 2k offset */
2502 u8 rsvd[760];
2503 struct ionic_port_pb_stats pb_stats;
2504 };
2505
2506 /**
2507 * struct ionic_lif_stats - LIF statistics structure
2508 */
2509 struct ionic_lif_stats {
2510 /* RX */
2511 __le64 rx_ucast_bytes;
2512 __le64 rx_ucast_packets;
2513 __le64 rx_mcast_bytes;
2514 __le64 rx_mcast_packets;
2515 __le64 rx_bcast_bytes;
2516 __le64 rx_bcast_packets;
2517 __le64 rsvd0;
2518 __le64 rsvd1;
2519 /* RX drops */
2520 __le64 rx_ucast_drop_bytes;
2521 __le64 rx_ucast_drop_packets;
2522 __le64 rx_mcast_drop_bytes;
2523 __le64 rx_mcast_drop_packets;
2524 __le64 rx_bcast_drop_bytes;
2525 __le64 rx_bcast_drop_packets;
2526 __le64 rx_dma_error;
2527 __le64 rsvd2;
2528 /* TX */
2529 __le64 tx_ucast_bytes;
2530 __le64 tx_ucast_packets;
2531 __le64 tx_mcast_bytes;
2532 __le64 tx_mcast_packets;
2533 __le64 tx_bcast_bytes;
2534 __le64 tx_bcast_packets;
2535 __le64 rsvd3;
2536 __le64 rsvd4;
2537 /* TX drops */
2538 __le64 tx_ucast_drop_bytes;
2539 __le64 tx_ucast_drop_packets;
2540 __le64 tx_mcast_drop_bytes;
2541 __le64 tx_mcast_drop_packets;
2542 __le64 tx_bcast_drop_bytes;
2543 __le64 tx_bcast_drop_packets;
2544 __le64 tx_dma_error;
2545 __le64 rsvd5;
2546 /* Rx Queue/Ring drops */
2547 __le64 rx_queue_disabled;
2548 __le64 rx_queue_empty;
2549 __le64 rx_queue_error;
2550 __le64 rx_desc_fetch_error;
2551 __le64 rx_desc_data_error;
2552 __le64 rsvd6;
2553 __le64 rsvd7;
2554 __le64 rsvd8;
2555 /* Tx Queue/Ring drops */
2556 __le64 tx_queue_disabled;
2557 __le64 tx_queue_error;
2558 __le64 tx_desc_fetch_error;
2559 __le64 tx_desc_data_error;
2560 __le64 tx_queue_empty;
2561 __le64 rsvd10;
2562 __le64 rsvd11;
2563 __le64 rsvd12;
2564
2565 /* RDMA/ROCE TX */
2566 __le64 tx_rdma_ucast_bytes;
2567 __le64 tx_rdma_ucast_packets;
2568 __le64 tx_rdma_mcast_bytes;
2569 __le64 tx_rdma_mcast_packets;
2570 __le64 tx_rdma_cnp_packets;
2571 __le64 rsvd13;
2572 __le64 rsvd14;
2573 __le64 rsvd15;
2574
2575 /* RDMA/ROCE RX */
2576 __le64 rx_rdma_ucast_bytes;
2577 __le64 rx_rdma_ucast_packets;
2578 __le64 rx_rdma_mcast_bytes;
2579 __le64 rx_rdma_mcast_packets;
2580 __le64 rx_rdma_cnp_packets;
2581 __le64 rx_rdma_ecn_packets;
2582 __le64 rsvd16;
2583 __le64 rsvd17;
2584
2585 __le64 rsvd18;
2586 __le64 rsvd19;
2587 __le64 rsvd20;
2588 __le64 rsvd21;
2589 __le64 rsvd22;
2590 __le64 rsvd23;
2591 __le64 rsvd24;
2592 __le64 rsvd25;
2593
2594 __le64 rsvd26;
2595 __le64 rsvd27;
2596 __le64 rsvd28;
2597 __le64 rsvd29;
2598 __le64 rsvd30;
2599 __le64 rsvd31;
2600 __le64 rsvd32;
2601 __le64 rsvd33;
2602
2603 __le64 rsvd34;
2604 __le64 rsvd35;
2605 __le64 rsvd36;
2606 __le64 rsvd37;
2607 __le64 rsvd38;
2608 __le64 rsvd39;
2609 __le64 rsvd40;
2610 __le64 rsvd41;
2611
2612 __le64 rsvd42;
2613 __le64 rsvd43;
2614 __le64 rsvd44;
2615 __le64 rsvd45;
2616 __le64 rsvd46;
2617 __le64 rsvd47;
2618 __le64 rsvd48;
2619 __le64 rsvd49;
2620
2621 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */
2622 __le64 rdma_req_rx_pkt_seq_err;
2623 __le64 rdma_req_rx_rnr_retry_err;
2624 __le64 rdma_req_rx_remote_access_err;
2625 __le64 rdma_req_rx_remote_inv_req_err;
2626 __le64 rdma_req_rx_remote_oper_err;
2627 __le64 rdma_req_rx_implied_nak_seq_err;
2628 __le64 rdma_req_rx_cqe_err;
2629 __le64 rdma_req_rx_cqe_flush_err;
2630
2631 __le64 rdma_req_rx_dup_responses;
2632 __le64 rdma_req_rx_invalid_packets;
2633 __le64 rdma_req_tx_local_access_err;
2634 __le64 rdma_req_tx_local_oper_err;
2635 __le64 rdma_req_tx_memory_mgmt_err;
2636 __le64 rsvd52;
2637 __le64 rsvd53;
2638 __le64 rsvd54;
2639
2640 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */
2641 __le64 rdma_resp_rx_dup_requests;
2642 __le64 rdma_resp_rx_out_of_buffer;
2643 __le64 rdma_resp_rx_out_of_seq_pkts;
2644 __le64 rdma_resp_rx_cqe_err;
2645 __le64 rdma_resp_rx_cqe_flush_err;
2646 __le64 rdma_resp_rx_local_len_err;
2647 __le64 rdma_resp_rx_inv_request_err;
2648 __le64 rdma_resp_rx_local_qp_oper_err;
2649
2650 __le64 rdma_resp_rx_out_of_atomic_resource;
2651 __le64 rdma_resp_tx_pkt_seq_err;
2652 __le64 rdma_resp_tx_remote_inv_req_err;
2653 __le64 rdma_resp_tx_remote_access_err;
2654 __le64 rdma_resp_tx_remote_oper_err;
2655 __le64 rdma_resp_tx_rnr_retry_err;
2656 __le64 rsvd57;
2657 __le64 rsvd58;
2658 };
2659
2660 /**
2661 * struct ionic_lif_info - LIF info structure
2662 * @config: LIF configuration structure
2663 * @status: LIF status structure
2664 * @stats: LIF statistics structure
2665 */
2666 struct ionic_lif_info {
2667 union ionic_lif_config config;
2668 struct ionic_lif_status status;
2669 struct ionic_lif_stats stats;
2670 };
2671
2672 union ionic_dev_cmd {
2673 u32 words[16];
2674 struct ionic_admin_cmd cmd;
2675 struct ionic_nop_cmd nop;
2676
2677 struct ionic_dev_identify_cmd identify;
2678 struct ionic_dev_init_cmd init;
2679 struct ionic_dev_reset_cmd reset;
2680 struct ionic_dev_getattr_cmd getattr;
2681 struct ionic_dev_setattr_cmd setattr;
2682
2683 struct ionic_port_identify_cmd port_identify;
2684 struct ionic_port_init_cmd port_init;
2685 struct ionic_port_reset_cmd port_reset;
2686 struct ionic_port_getattr_cmd port_getattr;
2687 struct ionic_port_setattr_cmd port_setattr;
2688
2689 struct ionic_vf_setattr_cmd vf_setattr;
2690 struct ionic_vf_getattr_cmd vf_getattr;
2691
2692 struct ionic_lif_identify_cmd lif_identify;
2693 struct ionic_lif_init_cmd lif_init;
2694 struct ionic_lif_reset_cmd lif_reset;
2695
2696 struct ionic_qos_identify_cmd qos_identify;
2697 struct ionic_qos_init_cmd qos_init;
2698 struct ionic_qos_reset_cmd qos_reset;
2699 struct ionic_qos_clear_stats_cmd qos_clear_stats;
2700
2701 struct ionic_q_identify_cmd q_identify;
2702 struct ionic_q_init_cmd q_init;
2703 struct ionic_q_control_cmd q_control;
2704
2705 struct ionic_fw_download_cmd fw_download;
2706 struct ionic_fw_control_cmd fw_control;
2707 };
2708
2709 union ionic_dev_cmd_comp {
2710 u32 words[4];
2711 u8 status;
2712 struct ionic_admin_comp comp;
2713 struct ionic_nop_comp nop;
2714
2715 struct ionic_dev_identify_comp identify;
2716 struct ionic_dev_init_comp init;
2717 struct ionic_dev_reset_comp reset;
2718 struct ionic_dev_getattr_comp getattr;
2719 struct ionic_dev_setattr_comp setattr;
2720
2721 struct ionic_port_identify_comp port_identify;
2722 struct ionic_port_init_comp port_init;
2723 struct ionic_port_reset_comp port_reset;
2724 struct ionic_port_getattr_comp port_getattr;
2725 struct ionic_port_setattr_comp port_setattr;
2726
2727 struct ionic_vf_setattr_comp vf_setattr;
2728 struct ionic_vf_getattr_comp vf_getattr;
2729
2730 struct ionic_lif_identify_comp lif_identify;
2731 struct ionic_lif_init_comp lif_init;
2732 ionic_lif_reset_comp lif_reset;
2733
2734 struct ionic_qos_identify_comp qos_identify;
2735 ionic_qos_init_comp qos_init;
2736 ionic_qos_reset_comp qos_reset;
2737
2738 struct ionic_q_identify_comp q_identify;
2739 struct ionic_q_init_comp q_init;
2740
2741 ionic_fw_download_comp fw_download;
2742 struct ionic_fw_control_comp fw_control;
2743 };
2744
2745 /**
2746 * union ionic_dev_info_regs - Device info register format (read-only)
2747 * @signature: Signature value of 0x44455649 ('DEVI')
2748 * @version: Current version of info
2749 * @asic_type: Asic type
2750 * @asic_rev: Asic revision
2751 * @fw_status: Firmware status
2752 * @fw_heartbeat: Firmware heartbeat counter
2753 * @serial_num: Serial number
2754 * @fw_version: Firmware version
2755 */
2756 union ionic_dev_info_regs {
2757 #define IONIC_DEVINFO_FWVERS_BUFLEN 32
2758 #define IONIC_DEVINFO_SERIAL_BUFLEN 32
2759 struct {
2760 u32 signature;
2761 u8 version;
2762 u8 asic_type;
2763 u8 asic_rev;
2764 #define IONIC_FW_STS_F_RUNNING 0x1
2765 u8 fw_status;
2766 u32 fw_heartbeat;
2767 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN];
2768 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN];
2769 };
2770 u32 words[512];
2771 };
2772
2773 /**
2774 * union ionic_dev_cmd_regs - Device command register format (read-write)
2775 * @doorbell: Device Cmd Doorbell, write-only
2776 * Write a 1 to signal device to process cmd,
2777 * poll done for completion.
2778 * @done: Done indicator, bit 0 == 1 when command is complete
2779 * @cmd: Opcode-specific command bytes
2780 * @comp: Opcode-specific response bytes
2781 * @data: Opcode-specific side-data
2782 */
2783 union ionic_dev_cmd_regs {
2784 struct {
2785 u32 doorbell;
2786 u32 done;
2787 union ionic_dev_cmd cmd;
2788 union ionic_dev_cmd_comp comp;
2789 u8 rsvd[48];
2790 u32 data[478];
2791 } __packed;
2792 u32 words[512];
2793 };
2794
2795 /**
2796 * union ionic_dev_regs - Device register format for bar 0 page 0
2797 * @info: Device info registers
2798 * @devcmd: Device command registers
2799 */
2800 union ionic_dev_regs {
2801 struct {
2802 union ionic_dev_info_regs info;
2803 union ionic_dev_cmd_regs devcmd;
2804 } __packed;
2805 __le32 words[1024];
2806 };
2807
2808 union ionic_adminq_cmd {
2809 struct ionic_admin_cmd cmd;
2810 struct ionic_nop_cmd nop;
2811 struct ionic_q_identify_cmd q_identify;
2812 struct ionic_q_init_cmd q_init;
2813 struct ionic_q_control_cmd q_control;
2814 struct ionic_lif_setattr_cmd lif_setattr;
2815 struct ionic_lif_getattr_cmd lif_getattr;
2816 struct ionic_rx_mode_set_cmd rx_mode_set;
2817 struct ionic_rx_filter_add_cmd rx_filter_add;
2818 struct ionic_rx_filter_del_cmd rx_filter_del;
2819 struct ionic_rdma_reset_cmd rdma_reset;
2820 struct ionic_rdma_queue_cmd rdma_queue;
2821 struct ionic_fw_download_cmd fw_download;
2822 struct ionic_fw_control_cmd fw_control;
2823 };
2824
2825 union ionic_adminq_comp {
2826 struct ionic_admin_comp comp;
2827 struct ionic_nop_comp nop;
2828 struct ionic_q_identify_comp q_identify;
2829 struct ionic_q_init_comp q_init;
2830 struct ionic_lif_setattr_comp lif_setattr;
2831 struct ionic_lif_getattr_comp lif_getattr;
2832 struct ionic_rx_filter_add_comp rx_filter_add;
2833 struct ionic_fw_control_comp fw_control;
2834 };
2835
2836 #define IONIC_BARS_MAX 6
2837 #define IONIC_PCI_BAR_DBELL 1
2838
2839 /* BAR0 */
2840 #define IONIC_BAR0_SIZE 0x8000
2841
2842 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000
2843 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800
2844 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00
2845 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000
2846 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000
2847 #define IONIC_DEV_CMD_DONE 0x00000001
2848
2849 #define IONIC_ASIC_TYPE_CAPRI 0
2850
2851 /**
2852 * struct ionic_doorbell - Doorbell register layout
2853 * @p_index: Producer index
2854 * @ring: Selects the specific ring of the queue to update
2855 * Type-specific meaning:
2856 * ring=0: Default producer/consumer queue
2857 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs
2858 * send events to EQs when armed. EQs send
2859 * interrupts when armed.
2860 * @qid_lo: Queue destination for the producer index and flags (low bits)
2861 * @qid_hi: Queue destination for the producer index and flags (high bits)
2862 */
2863 struct ionic_doorbell {
2864 __le16 p_index;
2865 u8 ring;
2866 u8 qid_lo;
2867 __le16 qid_hi;
2868 u16 rsvd2;
2869 };
2870
2871 struct ionic_intr_status {
2872 u32 status[2];
2873 };
2874
2875 struct ionic_notifyq_cmd {
2876 __le32 data; /* Not used but needed for qcq structure */
2877 };
2878
2879 union ionic_notifyq_comp {
2880 struct ionic_notifyq_event event;
2881 struct ionic_link_change_event link_change;
2882 struct ionic_reset_event reset;
2883 struct ionic_heartbeat_event heartbeat;
2884 struct ionic_log_event log;
2885 };
2886
2887 /* Deprecate */
2888 struct ionic_identity {
2889 union ionic_drv_identity drv;
2890 union ionic_dev_identity dev;
2891 union ionic_lif_identity lif;
2892 union ionic_port_identity port;
2893 union ionic_qos_identity qos;
2894 union ionic_q_identity txq;
2895 };
2896
2897 #endif /* _IONIC_IF_H_ */
2898
