1 /* 2 * Copyright © 2014-2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DEVICE_INFO_H_ 26 #define _INTEL_DEVICE_INFO_H_ 27 28 #include <uapi/drm/i915_drm.h> 29 30 #include "display/intel_display.h" 31 32 #include "gt/intel_engine_types.h" 33 #include "gt/intel_context_types.h" 34 #include "gt/intel_sseu.h" 35 36 struct drm_printer; 37 struct drm_i915_private; 38 39 /* Keep in gen based order, and chronological order within a gen */ 40 enum intel_platform { 41 INTEL_PLATFORM_UNINITIALIZED = 0, 42 /* gen2 */ 43 INTEL_I830, 44 INTEL_I845G, 45 INTEL_I85X, 46 INTEL_I865G, 47 /* gen3 */ 48 INTEL_I915G, 49 INTEL_I915GM, 50 INTEL_I945G, 51 INTEL_I945GM, 52 INTEL_G33, 53 INTEL_PINEVIEW, 54 /* gen4 */ 55 INTEL_I965G, 56 INTEL_I965GM, 57 INTEL_G45, 58 INTEL_GM45, 59 /* gen5 */ 60 INTEL_IRONLAKE, 61 /* gen6 */ 62 INTEL_SANDYBRIDGE, 63 /* gen7 */ 64 INTEL_IVYBRIDGE, 65 INTEL_VALLEYVIEW, 66 INTEL_HASWELL, 67 /* gen8 */ 68 INTEL_BROADWELL, 69 INTEL_CHERRYVIEW, 70 /* gen9 */ 71 INTEL_SKYLAKE, 72 INTEL_BROXTON, 73 INTEL_KABYLAKE, 74 INTEL_GEMINILAKE, 75 INTEL_COFFEELAKE, 76 /* gen10 */ 77 INTEL_CANNONLAKE, 78 /* gen11 */ 79 INTEL_ICELAKE, 80 INTEL_ELKHARTLAKE, 81 /* gen12 */ 82 INTEL_TIGERLAKE, 83 INTEL_MAX_PLATFORMS 84 }; 85 86 /* 87 * Subplatform bits share the same namespace per parent platform. In other words 88 * it is fine for the same bit to be used on multiple parent platforms. 89 */ 90 91 #define INTEL_SUBPLATFORM_BITS (3) 92 93 /* HSW/BDW/SKL/KBL/CFL */ 94 #define INTEL_SUBPLATFORM_ULT (0) 95 #define INTEL_SUBPLATFORM_ULX (1) 96 97 /* CNL/ICL */ 98 #define INTEL_SUBPLATFORM_PORTF (0) 99 100 enum intel_ppgtt_type { 101 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, 102 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, 103 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL, 104 }; 105 106 #define DEV_INFO_FOR_EACH_FLAG(func) \ 107 func(is_mobile); \ 108 func(is_lp); \ 109 func(require_force_probe); \ 110 /* Keep has_* in alphabetical order */ \ 111 func(has_64bit_reloc); \ 112 func(gpu_reset_clobbers_display); \ 113 func(has_reset_engine); \ 114 func(has_fpga_dbg); \ 115 func(has_global_mocs); \ 116 func(has_gt_uc); \ 117 func(has_l3_dpf); \ 118 func(has_llc); \ 119 func(has_logical_ring_contexts); \ 120 func(has_logical_ring_elsq); \ 121 func(has_logical_ring_preemption); \ 122 func(has_pooled_eu); \ 123 func(has_rc6); \ 124 func(has_rc6p); \ 125 func(has_rps); \ 126 func(has_runtime_pm); \ 127 func(has_snoop); \ 128 func(has_coherent_ggtt); \ 129 func(unfenced_needs_alignment); \ 130 func(hws_needs_physical); 131 132 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 133 /* Keep in alphabetical order */ \ 134 func(cursor_needs_physical); \ 135 func(has_csr); \ 136 func(has_ddi); \ 137 func(has_dp_mst); \ 138 func(has_fbc); \ 139 func(has_gmch); \ 140 func(has_hotplug); \ 141 func(has_ipc); \ 142 func(has_modular_fia); \ 143 func(has_overlay); \ 144 func(has_psr); \ 145 func(overlay_needs_physical); \ 146 func(supports_tv); 147 148 struct intel_device_info { 149 u16 gen_mask; 150 151 u8 gen; 152 u8 gt; /* GT number, 0 if undefined */ 153 intel_engine_mask_t engine_mask; /* Engines supported by the HW */ 154 155 enum intel_platform platform; 156 157 enum intel_ppgtt_type ppgtt_type; 158 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */ 159 160 unsigned int page_sizes; /* page sizes supported by the HW */ 161 162 u32 display_mmio_offset; 163 164 u8 num_pipes; 165 166 #define DEFINE_FLAG(name) u8 name:1 167 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); 168 #undef DEFINE_FLAG 169 170 struct { 171 #define DEFINE_FLAG(name) u8 name:1 172 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 173 #undef DEFINE_FLAG 174 } display; 175 176 u16 ddb_size; /* in blocks */ 177 178 /* Register offsets for the various display pipes and transcoders */ 179 int pipe_offsets[I915_MAX_TRANSCODERS]; 180 int trans_offsets[I915_MAX_TRANSCODERS]; 181 int cursor_offsets[I915_MAX_PIPES]; 182 183 struct color_luts { 184 u32 degamma_lut_size; 185 u32 gamma_lut_size; 186 u32 degamma_lut_tests; 187 u32 gamma_lut_tests; 188 } color; 189 }; 190 191 struct intel_runtime_info { 192 /* 193 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into 194 * into single runtime conditionals, and also to provide groundwork 195 * for future per platform, or per SKU build optimizations. 196 * 197 * Array can be extended when necessary if the corresponding 198 * BUILD_BUG_ON is hit. 199 */ 200 u32 platform_mask[2]; 201 202 u16 device_id; 203 204 u8 num_sprites[I915_MAX_PIPES]; 205 u8 num_scalers[I915_MAX_PIPES]; 206 207 u8 num_engines; 208 209 /* Slice/subslice/EU info */ 210 struct sseu_dev_info sseu; 211 212 u32 cs_timestamp_frequency_khz; 213 214 /* Media engine access to SFC per instance */ 215 u8 vdbox_sfc_access; 216 }; 217 218 struct intel_driver_caps { 219 unsigned int scheduler; 220 bool has_logical_contexts:1; 221 }; 222 223 const char *intel_platform_name(enum intel_platform platform); 224 225 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv); 226 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); 227 void intel_device_info_dump_flags(const struct intel_device_info *info, 228 struct drm_printer *p); 229 void intel_device_info_dump_runtime(const struct intel_runtime_info *info, 230 struct drm_printer *p); 231 void intel_device_info_dump_topology(const struct sseu_dev_info *sseu, 232 struct drm_printer *p); 233 234 void intel_device_info_init_mmio(struct drm_i915_private *dev_priv); 235 236 void intel_driver_caps_print(const struct intel_driver_caps *caps, 237 struct drm_printer *p); 238 239 #endif 240
