1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef MAC_H 18 #define MAC_H 19 #include <net/cfg80211.h> 20 21 #define set11nTries(_series, _index) \ 22 (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) 23 24 #define set11nRate(_series, _index) \ 25 (SM((_series)[_index].Rate, AR_XmitRate##_index)) 26 27 #define set11nPktDurRTSCTS(_series, _index) \ 28 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \ 29 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \ 30 AR_RTSCTSQual##_index : 0)) 31 32 #define set11nRateFlags(_series, _index) \ 33 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ 34 AR_2040_##_index : 0) \ 35 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ 36 AR_GI##_index : 0) \ 37 |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \ 38 AR_STBC##_index : 0) \ 39 |SM((_series)[_index].ChSel, AR_ChainSel##_index)) 40 41 #define CCK_SIFS_TIME 10 42 #define CCK_PREAMBLE_BITS 144 43 #define CCK_PLCP_BITS 48 44 45 #define OFDM_SIFS_TIME 16 46 #define OFDM_PREAMBLE_TIME 20 47 #define OFDM_PLCP_BITS 22 48 #define OFDM_SYMBOL_TIME 4 49 50 #define OFDM_SIFS_TIME_HALF 32 51 #define OFDM_PREAMBLE_TIME_HALF 40 52 #define OFDM_PLCP_BITS_HALF 22 53 #define OFDM_SYMBOL_TIME_HALF 8 54 55 #define OFDM_SIFS_TIME_QUARTER 64 56 #define OFDM_PREAMBLE_TIME_QUARTER 80 57 #define OFDM_PLCP_BITS_QUARTER 22 58 #define OFDM_SYMBOL_TIME_QUARTER 16 59 60 #define INIT_AIFS 2 61 #define INIT_CWMIN 15 62 #define INIT_CWMIN_11B 31 63 #define INIT_CWMAX 1023 64 #define INIT_SH_RETRY 10 65 #define INIT_LG_RETRY 10 66 #define INIT_SSH_RETRY 32 67 #define INIT_SLG_RETRY 32 68 69 #define ATH9K_TXERR_XRETRY 0x01 70 #define ATH9K_TXERR_FILT 0x02 71 #define ATH9K_TXERR_FIFO 0x04 72 #define ATH9K_TXERR_XTXOP 0x08 73 #define ATH9K_TXERR_TIMER_EXPIRED 0x10 74 #define ATH9K_TX_ACKED 0x20 75 #define ATH9K_TX_FLUSH 0x40 76 #define ATH9K_TXERR_MASK \ 77 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \ 78 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED | ATH9K_TX_FLUSH) 79 80 #define ATH9K_TX_BA 0x01 81 #define ATH9K_TX_PWRMGMT 0x02 82 #define ATH9K_TX_DESC_CFG_ERR 0x04 83 #define ATH9K_TX_DATA_UNDERRUN 0x08 84 #define ATH9K_TX_DELIM_UNDERRUN 0x10 85 #define ATH9K_TX_SW_FILTERED 0x80 86 87 /* 64 bytes */ 88 #define MIN_TX_FIFO_THRESHOLD 0x1 89 90 /* 91 * Single stream device AR9285 and AR9271 require 2 KB 92 * to work around a hardware issue, all other devices 93 * have can use the max 4 KB limit. 94 */ 95 #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) 96 97 struct ath_tx_status { 98 u32 ts_tstamp; 99 u16 ts_seqnum; 100 u8 ts_status; 101 u8 ts_rateindex; 102 int8_t ts_rssi; 103 u8 ts_shortretry; 104 u8 ts_longretry; 105 u8 ts_virtcol; 106 u8 ts_flags; 107 int8_t ts_rssi_ctl0; 108 int8_t ts_rssi_ctl1; 109 int8_t ts_rssi_ctl2; 110 int8_t ts_rssi_ext0; 111 int8_t ts_rssi_ext1; 112 int8_t ts_rssi_ext2; 113 u8 qid; 114 u16 desc_id; 115 u8 tid; 116 u32 ba_low; 117 u32 ba_high; 118 u32 evm0; 119 u32 evm1; 120 u32 evm2; 121 u32 duration; 122 }; 123 124 struct ath_rx_status { 125 u32 rs_tstamp; 126 u16 rs_datalen; 127 u8 rs_status; 128 u8 rs_phyerr; 129 int8_t rs_rssi; 130 u8 rs_keyix; 131 u8 rs_rate; 132 u8 rs_antenna; 133 u8 rs_more; 134 int8_t rs_rssi_ctl[3]; 135 int8_t rs_rssi_ext[3]; 136 u8 rs_isaggr; 137 u8 rs_firstaggr; 138 u8 rs_moreaggr; 139 u8 rs_num_delims; 140 u8 rs_flags; 141 bool is_mybeacon; 142 u32 evm0; 143 u32 evm1; 144 u32 evm2; 145 u32 evm3; 146 u32 evm4; 147 u16 enc_flags; 148 enum rate_info_bw bw; 149 }; 150 151 struct ath_htc_rx_status { 152 __be64 rs_tstamp; 153 __be16 rs_datalen; 154 u8 rs_status; 155 u8 rs_phyerr; 156 int8_t rs_rssi; 157 int8_t rs_rssi_ctl[3]; 158 int8_t rs_rssi_ext[3]; 159 u8 rs_keyix; 160 u8 rs_rate; 161 u8 rs_antenna; 162 u8 rs_more; 163 u8 rs_isaggr; 164 u8 rs_moreaggr; 165 u8 rs_num_delims; 166 u8 rs_flags; 167 u8 rs_dummy; 168 /* FIXME: evm* never used? */ 169 __be32 evm0; 170 __be32 evm1; 171 __be32 evm2; 172 }; 173 174 #define ATH9K_RXERR_CRC 0x01 175 #define ATH9K_RXERR_PHY 0x02 176 #define ATH9K_RXERR_FIFO 0x04 177 #define ATH9K_RXERR_DECRYPT 0x08 178 #define ATH9K_RXERR_MIC 0x10 179 #define ATH9K_RXERR_KEYMISS 0x20 180 #define ATH9K_RXERR_CORRUPT_DESC 0x40 181 182 #define ATH9K_RX_MORE 0x01 183 #define ATH9K_RX_MORE_AGGR 0x02 184 #define ATH9K_RX_GI 0x04 185 #define ATH9K_RX_2040 0x08 186 #define ATH9K_RX_DELIM_CRC_PRE 0x10 187 #define ATH9K_RX_DELIM_CRC_POST 0x20 188 #define ATH9K_RX_DECRYPT_BUSY 0x40 189 190 #define ATH9K_RXKEYIX_INVALID ((u8)-1) 191 #define ATH9K_TXKEYIX_INVALID ((u8)-1) 192 193 enum ath9k_phyerr { 194 ATH9K_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 195 ATH9K_PHYERR_TIMING = 1, /* Timing error */ 196 ATH9K_PHYERR_PARITY = 2, /* Illegal parity */ 197 ATH9K_PHYERR_RATE = 3, /* Illegal rate */ 198 ATH9K_PHYERR_LENGTH = 4, /* Illegal length */ 199 ATH9K_PHYERR_RADAR = 5, /* Radar detect */ 200 ATH9K_PHYERR_SERVICE = 6, /* Illegal service */ 201 ATH9K_PHYERR_TOR = 7, /* Transmit override receive */ 202 203 ATH9K_PHYERR_OFDM_TIMING = 17, 204 ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18, 205 ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19, 206 ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20, 207 ATH9K_PHYERR_OFDM_POWER_DROP = 21, 208 ATH9K_PHYERR_OFDM_SERVICE = 22, 209 ATH9K_PHYERR_OFDM_RESTART = 23, 210 211 ATH9K_PHYERR_CCK_BLOCKER = 24, 212 ATH9K_PHYERR_CCK_TIMING = 25, 213 ATH9K_PHYERR_CCK_HEADER_CRC = 26, 214 ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27, 215 ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 28, 216 ATH9K_PHYERR_CCK_POWER_DROP = 29, 217 ATH9K_PHYERR_CCK_SERVICE = 30, 218 ATH9K_PHYERR_CCK_RESTART = 31, 219 220 ATH9K_PHYERR_HT_CRC_ERROR = 32, 221 ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 33, 222 ATH9K_PHYERR_HT_RATE_ILLEGAL = 34, 223 ATH9K_PHYERR_HT_ZLF = 35, 224 225 ATH9K_PHYERR_FALSE_RADAR_EXT = 36, 226 ATH9K_PHYERR_GREEN_FIELD = 37, 227 ATH9K_PHYERR_SPECTRAL = 38, 228 229 ATH9K_PHYERR_MAX = 39, 230 }; 231 232 struct ath_desc { 233 u32 ds_link; 234 u32 ds_data; 235 u32 ds_ctl0; 236 u32 ds_ctl1; 237 u32 ds_hw[20]; 238 void *ds_vdata; 239 } __packed __aligned(4); 240 241 #define ATH9K_TXDESC_NOACK 0x0002 242 #define ATH9K_TXDESC_RTSENA 0x0004 243 #define ATH9K_TXDESC_CTSENA 0x0008 244 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for 245 * the descriptor its marked on. We take a tx interrupt to reap 246 * descriptors when the h/w hits an EOL condition or 247 * when the descriptor is specifically marked to generate 248 * an interrupt with this flag. Descriptors should be 249 * marked periodically to insure timely replenishing of the 250 * supply needed for sending frames. Defering interrupts 251 * reduces system load and potentially allows more concurrent 252 * work to be done but if done to aggressively can cause 253 * senders to backup. When the hardware queue is left too 254 * large rate control information may also be too out of 255 * date. An Alternative for this is TX interrupt mitigation 256 * but this needs more testing. */ 257 #define ATH9K_TXDESC_INTREQ 0x0010 258 #define ATH9K_TXDESC_VEOL 0x0020 259 #define ATH9K_TXDESC_EXT_ONLY 0x0040 260 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080 261 #define ATH9K_TXDESC_VMF 0x0100 262 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200 263 #define ATH9K_TXDESC_LOWRXCHAIN 0x0400 264 #define ATH9K_TXDESC_LDPC 0x0800 265 #define ATH9K_TXDESC_CLRDMASK 0x1000 266 267 #define ATH9K_TXDESC_PAPRD 0x70000 268 #define ATH9K_TXDESC_PAPRD_S 16 269 270 #define ATH9K_RXDESC_INTREQ 0x0020 271 272 struct ar5416_desc { 273 u32 ds_link; 274 u32 ds_data; 275 u32 ds_ctl0; 276 u32 ds_ctl1; 277 union { 278 struct { 279 u32 ctl2; 280 u32 ctl3; 281 u32 ctl4; 282 u32 ctl5; 283 u32 ctl6; 284 u32 ctl7; 285 u32 ctl8; 286 u32 ctl9; 287 u32 ctl10; 288 u32 ctl11; 289 u32 status0; 290 u32 status1; 291 u32 status2; 292 u32 status3; 293 u32 status4; 294 u32 status5; 295 u32 status6; 296 u32 status7; 297 u32 status8; 298 u32 status9; 299 } tx; 300 struct { 301 u32 status0; 302 u32 status1; 303 u32 status2; 304 u32 status3; 305 u32 status4; 306 u32 status5; 307 u32 status6; 308 u32 status7; 309 u32 status8; 310 } rx; 311 } u; 312 } __packed __aligned(4); 313 314 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) 315 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) 316 317 #define ds_ctl2 u.tx.ctl2 318 #define ds_ctl3 u.tx.ctl3 319 #define ds_ctl4 u.tx.ctl4 320 #define ds_ctl5 u.tx.ctl5 321 #define ds_ctl6 u.tx.ctl6 322 #define ds_ctl7 u.tx.ctl7 323 #define ds_ctl8 u.tx.ctl8 324 #define ds_ctl9 u.tx.ctl9 325 #define ds_ctl10 u.tx.ctl10 326 #define ds_ctl11 u.tx.ctl11 327 328 #define ds_txstatus0 u.tx.status0 329 #define ds_txstatus1 u.tx.status1 330 #define ds_txstatus2 u.tx.status2 331 #define ds_txstatus3 u.tx.status3 332 #define ds_txstatus4 u.tx.status4 333 #define ds_txstatus5 u.tx.status5 334 #define ds_txstatus6 u.tx.status6 335 #define ds_txstatus7 u.tx.status7 336 #define ds_txstatus8 u.tx.status8 337 #define ds_txstatus9 u.tx.status9 338 339 #define ds_rxstatus0 u.rx.status0 340 #define ds_rxstatus1 u.rx.status1 341 #define ds_rxstatus2 u.rx.status2 342 #define ds_rxstatus3 u.rx.status3 343 #define ds_rxstatus4 u.rx.status4 344 #define ds_rxstatus5 u.rx.status5 345 #define ds_rxstatus6 u.rx.status6 346 #define ds_rxstatus7 u.rx.status7 347 #define ds_rxstatus8 u.rx.status8 348 349 #define AR_FrameLen 0x00000fff 350 #define AR_VirtMoreFrag 0x00001000 351 #define AR_TxCtlRsvd00 0x0000e000 352 #define AR_XmitPower0 0x003f0000 353 #define AR_XmitPower0_S 16 354 #define AR_XmitPower1 0x3f000000 355 #define AR_XmitPower1_S 24 356 #define AR_XmitPower2 0x3f000000 357 #define AR_XmitPower2_S 24 358 #define AR_XmitPower3 0x3f000000 359 #define AR_XmitPower3_S 24 360 #define AR_RTSEnable 0x00400000 361 #define AR_VEOL 0x00800000 362 #define AR_ClrDestMask 0x01000000 363 #define AR_TxCtlRsvd01 0x1e000000 364 #define AR_TxIntrReq 0x20000000 365 #define AR_DestIdxValid 0x40000000 366 #define AR_CTSEnable 0x80000000 367 368 #define AR_TxMore 0x00001000 369 #define AR_DestIdx 0x000fe000 370 #define AR_DestIdx_S 13 371 #define AR_FrameType 0x00f00000 372 #define AR_FrameType_S 20 373 #define AR_NoAck 0x01000000 374 #define AR_InsertTS 0x02000000 375 #define AR_CorruptFCS 0x04000000 376 #define AR_ExtOnly 0x08000000 377 #define AR_ExtAndCtl 0x10000000 378 #define AR_MoreAggr 0x20000000 379 #define AR_IsAggr 0x40000000 380 381 #define AR_BurstDur 0x00007fff 382 #define AR_BurstDur_S 0 383 #define AR_DurUpdateEna 0x00008000 384 #define AR_XmitDataTries0 0x000f0000 385 #define AR_XmitDataTries0_S 16 386 #define AR_XmitDataTries1 0x00f00000 387 #define AR_XmitDataTries1_S 20 388 #define AR_XmitDataTries2 0x0f000000 389 #define AR_XmitDataTries2_S 24 390 #define AR_XmitDataTries3 0xf0000000 391 #define AR_XmitDataTries3_S 28 392 393 #define AR_XmitRate0 0x000000ff 394 #define AR_XmitRate0_S 0 395 #define AR_XmitRate1 0x0000ff00 396 #define AR_XmitRate1_S 8 397 #define AR_XmitRate2 0x00ff0000 398 #define AR_XmitRate2_S 16 399 #define AR_XmitRate3 0xff000000 400 #define AR_XmitRate3_S 24 401 402 #define AR_PacketDur0 0x00007fff 403 #define AR_PacketDur0_S 0 404 #define AR_RTSCTSQual0 0x00008000 405 #define AR_PacketDur1 0x7fff0000 406 #define AR_PacketDur1_S 16 407 #define AR_RTSCTSQual1 0x80000000 408 409 #define AR_PacketDur2 0x00007fff 410 #define AR_PacketDur2_S 0 411 #define AR_RTSCTSQual2 0x00008000 412 #define AR_PacketDur3 0x7fff0000 413 #define AR_PacketDur3_S 16 414 #define AR_RTSCTSQual3 0x80000000 415 416 #define AR_AggrLen 0x0000ffff 417 #define AR_AggrLen_S 0 418 #define AR_TxCtlRsvd60 0x00030000 419 #define AR_PadDelim 0x03fc0000 420 #define AR_PadDelim_S 18 421 #define AR_EncrType 0x0c000000 422 #define AR_EncrType_S 26 423 #define AR_TxCtlRsvd61 0xf0000000 424 #define AR_LDPC 0x80000000 425 426 #define AR_2040_0 0x00000001 427 #define AR_GI0 0x00000002 428 #define AR_ChainSel0 0x0000001c 429 #define AR_ChainSel0_S 2 430 #define AR_2040_1 0x00000020 431 #define AR_GI1 0x00000040 432 #define AR_ChainSel1 0x00000380 433 #define AR_ChainSel1_S 7 434 #define AR_2040_2 0x00000400 435 #define AR_GI2 0x00000800 436 #define AR_ChainSel2 0x00007000 437 #define AR_ChainSel2_S 12 438 #define AR_2040_3 0x00008000 439 #define AR_GI3 0x00010000 440 #define AR_ChainSel3 0x000e0000 441 #define AR_ChainSel3_S 17 442 #define AR_RTSCTSRate 0x0ff00000 443 #define AR_RTSCTSRate_S 20 444 #define AR_STBC0 0x10000000 445 #define AR_STBC1 0x20000000 446 #define AR_STBC2 0x40000000 447 #define AR_STBC3 0x80000000 448 449 #define AR_TxRSSIAnt00 0x000000ff 450 #define AR_TxRSSIAnt00_S 0 451 #define AR_TxRSSIAnt01 0x0000ff00 452 #define AR_TxRSSIAnt01_S 8 453 #define AR_TxRSSIAnt02 0x00ff0000 454 #define AR_TxRSSIAnt02_S 16 455 #define AR_TxStatusRsvd00 0x3f000000 456 #define AR_TxBaStatus 0x40000000 457 #define AR_TxStatusRsvd01 0x80000000 458 459 /* 460 * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was 461 * transmitted successfully. If clear, no ACK or BA was received to indicate 462 * successful transmission when we were expecting an ACK or BA. 463 */ 464 #define AR_FrmXmitOK 0x00000001 465 #define AR_ExcessiveRetries 0x00000002 466 #define AR_FIFOUnderrun 0x00000004 467 #define AR_Filtered 0x00000008 468 #define AR_RTSFailCnt 0x000000f0 469 #define AR_RTSFailCnt_S 4 470 #define AR_DataFailCnt 0x00000f00 471 #define AR_DataFailCnt_S 8 472 #define AR_VirtRetryCnt 0x0000f000 473 #define AR_VirtRetryCnt_S 12 474 #define AR_TxDelimUnderrun 0x00010000 475 #define AR_TxDataUnderrun 0x00020000 476 #define AR_DescCfgErr 0x00040000 477 #define AR_TxTimerExpired 0x00080000 478 #define AR_TxStatusRsvd10 0xfff00000 479 480 #define AR_SendTimestamp ds_txstatus2 481 #define AR_BaBitmapLow ds_txstatus3 482 #define AR_BaBitmapHigh ds_txstatus4 483 484 #define AR_TxRSSIAnt10 0x000000ff 485 #define AR_TxRSSIAnt10_S 0 486 #define AR_TxRSSIAnt11 0x0000ff00 487 #define AR_TxRSSIAnt11_S 8 488 #define AR_TxRSSIAnt12 0x00ff0000 489 #define AR_TxRSSIAnt12_S 16 490 #define AR_TxRSSICombined 0xff000000 491 #define AR_TxRSSICombined_S 24 492 493 #define AR_TxTid 0xf0000000 494 #define AR_TxTid_S 28 495 496 #define AR_TxEVM0 ds_txstatus5 497 #define AR_TxEVM1 ds_txstatus6 498 #define AR_TxEVM2 ds_txstatus7 499 500 #define AR_TxDone 0x00000001 501 #define AR_SeqNum 0x00001ffe 502 #define AR_SeqNum_S 1 503 #define AR_TxStatusRsvd80 0x0001e000 504 #define AR_TxOpExceeded 0x00020000 505 #define AR_TxStatusRsvd81 0x001c0000 506 #define AR_FinalTxIdx 0x00600000 507 #define AR_FinalTxIdx_S 21 508 #define AR_TxStatusRsvd82 0x01800000 509 #define AR_PowerMgmt 0x02000000 510 #define AR_TxStatusRsvd83 0xfc000000 511 512 #define AR_RxCTLRsvd00 0xffffffff 513 514 #define AR_RxCtlRsvd00 0x00001000 515 #define AR_RxIntrReq 0x00002000 516 #define AR_RxCtlRsvd01 0xffffc000 517 518 #define AR_RxRSSIAnt00 0x000000ff 519 #define AR_RxRSSIAnt00_S 0 520 #define AR_RxRSSIAnt01 0x0000ff00 521 #define AR_RxRSSIAnt01_S 8 522 #define AR_RxRSSIAnt02 0x00ff0000 523 #define AR_RxRSSIAnt02_S 16 524 #define AR_RxRate 0xff000000 525 #define AR_RxRate_S 24 526 #define AR_RxStatusRsvd00 0xff000000 527 528 #define AR_DataLen 0x00000fff 529 #define AR_RxMore 0x00001000 530 #define AR_NumDelim 0x003fc000 531 #define AR_NumDelim_S 14 532 #define AR_RxStatusRsvd10 0xff800000 533 534 #define AR_RcvTimestamp ds_rxstatus2 535 536 #define AR_GI 0x00000001 537 #define AR_2040 0x00000002 538 #define AR_Parallel40 0x00000004 539 #define AR_Parallel40_S 2 540 #define AR_STBC 0x00000008 /* on ar9280 and later */ 541 #define AR_RxStatusRsvd30 0x000000f0 542 #define AR_RxAntenna 0xffffff00 543 #define AR_RxAntenna_S 8 544 545 #define AR_RxRSSIAnt10 0x000000ff 546 #define AR_RxRSSIAnt10_S 0 547 #define AR_RxRSSIAnt11 0x0000ff00 548 #define AR_RxRSSIAnt11_S 8 549 #define AR_RxRSSIAnt12 0x00ff0000 550 #define AR_RxRSSIAnt12_S 16 551 #define AR_RxRSSICombined 0xff000000 552 #define AR_RxRSSICombined_S 24 553 554 #define AR_RxEVM0 ds_rxstatus4 555 #define AR_RxEVM1 ds_rxstatus5 556 #define AR_RxEVM2 ds_rxstatus6 557 558 #define AR_RxDone 0x00000001 559 #define AR_RxFrameOK 0x00000002 560 #define AR_CRCErr 0x00000004 561 #define AR_DecryptCRCErr 0x00000008 562 #define AR_PHYErr 0x00000010 563 #define AR_MichaelErr 0x00000020 564 #define AR_PreDelimCRCErr 0x00000040 565 #define AR_RxStatusRsvd70 0x00000080 566 #define AR_RxKeyIdxValid 0x00000100 567 #define AR_KeyIdx 0x0000fe00 568 #define AR_KeyIdx_S 9 569 #define AR_PHYErrCode 0x0000ff00 570 #define AR_PHYErrCode_S 8 571 #define AR_RxMoreAggr 0x00010000 572 #define AR_RxAggr 0x00020000 573 #define AR_PostDelimCRCErr 0x00040000 574 #define AR_RxStatusRsvd71 0x3ff80000 575 #define AR_RxFirstAggr 0x20000000 576 #define AR_DecryptBusyErr 0x40000000 577 #define AR_KeyMiss 0x80000000 578 579 enum ath9k_tx_queue { 580 ATH9K_TX_QUEUE_INACTIVE = 0, 581 ATH9K_TX_QUEUE_DATA, 582 ATH9K_TX_QUEUE_BEACON, 583 ATH9K_TX_QUEUE_CAB, 584 ATH9K_TX_QUEUE_UAPSD, 585 ATH9K_TX_QUEUE_PSPOLL 586 }; 587 588 #define ATH9K_NUM_TX_QUEUES 10 589 590 /* Used as a queue subtype instead of a WMM AC */ 591 #define ATH9K_WME_UPSD 4 592 593 enum ath9k_tx_queue_flags { 594 TXQ_FLAG_TXINT_ENABLE = 0x0001, 595 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, 596 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, 597 TXQ_FLAG_TXURNINT_ENABLE = 0x0008, 598 TXQ_FLAG_BACKOFF_DISABLE = 0x0010, 599 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, 600 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, 601 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, 602 }; 603 604 #define ATH9K_TXQ_USEDEFAULT ((u32) -1) 605 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 606 607 #define ATH9K_DECOMP_MASK_SIZE 128 608 609 enum ath9k_pkt_type { 610 ATH9K_PKT_TYPE_NORMAL = 0, 611 ATH9K_PKT_TYPE_ATIM, 612 ATH9K_PKT_TYPE_PSPOLL, 613 ATH9K_PKT_TYPE_BEACON, 614 ATH9K_PKT_TYPE_PROBE_RESP, 615 ATH9K_PKT_TYPE_CHIRP, 616 ATH9K_PKT_TYPE_GRP_POLL, 617 }; 618 619 struct ath9k_tx_queue_info { 620 u32 tqi_ver; 621 enum ath9k_tx_queue tqi_type; 622 int tqi_subtype; 623 enum ath9k_tx_queue_flags tqi_qflags; 624 u32 tqi_priority; 625 u32 tqi_aifs; 626 u32 tqi_cwmin; 627 u32 tqi_cwmax; 628 u16 tqi_shretry; 629 u16 tqi_lgretry; 630 u32 tqi_cbrPeriod; 631 u32 tqi_cbrOverflowLimit; 632 u32 tqi_burstTime; 633 u32 tqi_readyTime; 634 u32 tqi_physCompBuf; 635 u32 tqi_intFlags; 636 }; 637 638 enum ath9k_rx_filter { 639 ATH9K_RX_FILTER_UCAST = 0x00000001, 640 ATH9K_RX_FILTER_MCAST = 0x00000002, 641 ATH9K_RX_FILTER_BCAST = 0x00000004, 642 ATH9K_RX_FILTER_CONTROL = 0x00000008, 643 ATH9K_RX_FILTER_BEACON = 0x00000010, 644 ATH9K_RX_FILTER_PROM = 0x00000020, 645 ATH9K_RX_FILTER_PROBEREQ = 0x00000080, 646 ATH9K_RX_FILTER_PHYERR = 0x00000100, 647 ATH9K_RX_FILTER_MYBEACON = 0x00000200, 648 ATH9K_RX_FILTER_COMP_BAR = 0x00000400, 649 ATH9K_RX_FILTER_COMP_BA = 0x00000800, 650 ATH9K_RX_FILTER_UNCOMP_BA_BAR = 0x00001000, 651 ATH9K_RX_FILTER_PSPOLL = 0x00004000, 652 ATH9K_RX_FILTER_PHYRADAR = 0x00002000, 653 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 654 ATH9K_RX_FILTER_CONTROL_WRAPPER = 0x00080000, 655 ATH9K_RX_FILTER_4ADDRESS = 0x00100000, 656 }; 657 658 #define ATH9K_RATESERIES_RTS_CTS 0x0001 659 #define ATH9K_RATESERIES_2040 0x0002 660 #define ATH9K_RATESERIES_HALFGI 0x0004 661 #define ATH9K_RATESERIES_STBC 0x0008 662 663 struct ath9k_11n_rate_series { 664 u32 Tries; 665 u32 Rate; 666 u32 PktDuration; 667 u32 ChSel; 668 u32 RateFlags; 669 }; 670 671 enum aggr_type { 672 AGGR_BUF_NONE, 673 AGGR_BUF_FIRST, 674 AGGR_BUF_MIDDLE, 675 AGGR_BUF_LAST, 676 }; 677 678 enum ath9k_key_type { 679 ATH9K_KEY_TYPE_CLEAR, 680 ATH9K_KEY_TYPE_WEP, 681 ATH9K_KEY_TYPE_AES, 682 ATH9K_KEY_TYPE_TKIP, 683 }; 684 685 struct ath_tx_info { 686 u8 qcu; 687 688 bool is_first; 689 bool is_last; 690 691 enum aggr_type aggr; 692 u8 ndelim; 693 u16 aggr_len; 694 695 dma_addr_t link; 696 int pkt_len; 697 u32 flags; 698 699 dma_addr_t buf_addr[4]; 700 int buf_len[4]; 701 702 struct ath9k_11n_rate_series rates[4]; 703 u8 rtscts_rate; 704 bool dur_update; 705 706 enum ath9k_pkt_type type; 707 enum ath9k_key_type keytype; 708 u8 keyix; 709 u8 txpower[4]; 710 }; 711 712 struct ath_hw; 713 struct ath9k_channel; 714 enum ath9k_int; 715 716 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); 717 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); 718 void ath9k_hw_txstart(struct ath_hw *ah, u32 q); 719 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); 720 bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel); 721 bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q); 722 void ath9k_hw_abort_tx_dma(struct ath_hw *ah); 723 bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 724 const struct ath9k_tx_queue_info *qinfo); 725 bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q, 726 struct ath9k_tx_queue_info *qinfo); 727 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, 728 const struct ath9k_tx_queue_info *qinfo); 729 bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q); 730 bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q); 731 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, 732 struct ath_rx_status *rs); 733 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, 734 u32 size, u32 flags); 735 bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set); 736 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); 737 void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning); 738 void ath9k_hw_abortpcurecv(struct ath_hw *ah); 739 bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset); 740 int ath9k_hw_beaconq_setup(struct ath_hw *ah); 741 void ath9k_hw_set_tx_filter(struct ath_hw *ah, u8 destidx, bool set); 742 743 /* Interrupt Handling */ 744 bool ath9k_hw_intrpend(struct ath_hw *ah); 745 void ath9k_hw_set_interrupts(struct ath_hw *ah); 746 void ath9k_hw_enable_interrupts(struct ath_hw *ah); 747 void ath9k_hw_disable_interrupts(struct ath_hw *ah); 748 void ath9k_hw_kill_interrupts(struct ath_hw *ah); 749 void ath9k_hw_resume_interrupts(struct ath_hw *ah); 750 751 void ar9002_hw_attach_mac_ops(struct ath_hw *ah); 752 753 #endif /* MAC_H */ 754
