1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
35
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hash.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/mm_types.h>
44 #include <linux/perf_event.h>
45 #include <linux/pm_qos.h>
46 #include <linux/reservation.h>
47 #include <linux/shmem_fs.h>
48
49 #include <drm/drmP.h>
50 #include <drm/intel-gtt.h>
51 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
52 #include <drm/drm_gem.h>
53 #include <drm/drm_auth.h>
54 #include <drm/drm_cache.h>
55
56 #include "i915_params.h"
57 #include "i915_reg.h"
58 #include "i915_utils.h"
59
60 #include "intel_bios.h"
61 #include "intel_device_info.h"
62 #include "intel_display.h"
63 #include "intel_dpll_mgr.h"
64 #include "intel_lrc.h"
65 #include "intel_opregion.h"
66 #include "intel_ringbuffer.h"
67 #include "intel_uncore.h"
68 #include "intel_wopcm.h"
69 #include "intel_uc.h"
70
71 #include "i915_gem.h"
72 #include "i915_gem_context.h"
73 #include "i915_gem_fence_reg.h"
74 #include "i915_gem_object.h"
75 #include "i915_gem_gtt.h"
76 #include "i915_gpu_error.h"
77 #include "i915_request.h"
78 #include "i915_scheduler.h"
79 #include "i915_timeline.h"
80 #include "i915_vma.h"
81
82 #include "intel_gvt.h"
83
84 /* General customization:
85 */
86
87 #define DRIVER_NAME "i915"
88 #define DRIVER_DESC "Intel Graphics"
89 #define DRIVER_DATE "20180719"
90 #define DRIVER_TIMESTAMP 1532015279
91
92 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
93 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
94 * which may not necessarily be a user visible problem. This will either
95 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
96 * enable distros and users to tailor their preferred amount of i915 abrt
97 * spam.
98 */
99 #define I915_STATE_WARN(condition, format...) ({ \
100 int __ret_warn_on = !!(condition); \
101 if (unlikely(__ret_warn_on)) \
102 if (!WARN(i915_modparams.verbose_state_checks, format)) \
103 DRM_ERROR(format); \
104 unlikely(__ret_warn_on); \
105 })
106
107 #define I915_STATE_WARN_ON(x) \
108 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
109
110 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
111
112 bool __i915_inject_load_failure(const char *func, int line);
113 #define i915_inject_load_failure() \
114 __i915_inject_load_failure(__func__, __LINE__)
115
116 bool i915_error_injected(void);
117
118 #else
119
120 #define i915_inject_load_failure() false
121 #define i915_error_injected() false
122
123 #endif
124
125 #define i915_load_error(i915, fmt, ...) \
126 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
127 fmt, ##__VA_ARGS__)
128
129 typedef struct {
130 uint32_t val;
131 } uint_fixed_16_16_t;
132
133 #define FP_16_16_MAX ({ \
134 uint_fixed_16_16_t fp; \
135 fp.val = UINT_MAX; \
136 fp; \
137 })
138
is_fixed16_zero(uint_fixed_16_16_t val)139 static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
140 {
141 if (val.val == 0)
142 return true;
143 return false;
144 }
145
u32_to_fixed16(uint32_t val)146 static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
147 {
148 uint_fixed_16_16_t fp;
149
150 WARN_ON(val > U16_MAX);
151
152 fp.val = val << 16;
153 return fp;
154 }
155
fixed16_to_u32_round_up(uint_fixed_16_16_t fp)156 static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
157 {
158 return DIV_ROUND_UP(fp.val, 1 << 16);
159 }
160
fixed16_to_u32(uint_fixed_16_16_t fp)161 static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
162 {
163 return fp.val >> 16;
164 }
165
min_fixed16(uint_fixed_16_16_t min1,uint_fixed_16_16_t min2)166 static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
167 uint_fixed_16_16_t min2)
168 {
169 uint_fixed_16_16_t min;
170
171 min.val = min(min1.val, min2.val);
172 return min;
173 }
174
max_fixed16(uint_fixed_16_16_t max1,uint_fixed_16_16_t max2)175 static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
176 uint_fixed_16_16_t max2)
177 {
178 uint_fixed_16_16_t max;
179
180 max.val = max(max1.val, max2.val);
181 return max;
182 }
183
clamp_u64_to_fixed16(uint64_t val)184 static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
185 {
186 uint_fixed_16_16_t fp;
187 WARN_ON(val > U32_MAX);
188 fp.val = (uint32_t) val;
189 return fp;
190 }
191
div_round_up_fixed16(uint_fixed_16_16_t val,uint_fixed_16_16_t d)192 static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
193 uint_fixed_16_16_t d)
194 {
195 return DIV_ROUND_UP(val.val, d.val);
196 }
197
mul_round_up_u32_fixed16(uint32_t val,uint_fixed_16_16_t mul)198 static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
199 uint_fixed_16_16_t mul)
200 {
201 uint64_t intermediate_val;
202
203 intermediate_val = (uint64_t) val * mul.val;
204 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
205 WARN_ON(intermediate_val > U32_MAX);
206 return (uint32_t) intermediate_val;
207 }
208
mul_fixed16(uint_fixed_16_16_t val,uint_fixed_16_16_t mul)209 static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
210 uint_fixed_16_16_t mul)
211 {
212 uint64_t intermediate_val;
213
214 intermediate_val = (uint64_t) val.val * mul.val;
215 intermediate_val = intermediate_val >> 16;
216 return clamp_u64_to_fixed16(intermediate_val);
217 }
218
div_fixed16(uint32_t val,uint32_t d)219 static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
220 {
221 uint64_t interm_val;
222
223 interm_val = (uint64_t)val << 16;
224 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
225 return clamp_u64_to_fixed16(interm_val);
226 }
227
div_round_up_u32_fixed16(uint32_t val,uint_fixed_16_16_t d)228 static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
229 uint_fixed_16_16_t d)
230 {
231 uint64_t interm_val;
232
233 interm_val = (uint64_t)val << 16;
234 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
235 WARN_ON(interm_val > U32_MAX);
236 return (uint32_t) interm_val;
237 }
238
mul_u32_fixed16(uint32_t val,uint_fixed_16_16_t mul)239 static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
240 uint_fixed_16_16_t mul)
241 {
242 uint64_t intermediate_val;
243
244 intermediate_val = (uint64_t) val * mul.val;
245 return clamp_u64_to_fixed16(intermediate_val);
246 }
247
add_fixed16(uint_fixed_16_16_t add1,uint_fixed_16_16_t add2)248 static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
249 uint_fixed_16_16_t add2)
250 {
251 uint64_t interm_sum;
252
253 interm_sum = (uint64_t) add1.val + add2.val;
254 return clamp_u64_to_fixed16(interm_sum);
255 }
256
add_fixed16_u32(uint_fixed_16_16_t add1,uint32_t add2)257 static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
258 uint32_t add2)
259 {
260 uint64_t interm_sum;
261 uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);
262
263 interm_sum = (uint64_t) add1.val + interm_add2.val;
264 return clamp_u64_to_fixed16(interm_sum);
265 }
266
267 enum hpd_pin {
268 HPD_NONE = 0,
269 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
270 HPD_CRT,
271 HPD_SDVO_B,
272 HPD_SDVO_C,
273 HPD_PORT_A,
274 HPD_PORT_B,
275 HPD_PORT_C,
276 HPD_PORT_D,
277 HPD_PORT_E,
278 HPD_PORT_F,
279 HPD_NUM_PINS
280 };
281
282 #define for_each_hpd_pin(__pin) \
283 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
284
285 #define HPD_STORM_DEFAULT_THRESHOLD 5
286
287 struct i915_hotplug {
288 struct work_struct hotplug_work;
289
290 struct {
291 unsigned long last_jiffies;
292 int count;
293 enum {
294 HPD_ENABLED = 0,
295 HPD_DISABLED = 1,
296 HPD_MARK_DISABLED = 2
297 } state;
298 } stats[HPD_NUM_PINS];
299 u32 event_bits;
300 struct delayed_work reenable_work;
301
302 u32 long_port_mask;
303 u32 short_port_mask;
304 struct work_struct dig_port_work;
305
306 struct work_struct poll_init_work;
307 bool poll_enabled;
308
309 unsigned int hpd_storm_threshold;
310
311 /*
312 * if we get a HPD irq from DP and a HPD irq from non-DP
313 * the non-DP HPD could block the workqueue on a mode config
314 * mutex getting, that userspace may have taken. However
315 * userspace is waiting on the DP workqueue to run which is
316 * blocked behind the non-DP one.
317 */
318 struct workqueue_struct *dp_wq;
319 };
320
321 #define I915_GEM_GPU_DOMAINS \
322 (I915_GEM_DOMAIN_RENDER | \
323 I915_GEM_DOMAIN_SAMPLER | \
324 I915_GEM_DOMAIN_COMMAND | \
325 I915_GEM_DOMAIN_INSTRUCTION | \
326 I915_GEM_DOMAIN_VERTEX)
327
328 struct drm_i915_private;
329 struct i915_mm_struct;
330 struct i915_mmu_object;
331
332 struct drm_i915_file_private {
333 struct drm_i915_private *dev_priv;
334 struct drm_file *file;
335
336 struct {
337 spinlock_t lock;
338 struct list_head request_list;
339 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
340 * chosen to prevent the CPU getting more than a frame ahead of the GPU
341 * (when using lax throttling for the frontbuffer). We also use it to
342 * offer free GPU waitboosts for severely congested workloads.
343 */
344 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
345 } mm;
346 struct idr context_idr;
347
348 struct intel_rps_client {
349 atomic_t boosts;
350 } rps_client;
351
352 unsigned int bsd_engine;
353
354 /*
355 * Every context ban increments per client ban score. Also
356 * hangs in short succession increments ban score. If ban threshold
357 * is reached, client is considered banned and submitting more work
358 * will fail. This is a stop gap measure to limit the badly behaving
359 * clients access to gpu. Note that unbannable contexts never increment
360 * the client ban score.
361 */
362 #define I915_CLIENT_SCORE_HANG_FAST 1
363 #define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
364 #define I915_CLIENT_SCORE_CONTEXT_BAN 3
365 #define I915_CLIENT_SCORE_BANNED 9
366 /** ban_score: Accumulated score of all ctx bans and fast hangs. */
367 atomic_t ban_score;
368 unsigned long hang_timestamp;
369 };
370
371 /* Interface history:
372 *
373 * 1.1: Original.
374 * 1.2: Add Power Management
375 * 1.3: Add vblank support
376 * 1.4: Fix cmdbuffer path, add heap destroy
377 * 1.5: Add vblank pipe configuration
378 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
379 * - Support vertical blank on secondary display pipe
380 */
381 #define DRIVER_MAJOR 1
382 #define DRIVER_MINOR 6
383 #define DRIVER_PATCHLEVEL 0
384
385 struct intel_overlay;
386 struct intel_overlay_error_state;
387
388 struct sdvo_device_mapping {
389 u8 initialized;
390 u8 dvo_port;
391 u8 slave_addr;
392 u8 dvo_wiring;
393 u8 i2c_pin;
394 u8 ddc_pin;
395 };
396
397 struct intel_connector;
398 struct intel_encoder;
399 struct intel_atomic_state;
400 struct intel_crtc_state;
401 struct intel_initial_plane_config;
402 struct intel_crtc;
403 struct intel_limit;
404 struct dpll;
405 struct intel_cdclk_state;
406
407 struct drm_i915_display_funcs {
408 void (*get_cdclk)(struct drm_i915_private *dev_priv,
409 struct intel_cdclk_state *cdclk_state);
410 void (*set_cdclk)(struct drm_i915_private *dev_priv,
411 const struct intel_cdclk_state *cdclk_state);
412 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
413 enum i9xx_plane_id i9xx_plane);
414 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
415 int (*compute_intermediate_wm)(struct drm_device *dev,
416 struct intel_crtc *intel_crtc,
417 struct intel_crtc_state *newstate);
418 void (*initial_watermarks)(struct intel_atomic_state *state,
419 struct intel_crtc_state *cstate);
420 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
421 struct intel_crtc_state *cstate);
422 void (*optimize_watermarks)(struct intel_atomic_state *state,
423 struct intel_crtc_state *cstate);
424 int (*compute_global_watermarks)(struct drm_atomic_state *state);
425 void (*update_wm)(struct intel_crtc *crtc);
426 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
427 /* Returns the active state of the crtc, and if the crtc is active,
428 * fills out the pipe-config with the hw state. */
429 bool (*get_pipe_config)(struct intel_crtc *,
430 struct intel_crtc_state *);
431 void (*get_initial_plane_config)(struct intel_crtc *,
432 struct intel_initial_plane_config *);
433 int (*crtc_compute_clock)(struct intel_crtc *crtc,
434 struct intel_crtc_state *crtc_state);
435 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
436 struct drm_atomic_state *old_state);
437 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
438 struct drm_atomic_state *old_state);
439 void (*update_crtcs)(struct drm_atomic_state *state);
440 void (*audio_codec_enable)(struct intel_encoder *encoder,
441 const struct intel_crtc_state *crtc_state,
442 const struct drm_connector_state *conn_state);
443 void (*audio_codec_disable)(struct intel_encoder *encoder,
444 const struct intel_crtc_state *old_crtc_state,
445 const struct drm_connector_state *old_conn_state);
446 void (*fdi_link_train)(struct intel_crtc *crtc,
447 const struct intel_crtc_state *crtc_state);
448 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
449 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
450 /* clock updates for mode set */
451 /* cursor updates */
452 /* render clock increase/decrease */
453 /* display clock increase/decrease */
454 /* pll clock increase/decrease */
455
456 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
457 void (*load_luts)(struct drm_crtc_state *crtc_state);
458 };
459
460 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
461 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
462 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
463
464 struct intel_csr {
465 struct work_struct work;
466 const char *fw_path;
467 uint32_t *dmc_payload;
468 uint32_t dmc_fw_size;
469 uint32_t version;
470 uint32_t mmio_count;
471 i915_reg_t mmioaddr[8];
472 uint32_t mmiodata[8];
473 uint32_t dc_state;
474 uint32_t allowed_dc_mask;
475 };
476
477 enum i915_cache_level {
478 I915_CACHE_NONE = 0,
479 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
480 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
481 caches, eg sampler/render caches, and the
482 large Last-Level-Cache. LLC is coherent with
483 the CPU, but L3 is only visible to the GPU. */
484 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
485 };
486
487 #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
488
489 enum fb_op_origin {
490 ORIGIN_GTT,
491 ORIGIN_CPU,
492 ORIGIN_CS,
493 ORIGIN_FLIP,
494 ORIGIN_DIRTYFB,
495 };
496
497 struct intel_fbc {
498 /* This is always the inner lock when overlapping with struct_mutex and
499 * it's the outer lock when overlapping with stolen_lock. */
500 struct mutex lock;
501 unsigned threshold;
502 unsigned int possible_framebuffer_bits;
503 unsigned int busy_bits;
504 unsigned int visible_pipes_mask;
505 struct intel_crtc *crtc;
506
507 struct drm_mm_node compressed_fb;
508 struct drm_mm_node *compressed_llb;
509
510 bool false_color;
511
512 bool enabled;
513 bool active;
514 bool flip_pending;
515
516 bool underrun_detected;
517 struct work_struct underrun_work;
518
519 /*
520 * Due to the atomic rules we can't access some structures without the
521 * appropriate locking, so we cache information here in order to avoid
522 * these problems.
523 */
524 struct intel_fbc_state_cache {
525 struct i915_vma *vma;
526 unsigned long flags;
527
528 struct {
529 unsigned int mode_flags;
530 uint32_t hsw_bdw_pixel_rate;
531 } crtc;
532
533 struct {
534 unsigned int rotation;
535 int src_w;
536 int src_h;
537 bool visible;
538 /*
539 * Display surface base address adjustement for
540 * pageflips. Note that on gen4+ this only adjusts up
541 * to a tile, offsets within a tile are handled in
542 * the hw itself (with the TILEOFF register).
543 */
544 int adjusted_x;
545 int adjusted_y;
546
547 int y;
548 } plane;
549
550 struct {
551 const struct drm_format_info *format;
552 unsigned int stride;
553 } fb;
554 } state_cache;
555
556 /*
557 * This structure contains everything that's relevant to program the
558 * hardware registers. When we want to figure out if we need to disable
559 * and re-enable FBC for a new configuration we just check if there's
560 * something different in the struct. The genx_fbc_activate functions
561 * are supposed to read from it in order to program the registers.
562 */
563 struct intel_fbc_reg_params {
564 struct i915_vma *vma;
565 unsigned long flags;
566
567 struct {
568 enum pipe pipe;
569 enum i9xx_plane_id i9xx_plane;
570 unsigned int fence_y_offset;
571 } crtc;
572
573 struct {
574 const struct drm_format_info *format;
575 unsigned int stride;
576 } fb;
577
578 int cfb_size;
579 unsigned int gen9_wa_cfb_stride;
580 } params;
581
582 const char *no_fbc_reason;
583 };
584
585 /*
586 * HIGH_RR is the highest eDP panel refresh rate read from EDID
587 * LOW_RR is the lowest eDP panel refresh rate found from EDID
588 * parsing for same resolution.
589 */
590 enum drrs_refresh_rate_type {
591 DRRS_HIGH_RR,
592 DRRS_LOW_RR,
593 DRRS_MAX_RR, /* RR count */
594 };
595
596 enum drrs_support_type {
597 DRRS_NOT_SUPPORTED = 0,
598 STATIC_DRRS_SUPPORT = 1,
599 SEAMLESS_DRRS_SUPPORT = 2
600 };
601
602 struct intel_dp;
603 struct i915_drrs {
604 struct mutex mutex;
605 struct delayed_work work;
606 struct intel_dp *dp;
607 unsigned busy_frontbuffer_bits;
608 enum drrs_refresh_rate_type refresh_rate_type;
609 enum drrs_support_type type;
610 };
611
612 struct i915_psr {
613 struct mutex lock;
614 bool sink_support;
615 struct intel_dp *enabled;
616 bool active;
617 struct work_struct work;
618 unsigned busy_frontbuffer_bits;
619 bool sink_psr2_support;
620 bool link_standby;
621 bool colorimetry_support;
622 bool alpm;
623 bool psr2_enabled;
624 u8 sink_sync_latency;
625 bool debug;
626 ktime_t last_entry_attempt;
627 ktime_t last_exit;
628 };
629
630 enum intel_pch {
631 PCH_NONE = 0, /* No PCH present */
632 PCH_IBX, /* Ibexpeak PCH */
633 PCH_CPT, /* Cougarpoint/Pantherpoint PCH */
634 PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
635 PCH_SPT, /* Sunrisepoint PCH */
636 PCH_KBP, /* Kaby Lake PCH */
637 PCH_CNP, /* Cannon Lake PCH */
638 PCH_ICP, /* Ice Lake PCH */
639 PCH_NOP, /* PCH without south display */
640 };
641
642 enum intel_sbi_destination {
643 SBI_ICLK,
644 SBI_MPHY,
645 };
646
647 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
648 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
649 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
650 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
651 #define QUIRK_INCREASE_T12_DELAY (1<<6)
652 #define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
653
654 struct intel_fbdev;
655 struct intel_fbc_work;
656
657 struct intel_gmbus {
658 struct i2c_adapter adapter;
659 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
660 u32 force_bit;
661 u32 reg0;
662 i915_reg_t gpio_reg;
663 struct i2c_algo_bit_data bit_algo;
664 struct drm_i915_private *dev_priv;
665 };
666
667 struct i915_suspend_saved_registers {
668 u32 saveDSPARB;
669 u32 saveFBC_CONTROL;
670 u32 saveCACHE_MODE_0;
671 u32 saveMI_ARB_STATE;
672 u32 saveSWF0[16];
673 u32 saveSWF1[16];
674 u32 saveSWF3[3];
675 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
676 u32 savePCH_PORT_HOTPLUG;
677 u16 saveGCDGMBUS;
678 };
679
680 struct vlv_s0ix_state {
681 /* GAM */
682 u32 wr_watermark;
683 u32 gfx_prio_ctrl;
684 u32 arb_mode;
685 u32 gfx_pend_tlb0;
686 u32 gfx_pend_tlb1;
687 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
688 u32 media_max_req_count;
689 u32 gfx_max_req_count;
690 u32 render_hwsp;
691 u32 ecochk;
692 u32 bsd_hwsp;
693 u32 blt_hwsp;
694 u32 tlb_rd_addr;
695
696 /* MBC */
697 u32 g3dctl;
698 u32 gsckgctl;
699 u32 mbctl;
700
701 /* GCP */
702 u32 ucgctl1;
703 u32 ucgctl3;
704 u32 rcgctl1;
705 u32 rcgctl2;
706 u32 rstctl;
707 u32 misccpctl;
708
709 /* GPM */
710 u32 gfxpause;
711 u32 rpdeuhwtc;
712 u32 rpdeuc;
713 u32 ecobus;
714 u32 pwrdwnupctl;
715 u32 rp_down_timeout;
716 u32 rp_deucsw;
717 u32 rcubmabdtmr;
718 u32 rcedata;
719 u32 spare2gh;
720
721 /* Display 1 CZ domain */
722 u32 gt_imr;
723 u32 gt_ier;
724 u32 pm_imr;
725 u32 pm_ier;
726 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
727
728 /* GT SA CZ domain */
729 u32 tilectl;
730 u32 gt_fifoctl;
731 u32 gtlc_wake_ctrl;
732 u32 gtlc_survive;
733 u32 pmwgicz;
734
735 /* Display 2 CZ domain */
736 u32 gu_ctl0;
737 u32 gu_ctl1;
738 u32 pcbr;
739 u32 clock_gate_dis2;
740 };
741
742 struct intel_rps_ei {
743 ktime_t ktime;
744 u32 render_c0;
745 u32 media_c0;
746 };
747
748 struct intel_rps {
749 /*
750 * work, interrupts_enabled and pm_iir are protected by
751 * dev_priv->irq_lock
752 */
753 struct work_struct work;
754 bool interrupts_enabled;
755 u32 pm_iir;
756
757 /* PM interrupt bits that should never be masked */
758 u32 pm_intrmsk_mbz;
759
760 /* Frequencies are stored in potentially platform dependent multiples.
761 * In other words, *_freq needs to be multiplied by X to be interesting.
762 * Soft limits are those which are used for the dynamic reclocking done
763 * by the driver (raise frequencies under heavy loads, and lower for
764 * lighter loads). Hard limits are those imposed by the hardware.
765 *
766 * A distinction is made for overclocking, which is never enabled by
767 * default, and is considered to be above the hard limit if it's
768 * possible at all.
769 */
770 u8 cur_freq; /* Current frequency (cached, may not == HW) */
771 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
772 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
773 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
774 u8 min_freq; /* AKA RPn. Minimum frequency */
775 u8 boost_freq; /* Frequency to request when wait boosting */
776 u8 idle_freq; /* Frequency to request when we are idle */
777 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
778 u8 rp1_freq; /* "less than" RP0 power/freqency */
779 u8 rp0_freq; /* Non-overclocked max frequency. */
780 u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
781
782 int last_adj;
783
784 struct {
785 struct mutex mutex;
786
787 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
788 unsigned int interactive;
789
790 u8 up_threshold; /* Current %busy required to uplock */
791 u8 down_threshold; /* Current %busy required to downclock */
792 } power;
793
794 bool enabled;
795 atomic_t num_waiters;
796 atomic_t boosts;
797
798 /* manual wa residency calculations */
799 struct intel_rps_ei ei;
800 };
801
802 struct intel_rc6 {
803 bool enabled;
804 u64 prev_hw_residency[4];
805 u64 cur_residency[4];
806 };
807
808 struct intel_llc_pstate {
809 bool enabled;
810 };
811
812 struct intel_gen6_power_mgmt {
813 struct intel_rps rps;
814 struct intel_rc6 rc6;
815 struct intel_llc_pstate llc_pstate;
816 };
817
818 /* defined intel_pm.c */
819 extern spinlock_t mchdev_lock;
820
821 struct intel_ilk_power_mgmt {
822 u8 cur_delay;
823 u8 min_delay;
824 u8 max_delay;
825 u8 fmax;
826 u8 fstart;
827
828 u64 last_count1;
829 unsigned long last_time1;
830 unsigned long chipset_power;
831 u64 last_count2;
832 u64 last_time2;
833 unsigned long gfx_power;
834 u8 corr;
835
836 int c_m;
837 int r_t;
838 };
839
840 struct drm_i915_private;
841 struct i915_power_well;
842
843 struct i915_power_well_ops {
844 /*
845 * Synchronize the well's hw state to match the current sw state, for
846 * example enable/disable it based on the current refcount. Called
847 * during driver init and resume time, possibly after first calling
848 * the enable/disable handlers.
849 */
850 void (*sync_hw)(struct drm_i915_private *dev_priv,
851 struct i915_power_well *power_well);
852 /*
853 * Enable the well and resources that depend on it (for example
854 * interrupts located on the well). Called after the 0->1 refcount
855 * transition.
856 */
857 void (*enable)(struct drm_i915_private *dev_priv,
858 struct i915_power_well *power_well);
859 /*
860 * Disable the well and resources that depend on it. Called after
861 * the 1->0 refcount transition.
862 */
863 void (*disable)(struct drm_i915_private *dev_priv,
864 struct i915_power_well *power_well);
865 /* Returns the hw enabled state. */
866 bool (*is_enabled)(struct drm_i915_private *dev_priv,
867 struct i915_power_well *power_well);
868 };
869
870 /* Power well structure for haswell */
871 struct i915_power_well {
872 const char *name;
873 bool always_on;
874 /* power well enable/disable usage count */
875 int count;
876 /* cached hw enabled state */
877 bool hw_enabled;
878 u64 domains;
879 /* unique identifier for this power well */
880 enum i915_power_well_id id;
881 /*
882 * Arbitraty data associated with this power well. Platform and power
883 * well specific.
884 */
885 union {
886 struct {
887 enum dpio_phy phy;
888 } bxt;
889 struct {
890 /* Mask of pipes whose IRQ logic is backed by the pw */
891 u8 irq_pipe_mask;
892 /* The pw is backing the VGA functionality */
893 bool has_vga:1;
894 bool has_fuses:1;
895 } hsw;
896 };
897 const struct i915_power_well_ops *ops;
898 };
899
900 struct i915_power_domains {
901 /*
902 * Power wells needed for initialization at driver init and suspend
903 * time are on. They are kept on until after the first modeset.
904 */
905 bool init_power_on;
906 bool initializing;
907 int power_well_count;
908
909 struct mutex lock;
910 int domain_use_count[POWER_DOMAIN_NUM];
911 struct i915_power_well *power_wells;
912 };
913
914 #define MAX_L3_SLICES 2
915 struct intel_l3_parity {
916 u32 *remap_info[MAX_L3_SLICES];
917 struct work_struct error_work;
918 int which_slice;
919 };
920
921 struct i915_gem_mm {
922 /** Memory allocator for GTT stolen memory */
923 struct drm_mm stolen;
924 /** Protects the usage of the GTT stolen memory allocator. This is
925 * always the inner lock when overlapping with struct_mutex. */
926 struct mutex stolen_lock;
927
928 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
929 spinlock_t obj_lock;
930
931 /** List of all objects in gtt_space. Used to restore gtt
932 * mappings on resume */
933 struct list_head bound_list;
934 /**
935 * List of objects which are not bound to the GTT (thus
936 * are idle and not used by the GPU). These objects may or may
937 * not actually have any pages attached.
938 */
939 struct list_head unbound_list;
940
941 /** List of all objects in gtt_space, currently mmaped by userspace.
942 * All objects within this list must also be on bound_list.
943 */
944 struct list_head userfault_list;
945
946 /**
947 * List of objects which are pending destruction.
948 */
949 struct llist_head free_list;
950 struct work_struct free_work;
951 spinlock_t free_lock;
952 /**
953 * Count of objects pending destructions. Used to skip needlessly
954 * waiting on an RCU barrier if no objects are waiting to be freed.
955 */
956 atomic_t free_count;
957
958 /**
959 * Small stash of WC pages
960 */
961 struct pagestash wc_stash;
962
963 /**
964 * tmpfs instance used for shmem backed objects
965 */
966 struct vfsmount *gemfs;
967
968 /** PPGTT used for aliasing the PPGTT with the GTT */
969 struct i915_hw_ppgtt *aliasing_ppgtt;
970
971 struct notifier_block oom_notifier;
972 struct notifier_block vmap_notifier;
973 struct shrinker shrinker;
974
975 /** LRU list of objects with fence regs on them. */
976 struct list_head fence_list;
977
978 /**
979 * Workqueue to fault in userptr pages, flushed by the execbuf
980 * when required but otherwise left to userspace to try again
981 * on EAGAIN.
982 */
983 struct workqueue_struct *userptr_wq;
984
985 u64 unordered_timeline;
986
987 /* the indicator for dispatch video commands on two BSD rings */
988 atomic_t bsd_engine_dispatch_index;
989
990 /** Bit 6 swizzling required for X tiling */
991 uint32_t bit_6_swizzle_x;
992 /** Bit 6 swizzling required for Y tiling */
993 uint32_t bit_6_swizzle_y;
994
995 /* accounting, useful for userland debugging */
996 spinlock_t object_stat_lock;
997 u64 object_memory;
998 u32 object_count;
999 };
1000
1001 #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */
1002
1003 #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
1004 #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */
1005
1006 #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */
1007 #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */
1008
1009 #define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ) /* Reset but no recovery? */
1010
1011 #define DP_AUX_A 0x40
1012 #define DP_AUX_B 0x10
1013 #define DP_AUX_C 0x20
1014 #define DP_AUX_D 0x30
1015 #define DP_AUX_E 0x50
1016 #define DP_AUX_F 0x60
1017
1018 #define DDC_PIN_B 0x05
1019 #define DDC_PIN_C 0x04
1020 #define DDC_PIN_D 0x06
1021
1022 struct ddi_vbt_port_info {
1023 int max_tmds_clock;
1024
1025 /*
1026 * This is an index in the HDMI/DVI DDI buffer translation table.
1027 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1028 * populate this field.
1029 */
1030 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1031 uint8_t hdmi_level_shift;
1032
1033 uint8_t supports_dvi:1;
1034 uint8_t supports_hdmi:1;
1035 uint8_t supports_dp:1;
1036 uint8_t supports_edp:1;
1037
1038 uint8_t alternate_aux_channel;
1039 uint8_t alternate_ddc_pin;
1040
1041 uint8_t dp_boost_level;
1042 uint8_t hdmi_boost_level;
1043 int dp_max_link_rate; /* 0 for not limited by VBT */
1044 };
1045
1046 enum psr_lines_to_wait {
1047 PSR_0_LINES_TO_WAIT = 0,
1048 PSR_1_LINE_TO_WAIT,
1049 PSR_4_LINES_TO_WAIT,
1050 PSR_8_LINES_TO_WAIT
1051 };
1052
1053 struct intel_vbt_data {
1054 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1055 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1056
1057 /* Feature bits */
1058 unsigned int int_tv_support:1;
1059 unsigned int lvds_dither:1;
1060 unsigned int int_crt_support:1;
1061 unsigned int lvds_use_ssc:1;
1062 unsigned int int_lvds_support:1;
1063 unsigned int display_clock_mode:1;
1064 unsigned int fdi_rx_polarity_inverted:1;
1065 unsigned int panel_type:4;
1066 int lvds_ssc_freq;
1067 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1068
1069 enum drrs_support_type drrs_type;
1070
1071 struct {
1072 int rate;
1073 int lanes;
1074 int preemphasis;
1075 int vswing;
1076 bool low_vswing;
1077 bool initialized;
1078 int bpp;
1079 struct edp_power_seq pps;
1080 } edp;
1081
1082 struct {
1083 bool enable;
1084 bool full_link;
1085 bool require_aux_wakeup;
1086 int idle_frames;
1087 enum psr_lines_to_wait lines_to_wait;
1088 int tp1_wakeup_time_us;
1089 int tp2_tp3_wakeup_time_us;
1090 } psr;
1091
1092 struct {
1093 u16 pwm_freq_hz;
1094 bool present;
1095 bool active_low_pwm;
1096 u8 min_brightness; /* min_brightness/255 of max */
1097 u8 controller; /* brightness controller number */
1098 enum intel_backlight_type type;
1099 } backlight;
1100
1101 /* MIPI DSI */
1102 struct {
1103 u16 panel_id;
1104 struct mipi_config *config;
1105 struct mipi_pps_data *pps;
1106 u16 bl_ports;
1107 u16 cabc_ports;
1108 u8 seq_version;
1109 u32 size;
1110 u8 *data;
1111 const u8 *sequence[MIPI_SEQ_MAX];
1112 u8 *deassert_seq; /* Used by fixup_mipi_sequences() */
1113 } dsi;
1114
1115 int crt_ddc_pin;
1116
1117 int child_dev_num;
1118 struct child_device_config *child_dev;
1119
1120 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1121 struct sdvo_device_mapping sdvo_mappings[2];
1122 };
1123
1124 enum intel_ddb_partitioning {
1125 INTEL_DDB_PART_1_2,
1126 INTEL_DDB_PART_5_6, /* IVB+ */
1127 };
1128
1129 struct intel_wm_level {
1130 bool enable;
1131 uint32_t pri_val;
1132 uint32_t spr_val;
1133 uint32_t cur_val;
1134 uint32_t fbc_val;
1135 };
1136
1137 struct ilk_wm_values {
1138 uint32_t wm_pipe[3];
1139 uint32_t wm_lp[3];
1140 uint32_t wm_lp_spr[3];
1141 uint32_t wm_linetime[3];
1142 bool enable_fbc_wm;
1143 enum intel_ddb_partitioning partitioning;
1144 };
1145
1146 struct g4x_pipe_wm {
1147 uint16_t plane[I915_MAX_PLANES];
1148 uint16_t fbc;
1149 };
1150
1151 struct g4x_sr_wm {
1152 uint16_t plane;
1153 uint16_t cursor;
1154 uint16_t fbc;
1155 };
1156
1157 struct vlv_wm_ddl_values {
1158 uint8_t plane[I915_MAX_PLANES];
1159 };
1160
1161 struct vlv_wm_values {
1162 struct g4x_pipe_wm pipe[3];
1163 struct g4x_sr_wm sr;
1164 struct vlv_wm_ddl_values ddl[3];
1165 uint8_t level;
1166 bool cxsr;
1167 };
1168
1169 struct g4x_wm_values {
1170 struct g4x_pipe_wm pipe[2];
1171 struct g4x_sr_wm sr;
1172 struct g4x_sr_wm hpll;
1173 bool cxsr;
1174 bool hpll_en;
1175 bool fbc_en;
1176 };
1177
1178 struct skl_ddb_entry {
1179 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1180 };
1181
skl_ddb_entry_size(const struct skl_ddb_entry * entry)1182 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1183 {
1184 return entry->end - entry->start;
1185 }
1186
skl_ddb_entry_equal(const struct skl_ddb_entry * e1,const struct skl_ddb_entry * e2)1187 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1188 const struct skl_ddb_entry *e2)
1189 {
1190 if (e1->start == e2->start && e1->end == e2->end)
1191 return true;
1192
1193 return false;
1194 }
1195
1196 struct skl_ddb_allocation {
1197 /* packed/y */
1198 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1199 struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1200 u8 enabled_slices; /* GEN11 has configurable 2 slices */
1201 };
1202
1203 struct skl_ddb_values {
1204 unsigned dirty_pipes;
1205 struct skl_ddb_allocation ddb;
1206 };
1207
1208 struct skl_wm_level {
1209 bool plane_en;
1210 uint16_t plane_res_b;
1211 uint8_t plane_res_l;
1212 };
1213
1214 /* Stores plane specific WM parameters */
1215 struct skl_wm_params {
1216 bool x_tiled, y_tiled;
1217 bool rc_surface;
1218 bool is_planar;
1219 uint32_t width;
1220 uint8_t cpp;
1221 uint32_t plane_pixel_rate;
1222 uint32_t y_min_scanlines;
1223 uint32_t plane_bytes_per_line;
1224 uint_fixed_16_16_t plane_blocks_per_line;
1225 uint_fixed_16_16_t y_tile_minimum;
1226 uint32_t linetime_us;
1227 uint32_t dbuf_block_size;
1228 };
1229
1230 /*
1231 * This struct helps tracking the state needed for runtime PM, which puts the
1232 * device in PCI D3 state. Notice that when this happens, nothing on the
1233 * graphics device works, even register access, so we don't get interrupts nor
1234 * anything else.
1235 *
1236 * Every piece of our code that needs to actually touch the hardware needs to
1237 * either call intel_runtime_pm_get or call intel_display_power_get with the
1238 * appropriate power domain.
1239 *
1240 * Our driver uses the autosuspend delay feature, which means we'll only really
1241 * suspend if we stay with zero refcount for a certain amount of time. The
1242 * default value is currently very conservative (see intel_runtime_pm_enable), but
1243 * it can be changed with the standard runtime PM files from sysfs.
1244 *
1245 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1246 * goes back to false exactly before we reenable the IRQs. We use this variable
1247 * to check if someone is trying to enable/disable IRQs while they're supposed
1248 * to be disabled. This shouldn't happen and we'll print some error messages in
1249 * case it happens.
1250 *
1251 * For more, read the Documentation/power/runtime_pm.txt.
1252 */
1253 struct i915_runtime_pm {
1254 atomic_t wakeref_count;
1255 bool suspended;
1256 bool irqs_enabled;
1257 };
1258
1259 enum intel_pipe_crc_source {
1260 INTEL_PIPE_CRC_SOURCE_NONE,
1261 INTEL_PIPE_CRC_SOURCE_PLANE1,
1262 INTEL_PIPE_CRC_SOURCE_PLANE2,
1263 INTEL_PIPE_CRC_SOURCE_PF,
1264 INTEL_PIPE_CRC_SOURCE_PIPE,
1265 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1266 INTEL_PIPE_CRC_SOURCE_TV,
1267 INTEL_PIPE_CRC_SOURCE_DP_B,
1268 INTEL_PIPE_CRC_SOURCE_DP_C,
1269 INTEL_PIPE_CRC_SOURCE_DP_D,
1270 INTEL_PIPE_CRC_SOURCE_AUTO,
1271 INTEL_PIPE_CRC_SOURCE_MAX,
1272 };
1273
1274 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1275 struct intel_pipe_crc {
1276 spinlock_t lock;
1277 int skipped;
1278 enum intel_pipe_crc_source source;
1279 };
1280
1281 struct i915_frontbuffer_tracking {
1282 spinlock_t lock;
1283
1284 /*
1285 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1286 * scheduled flips.
1287 */
1288 unsigned busy_bits;
1289 unsigned flip_bits;
1290 };
1291
1292 struct i915_wa_reg {
1293 u32 addr;
1294 u32 value;
1295 /* bitmask representing WA bits */
1296 u32 mask;
1297 };
1298
1299 #define I915_MAX_WA_REGS 16
1300
1301 struct i915_workarounds {
1302 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1303 u32 count;
1304 };
1305
1306 struct i915_virtual_gpu {
1307 bool active;
1308 u32 caps;
1309 };
1310
1311 /* used in computing the new watermarks state */
1312 struct intel_wm_config {
1313 unsigned int num_pipes_active;
1314 bool sprites_enabled;
1315 bool sprites_scaled;
1316 };
1317
1318 struct i915_oa_format {
1319 u32 format;
1320 int size;
1321 };
1322
1323 struct i915_oa_reg {
1324 i915_reg_t addr;
1325 u32 value;
1326 };
1327
1328 struct i915_oa_config {
1329 char uuid[UUID_STRING_LEN + 1];
1330 int id;
1331
1332 const struct i915_oa_reg *mux_regs;
1333 u32 mux_regs_len;
1334 const struct i915_oa_reg *b_counter_regs;
1335 u32 b_counter_regs_len;
1336 const struct i915_oa_reg *flex_regs;
1337 u32 flex_regs_len;
1338
1339 struct attribute_group sysfs_metric;
1340 struct attribute *attrs[2];
1341 struct device_attribute sysfs_metric_id;
1342
1343 atomic_t ref_count;
1344 };
1345
1346 struct i915_perf_stream;
1347
1348 /**
1349 * struct i915_perf_stream_ops - the OPs to support a specific stream type
1350 */
1351 struct i915_perf_stream_ops {
1352 /**
1353 * @enable: Enables the collection of HW samples, either in response to
1354 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
1355 * without `I915_PERF_FLAG_DISABLED`.
1356 */
1357 void (*enable)(struct i915_perf_stream *stream);
1358
1359 /**
1360 * @disable: Disables the collection of HW samples, either in response
1361 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
1362 * the stream.
1363 */
1364 void (*disable)(struct i915_perf_stream *stream);
1365
1366 /**
1367 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1368 * once there is something ready to read() for the stream
1369 */
1370 void (*poll_wait)(struct i915_perf_stream *stream,
1371 struct file *file,
1372 poll_table *wait);
1373
1374 /**
1375 * @wait_unlocked: For handling a blocking read, wait until there is
1376 * something to ready to read() for the stream. E.g. wait on the same
1377 * wait queue that would be passed to poll_wait().
1378 */
1379 int (*wait_unlocked)(struct i915_perf_stream *stream);
1380
1381 /**
1382 * @read: Copy buffered metrics as records to userspace
1383 * **buf**: the userspace, destination buffer
1384 * **count**: the number of bytes to copy, requested by userspace
1385 * **offset**: zero at the start of the read, updated as the read
1386 * proceeds, it represents how many bytes have been copied so far and
1387 * the buffer offset for copying the next record.
1388 *
1389 * Copy as many buffered i915 perf samples and records for this stream
1390 * to userspace as will fit in the given buffer.
1391 *
1392 * Only write complete records; returning -%ENOSPC if there isn't room
1393 * for a complete record.
1394 *
1395 * Return any error condition that results in a short read such as
1396 * -%ENOSPC or -%EFAULT, even though these may be squashed before
1397 * returning to userspace.
1398 */
1399 int (*read)(struct i915_perf_stream *stream,
1400 char __user *buf,
1401 size_t count,
1402 size_t *offset);
1403
1404 /**
1405 * @destroy: Cleanup any stream specific resources.
1406 *
1407 * The stream will always be disabled before this is called.
1408 */
1409 void (*destroy)(struct i915_perf_stream *stream);
1410 };
1411
1412 /**
1413 * struct i915_perf_stream - state for a single open stream FD
1414 */
1415 struct i915_perf_stream {
1416 /**
1417 * @dev_priv: i915 drm device
1418 */
1419 struct drm_i915_private *dev_priv;
1420
1421 /**
1422 * @link: Links the stream into ``&drm_i915_private->streams``
1423 */
1424 struct list_head link;
1425
1426 /**
1427 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
1428 * properties given when opening a stream, representing the contents
1429 * of a single sample as read() by userspace.
1430 */
1431 u32 sample_flags;
1432
1433 /**
1434 * @sample_size: Considering the configured contents of a sample
1435 * combined with the required header size, this is the total size
1436 * of a single sample record.
1437 */
1438 int sample_size;
1439
1440 /**
1441 * @ctx: %NULL if measuring system-wide across all contexts or a
1442 * specific context that is being monitored.
1443 */
1444 struct i915_gem_context *ctx;
1445
1446 /**
1447 * @enabled: Whether the stream is currently enabled, considering
1448 * whether the stream was opened in a disabled state and based
1449 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
1450 */
1451 bool enabled;
1452
1453 /**
1454 * @ops: The callbacks providing the implementation of this specific
1455 * type of configured stream.
1456 */
1457 const struct i915_perf_stream_ops *ops;
1458
1459 /**
1460 * @oa_config: The OA configuration used by the stream.
1461 */
1462 struct i915_oa_config *oa_config;
1463 };
1464
1465 /**
1466 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
1467 */
1468 struct i915_oa_ops {
1469 /**
1470 * @is_valid_b_counter_reg: Validates register's address for
1471 * programming boolean counters for a particular platform.
1472 */
1473 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1474 u32 addr);
1475
1476 /**
1477 * @is_valid_mux_reg: Validates register's address for programming mux
1478 * for a particular platform.
1479 */
1480 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1481
1482 /**
1483 * @is_valid_flex_reg: Validates register's address for programming
1484 * flex EU filtering for a particular platform.
1485 */
1486 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1487
1488 /**
1489 * @init_oa_buffer: Resets the head and tail pointers of the
1490 * circular buffer for periodic OA reports.
1491 *
1492 * Called when first opening a stream for OA metrics, but also may be
1493 * called in response to an OA buffer overflow or other error
1494 * condition.
1495 *
1496 * Note it may be necessary to clear the full OA buffer here as part of
1497 * maintaining the invariable that new reports must be written to
1498 * zeroed memory for us to be able to reliable detect if an expected
1499 * report has not yet landed in memory. (At least on Haswell the OA
1500 * buffer tail pointer is not synchronized with reports being visible
1501 * to the CPU)
1502 */
1503 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1504
1505 /**
1506 * @enable_metric_set: Selects and applies any MUX configuration to set
1507 * up the Boolean and Custom (B/C) counters that are part of the
1508 * counter reports being sampled. May apply system constraints such as
1509 * disabling EU clock gating as required.
1510 */
1511 int (*enable_metric_set)(struct drm_i915_private *dev_priv,
1512 const struct i915_oa_config *oa_config);
1513
1514 /**
1515 * @disable_metric_set: Remove system constraints associated with using
1516 * the OA unit.
1517 */
1518 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1519
1520 /**
1521 * @oa_enable: Enable periodic sampling
1522 */
1523 void (*oa_enable)(struct drm_i915_private *dev_priv);
1524
1525 /**
1526 * @oa_disable: Disable periodic sampling
1527 */
1528 void (*oa_disable)(struct drm_i915_private *dev_priv);
1529
1530 /**
1531 * @read: Copy data from the circular OA buffer into a given userspace
1532 * buffer.
1533 */
1534 int (*read)(struct i915_perf_stream *stream,
1535 char __user *buf,
1536 size_t count,
1537 size_t *offset);
1538
1539 /**
1540 * @oa_hw_tail_read: read the OA tail pointer register
1541 *
1542 * In particular this enables us to share all the fiddly code for
1543 * handling the OA unit tail pointer race that affects multiple
1544 * generations.
1545 */
1546 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1547 };
1548
1549 struct intel_cdclk_state {
1550 unsigned int cdclk, vco, ref, bypass;
1551 u8 voltage_level;
1552 };
1553
1554 struct drm_i915_private {
1555 struct drm_device drm;
1556
1557 struct kmem_cache *objects;
1558 struct kmem_cache *vmas;
1559 struct kmem_cache *luts;
1560 struct kmem_cache *requests;
1561 struct kmem_cache *dependencies;
1562 struct kmem_cache *priorities;
1563
1564 const struct intel_device_info info;
1565 struct intel_driver_caps caps;
1566
1567 /**
1568 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
1569 * end of stolen which we can optionally use to create GEM objects
1570 * backed by stolen memory. Note that stolen_usable_size tells us
1571 * exactly how much of this we are actually allowed to use, given that
1572 * some portion of it is in fact reserved for use by hardware functions.
1573 */
1574 struct resource dsm;
1575 /**
1576 * Reseved portion of Data Stolen Memory
1577 */
1578 struct resource dsm_reserved;
1579
1580 /*
1581 * Stolen memory is segmented in hardware with different portions
1582 * offlimits to certain functions.
1583 *
1584 * The drm_mm is initialised to the total accessible range, as found
1585 * from the PCI config. On Broadwell+, this is further restricted to
1586 * avoid the first page! The upper end of stolen memory is reserved for
1587 * hardware functions and similarly removed from the accessible range.
1588 */
1589 resource_size_t stolen_usable_size; /* Total size minus reserved ranges */
1590
1591 void __iomem *regs;
1592
1593 struct intel_uncore uncore;
1594
1595 struct i915_virtual_gpu vgpu;
1596
1597 struct intel_gvt *gvt;
1598
1599 struct intel_wopcm wopcm;
1600
1601 struct intel_huc huc;
1602 struct intel_guc guc;
1603
1604 struct intel_csr csr;
1605
1606 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1607
1608 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1609 * controller on different i2c buses. */
1610 struct mutex gmbus_mutex;
1611
1612 /**
1613 * Base address of the gmbus and gpio block.
1614 */
1615 uint32_t gpio_mmio_base;
1616
1617 /* MMIO base address for MIPI regs */
1618 uint32_t mipi_mmio_base;
1619
1620 uint32_t psr_mmio_base;
1621
1622 uint32_t pps_mmio_base;
1623
1624 wait_queue_head_t gmbus_wait_queue;
1625
1626 struct pci_dev *bridge_dev;
1627 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1628 /* Context used internally to idle the GPU and setup initial state */
1629 struct i915_gem_context *kernel_context;
1630 /* Context only to be used for injecting preemption commands */
1631 struct i915_gem_context *preempt_context;
1632 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1633 [MAX_ENGINE_INSTANCE + 1];
1634
1635 struct drm_dma_handle *status_page_dmah;
1636 struct resource mch_res;
1637
1638 /* protects the irq masks */
1639 spinlock_t irq_lock;
1640
1641 bool display_irqs_enabled;
1642
1643 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1644 struct pm_qos_request pm_qos;
1645
1646 /* Sideband mailbox protection */
1647 struct mutex sb_lock;
1648
1649 /** Cached value of IMR to avoid reads in updating the bitfield */
1650 union {
1651 u32 irq_mask;
1652 u32 de_irq_mask[I915_MAX_PIPES];
1653 };
1654 u32 gt_irq_mask;
1655 u32 pm_imr;
1656 u32 pm_ier;
1657 u32 pm_rps_events;
1658 u32 pm_guc_events;
1659 u32 pipestat_irq_mask[I915_MAX_PIPES];
1660
1661 struct i915_hotplug hotplug;
1662 struct intel_fbc fbc;
1663 struct i915_drrs drrs;
1664 struct intel_opregion opregion;
1665 struct intel_vbt_data vbt;
1666
1667 bool preserve_bios_swizzle;
1668
1669 /* overlay */
1670 struct intel_overlay *overlay;
1671
1672 /* backlight registers and fields in struct intel_panel */
1673 struct mutex backlight_lock;
1674
1675 /* LVDS info */
1676 bool no_aux_handshake;
1677
1678 /* protects panel power sequencer state */
1679 struct mutex pps_mutex;
1680
1681 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1682 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1683
1684 unsigned int fsb_freq, mem_freq, is_ddr3;
1685 unsigned int skl_preferred_vco_freq;
1686 unsigned int max_cdclk_freq;
1687
1688 unsigned int max_dotclk_freq;
1689 unsigned int rawclk_freq;
1690 unsigned int hpll_freq;
1691 unsigned int fdi_pll_freq;
1692 unsigned int czclk_freq;
1693
1694 struct {
1695 /*
1696 * The current logical cdclk state.
1697 * See intel_atomic_state.cdclk.logical
1698 *
1699 * For reading holding any crtc lock is sufficient,
1700 * for writing must hold all of them.
1701 */
1702 struct intel_cdclk_state logical;
1703 /*
1704 * The current actual cdclk state.
1705 * See intel_atomic_state.cdclk.actual
1706 */
1707 struct intel_cdclk_state actual;
1708 /* The current hardware cdclk state */
1709 struct intel_cdclk_state hw;
1710 } cdclk;
1711
1712 /**
1713 * wq - Driver workqueue for GEM.
1714 *
1715 * NOTE: Work items scheduled here are not allowed to grab any modeset
1716 * locks, for otherwise the flushing done in the pageflip code will
1717 * result in deadlocks.
1718 */
1719 struct workqueue_struct *wq;
1720
1721 /* ordered wq for modesets */
1722 struct workqueue_struct *modeset_wq;
1723
1724 /* Display functions */
1725 struct drm_i915_display_funcs display;
1726
1727 /* PCH chipset type */
1728 enum intel_pch pch_type;
1729 unsigned short pch_id;
1730
1731 unsigned long quirks;
1732
1733 struct drm_atomic_state *modeset_restore_state;
1734 struct drm_modeset_acquire_ctx reset_ctx;
1735
1736 struct i915_ggtt ggtt; /* VM representing the global address space */
1737
1738 struct i915_gem_mm mm;
1739 DECLARE_HASHTABLE(mm_structs, 7);
1740 struct mutex mm_lock;
1741
1742 struct intel_ppat ppat;
1743
1744 /* Kernel Modesetting */
1745
1746 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1747 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1748
1749 #ifdef CONFIG_DEBUG_FS
1750 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1751 #endif
1752
1753 /* dpll and cdclk state is protected by connection_mutex */
1754 int num_shared_dpll;
1755 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1756 const struct intel_dpll_mgr *dpll_mgr;
1757
1758 /*
1759 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1760 * Must be global rather than per dpll, because on some platforms
1761 * plls share registers.
1762 */
1763 struct mutex dpll_lock;
1764
1765 unsigned int active_crtcs;
1766 /* minimum acceptable cdclk for each pipe */
1767 int min_cdclk[I915_MAX_PIPES];
1768 /* minimum acceptable voltage level for each pipe */
1769 u8 min_voltage_level[I915_MAX_PIPES];
1770
1771 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1772
1773 struct i915_workarounds workarounds;
1774
1775 struct i915_frontbuffer_tracking fb_tracking;
1776
1777 struct intel_atomic_helper {
1778 struct llist_head free_list;
1779 struct work_struct free_work;
1780 } atomic_helper;
1781
1782 u16 orig_clock;
1783
1784 bool mchbar_need_disable;
1785
1786 struct intel_l3_parity l3_parity;
1787
1788 /* Cannot be determined by PCIID. You must always read a register. */
1789 u32 edram_cap;
1790
1791 /*
1792 * Protects RPS/RC6 register access and PCU communication.
1793 * Must be taken after struct_mutex if nested. Note that
1794 * this lock may be held for long periods of time when
1795 * talking to hw - so only take it when talking to hw!
1796 */
1797 struct mutex pcu_lock;
1798
1799 /* gen6+ GT PM state */
1800 struct intel_gen6_power_mgmt gt_pm;
1801
1802 /* ilk-only ips/rps state. Everything in here is protected by the global
1803 * mchdev_lock in intel_pm.c */
1804 struct intel_ilk_power_mgmt ips;
1805
1806 struct i915_power_domains power_domains;
1807
1808 struct i915_psr psr;
1809
1810 struct i915_gpu_error gpu_error;
1811
1812 struct drm_i915_gem_object *vlv_pctx;
1813
1814 /* list of fbdev register on this device */
1815 struct intel_fbdev *fbdev;
1816 struct work_struct fbdev_suspend_work;
1817
1818 struct drm_property *broadcast_rgb_property;
1819 struct drm_property *force_audio_property;
1820
1821 /* hda/i915 audio component */
1822 struct i915_audio_component *audio_component;
1823 bool audio_component_registered;
1824 /**
1825 * av_mutex - mutex for audio/video sync
1826 *
1827 */
1828 struct mutex av_mutex;
1829
1830 struct {
1831 struct list_head list;
1832 struct llist_head free_list;
1833 struct work_struct free_work;
1834
1835 /* The hw wants to have a stable context identifier for the
1836 * lifetime of the context (for OA, PASID, faults, etc).
1837 * This is limited in execlists to 21 bits.
1838 */
1839 struct ida hw_ida;
1840 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1841 #define MAX_GUC_CONTEXT_HW_ID (1 << 20) /* exclusive */
1842 #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */
1843 } contexts;
1844
1845 u32 fdi_rx_config;
1846
1847 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1848 u32 chv_phy_control;
1849 /*
1850 * Shadows for CHV DPLL_MD regs to keep the state
1851 * checker somewhat working in the presence hardware
1852 * crappiness (can't read out DPLL_MD for pipes B & C).
1853 */
1854 u32 chv_dpll_md[I915_MAX_PIPES];
1855 u32 bxt_phy_grc;
1856
1857 u32 suspend_count;
1858 bool power_domains_suspended;
1859 struct i915_suspend_saved_registers regfile;
1860 struct vlv_s0ix_state vlv_s0ix_state;
1861
1862 enum {
1863 I915_SAGV_UNKNOWN = 0,
1864 I915_SAGV_DISABLED,
1865 I915_SAGV_ENABLED,
1866 I915_SAGV_NOT_CONTROLLED
1867 } sagv_status;
1868
1869 struct {
1870 /*
1871 * Raw watermark latency values:
1872 * in 0.1us units for WM0,
1873 * in 0.5us units for WM1+.
1874 */
1875 /* primary */
1876 uint16_t pri_latency[5];
1877 /* sprite */
1878 uint16_t spr_latency[5];
1879 /* cursor */
1880 uint16_t cur_latency[5];
1881 /*
1882 * Raw watermark memory latency values
1883 * for SKL for all 8 levels
1884 * in 1us units.
1885 */
1886 uint16_t skl_latency[8];
1887
1888 /* current hardware state */
1889 union {
1890 struct ilk_wm_values hw;
1891 struct skl_ddb_values skl_hw;
1892 struct vlv_wm_values vlv;
1893 struct g4x_wm_values g4x;
1894 };
1895
1896 uint8_t max_level;
1897
1898 /*
1899 * Should be held around atomic WM register writing; also
1900 * protects * intel_crtc->wm.active and
1901 * cstate->wm.need_postvbl_update.
1902 */
1903 struct mutex wm_mutex;
1904
1905 /*
1906 * Set during HW readout of watermarks/DDB. Some platforms
1907 * need to know when we're still using BIOS-provided values
1908 * (which we don't fully trust).
1909 */
1910 bool distrust_bios_wm;
1911 } wm;
1912
1913 struct i915_runtime_pm runtime_pm;
1914
1915 struct {
1916 bool initialized;
1917
1918 struct kobject *metrics_kobj;
1919 struct ctl_table_header *sysctl_header;
1920
1921 /*
1922 * Lock associated with adding/modifying/removing OA configs
1923 * in dev_priv->perf.metrics_idr.
1924 */
1925 struct mutex metrics_lock;
1926
1927 /*
1928 * List of dynamic configurations, you need to hold
1929 * dev_priv->perf.metrics_lock to access it.
1930 */
1931 struct idr metrics_idr;
1932
1933 /*
1934 * Lock associated with anything below within this structure
1935 * except exclusive_stream.
1936 */
1937 struct mutex lock;
1938 struct list_head streams;
1939
1940 struct {
1941 /*
1942 * The stream currently using the OA unit. If accessed
1943 * outside a syscall associated to its file
1944 * descriptor, you need to hold
1945 * dev_priv->drm.struct_mutex.
1946 */
1947 struct i915_perf_stream *exclusive_stream;
1948
1949 struct intel_context *pinned_ctx;
1950 u32 specific_ctx_id;
1951 u32 specific_ctx_id_mask;
1952
1953 struct hrtimer poll_check_timer;
1954 wait_queue_head_t poll_wq;
1955 bool pollin;
1956
1957 /**
1958 * For rate limiting any notifications of spurious
1959 * invalid OA reports
1960 */
1961 struct ratelimit_state spurious_report_rs;
1962
1963 bool periodic;
1964 int period_exponent;
1965
1966 struct i915_oa_config test_config;
1967
1968 struct {
1969 struct i915_vma *vma;
1970 u8 *vaddr;
1971 u32 last_ctx_id;
1972 int format;
1973 int format_size;
1974
1975 /**
1976 * Locks reads and writes to all head/tail state
1977 *
1978 * Consider: the head and tail pointer state
1979 * needs to be read consistently from a hrtimer
1980 * callback (atomic context) and read() fop
1981 * (user context) with tail pointer updates
1982 * happening in atomic context and head updates
1983 * in user context and the (unlikely)
1984 * possibility of read() errors needing to
1985 * reset all head/tail state.
1986 *
1987 * Note: Contention or performance aren't
1988 * currently a significant concern here
1989 * considering the relatively low frequency of
1990 * hrtimer callbacks (5ms period) and that
1991 * reads typically only happen in response to a
1992 * hrtimer event and likely complete before the
1993 * next callback.
1994 *
1995 * Note: This lock is not held *while* reading
1996 * and copying data to userspace so the value
1997 * of head observed in htrimer callbacks won't
1998 * represent any partial consumption of data.
1999 */
2000 spinlock_t ptr_lock;
2001
2002 /**
2003 * One 'aging' tail pointer and one 'aged'
2004 * tail pointer ready to used for reading.
2005 *
2006 * Initial values of 0xffffffff are invalid
2007 * and imply that an update is required
2008 * (and should be ignored by an attempted
2009 * read)
2010 */
2011 struct {
2012 u32 offset;
2013 } tails[2];
2014
2015 /**
2016 * Index for the aged tail ready to read()
2017 * data up to.
2018 */
2019 unsigned int aged_tail_idx;
2020
2021 /**
2022 * A monotonic timestamp for when the current
2023 * aging tail pointer was read; used to
2024 * determine when it is old enough to trust.
2025 */
2026 u64 aging_timestamp;
2027
2028 /**
2029 * Although we can always read back the head
2030 * pointer register, we prefer to avoid
2031 * trusting the HW state, just to avoid any
2032 * risk that some hardware condition could
2033 * somehow bump the head pointer unpredictably
2034 * and cause us to forward the wrong OA buffer
2035 * data to userspace.
2036 */
2037 u32 head;
2038 } oa_buffer;
2039
2040 u32 gen7_latched_oastatus1;
2041 u32 ctx_oactxctrl_offset;
2042 u32 ctx_flexeu0_offset;
2043
2044 /**
2045 * The RPT_ID/reason field for Gen8+ includes a bit
2046 * to determine if the CTX ID in the report is valid
2047 * but the specific bit differs between Gen 8 and 9
2048 */
2049 u32 gen8_valid_ctx_bit;
2050
2051 struct i915_oa_ops ops;
2052 const struct i915_oa_format *oa_formats;
2053 } oa;
2054 } perf;
2055
2056 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2057 struct {
2058 void (*resume)(struct drm_i915_private *);
2059 void (*cleanup_engine)(struct intel_engine_cs *engine);
2060
2061 struct list_head timelines;
2062
2063 struct list_head active_rings;
2064 struct list_head closed_vma;
2065 u32 active_requests;
2066 u32 request_serial;
2067
2068 /**
2069 * Is the GPU currently considered idle, or busy executing
2070 * userspace requests? Whilst idle, we allow runtime power
2071 * management to power down the hardware and display clocks.
2072 * In order to reduce the effect on performance, there
2073 * is a slight delay before we do so.
2074 */
2075 bool awake;
2076
2077 /**
2078 * The number of times we have woken up.
2079 */
2080 unsigned int epoch;
2081 #define I915_EPOCH_INVALID 0
2082
2083 /**
2084 * We leave the user IRQ off as much as possible,
2085 * but this means that requests will finish and never
2086 * be retired once the system goes idle. Set a timer to
2087 * fire periodically while the ring is running. When it
2088 * fires, go retire requests.
2089 */
2090 struct delayed_work retire_work;
2091
2092 /**
2093 * When we detect an idle GPU, we want to turn on
2094 * powersaving features. So once we see that there
2095 * are no more requests outstanding and no more
2096 * arrive within a small period of time, we fire
2097 * off the idle_work.
2098 */
2099 struct delayed_work idle_work;
2100
2101 ktime_t last_init_time;
2102 } gt;
2103
2104 /* perform PHY state sanity checks? */
2105 bool chv_phy_assert[2];
2106
2107 bool ipc_enabled;
2108
2109 /* Used to save the pipe-to-encoder mapping for audio */
2110 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2111
2112 /* necessary resource sharing with HDMI LPE audio driver. */
2113 struct {
2114 struct platform_device *platdev;
2115 int irq;
2116 } lpe_audio;
2117
2118 struct i915_pmu pmu;
2119
2120 /*
2121 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2122 * will be rejected. Instead look for a better place.
2123 */
2124 };
2125
to_i915(const struct drm_device * dev)2126 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2127 {
2128 return container_of(dev, struct drm_i915_private, drm);
2129 }
2130
kdev_to_i915(struct device * kdev)2131 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2132 {
2133 return to_i915(dev_get_drvdata(kdev));
2134 }
2135
wopcm_to_i915(struct intel_wopcm * wopcm)2136 static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2137 {
2138 return container_of(wopcm, struct drm_i915_private, wopcm);
2139 }
2140
guc_to_i915(struct intel_guc * guc)2141 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2142 {
2143 return container_of(guc, struct drm_i915_private, guc);
2144 }
2145
huc_to_i915(struct intel_huc * huc)2146 static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2147 {
2148 return container_of(huc, struct drm_i915_private, huc);
2149 }
2150
2151 /* Simple iterator over all initialised engines */
2152 #define for_each_engine(engine__, dev_priv__, id__) \
2153 for ((id__) = 0; \
2154 (id__) < I915_NUM_ENGINES; \
2155 (id__)++) \
2156 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2157
2158 /* Iterator over subset of engines selected by mask */
2159 #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2160 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
2161 (tmp__) ? \
2162 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2163 0;)
2164
2165 enum hdmi_force_audio {
2166 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
2167 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
2168 HDMI_AUDIO_AUTO, /* trust EDID */
2169 HDMI_AUDIO_ON, /* force turn on HDMI audio */
2170 };
2171
2172 #define I915_GTT_OFFSET_NONE ((u32)-1)
2173
2174 /*
2175 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2176 * considered to be the frontbuffer for the given plane interface-wise. This
2177 * doesn't mean that the hw necessarily already scans it out, but that any
2178 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2179 *
2180 * We have one bit per pipe and per scanout plane type.
2181 */
2182 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2183 #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2184 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2185 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2186 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2187 })
2188 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2189 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2190 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2191 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2192 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2193
2194 /*
2195 * Optimised SGL iterator for GEM objects
2196 */
2197 static __always_inline struct sgt_iter {
2198 struct scatterlist *sgp;
2199 union {
2200 unsigned long pfn;
2201 dma_addr_t dma;
2202 };
2203 unsigned int curr;
2204 unsigned int max;
__sgt_iter(struct scatterlist * sgl,bool dma)2205 } __sgt_iter(struct scatterlist *sgl, bool dma) {
2206 struct sgt_iter s = { .sgp = sgl };
2207
2208 if (s.sgp) {
2209 s.max = s.curr = s.sgp->offset;
2210 s.max += s.sgp->length;
2211 if (dma)
2212 s.dma = sg_dma_address(s.sgp);
2213 else
2214 s.pfn = page_to_pfn(sg_page(s.sgp));
2215 }
2216
2217 return s;
2218 }
2219
____sg_next(struct scatterlist * sg)2220 static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2221 {
2222 ++sg;
2223 if (unlikely(sg_is_chain(sg)))
2224 sg = sg_chain_ptr(sg);
2225 return sg;
2226 }
2227
2228 /**
2229 * __sg_next - return the next scatterlist entry in a list
2230 * @sg: The current sg entry
2231 *
2232 * Description:
2233 * If the entry is the last, return NULL; otherwise, step to the next
2234 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2235 * otherwise just return the pointer to the current element.
2236 **/
__sg_next(struct scatterlist * sg)2237 static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2238 {
2239 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2240 }
2241
2242 /**
2243 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2244 * @__dmap: DMA address (output)
2245 * @__iter: 'struct sgt_iter' (iterator state, internal)
2246 * @__sgt: sg_table to iterate over (input)
2247 */
2248 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2249 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2250 ((__dmap) = (__iter).dma + (__iter).curr); \
2251 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2252 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2253
2254 /**
2255 * for_each_sgt_page - iterate over the pages of the given sg_table
2256 * @__pp: page pointer (output)
2257 * @__iter: 'struct sgt_iter' (iterator state, internal)
2258 * @__sgt: sg_table to iterate over (input)
2259 */
2260 #define for_each_sgt_page(__pp, __iter, __sgt) \
2261 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2262 ((__pp) = (__iter).pfn == 0 ? NULL : \
2263 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2264 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2265 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2266
i915_sg_page_sizes(struct scatterlist * sg)2267 static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2268 {
2269 unsigned int page_sizes;
2270
2271 page_sizes = 0;
2272 while (sg) {
2273 GEM_BUG_ON(sg->offset);
2274 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2275 page_sizes |= sg->length;
2276 sg = __sg_next(sg);
2277 }
2278
2279 return page_sizes;
2280 }
2281
i915_sg_segment_size(void)2282 static inline unsigned int i915_sg_segment_size(void)
2283 {
2284 unsigned int size = swiotlb_max_segment();
2285
2286 if (size == 0)
2287 return SCATTERLIST_MAX_SEGMENT;
2288
2289 size = rounddown(size, PAGE_SIZE);
2290 /* swiotlb_max_segment_size can return 1 byte when it means one page. */
2291 if (size < PAGE_SIZE)
2292 size = PAGE_SIZE;
2293
2294 return size;
2295 }
2296
2297 static inline const struct intel_device_info *
intel_info(const struct drm_i915_private * dev_priv)2298 intel_info(const struct drm_i915_private *dev_priv)
2299 {
2300 return &dev_priv->info;
2301 }
2302
2303 #define INTEL_INFO(dev_priv) intel_info((dev_priv))
2304 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2305
2306 #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2307 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2308
2309 #define REVID_FOREVER 0xff
2310 #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2311
2312 #define GEN_FOREVER (0)
2313
2314 #define INTEL_GEN_MASK(s, e) ( \
2315 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2316 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2317 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2318 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2319 )
2320
2321 /*
2322 * Returns true if Gen is in inclusive range [Start, End].
2323 *
2324 * Use GEN_FOREVER for unbound start and or end.
2325 */
2326 #define IS_GEN(dev_priv, s, e) \
2327 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2328
2329 /*
2330 * Return true if revision is in range [since,until] inclusive.
2331 *
2332 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2333 */
2334 #define IS_REVID(p, since, until) \
2335 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2336
2337 #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2338
2339 #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2340 #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2341 #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2342 #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2343 #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2344 #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2345 #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2346 #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2347 #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2348 #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2349 #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2350 #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2351 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2352 #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2353 #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2354 #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2355 #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2356 #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2357 #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2358 #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2359 (dev_priv)->info.gt == 1)
2360 #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2361 #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2362 #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2363 #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2364 #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2365 #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2366 #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2367 #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2368 #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2369 #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2370 #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2371 #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2372 #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2373 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2374 #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2375 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2376 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2377 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2378 /* ULX machines are also considered ULT. */
2379 #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2380 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2381 #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2382 (dev_priv)->info.gt == 3)
2383 #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2384 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2385 #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2386 (dev_priv)->info.gt == 3)
2387 /* ULX machines are also considered ULT. */
2388 #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2389 INTEL_DEVID(dev_priv) == 0x0A1E)
2390 #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2391 INTEL_DEVID(dev_priv) == 0x1913 || \
2392 INTEL_DEVID(dev_priv) == 0x1916 || \
2393 INTEL_DEVID(dev_priv) == 0x1921 || \
2394 INTEL_DEVID(dev_priv) == 0x1926)
2395 #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2396 INTEL_DEVID(dev_priv) == 0x1915 || \
2397 INTEL_DEVID(dev_priv) == 0x191E)
2398 #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2399 INTEL_DEVID(dev_priv) == 0x5913 || \
2400 INTEL_DEVID(dev_priv) == 0x5916 || \
2401 INTEL_DEVID(dev_priv) == 0x5921 || \
2402 INTEL_DEVID(dev_priv) == 0x5926)
2403 #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2404 INTEL_DEVID(dev_priv) == 0x5915 || \
2405 INTEL_DEVID(dev_priv) == 0x591E)
2406 #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2407 (dev_priv)->info.gt == 2)
2408 #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2409 (dev_priv)->info.gt == 3)
2410 #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2411 (dev_priv)->info.gt == 4)
2412 #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2413 (dev_priv)->info.gt == 2)
2414 #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2415 (dev_priv)->info.gt == 3)
2416 #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2417 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2418 #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2419 (dev_priv)->info.gt == 2)
2420 #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2421 (dev_priv)->info.gt == 3)
2422 #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
2423 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2424
2425 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2426
2427 #define SKL_REVID_A0 0x0
2428 #define SKL_REVID_B0 0x1
2429 #define SKL_REVID_C0 0x2
2430 #define SKL_REVID_D0 0x3
2431 #define SKL_REVID_E0 0x4
2432 #define SKL_REVID_F0 0x5
2433 #define SKL_REVID_G0 0x6
2434 #define SKL_REVID_H0 0x7
2435
2436 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2437
2438 #define BXT_REVID_A0 0x0
2439 #define BXT_REVID_A1 0x1
2440 #define BXT_REVID_B0 0x3
2441 #define BXT_REVID_B_LAST 0x8
2442 #define BXT_REVID_C0 0x9
2443
2444 #define IS_BXT_REVID(dev_priv, since, until) \
2445 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2446
2447 #define KBL_REVID_A0 0x0
2448 #define KBL_REVID_B0 0x1
2449 #define KBL_REVID_C0 0x2
2450 #define KBL_REVID_D0 0x3
2451 #define KBL_REVID_E0 0x4
2452
2453 #define IS_KBL_REVID(dev_priv, since, until) \
2454 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2455
2456 #define GLK_REVID_A0 0x0
2457 #define GLK_REVID_A1 0x1
2458
2459 #define IS_GLK_REVID(dev_priv, since, until) \
2460 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2461
2462 #define CNL_REVID_A0 0x0
2463 #define CNL_REVID_B0 0x1
2464 #define CNL_REVID_C0 0x2
2465
2466 #define IS_CNL_REVID(p, since, until) \
2467 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2468
2469 #define ICL_REVID_A0 0x0
2470 #define ICL_REVID_A2 0x1
2471 #define ICL_REVID_B0 0x3
2472 #define ICL_REVID_B2 0x4
2473 #define ICL_REVID_C0 0x5
2474
2475 #define IS_ICL_REVID(p, since, until) \
2476 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2477
2478 /*
2479 * The genX designation typically refers to the render engine, so render
2480 * capability related checks should use IS_GEN, while display and other checks
2481 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2482 * chips, etc.).
2483 */
2484 #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2485 #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2486 #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2487 #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2488 #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2489 #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2490 #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2491 #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2492 #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2493 #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
2494
2495 #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2496 #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2497 #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2498
2499 #define ENGINE_MASK(id) BIT(id)
2500 #define RENDER_RING ENGINE_MASK(RCS)
2501 #define BSD_RING ENGINE_MASK(VCS)
2502 #define BLT_RING ENGINE_MASK(BCS)
2503 #define VEBOX_RING ENGINE_MASK(VECS)
2504 #define BSD2_RING ENGINE_MASK(VCS2)
2505 #define BSD3_RING ENGINE_MASK(VCS3)
2506 #define BSD4_RING ENGINE_MASK(VCS4)
2507 #define VEBOX2_RING ENGINE_MASK(VECS2)
2508 #define ALL_ENGINES (~0)
2509
2510 #define HAS_ENGINE(dev_priv, id) \
2511 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2512
2513 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2514 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2515 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2516 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2517
2518 #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
2519
2520 #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2521 #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2522 #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2523 #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2524 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2525
2526 #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2527
2528 #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2529 ((dev_priv)->info.has_logical_ring_contexts)
2530 #define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2531 ((dev_priv)->info.has_logical_ring_elsq)
2532 #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2533 ((dev_priv)->info.has_logical_ring_preemption)
2534
2535 #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2536
2537 #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
2538 #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
2539 #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
2540 #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2541 GEM_BUG_ON((sizes) == 0); \
2542 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2543 })
2544
2545 #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2546 #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2547 ((dev_priv)->info.overlay_needs_physical)
2548
2549 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2550 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2551
2552 /* WaRsDisableCoarsePowerGating:skl,cnl */
2553 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2554 (IS_CANNONLAKE(dev_priv) || \
2555 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2556
2557 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2558 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2559 IS_GEMINILAKE(dev_priv) || \
2560 IS_KABYLAKE(dev_priv))
2561
2562 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2563 * rows, which changed the alignment requirements and fence programming.
2564 */
2565 #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2566 !(IS_I915G(dev_priv) || \
2567 IS_I915GM(dev_priv)))
2568 #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2569 #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2570
2571 #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2572 #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2573 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2574
2575 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2576
2577 #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2578
2579 #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2580 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2581 #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2582
2583 #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2584 #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2585 #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
2586
2587 #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2588
2589 #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2590 #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2591
2592 #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
2593
2594 /*
2595 * For now, anything with a GuC requires uCode loading, and then supports
2596 * command submission once loaded. But these are logically independent
2597 * properties, so we have separate macros to test them.
2598 */
2599 #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2600 #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2601 #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2602 #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2603
2604 /* For now, anything with a GuC has also HuC */
2605 #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2606 #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2607
2608 /* Having a GuC is not the same as using a GuC */
2609 #define USES_GUC(dev_priv) intel_uc_is_using_guc()
2610 #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
2611 #define USES_HUC(dev_priv) intel_uc_is_using_huc()
2612
2613 #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2614
2615 #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2616
2617 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
2618 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2619 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2620 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2621 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2622 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2623 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2624 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2625 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2626 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2627 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2628 #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2629 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2630 #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2631 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2632 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2633 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2634
2635 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2636 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2637 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2638 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2639 #define HAS_PCH_CNP_LP(dev_priv) \
2640 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2641 #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2642 #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2643 #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2644 #define HAS_PCH_LPT_LP(dev_priv) \
2645 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2646 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2647 #define HAS_PCH_LPT_H(dev_priv) \
2648 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2649 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2650 #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2651 #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2652 #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2653 #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2654
2655 #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2656
2657 #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2658
2659 /* DPF == dynamic parity feature */
2660 #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2661 #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2662 2 : HAS_L3_DPF(dev_priv))
2663
2664 #define GT_FREQUENCY_MULTIPLIER 50
2665 #define GEN9_FREQ_SCALER 3
2666
2667 #include "i915_trace.h"
2668
intel_vtd_active(void)2669 static inline bool intel_vtd_active(void)
2670 {
2671 #ifdef CONFIG_INTEL_IOMMU
2672 if (intel_iommu_gfx_mapped)
2673 return true;
2674 #endif
2675 return false;
2676 }
2677
intel_scanout_needs_vtd_wa(struct drm_i915_private * dev_priv)2678 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2679 {
2680 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2681 }
2682
2683 static inline bool
intel_ggtt_update_needs_vtd_wa(struct drm_i915_private * dev_priv)2684 intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2685 {
2686 return IS_BROXTON(dev_priv) && intel_vtd_active();
2687 }
2688
2689 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2690 int enable_ppgtt);
2691
2692 /* i915_drv.c */
2693 void __printf(3, 4)
2694 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
2695 const char *fmt, ...);
2696
2697 #define i915_report_error(dev_priv, fmt, ...) \
2698 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2699
2700 #ifdef CONFIG_COMPAT
2701 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2702 unsigned long arg);
2703 #else
2704 #define i915_compat_ioctl NULL
2705 #endif
2706 extern const struct dev_pm_ops i915_pm_ops;
2707
2708 extern int i915_driver_load(struct pci_dev *pdev,
2709 const struct pci_device_id *ent);
2710 extern void i915_driver_unload(struct drm_device *dev);
2711 extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2712 extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2713
2714 extern void i915_reset(struct drm_i915_private *i915,
2715 unsigned int stalled_mask,
2716 const char *reason);
2717 extern int i915_reset_engine(struct intel_engine_cs *engine,
2718 const char *reason);
2719
2720 extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2721 extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2722 extern int intel_guc_reset_engine(struct intel_guc *guc,
2723 struct intel_engine_cs *engine);
2724 extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2725 extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2726 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2727 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2728 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2729 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2730 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2731
2732 int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2733 int intel_engines_init(struct drm_i915_private *dev_priv);
2734
2735 u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2736
2737 /* intel_hotplug.c */
2738 void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2739 u32 pin_mask, u32 long_mask);
2740 void intel_hpd_init(struct drm_i915_private *dev_priv);
2741 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2742 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2743 enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2744 enum port port);
2745 bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2746 void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2747
2748 /* i915_irq.c */
i915_queue_hangcheck(struct drm_i915_private * dev_priv)2749 static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2750 {
2751 unsigned long delay;
2752
2753 if (unlikely(!i915_modparams.enable_hangcheck))
2754 return;
2755
2756 /* Don't continually defer the hangcheck so that it is always run at
2757 * least once after work has been scheduled on any ring. Otherwise,
2758 * we will ignore a hung ring if a second ring is kept busy.
2759 */
2760
2761 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2762 queue_delayed_work(system_long_wq,
2763 &dev_priv->gpu_error.hangcheck_work, delay);
2764 }
2765
2766 __printf(4, 5)
2767 void i915_handle_error(struct drm_i915_private *dev_priv,
2768 u32 engine_mask,
2769 unsigned long flags,
2770 const char *fmt, ...);
2771 #define I915_ERROR_CAPTURE BIT(0)
2772
2773 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2774 extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2775 int intel_irq_install(struct drm_i915_private *dev_priv);
2776 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2777
intel_gvt_active(struct drm_i915_private * dev_priv)2778 static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2779 {
2780 return dev_priv->gvt;
2781 }
2782
intel_vgpu_active(struct drm_i915_private * dev_priv)2783 static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2784 {
2785 return dev_priv->vgpu.active;
2786 }
2787
2788 u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
2789 enum pipe pipe);
2790 void
2791 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2792 u32 status_mask);
2793
2794 void
2795 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2796 u32 status_mask);
2797
2798 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2799 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2800 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2801 uint32_t mask,
2802 uint32_t bits);
2803 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2804 uint32_t interrupt_mask,
2805 uint32_t enabled_irq_mask);
2806 static inline void
ilk_enable_display_irq(struct drm_i915_private * dev_priv,uint32_t bits)2807 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2808 {
2809 ilk_update_display_irq(dev_priv, bits, bits);
2810 }
2811 static inline void
ilk_disable_display_irq(struct drm_i915_private * dev_priv,uint32_t bits)2812 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2813 {
2814 ilk_update_display_irq(dev_priv, bits, 0);
2815 }
2816 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2817 enum pipe pipe,
2818 uint32_t interrupt_mask,
2819 uint32_t enabled_irq_mask);
bdw_enable_pipe_irq(struct drm_i915_private * dev_priv,enum pipe pipe,uint32_t bits)2820 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2821 enum pipe pipe, uint32_t bits)
2822 {
2823 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2824 }
bdw_disable_pipe_irq(struct drm_i915_private * dev_priv,enum pipe pipe,uint32_t bits)2825 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2826 enum pipe pipe, uint32_t bits)
2827 {
2828 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2829 }
2830 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2831 uint32_t interrupt_mask,
2832 uint32_t enabled_irq_mask);
2833 static inline void
ibx_enable_display_interrupt(struct drm_i915_private * dev_priv,uint32_t bits)2834 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2835 {
2836 ibx_display_interrupt_update(dev_priv, bits, bits);
2837 }
2838 static inline void
ibx_disable_display_interrupt(struct drm_i915_private * dev_priv,uint32_t bits)2839 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2840 {
2841 ibx_display_interrupt_update(dev_priv, bits, 0);
2842 }
2843
2844 /* i915_gem.c */
2845 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2846 struct drm_file *file_priv);
2847 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2848 struct drm_file *file_priv);
2849 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2850 struct drm_file *file_priv);
2851 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2852 struct drm_file *file_priv);
2853 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2854 struct drm_file *file_priv);
2855 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2856 struct drm_file *file_priv);
2857 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2858 struct drm_file *file_priv);
2859 int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2860 struct drm_file *file_priv);
2861 int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2862 struct drm_file *file_priv);
2863 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2864 struct drm_file *file_priv);
2865 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2866 struct drm_file *file);
2867 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2868 struct drm_file *file);
2869 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2870 struct drm_file *file_priv);
2871 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2872 struct drm_file *file_priv);
2873 int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2874 struct drm_file *file_priv);
2875 int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2876 struct drm_file *file_priv);
2877 int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2878 void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2879 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2880 struct drm_file *file);
2881 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2882 struct drm_file *file_priv);
2883 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2884 struct drm_file *file_priv);
2885 void i915_gem_sanitize(struct drm_i915_private *i915);
2886 int i915_gem_init_early(struct drm_i915_private *dev_priv);
2887 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2888 void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2889 int i915_gem_freeze(struct drm_i915_private *dev_priv);
2890 int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2891
2892 void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2893 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2894 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2895 const struct drm_i915_gem_object_ops *ops);
2896 struct drm_i915_gem_object *
2897 i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2898 struct drm_i915_gem_object *
2899 i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2900 const void *data, size_t size);
2901 void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2902 void i915_gem_free_object(struct drm_gem_object *obj);
2903
i915_gem_drain_freed_objects(struct drm_i915_private * i915)2904 static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2905 {
2906 if (!atomic_read(&i915->mm.free_count))
2907 return;
2908
2909 /* A single pass should suffice to release all the freed objects (along
2910 * most call paths) , but be a little more paranoid in that freeing
2911 * the objects does take a little amount of time, during which the rcu
2912 * callbacks could have added new objects into the freed list, and
2913 * armed the work again.
2914 */
2915 do {
2916 rcu_barrier();
2917 } while (flush_work(&i915->mm.free_work));
2918 }
2919
i915_gem_drain_workqueue(struct drm_i915_private * i915)2920 static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2921 {
2922 /*
2923 * Similar to objects above (see i915_gem_drain_freed-objects), in
2924 * general we have workers that are armed by RCU and then rearm
2925 * themselves in their callbacks. To be paranoid, we need to
2926 * drain the workqueue a second time after waiting for the RCU
2927 * grace period so that we catch work queued via RCU from the first
2928 * pass. As neither drain_workqueue() nor flush_workqueue() report
2929 * a result, we make an assumption that we only don't require more
2930 * than 2 passes to catch all recursive RCU delayed work.
2931 *
2932 */
2933 int pass = 2;
2934 do {
2935 rcu_barrier();
2936 drain_workqueue(i915->wq);
2937 } while (--pass);
2938 }
2939
2940 struct i915_vma * __must_check
2941 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2942 const struct i915_ggtt_view *view,
2943 u64 size,
2944 u64 alignment,
2945 u64 flags);
2946
2947 int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2948 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2949
2950 void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2951
__sg_page_count(const struct scatterlist * sg)2952 static inline int __sg_page_count(const struct scatterlist *sg)
2953 {
2954 return sg->length >> PAGE_SHIFT;
2955 }
2956
2957 struct scatterlist *
2958 i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2959 unsigned int n, unsigned int *offset);
2960
2961 struct page *
2962 i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2963 unsigned int n);
2964
2965 struct page *
2966 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2967 unsigned int n);
2968
2969 dma_addr_t
2970 i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2971 unsigned long n);
2972
2973 void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2974 struct sg_table *pages,
2975 unsigned int sg_page_sizes);
2976 int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2977
2978 static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object * obj)2979 i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2980 {
2981 might_lock(&obj->mm.lock);
2982
2983 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
2984 return 0;
2985
2986 return __i915_gem_object_get_pages(obj);
2987 }
2988
2989 static inline bool
i915_gem_object_has_pages(struct drm_i915_gem_object * obj)2990 i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
2991 {
2992 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
2993 }
2994
2995 static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object * obj)2996 __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2997 {
2998 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2999
3000 atomic_inc(&obj->mm.pages_pin_count);
3001 }
3002
3003 static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object * obj)3004 i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3005 {
3006 return atomic_read(&obj->mm.pages_pin_count);
3007 }
3008
3009 static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object * obj)3010 __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3011 {
3012 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3013 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3014
3015 atomic_dec(&obj->mm.pages_pin_count);
3016 }
3017
3018 static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object * obj)3019 i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3020 {
3021 __i915_gem_object_unpin_pages(obj);
3022 }
3023
3024 enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
3025 I915_MM_NORMAL = 0,
3026 I915_MM_SHRINKER
3027 };
3028
3029 void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3030 enum i915_mm_subclass subclass);
3031 void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3032
3033 enum i915_map_type {
3034 I915_MAP_WB = 0,
3035 I915_MAP_WC,
3036 #define I915_MAP_OVERRIDE BIT(31)
3037 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
3038 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3039 };
3040
3041 /**
3042 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3043 * @obj: the object to map into kernel address space
3044 * @type: the type of mapping, used to select pgprot_t
3045 *
3046 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3047 * pages and then returns a contiguous mapping of the backing storage into
3048 * the kernel address space. Based on the @type of mapping, the PTE will be
3049 * set to either WriteBack or WriteCombine (via pgprot_t).
3050 *
3051 * The caller is responsible for calling i915_gem_object_unpin_map() when the
3052 * mapping is no longer required.
3053 *
3054 * Returns the pointer through which to access the mapped object, or an
3055 * ERR_PTR() on error.
3056 */
3057 void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3058 enum i915_map_type type);
3059
3060 /**
3061 * i915_gem_object_unpin_map - releases an earlier mapping
3062 * @obj: the object to unmap
3063 *
3064 * After pinning the object and mapping its pages, once you are finished
3065 * with your access, call i915_gem_object_unpin_map() to release the pin
3066 * upon the mapping. Once the pin count reaches zero, that mapping may be
3067 * removed.
3068 */
i915_gem_object_unpin_map(struct drm_i915_gem_object * obj)3069 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3070 {
3071 i915_gem_object_unpin_pages(obj);
3072 }
3073
3074 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3075 unsigned int *needs_clflush);
3076 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3077 unsigned int *needs_clflush);
3078 #define CLFLUSH_BEFORE BIT(0)
3079 #define CLFLUSH_AFTER BIT(1)
3080 #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3081
3082 static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object * obj)3083 i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3084 {
3085 i915_gem_object_unpin_pages(obj);
3086 }
3087
3088 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3089 int i915_gem_dumb_create(struct drm_file *file_priv,
3090 struct drm_device *dev,
3091 struct drm_mode_create_dumb *args);
3092 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3093 uint32_t handle, uint64_t *offset);
3094 int i915_gem_mmap_gtt_version(void);
3095
3096 void i915_gem_track_fb(struct drm_i915_gem_object *old,
3097 struct drm_i915_gem_object *new,
3098 unsigned frontbuffer_bits);
3099
3100 int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3101
3102 struct i915_request *
3103 i915_gem_find_active_request(struct intel_engine_cs *engine);
3104
i915_reset_backoff(struct i915_gpu_error * error)3105 static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3106 {
3107 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3108 }
3109
i915_reset_handoff(struct i915_gpu_error * error)3110 static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3111 {
3112 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3113 }
3114
i915_terminally_wedged(struct i915_gpu_error * error)3115 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3116 {
3117 return unlikely(test_bit(I915_WEDGED, &error->flags));
3118 }
3119
i915_reset_backoff_or_wedged(struct i915_gpu_error * error)3120 static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3121 {
3122 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3123 }
3124
i915_reset_count(struct i915_gpu_error * error)3125 static inline u32 i915_reset_count(struct i915_gpu_error *error)
3126 {
3127 return READ_ONCE(error->reset_count);
3128 }
3129
i915_reset_engine_count(struct i915_gpu_error * error,struct intel_engine_cs * engine)3130 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3131 struct intel_engine_cs *engine)
3132 {
3133 return READ_ONCE(error->reset_engine_count[engine->id]);
3134 }
3135
3136 struct i915_request *
3137 i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3138 int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3139 void i915_gem_reset(struct drm_i915_private *dev_priv,
3140 unsigned int stalled_mask);
3141 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3142 void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3143 void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3144 bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3145 void i915_gem_reset_engine(struct intel_engine_cs *engine,
3146 struct i915_request *request,
3147 bool stalled);
3148
3149 void i915_gem_init_mmio(struct drm_i915_private *i915);
3150 int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3151 int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3152 void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3153 void i915_gem_fini(struct drm_i915_private *dev_priv);
3154 void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3155 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3156 unsigned int flags, long timeout);
3157 int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3158 void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
3159 void i915_gem_resume(struct drm_i915_private *dev_priv);
3160 vm_fault_t i915_gem_fault(struct vm_fault *vmf);
3161 int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3162 unsigned int flags,
3163 long timeout,
3164 struct intel_rps_client *rps);
3165 int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3166 unsigned int flags,
3167 const struct i915_sched_attr *attr);
3168 #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3169
3170 int __must_check
3171 i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3172 int __must_check
3173 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3174 int __must_check
3175 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3176 struct i915_vma * __must_check
3177 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3178 u32 alignment,
3179 const struct i915_ggtt_view *view,
3180 unsigned int flags);
3181 void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3182 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3183 int align);
3184 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3185 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3186
3187 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3188 enum i915_cache_level cache_level);
3189
3190 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3191 struct dma_buf *dma_buf);
3192
3193 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3194 struct drm_gem_object *gem_obj, int flags);
3195
3196 static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space * vm)3197 i915_vm_to_ppgtt(struct i915_address_space *vm)
3198 {
3199 return container_of(vm, struct i915_hw_ppgtt, vm);
3200 }
3201
3202 /* i915_gem_fence_reg.c */
3203 struct drm_i915_fence_reg *
3204 i915_reserve_fence(struct drm_i915_private *dev_priv);
3205 void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3206
3207 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3208 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3209
3210 void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3211 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3212 struct sg_table *pages);
3213 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3214 struct sg_table *pages);
3215
3216 static inline struct i915_gem_context *
__i915_gem_context_lookup_rcu(struct drm_i915_file_private * file_priv,u32 id)3217 __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3218 {
3219 return idr_find(&file_priv->context_idr, id);
3220 }
3221
3222 static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private * file_priv,u32 id)3223 i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3224 {
3225 struct i915_gem_context *ctx;
3226
3227 rcu_read_lock();
3228 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3229 if (ctx && !kref_get_unless_zero(&ctx->ref))
3230 ctx = NULL;
3231 rcu_read_unlock();
3232
3233 return ctx;
3234 }
3235
3236 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3237 struct drm_file *file);
3238 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3239 struct drm_file *file);
3240 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3241 struct drm_file *file);
3242 void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3243 struct i915_gem_context *ctx,
3244 uint32_t *reg_state);
3245
3246 /* i915_gem_evict.c */
3247 int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3248 u64 min_size, u64 alignment,
3249 unsigned cache_level,
3250 u64 start, u64 end,
3251 unsigned flags);
3252 int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3253 struct drm_mm_node *node,
3254 unsigned int flags);
3255 int i915_gem_evict_vm(struct i915_address_space *vm);
3256
3257 void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3258
3259 /* belongs in i915_gem_gtt.h */
i915_gem_chipset_flush(struct drm_i915_private * dev_priv)3260 static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3261 {
3262 wmb();
3263 if (INTEL_GEN(dev_priv) < 6)
3264 intel_gtt_chipset_flush();
3265 }
3266
3267 /* i915_gem_stolen.c */
3268 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3269 struct drm_mm_node *node, u64 size,
3270 unsigned alignment);
3271 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3272 struct drm_mm_node *node, u64 size,
3273 unsigned alignment, u64 start,
3274 u64 end);
3275 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3276 struct drm_mm_node *node);
3277 int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3278 void i915_gem_cleanup_stolen(struct drm_device *dev);
3279 struct drm_i915_gem_object *
3280 i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3281 resource_size_t size);
3282 struct drm_i915_gem_object *
3283 i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3284 resource_size_t stolen_offset,
3285 resource_size_t gtt_offset,
3286 resource_size_t size);
3287
3288 /* i915_gem_internal.c */
3289 struct drm_i915_gem_object *
3290 i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3291 phys_addr_t size);
3292
3293 /* i915_gem_shrinker.c */
3294 unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3295 unsigned long target,
3296 unsigned long *nr_scanned,
3297 unsigned flags);
3298 #define I915_SHRINK_PURGEABLE 0x1
3299 #define I915_SHRINK_UNBOUND 0x2
3300 #define I915_SHRINK_BOUND 0x4
3301 #define I915_SHRINK_ACTIVE 0x8
3302 #define I915_SHRINK_VMAPS 0x10
3303 unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3304 void i915_gem_shrinker_register(struct drm_i915_private *i915);
3305 void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3306 void i915_gem_shrinker_taints_mutex(struct mutex *mutex);
3307
3308 /* i915_gem_tiling.c */
i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object * obj)3309 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3310 {
3311 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3312
3313 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3314 i915_gem_object_is_tiled(obj);
3315 }
3316
3317 u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3318 unsigned int tiling, unsigned int stride);
3319 u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3320 unsigned int tiling, unsigned int stride);
3321
3322 /* i915_debugfs.c */
3323 #ifdef CONFIG_DEBUG_FS
3324 int i915_debugfs_register(struct drm_i915_private *dev_priv);
3325 int i915_debugfs_connector_add(struct drm_connector *connector);
3326 void intel_display_crc_init(struct drm_i915_private *dev_priv);
3327 #else
i915_debugfs_register(struct drm_i915_private * dev_priv)3328 static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
i915_debugfs_connector_add(struct drm_connector * connector)3329 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3330 { return 0; }
intel_display_crc_init(struct drm_i915_private * dev_priv)3331 static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3332 #endif
3333
3334 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3335
3336 /* i915_cmd_parser.c */
3337 int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3338 void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3339 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3340 int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3341 struct drm_i915_gem_object *batch_obj,
3342 struct drm_i915_gem_object *shadow_batch_obj,
3343 u32 batch_start_offset,
3344 u32 batch_len,
3345 bool is_master);
3346
3347 /* i915_perf.c */
3348 extern void i915_perf_init(struct drm_i915_private *dev_priv);
3349 extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3350 extern void i915_perf_register(struct drm_i915_private *dev_priv);
3351 extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3352
3353 /* i915_suspend.c */
3354 extern int i915_save_state(struct drm_i915_private *dev_priv);
3355 extern int i915_restore_state(struct drm_i915_private *dev_priv);
3356
3357 /* i915_sysfs.c */
3358 void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3359 void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3360
3361 /* intel_lpe_audio.c */
3362 int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3363 void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3364 void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3365 void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3366 enum pipe pipe, enum port port,
3367 const void *eld, int ls_clock, bool dp_output);
3368
3369 /* intel_i2c.c */
3370 extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3371 extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3372 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3373 unsigned int pin);
3374 extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
3375
3376 extern struct i2c_adapter *
3377 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3378 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3379 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
intel_gmbus_is_forced_bit(struct i2c_adapter * adapter)3380 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3381 {
3382 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3383 }
3384 extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3385
3386 /* intel_bios.c */
3387 void intel_bios_init(struct drm_i915_private *dev_priv);
3388 void intel_bios_cleanup(struct drm_i915_private *dev_priv);
3389 bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3390 bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3391 bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3392 bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3393 bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3394 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3395 bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3396 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3397 enum port port);
3398 bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3399 enum port port);
3400
3401 /* intel_acpi.c */
3402 #ifdef CONFIG_ACPI
3403 extern void intel_register_dsm_handler(void);
3404 extern void intel_unregister_dsm_handler(void);
3405 #else
intel_register_dsm_handler(void)3406 static inline void intel_register_dsm_handler(void) { return; }
intel_unregister_dsm_handler(void)3407 static inline void intel_unregister_dsm_handler(void) { return; }
3408 #endif /* CONFIG_ACPI */
3409
3410 /* intel_device_info.c */
3411 static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private * dev_priv)3412 mkwrite_device_info(struct drm_i915_private *dev_priv)
3413 {
3414 return (struct intel_device_info *)&dev_priv->info;
3415 }
3416
3417 /* modesetting */
3418 extern void intel_modeset_init_hw(struct drm_device *dev);
3419 extern int intel_modeset_init(struct drm_device *dev);
3420 extern void intel_modeset_cleanup(struct drm_device *dev);
3421 extern int intel_connector_register(struct drm_connector *);
3422 extern void intel_connector_unregister(struct drm_connector *);
3423 extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3424 bool state);
3425 extern void intel_display_resume(struct drm_device *dev);
3426 extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3427 extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3428 extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3429 extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3430 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3431 extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
3432 bool interactive);
3433 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3434 bool enable);
3435
3436 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3437 struct drm_file *file);
3438
3439 /* overlay */
3440 extern struct intel_overlay_error_state *
3441 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3442 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3443 struct intel_overlay_error_state *error);
3444
3445 extern struct intel_display_error_state *
3446 intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3447 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3448 struct intel_display_error_state *error);
3449
3450 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3451 int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3452 u32 val, int fast_timeout_us,
3453 int slow_timeout_ms);
3454 #define sandybridge_pcode_write(dev_priv, mbox, val) \
3455 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3456
3457 int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3458 u32 reply_mask, u32 reply, int timeout_base_ms);
3459
3460 /* intel_sideband.c */
3461 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3462 int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3463 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3464 u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3465 void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3466 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3467 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3468 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3469 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3470 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3471 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3472 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3473 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3474 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3475 enum intel_sbi_destination destination);
3476 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3477 enum intel_sbi_destination destination);
3478 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3479 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3480
3481 /* intel_dpio_phy.c */
3482 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3483 enum dpio_phy *phy, enum dpio_channel *ch);
3484 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3485 enum port port, u32 margin, u32 scale,
3486 u32 enable, u32 deemphasis);
3487 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3488 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3489 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3490 enum dpio_phy phy);
3491 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3492 enum dpio_phy phy);
3493 uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3494 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3495 uint8_t lane_lat_optim_mask);
3496 uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3497
3498 void chv_set_phy_signal_level(struct intel_encoder *encoder,
3499 u32 deemph_reg_value, u32 margin_reg_value,
3500 bool uniq_trans_scale);
3501 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3502 const struct intel_crtc_state *crtc_state,
3503 bool reset);
3504 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3505 const struct intel_crtc_state *crtc_state);
3506 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3507 const struct intel_crtc_state *crtc_state);
3508 void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3509 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3510 const struct intel_crtc_state *old_crtc_state);
3511
3512 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3513 u32 demph_reg_value, u32 preemph_reg_value,
3514 u32 uniqtranscale_reg_value, u32 tx3_demph);
3515 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3516 const struct intel_crtc_state *crtc_state);
3517 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3518 const struct intel_crtc_state *crtc_state);
3519 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3520 const struct intel_crtc_state *old_crtc_state);
3521
3522 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3523 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3524 u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3525 const i915_reg_t reg);
3526
3527 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3528
intel_rc6_residency_us(struct drm_i915_private * dev_priv,const i915_reg_t reg)3529 static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3530 const i915_reg_t reg)
3531 {
3532 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3533 }
3534
3535 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3536 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3537
3538 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3539 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3540 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3541 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3542
3543 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3544 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3545 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3546 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3547
3548 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3549 * will be implemented using 2 32-bit writes in an arbitrary order with
3550 * an arbitrary delay between them. This can cause the hardware to
3551 * act upon the intermediate value, possibly leading to corruption and
3552 * machine death. For this reason we do not support I915_WRITE64, or
3553 * dev_priv->uncore.funcs.mmio_writeq.
3554 *
3555 * When reading a 64-bit value as two 32-bit values, the delay may cause
3556 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
3557 * occasionally a 64-bit register does not actualy support a full readq
3558 * and must be read using two 32-bit reads.
3559 *
3560 * You have been warned.
3561 */
3562 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3563
3564 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3565 u32 upper, lower, old_upper, loop = 0; \
3566 upper = I915_READ(upper_reg); \
3567 do { \
3568 old_upper = upper; \
3569 lower = I915_READ(lower_reg); \
3570 upper = I915_READ(upper_reg); \
3571 } while (upper != old_upper && loop++ < 2); \
3572 (u64)upper << 32 | lower; })
3573
3574 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3575 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3576
3577 #define __raw_read(x, s) \
3578 static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3579 i915_reg_t reg) \
3580 { \
3581 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3582 }
3583
3584 #define __raw_write(x, s) \
3585 static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3586 i915_reg_t reg, uint##x##_t val) \
3587 { \
3588 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3589 }
3590 __raw_read(8, b)
3591 __raw_read(16, w)
3592 __raw_read(32, l)
3593 __raw_read(64, q)
3594
3595 __raw_write(8, b)
3596 __raw_write(16, w)
3597 __raw_write(32, l)
3598 __raw_write(64, q)
3599
3600 #undef __raw_read
3601 #undef __raw_write
3602
3603 /* These are untraced mmio-accessors that are only valid to be used inside
3604 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3605 * controlled.
3606 *
3607 * Think twice, and think again, before using these.
3608 *
3609 * As an example, these accessors can possibly be used between:
3610 *
3611 * spin_lock_irq(&dev_priv->uncore.lock);
3612 * intel_uncore_forcewake_get__locked();
3613 *
3614 * and
3615 *
3616 * intel_uncore_forcewake_put__locked();
3617 * spin_unlock_irq(&dev_priv->uncore.lock);
3618 *
3619 *
3620 * Note: some registers may not need forcewake held, so
3621 * intel_uncore_forcewake_{get,put} can be omitted, see
3622 * intel_uncore_forcewake_for_reg().
3623 *
3624 * Certain architectures will die if the same cacheline is concurrently accessed
3625 * by different clients (e.g. on Ivybridge). Access to registers should
3626 * therefore generally be serialised, by either the dev_priv->uncore.lock or
3627 * a more localised lock guarding all access to that bank of registers.
3628 */
3629 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3630 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3631 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3632 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3633
3634 /* "Broadcast RGB" property */
3635 #define INTEL_BROADCAST_RGB_AUTO 0
3636 #define INTEL_BROADCAST_RGB_FULL 1
3637 #define INTEL_BROADCAST_RGB_LIMITED 2
3638
i915_vgacntrl_reg(struct drm_i915_private * dev_priv)3639 static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3640 {
3641 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3642 return VLV_VGACNTRL;
3643 else if (INTEL_GEN(dev_priv) >= 5)
3644 return CPU_VGACNTRL;
3645 else
3646 return VGACNTRL;
3647 }
3648
msecs_to_jiffies_timeout(const unsigned int m)3649 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3650 {
3651 unsigned long j = msecs_to_jiffies(m);
3652
3653 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3654 }
3655
nsecs_to_jiffies_timeout(const u64 n)3656 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3657 {
3658 /* nsecs_to_jiffies64() does not guard against overflow */
3659 if (NSEC_PER_SEC % HZ &&
3660 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
3661 return MAX_JIFFY_OFFSET;
3662
3663 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3664 }
3665
3666 /*
3667 * If you need to wait X milliseconds between events A and B, but event B
3668 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3669 * when event A happened, then just before event B you call this function and
3670 * pass the timestamp as the first argument, and X as the second argument.
3671 */
3672 static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies,int to_wait_ms)3673 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3674 {
3675 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3676
3677 /*
3678 * Don't re-read the value of "jiffies" every time since it may change
3679 * behind our back and break the math.
3680 */
3681 tmp_jiffies = jiffies;
3682 target_jiffies = timestamp_jiffies +
3683 msecs_to_jiffies_timeout(to_wait_ms);
3684
3685 if (time_after(target_jiffies, tmp_jiffies)) {
3686 remaining_jiffies = target_jiffies - tmp_jiffies;
3687 while (remaining_jiffies)
3688 remaining_jiffies =
3689 schedule_timeout_uninterruptible(remaining_jiffies);
3690 }
3691 }
3692
3693 static inline bool
__i915_request_irq_complete(const struct i915_request * rq)3694 __i915_request_irq_complete(const struct i915_request *rq)
3695 {
3696 struct intel_engine_cs *engine = rq->engine;
3697 u32 seqno;
3698
3699 /* Note that the engine may have wrapped around the seqno, and
3700 * so our request->global_seqno will be ahead of the hardware,
3701 * even though it completed the request before wrapping. We catch
3702 * this by kicking all the waiters before resetting the seqno
3703 * in hardware, and also signal the fence.
3704 */
3705 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
3706 return true;
3707
3708 /* The request was dequeued before we were awoken. We check after
3709 * inspecting the hw to confirm that this was the same request
3710 * that generated the HWS update. The memory barriers within
3711 * the request execution are sufficient to ensure that a check
3712 * after reading the value from hw matches this request.
3713 */
3714 seqno = i915_request_global_seqno(rq);
3715 if (!seqno)
3716 return false;
3717
3718 /* Before we do the heavier coherent read of the seqno,
3719 * check the value (hopefully) in the CPU cacheline.
3720 */
3721 if (__i915_request_completed(rq, seqno))
3722 return true;
3723
3724 /* Ensure our read of the seqno is coherent so that we
3725 * do not "miss an interrupt" (i.e. if this is the last
3726 * request and the seqno write from the GPU is not visible
3727 * by the time the interrupt fires, we will see that the
3728 * request is incomplete and go back to sleep awaiting
3729 * another interrupt that will never come.)
3730 *
3731 * Strictly, we only need to do this once after an interrupt,
3732 * but it is easier and safer to do it every time the waiter
3733 * is woken.
3734 */
3735 if (engine->irq_seqno_barrier &&
3736 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
3737 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3738
3739 /* The ordering of irq_posted versus applying the barrier
3740 * is crucial. The clearing of the current irq_posted must
3741 * be visible before we perform the barrier operation,
3742 * such that if a subsequent interrupt arrives, irq_posted
3743 * is reasserted and our task rewoken (which causes us to
3744 * do another __i915_request_irq_complete() immediately
3745 * and reapply the barrier). Conversely, if the clear
3746 * occurs after the barrier, then an interrupt that arrived
3747 * whilst we waited on the barrier would not trigger a
3748 * barrier on the next pass, and the read may not see the
3749 * seqno update.
3750 */
3751 engine->irq_seqno_barrier(engine);
3752
3753 /* If we consume the irq, but we are no longer the bottom-half,
3754 * the real bottom-half may not have serialised their own
3755 * seqno check with the irq-barrier (i.e. may have inspected
3756 * the seqno before we believe it coherent since they see
3757 * irq_posted == false but we are still running).
3758 */
3759 spin_lock_irq(&b->irq_lock);
3760 if (b->irq_wait && b->irq_wait->tsk != current)
3761 /* Note that if the bottom-half is changed as we
3762 * are sending the wake-up, the new bottom-half will
3763 * be woken by whomever made the change. We only have
3764 * to worry about when we steal the irq-posted for
3765 * ourself.
3766 */
3767 wake_up_process(b->irq_wait->tsk);
3768 spin_unlock_irq(&b->irq_lock);
3769
3770 if (__i915_request_completed(rq, seqno))
3771 return true;
3772 }
3773
3774 return false;
3775 }
3776
3777 void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3778 bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3779
3780 /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
3781 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
3782 * perform the operation. To check beforehand, pass in the parameters to
3783 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
3784 * you only need to pass in the minor offsets, page-aligned pointers are
3785 * always valid.
3786 *
3787 * For just checking for SSE4.1, in the foreknowledge that the future use
3788 * will be correctly aligned, just use i915_has_memcpy_from_wc().
3789 */
3790 #define i915_can_memcpy_from_wc(dst, src, len) \
3791 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3792
3793 #define i915_has_memcpy_from_wc() \
3794 i915_memcpy_from_wc(NULL, NULL, 0)
3795
3796 /* i915_mm.c */
3797 int remap_io_mapping(struct vm_area_struct *vma,
3798 unsigned long addr, unsigned long pfn, unsigned long size,
3799 struct io_mapping *iomap);
3800
intel_hws_csb_write_index(struct drm_i915_private * i915)3801 static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3802 {
3803 if (INTEL_GEN(i915) >= 10)
3804 return CNL_HWS_CSB_WRITE_INDEX;
3805 else
3806 return I915_HWS_CSB_WRITE_INDEX;
3807 }
3808
3809 #endif
3810