1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
3
4 #ifndef _I40E_TYPE_H_
5 #define _I40E_TYPE_H_
6
7 #include "i40e_status.h"
8 #include "i40e_osdep.h"
9 #include "i40e_register.h"
10 #include "i40e_adminq.h"
11 #include "i40e_hmc.h"
12 #include "i40e_lan_hmc.h"
13 #include "i40e_devids.h"
14
15 /* I40E_MASK is a macro used on 32 bit registers */
16 #define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
17
18 #define I40E_MAX_VSI_QP 16
19 #define I40E_MAX_VF_VSI 4
20 #define I40E_MAX_CHAINED_RX_BUFFERS 5
21 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
22
23 /* Max default timeout in ms, */
24 #define I40E_MAX_NVM_TIMEOUT 18000
25
26 /* Max timeout in ms for the phy to respond */
27 #define I40E_MAX_PHY_TIMEOUT 500
28
29 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
30 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
31
32 /* forward declaration */
33 struct i40e_hw;
34 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
35
36 /* Data type manipulation macros. */
37
38 #define I40E_DESC_UNUSED(R) \
39 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
40 (R)->next_to_clean - (R)->next_to_use - 1)
41
42 /* bitfields for Tx queue mapping in QTX_CTL */
43 #define I40E_QTX_CTL_VF_QUEUE 0x0
44 #define I40E_QTX_CTL_VM_QUEUE 0x1
45 #define I40E_QTX_CTL_PF_QUEUE 0x2
46
47 /* debug masks - set these bits in hw->debug_mask to control output */
48 enum i40e_debug_mask {
49 I40E_DEBUG_INIT = 0x00000001,
50 I40E_DEBUG_RELEASE = 0x00000002,
51
52 I40E_DEBUG_LINK = 0x00000010,
53 I40E_DEBUG_PHY = 0x00000020,
54 I40E_DEBUG_HMC = 0x00000040,
55 I40E_DEBUG_NVM = 0x00000080,
56 I40E_DEBUG_LAN = 0x00000100,
57 I40E_DEBUG_FLOW = 0x00000200,
58 I40E_DEBUG_DCB = 0x00000400,
59 I40E_DEBUG_DIAG = 0x00000800,
60 I40E_DEBUG_FD = 0x00001000,
61 I40E_DEBUG_PACKAGE = 0x00002000,
62 I40E_DEBUG_IWARP = 0x00F00000,
63 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
64 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
65 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
66 I40E_DEBUG_AQ_COMMAND = 0x06000000,
67 I40E_DEBUG_AQ = 0x0F000000,
68
69 I40E_DEBUG_USER = 0xF0000000,
70
71 I40E_DEBUG_ALL = 0xFFFFFFFF
72 };
73
74 #define I40E_MDIO_CLAUSE22_STCODE_MASK I40E_MASK(1, \
75 I40E_GLGEN_MSCA_STCODE_SHIFT)
76 #define I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK I40E_MASK(1, \
77 I40E_GLGEN_MSCA_OPCODE_SHIFT)
78 #define I40E_MDIO_CLAUSE22_OPCODE_READ_MASK I40E_MASK(2, \
79 I40E_GLGEN_MSCA_OPCODE_SHIFT)
80
81 #define I40E_MDIO_CLAUSE45_STCODE_MASK I40E_MASK(0, \
82 I40E_GLGEN_MSCA_STCODE_SHIFT)
83 #define I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK I40E_MASK(0, \
84 I40E_GLGEN_MSCA_OPCODE_SHIFT)
85 #define I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK I40E_MASK(1, \
86 I40E_GLGEN_MSCA_OPCODE_SHIFT)
87 #define I40E_MDIO_CLAUSE45_OPCODE_READ_MASK I40E_MASK(3, \
88 I40E_GLGEN_MSCA_OPCODE_SHIFT)
89
90 #define I40E_PHY_COM_REG_PAGE 0x1E
91 #define I40E_PHY_LED_LINK_MODE_MASK 0xF0
92 #define I40E_PHY_LED_MANUAL_ON 0x100
93 #define I40E_PHY_LED_PROV_REG_1 0xC430
94 #define I40E_PHY_LED_MODE_MASK 0xFFFF
95 #define I40E_PHY_LED_MODE_ORIG 0x80000000
96
97 /* These are structs for managing the hardware information and the operations.
98 * The structures of function pointers are filled out at init time when we
99 * know for sure exactly which hardware we're working with. This gives us the
100 * flexibility of using the same main driver code but adapting to slightly
101 * different hardware needs as new parts are developed. For this architecture,
102 * the Firmware and AdminQ are intended to insulate the driver from most of the
103 * future changes, but these structures will also do part of the job.
104 */
105 enum i40e_mac_type {
106 I40E_MAC_UNKNOWN = 0,
107 I40E_MAC_XL710,
108 I40E_MAC_VF,
109 I40E_MAC_X722,
110 I40E_MAC_X722_VF,
111 I40E_MAC_GENERIC,
112 };
113
114 enum i40e_media_type {
115 I40E_MEDIA_TYPE_UNKNOWN = 0,
116 I40E_MEDIA_TYPE_FIBER,
117 I40E_MEDIA_TYPE_BASET,
118 I40E_MEDIA_TYPE_BACKPLANE,
119 I40E_MEDIA_TYPE_CX4,
120 I40E_MEDIA_TYPE_DA,
121 I40E_MEDIA_TYPE_VIRTUAL
122 };
123
124 enum i40e_fc_mode {
125 I40E_FC_NONE = 0,
126 I40E_FC_RX_PAUSE,
127 I40E_FC_TX_PAUSE,
128 I40E_FC_FULL,
129 I40E_FC_PFC,
130 I40E_FC_DEFAULT
131 };
132
133 enum i40e_set_fc_aq_failures {
134 I40E_SET_FC_AQ_FAIL_NONE = 0,
135 I40E_SET_FC_AQ_FAIL_GET = 1,
136 I40E_SET_FC_AQ_FAIL_SET = 2,
137 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
138 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
139 };
140
141 enum i40e_vsi_type {
142 I40E_VSI_MAIN = 0,
143 I40E_VSI_VMDQ1 = 1,
144 I40E_VSI_VMDQ2 = 2,
145 I40E_VSI_CTRL = 3,
146 I40E_VSI_FCOE = 4,
147 I40E_VSI_MIRROR = 5,
148 I40E_VSI_SRIOV = 6,
149 I40E_VSI_FDIR = 7,
150 I40E_VSI_IWARP = 8,
151 I40E_VSI_TYPE_UNKNOWN
152 };
153
154 enum i40e_queue_type {
155 I40E_QUEUE_TYPE_RX = 0,
156 I40E_QUEUE_TYPE_TX,
157 I40E_QUEUE_TYPE_PE_CEQ,
158 I40E_QUEUE_TYPE_UNKNOWN
159 };
160
161 struct i40e_link_status {
162 enum i40e_aq_phy_type phy_type;
163 enum i40e_aq_link_speed link_speed;
164 u8 link_info;
165 u8 an_info;
166 u8 req_fec_info;
167 u8 fec_info;
168 u8 ext_info;
169 u8 loopback;
170 /* is Link Status Event notification to SW enabled */
171 bool lse_enable;
172 u16 max_frame_size;
173 bool crc_enable;
174 u8 pacing;
175 u8 requested_speeds;
176 u8 module_type[3];
177 /* 1st byte: module identifier */
178 #define I40E_MODULE_TYPE_SFP 0x03
179 /* 3rd byte: ethernet compliance codes for 1G */
180 #define I40E_MODULE_TYPE_1000BASE_SX 0x01
181 #define I40E_MODULE_TYPE_1000BASE_LX 0x02
182 };
183
184 struct i40e_phy_info {
185 struct i40e_link_status link_info;
186 struct i40e_link_status link_info_old;
187 bool get_link_info;
188 enum i40e_media_type media_type;
189 /* all the phy types the NVM is capable of */
190 u64 phy_types;
191 };
192
193 #define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
194 #define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
195 #define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
196 #define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
197 #define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
198 #define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
199 #define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
200 #define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
201 #define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
202 #define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
203 #define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
204 #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
205 #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
206 #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
207 #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
208 #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
209 #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
210 #define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
211 #define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
212 #define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
213 #define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
214 #define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
215 #define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
216 #define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
217 #define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
218 #define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
219 #define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
220 BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
221 #define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
222 /* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
223 * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
224 * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
225 * a shift is needed to adjust for this with values larger than 31. The
226 * only affected values are I40E_PHY_TYPE_25GBASE_*.
227 */
228 #define I40E_PHY_TYPE_OFFSET 1
229 #define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
230 I40E_PHY_TYPE_OFFSET)
231 #define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
232 I40E_PHY_TYPE_OFFSET)
233 #define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
234 I40E_PHY_TYPE_OFFSET)
235 #define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
236 I40E_PHY_TYPE_OFFSET)
237 #define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
238 I40E_PHY_TYPE_OFFSET)
239 #define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
240 I40E_PHY_TYPE_OFFSET)
241 /* Offset for 2.5G/5G PHY Types value to bit number conversion */
242 #define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T)
243 #define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T)
244 #define I40E_HW_CAP_MAX_GPIO 30
245 /* Capabilities of a PF or a VF or the whole device */
246 struct i40e_hw_capabilities {
247 u32 switch_mode;
248
249 /* Cloud filter modes:
250 * Mode1: Filter on L4 port only
251 * Mode2: Filter for non-tunneled traffic
252 * Mode3: Filter for tunnel traffic
253 */
254 #define I40E_CLOUD_FILTER_MODE1 0x6
255 #define I40E_CLOUD_FILTER_MODE2 0x7
256 #define I40E_SWITCH_MODE_MASK 0xF
257
258 u32 management_mode;
259 u32 mng_protocols_over_mctp;
260 u32 npar_enable;
261 u32 os2bmc;
262 u32 valid_functions;
263 bool sr_iov_1_1;
264 bool vmdq;
265 bool evb_802_1_qbg; /* Edge Virtual Bridging */
266 bool evb_802_1_qbh; /* Bridge Port Extension */
267 bool dcb;
268 bool fcoe;
269 bool iscsi; /* Indicates iSCSI enabled */
270 bool flex10_enable;
271 bool flex10_capable;
272 u32 flex10_mode;
273
274 u32 flex10_status;
275
276 bool sec_rev_disabled;
277 bool update_disabled;
278 #define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
279 #define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
280
281 bool mgmt_cem;
282 bool ieee_1588;
283 bool iwarp;
284 bool fd;
285 u32 fd_filters_guaranteed;
286 u32 fd_filters_best_effort;
287 bool rss;
288 u32 rss_table_size;
289 u32 rss_table_entry_width;
290 bool led[I40E_HW_CAP_MAX_GPIO];
291 bool sdp[I40E_HW_CAP_MAX_GPIO];
292 u32 nvm_image_type;
293 u32 num_flow_director_filters;
294 u32 num_vfs;
295 u32 vf_base_id;
296 u32 num_vsis;
297 u32 num_rx_qp;
298 u32 num_tx_qp;
299 u32 base_queue;
300 u32 num_msix_vectors;
301 u32 num_msix_vectors_vf;
302 u32 led_pin_num;
303 u32 sdp_pin_num;
304 u32 mdio_port_num;
305 u32 mdio_port_mode;
306 u8 rx_buf_chain_len;
307 u32 enabled_tcmap;
308 u32 maxtc;
309 u64 wr_csr_prot;
310 };
311
312 struct i40e_mac_info {
313 enum i40e_mac_type type;
314 u8 addr[ETH_ALEN];
315 u8 perm_addr[ETH_ALEN];
316 u8 san_addr[ETH_ALEN];
317 u8 port_addr[ETH_ALEN];
318 u16 max_fcoeq;
319 };
320
321 enum i40e_aq_resources_ids {
322 I40E_NVM_RESOURCE_ID = 1
323 };
324
325 enum i40e_aq_resource_access_type {
326 I40E_RESOURCE_READ = 1,
327 I40E_RESOURCE_WRITE
328 };
329
330 struct i40e_nvm_info {
331 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
332 u32 timeout; /* [ms] */
333 u16 sr_size; /* Shadow RAM size in words */
334 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
335 u16 version; /* NVM package version */
336 u32 eetrack; /* NVM data version */
337 u32 oem_ver; /* OEM version info */
338 };
339
340 /* definitions used in NVM update support */
341
342 enum i40e_nvmupd_cmd {
343 I40E_NVMUPD_INVALID,
344 I40E_NVMUPD_READ_CON,
345 I40E_NVMUPD_READ_SNT,
346 I40E_NVMUPD_READ_LCB,
347 I40E_NVMUPD_READ_SA,
348 I40E_NVMUPD_WRITE_ERA,
349 I40E_NVMUPD_WRITE_CON,
350 I40E_NVMUPD_WRITE_SNT,
351 I40E_NVMUPD_WRITE_LCB,
352 I40E_NVMUPD_WRITE_SA,
353 I40E_NVMUPD_CSUM_CON,
354 I40E_NVMUPD_CSUM_SA,
355 I40E_NVMUPD_CSUM_LCB,
356 I40E_NVMUPD_STATUS,
357 I40E_NVMUPD_EXEC_AQ,
358 I40E_NVMUPD_GET_AQ_RESULT,
359 I40E_NVMUPD_GET_AQ_EVENT,
360 };
361
362 enum i40e_nvmupd_state {
363 I40E_NVMUPD_STATE_INIT,
364 I40E_NVMUPD_STATE_READING,
365 I40E_NVMUPD_STATE_WRITING,
366 I40E_NVMUPD_STATE_INIT_WAIT,
367 I40E_NVMUPD_STATE_WRITE_WAIT,
368 I40E_NVMUPD_STATE_ERROR
369 };
370
371 /* nvm_access definition and its masks/shifts need to be accessible to
372 * application, core driver, and shared code. Where is the right file?
373 */
374 #define I40E_NVM_READ 0xB
375 #define I40E_NVM_WRITE 0xC
376
377 #define I40E_NVM_MOD_PNT_MASK 0xFF
378
379 #define I40E_NVM_TRANS_SHIFT 8
380 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
381 #define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12
382 #define I40E_NVM_PRESERVATION_FLAGS_MASK \
383 (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
384 #define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01
385 #define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02
386 #define I40E_NVM_CON 0x0
387 #define I40E_NVM_SNT 0x1
388 #define I40E_NVM_LCB 0x2
389 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
390 #define I40E_NVM_ERA 0x4
391 #define I40E_NVM_CSUM 0x8
392 #define I40E_NVM_AQE 0xe
393 #define I40E_NVM_EXEC 0xf
394
395
396 #define I40E_NVMUPD_MAX_DATA 4096
397
398 struct i40e_nvm_access {
399 u32 command;
400 u32 config;
401 u32 offset; /* in bytes */
402 u32 data_size; /* in bytes */
403 u8 data[1];
404 };
405
406 /* (Q)SFP module access definitions */
407 #define I40E_I2C_EEPROM_DEV_ADDR 0xA0
408 #define I40E_I2C_EEPROM_DEV_ADDR2 0xA2
409 #define I40E_MODULE_REVISION_ADDR 0x01
410 #define I40E_MODULE_SFF_8472_COMP 0x5E
411 #define I40E_MODULE_SFF_8472_SWAP 0x5C
412 #define I40E_MODULE_SFF_ADDR_MODE 0x04
413 #define I40E_MODULE_SFF_DDM_IMPLEMENTED 0x40
414 #define I40E_MODULE_TYPE_QSFP_PLUS 0x0D
415 #define I40E_MODULE_TYPE_QSFP28 0x11
416 #define I40E_MODULE_QSFP_MAX_LEN 640
417
418 /* PCI bus types */
419 enum i40e_bus_type {
420 i40e_bus_type_unknown = 0,
421 i40e_bus_type_pci,
422 i40e_bus_type_pcix,
423 i40e_bus_type_pci_express,
424 i40e_bus_type_reserved
425 };
426
427 /* PCI bus speeds */
428 enum i40e_bus_speed {
429 i40e_bus_speed_unknown = 0,
430 i40e_bus_speed_33 = 33,
431 i40e_bus_speed_66 = 66,
432 i40e_bus_speed_100 = 100,
433 i40e_bus_speed_120 = 120,
434 i40e_bus_speed_133 = 133,
435 i40e_bus_speed_2500 = 2500,
436 i40e_bus_speed_5000 = 5000,
437 i40e_bus_speed_8000 = 8000,
438 i40e_bus_speed_reserved
439 };
440
441 /* PCI bus widths */
442 enum i40e_bus_width {
443 i40e_bus_width_unknown = 0,
444 i40e_bus_width_pcie_x1 = 1,
445 i40e_bus_width_pcie_x2 = 2,
446 i40e_bus_width_pcie_x4 = 4,
447 i40e_bus_width_pcie_x8 = 8,
448 i40e_bus_width_32 = 32,
449 i40e_bus_width_64 = 64,
450 i40e_bus_width_reserved
451 };
452
453 /* Bus parameters */
454 struct i40e_bus_info {
455 enum i40e_bus_speed speed;
456 enum i40e_bus_width width;
457 enum i40e_bus_type type;
458
459 u16 func;
460 u16 device;
461 u16 lan_id;
462 u16 bus_id;
463 };
464
465 /* Flow control (FC) parameters */
466 struct i40e_fc_info {
467 enum i40e_fc_mode current_mode; /* FC mode in effect */
468 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
469 };
470
471 #define I40E_MAX_TRAFFIC_CLASS 8
472 #define I40E_MAX_USER_PRIORITY 8
473 #define I40E_DCBX_MAX_APPS 32
474 #define I40E_LLDPDU_SIZE 1500
475 #define I40E_TLV_STATUS_OPER 0x1
476 #define I40E_TLV_STATUS_SYNC 0x2
477 #define I40E_TLV_STATUS_ERR 0x4
478 #define I40E_CEE_OPER_MAX_APPS 3
479 #define I40E_APP_PROTOID_FCOE 0x8906
480 #define I40E_APP_PROTOID_ISCSI 0x0cbc
481 #define I40E_APP_PROTOID_FIP 0x8914
482 #define I40E_APP_SEL_ETHTYPE 0x1
483 #define I40E_APP_SEL_TCPIP 0x2
484 #define I40E_CEE_APP_SEL_ETHTYPE 0x0
485 #define I40E_CEE_APP_SEL_TCPIP 0x1
486
487 /* CEE or IEEE 802.1Qaz ETS Configuration data */
488 struct i40e_dcb_ets_config {
489 u8 willing;
490 u8 cbs;
491 u8 maxtcs;
492 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
493 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
494 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
495 };
496
497 /* CEE or IEEE 802.1Qaz PFC Configuration data */
498 struct i40e_dcb_pfc_config {
499 u8 willing;
500 u8 mbc;
501 u8 pfccap;
502 u8 pfcenable;
503 };
504
505 /* CEE or IEEE 802.1Qaz Application Priority data */
506 struct i40e_dcb_app_priority_table {
507 u8 priority;
508 u8 selector;
509 u16 protocolid;
510 };
511
512 struct i40e_dcbx_config {
513 u8 dcbx_mode;
514 #define I40E_DCBX_MODE_CEE 0x1
515 #define I40E_DCBX_MODE_IEEE 0x2
516 u8 app_mode;
517 #define I40E_DCBX_APPS_NON_WILLING 0x1
518 u32 numapps;
519 u32 tlv_status; /* CEE mode TLV status */
520 struct i40e_dcb_ets_config etscfg;
521 struct i40e_dcb_ets_config etsrec;
522 struct i40e_dcb_pfc_config pfc;
523 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
524 };
525
526 /* Port hardware description */
527 struct i40e_hw {
528 u8 __iomem *hw_addr;
529 void *back;
530
531 /* subsystem structs */
532 struct i40e_phy_info phy;
533 struct i40e_mac_info mac;
534 struct i40e_bus_info bus;
535 struct i40e_nvm_info nvm;
536 struct i40e_fc_info fc;
537
538 /* pci info */
539 u16 device_id;
540 u16 vendor_id;
541 u16 subsystem_device_id;
542 u16 subsystem_vendor_id;
543 u8 revision_id;
544 u8 port;
545 bool adapter_stopped;
546
547 /* capabilities for entire device and PCI func */
548 struct i40e_hw_capabilities dev_caps;
549 struct i40e_hw_capabilities func_caps;
550
551 /* Flow Director shared filter space */
552 u16 fdir_shared_filter_count;
553
554 /* device profile info */
555 u8 pf_id;
556 u16 main_vsi_seid;
557
558 /* for multi-function MACs */
559 u16 partition_id;
560 u16 num_partitions;
561 u16 num_ports;
562
563 /* Closest numa node to the device */
564 u16 numa_node;
565
566 /* Admin Queue info */
567 struct i40e_adminq_info aq;
568
569 /* state of nvm update process */
570 enum i40e_nvmupd_state nvmupd_state;
571 struct i40e_aq_desc nvm_wb_desc;
572 struct i40e_aq_desc nvm_aq_event_desc;
573 struct i40e_virt_mem nvm_buff;
574 bool nvm_release_on_done;
575 u16 nvm_wait_opcode;
576
577 /* HMC info */
578 struct i40e_hmc_info hmc; /* HMC info struct */
579
580 /* LLDP/DCBX Status */
581 u16 dcbx_status;
582
583 /* DCBX info */
584 struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
585 struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
586 struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
587
588 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
589 #define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
590 #define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
591 #define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
592 #define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
593 #define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5)
594 #define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)
595 #define I40E_HW_FLAG_DROP_MODE BIT_ULL(7)
596 #define I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE BIT_ULL(8)
597 u64 flags;
598
599 /* Used in set switch config AQ command */
600 u16 switch_tag;
601 u16 first_tag;
602 u16 second_tag;
603
604 /* debug mask */
605 u32 debug_mask;
606 char err_str[16];
607 };
608
i40e_is_vf(struct i40e_hw * hw)609 static inline bool i40e_is_vf(struct i40e_hw *hw)
610 {
611 return (hw->mac.type == I40E_MAC_VF ||
612 hw->mac.type == I40E_MAC_X722_VF);
613 }
614
615 struct i40e_driver_version {
616 u8 major_version;
617 u8 minor_version;
618 u8 build_version;
619 u8 subbuild_version;
620 u8 driver_string[32];
621 };
622
623 /* RX Descriptors */
624 union i40e_16byte_rx_desc {
625 struct {
626 __le64 pkt_addr; /* Packet buffer address */
627 __le64 hdr_addr; /* Header buffer address */
628 } read;
629 struct {
630 struct i40e_16b_rx_wb_qw0 {
631 struct {
632 union {
633 __le16 mirroring_status;
634 __le16 fcoe_ctx_id;
635 } mirr_fcoe;
636 __le16 l2tag1;
637 } lo_dword;
638 union {
639 __le32 rss; /* RSS Hash */
640 __le32 fd_id; /* Flow director filter id */
641 __le32 fcoe_param; /* FCoE DDP Context id */
642 } hi_dword;
643 } qword0;
644 struct {
645 /* ext status/error/pktype/length */
646 __le64 status_error_len;
647 } qword1;
648 } wb; /* writeback */
649 struct {
650 u64 qword[2];
651 } raw;
652 };
653
654 union i40e_32byte_rx_desc {
655 struct {
656 __le64 pkt_addr; /* Packet buffer address */
657 __le64 hdr_addr; /* Header buffer address */
658 /* bit 0 of hdr_buffer_addr is DD bit */
659 __le64 rsvd1;
660 __le64 rsvd2;
661 } read;
662 struct {
663 struct i40e_32b_rx_wb_qw0 {
664 struct {
665 union {
666 __le16 mirroring_status;
667 __le16 fcoe_ctx_id;
668 } mirr_fcoe;
669 __le16 l2tag1;
670 } lo_dword;
671 union {
672 __le32 rss; /* RSS Hash */
673 __le32 fcoe_param; /* FCoE DDP Context id */
674 /* Flow director filter id in case of
675 * Programming status desc WB
676 */
677 __le32 fd_id;
678 } hi_dword;
679 } qword0;
680 struct {
681 /* status/error/pktype/length */
682 __le64 status_error_len;
683 } qword1;
684 struct {
685 __le16 ext_status; /* extended status */
686 __le16 rsvd;
687 __le16 l2tag2_1;
688 __le16 l2tag2_2;
689 } qword2;
690 struct {
691 union {
692 __le32 flex_bytes_lo;
693 __le32 pe_status;
694 } lo_dword;
695 union {
696 __le32 flex_bytes_hi;
697 __le32 fd_id;
698 } hi_dword;
699 } qword3;
700 } wb; /* writeback */
701 struct {
702 u64 qword[4];
703 } raw;
704 };
705
706 enum i40e_rx_desc_status_bits {
707 /* Note: These are predefined bit offsets */
708 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
709 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
710 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
711 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
712 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
713 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
714 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
715 /* Note: Bit 8 is reserved in X710 and XL710 */
716 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
717 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
718 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
719 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
720 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
721 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
722 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
723 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
724 * UDP header
725 */
726 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
727 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
728 };
729
730 #define I40E_RXD_QW1_STATUS_SHIFT 0
731 #define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
732 << I40E_RXD_QW1_STATUS_SHIFT)
733
734 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
735 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
736 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
737
738 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
739 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
740 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
741
742 enum i40e_rx_desc_fltstat_values {
743 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
744 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
745 I40E_RX_DESC_FLTSTAT_RSV = 2,
746 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
747 };
748
749 #define I40E_RXD_QW1_ERROR_SHIFT 19
750 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
751
752 enum i40e_rx_desc_error_bits {
753 /* Note: These are predefined bit offsets */
754 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
755 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
756 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
757 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
758 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
759 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
760 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
761 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
762 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
763 };
764
765 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
766 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
767 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
768 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
769 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
770 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
771 };
772
773 #define I40E_RXD_QW1_PTYPE_SHIFT 30
774 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
775
776 /* Packet type non-ip values */
777 enum i40e_rx_l2_ptype {
778 I40E_RX_PTYPE_L2_RESERVED = 0,
779 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
780 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
781 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
782 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
783 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
784 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
785 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
786 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
787 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
788 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
789 I40E_RX_PTYPE_L2_ARP = 11,
790 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
791 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
792 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
793 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
794 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
795 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
796 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
797 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
798 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
799 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
800 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
801 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
802 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
803 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
804 };
805
806 struct i40e_rx_ptype_decoded {
807 u32 known:1;
808 u32 outer_ip:1;
809 u32 outer_ip_ver:1;
810 u32 outer_frag:1;
811 u32 tunnel_type:3;
812 u32 tunnel_end_prot:2;
813 u32 tunnel_end_frag:1;
814 u32 inner_prot:4;
815 u32 payload_layer:3;
816 };
817
818 enum i40e_rx_ptype_outer_ip {
819 I40E_RX_PTYPE_OUTER_L2 = 0,
820 I40E_RX_PTYPE_OUTER_IP = 1
821 };
822
823 enum i40e_rx_ptype_outer_ip_ver {
824 I40E_RX_PTYPE_OUTER_NONE = 0,
825 I40E_RX_PTYPE_OUTER_IPV4 = 0,
826 I40E_RX_PTYPE_OUTER_IPV6 = 1
827 };
828
829 enum i40e_rx_ptype_outer_fragmented {
830 I40E_RX_PTYPE_NOT_FRAG = 0,
831 I40E_RX_PTYPE_FRAG = 1
832 };
833
834 enum i40e_rx_ptype_tunnel_type {
835 I40E_RX_PTYPE_TUNNEL_NONE = 0,
836 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
837 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
838 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
839 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
840 };
841
842 enum i40e_rx_ptype_tunnel_end_prot {
843 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
844 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
845 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
846 };
847
848 enum i40e_rx_ptype_inner_prot {
849 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
850 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
851 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
852 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
853 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
854 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
855 };
856
857 enum i40e_rx_ptype_payload_layer {
858 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
859 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
860 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
861 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
862 };
863
864 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
865 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
866 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
867
868
869 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
870 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
871
872 enum i40e_rx_desc_ext_status_bits {
873 /* Note: These are predefined bit offsets */
874 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
875 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
876 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
877 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
878 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
879 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
880 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
881 };
882
883 enum i40e_rx_desc_pe_status_bits {
884 /* Note: These are predefined bit offsets */
885 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
886 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
887 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
888 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
889 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
890 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
891 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
892 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
893 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
894 };
895
896 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
897
898 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
899 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
900 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
901
902 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
903 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
904 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
905
906 enum i40e_rx_prog_status_desc_status_bits {
907 /* Note: These are predefined bit offsets */
908 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
909 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
910 };
911
912 enum i40e_rx_prog_status_desc_prog_id_masks {
913 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
914 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
915 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
916 };
917
918 enum i40e_rx_prog_status_desc_error_bits {
919 /* Note: These are predefined bit offsets */
920 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
921 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
922 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
923 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
924 };
925
926 /* TX Descriptor */
927 struct i40e_tx_desc {
928 __le64 buffer_addr; /* Address of descriptor's data buf */
929 __le64 cmd_type_offset_bsz;
930 };
931
932
933 enum i40e_tx_desc_dtype_value {
934 I40E_TX_DESC_DTYPE_DATA = 0x0,
935 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
936 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
937 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
938 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
939 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
940 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
941 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
942 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
943 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
944 };
945
946 #define I40E_TXD_QW1_CMD_SHIFT 4
947
948 enum i40e_tx_desc_cmd_bits {
949 I40E_TX_DESC_CMD_EOP = 0x0001,
950 I40E_TX_DESC_CMD_RS = 0x0002,
951 I40E_TX_DESC_CMD_ICRC = 0x0004,
952 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
953 I40E_TX_DESC_CMD_DUMMY = 0x0010,
954 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
955 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
956 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
957 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
958 I40E_TX_DESC_CMD_FCOET = 0x0080,
959 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
960 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
961 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
962 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
963 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
964 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
965 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
966 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
967 };
968
969 #define I40E_TXD_QW1_OFFSET_SHIFT 16
970
971 enum i40e_tx_desc_length_fields {
972 /* Note: These are predefined bit offsets */
973 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
974 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
975 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
976 };
977
978 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
979
980 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
981
982 /* Context descriptors */
983 struct i40e_tx_context_desc {
984 __le32 tunneling_params;
985 __le16 l2tag2;
986 __le16 rsvd;
987 __le64 type_cmd_tso_mss;
988 };
989
990
991 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
992
993 enum i40e_tx_ctx_desc_cmd_bits {
994 I40E_TX_CTX_DESC_TSO = 0x01,
995 I40E_TX_CTX_DESC_TSYN = 0x02,
996 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
997 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
998 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
999 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
1000 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
1001 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
1002 I40E_TX_CTX_DESC_SWPE = 0x40
1003 };
1004
1005 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
1006
1007 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
1008
1009
1010
1011 enum i40e_tx_ctx_desc_eipt_offload {
1012 I40E_TX_CTX_EXT_IP_NONE = 0x0,
1013 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
1014 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1015 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
1016 };
1017
1018 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1019
1020 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1021
1022 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1023 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1024
1025
1026
1027 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1028
1029
1030 #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1031 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1032 struct i40e_filter_program_desc {
1033 __le32 qindex_flex_ptype_vsi;
1034 __le32 rsvd;
1035 __le32 dtype_cmd_cntindex;
1036 __le32 fd_id;
1037 };
1038 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1039 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1040 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1041 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1042 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1043 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1044 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1045 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1046 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1047
1048 /* Packet Classifier Types for filters */
1049 enum i40e_filter_pctype {
1050 /* Note: Values 0-28 are reserved for future use.
1051 * Value 29, 30, 32 are not supported on XL710 and X710.
1052 */
1053 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1054 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1055 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1056 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1057 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1058 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1059 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1060 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1061 /* Note: Values 37-38 are reserved for future use.
1062 * Value 39, 40, 42 are not supported on XL710 and X710.
1063 */
1064 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1065 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1066 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1067 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1068 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1069 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1070 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1071 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1072 /* Note: Value 47 is reserved for future use */
1073 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1074 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1075 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1076 /* Note: Values 51-62 are reserved for future use */
1077 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1078 };
1079
1080 enum i40e_filter_program_desc_dest {
1081 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1082 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1083 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1084 };
1085
1086 enum i40e_filter_program_desc_fd_status {
1087 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1088 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1089 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1090 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1091 };
1092
1093 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1094 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1095 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1096
1097 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1098
1099 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1100
1101 enum i40e_filter_program_desc_pcmd {
1102 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1103 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1104 };
1105
1106 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1107 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1108
1109 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1110 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1111
1112 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1113 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1114 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1115 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1116
1117 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1118 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1119 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1120
1121 #define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1122 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1123 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1124
1125 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1126 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1127 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1128
1129 enum i40e_filter_type {
1130 I40E_FLOW_DIRECTOR_FLTR = 0,
1131 I40E_PE_QUAD_HASH_FLTR = 1,
1132 I40E_ETHERTYPE_FLTR,
1133 I40E_FCOE_CTX_FLTR,
1134 I40E_MAC_VLAN_FLTR,
1135 I40E_HASH_FLTR
1136 };
1137
1138 struct i40e_vsi_context {
1139 u16 seid;
1140 u16 uplink_seid;
1141 u16 vsi_number;
1142 u16 vsis_allocated;
1143 u16 vsis_unallocated;
1144 u16 flags;
1145 u8 pf_num;
1146 u8 vf_num;
1147 u8 connection_type;
1148 struct i40e_aqc_vsi_properties_data info;
1149 };
1150
1151 struct i40e_veb_context {
1152 u16 seid;
1153 u16 uplink_seid;
1154 u16 veb_number;
1155 u16 vebs_allocated;
1156 u16 vebs_unallocated;
1157 u16 flags;
1158 struct i40e_aqc_get_veb_parameters_completion info;
1159 };
1160
1161 /* Statistics collected by each port, VSI, VEB, and S-channel */
1162 struct i40e_eth_stats {
1163 u64 rx_bytes; /* gorc */
1164 u64 rx_unicast; /* uprc */
1165 u64 rx_multicast; /* mprc */
1166 u64 rx_broadcast; /* bprc */
1167 u64 rx_discards; /* rdpc */
1168 u64 rx_unknown_protocol; /* rupp */
1169 u64 tx_bytes; /* gotc */
1170 u64 tx_unicast; /* uptc */
1171 u64 tx_multicast; /* mptc */
1172 u64 tx_broadcast; /* bptc */
1173 u64 tx_discards; /* tdpc */
1174 u64 tx_errors; /* tepc */
1175 };
1176
1177 /* Statistics collected per VEB per TC */
1178 struct i40e_veb_tc_stats {
1179 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1180 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1181 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1182 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1183 };
1184
1185 /* Statistics collected by the MAC */
1186 struct i40e_hw_port_stats {
1187 /* eth stats collected by the port */
1188 struct i40e_eth_stats eth;
1189
1190 /* additional port specific stats */
1191 u64 tx_dropped_link_down; /* tdold */
1192 u64 crc_errors; /* crcerrs */
1193 u64 illegal_bytes; /* illerrc */
1194 u64 error_bytes; /* errbc */
1195 u64 mac_local_faults; /* mlfc */
1196 u64 mac_remote_faults; /* mrfc */
1197 u64 rx_length_errors; /* rlec */
1198 u64 link_xon_rx; /* lxonrxc */
1199 u64 link_xoff_rx; /* lxoffrxc */
1200 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1201 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1202 u64 link_xon_tx; /* lxontxc */
1203 u64 link_xoff_tx; /* lxofftxc */
1204 u64 priority_xon_tx[8]; /* pxontxc[8] */
1205 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1206 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1207 u64 rx_size_64; /* prc64 */
1208 u64 rx_size_127; /* prc127 */
1209 u64 rx_size_255; /* prc255 */
1210 u64 rx_size_511; /* prc511 */
1211 u64 rx_size_1023; /* prc1023 */
1212 u64 rx_size_1522; /* prc1522 */
1213 u64 rx_size_big; /* prc9522 */
1214 u64 rx_undersize; /* ruc */
1215 u64 rx_fragments; /* rfc */
1216 u64 rx_oversize; /* roc */
1217 u64 rx_jabber; /* rjc */
1218 u64 tx_size_64; /* ptc64 */
1219 u64 tx_size_127; /* ptc127 */
1220 u64 tx_size_255; /* ptc255 */
1221 u64 tx_size_511; /* ptc511 */
1222 u64 tx_size_1023; /* ptc1023 */
1223 u64 tx_size_1522; /* ptc1522 */
1224 u64 tx_size_big; /* ptc9522 */
1225 u64 mac_short_packet_dropped; /* mspdc */
1226 u64 checksum_error; /* xec */
1227 /* flow director stats */
1228 u64 fd_atr_match;
1229 u64 fd_sb_match;
1230 u64 fd_atr_tunnel_match;
1231 u32 fd_atr_status;
1232 u32 fd_sb_status;
1233 /* EEE LPI */
1234 u32 tx_lpi_status;
1235 u32 rx_lpi_status;
1236 u64 tx_lpi_count; /* etlpic */
1237 u64 rx_lpi_count; /* erlpic */
1238 };
1239
1240 /* Checksum and Shadow RAM pointers */
1241 #define I40E_SR_NVM_CONTROL_WORD 0x00
1242 #define I40E_EMP_MODULE_PTR 0x0F
1243 #define I40E_SR_EMP_MODULE_PTR 0x48
1244 #define I40E_SR_PBA_FLAGS 0x15
1245 #define I40E_SR_PBA_BLOCK_PTR 0x16
1246 #define I40E_SR_BOOT_CONFIG_PTR 0x17
1247 #define I40E_NVM_OEM_VER_OFF 0x83
1248 #define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1249 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1250 #define I40E_SR_NVM_EETRACK_LO 0x2D
1251 #define I40E_SR_NVM_EETRACK_HI 0x2E
1252 #define I40E_SR_VPD_PTR 0x2F
1253 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1254 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1255 #define I40E_SR_EMP_SR_SETTINGS_PTR 0x48
1256
1257 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1258 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1259 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1260 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1261 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1262 #define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)
1263 #define I40E_PTR_TYPE BIT(15)
1264 #define I40E_SR_OCP_CFG_WORD0 0x2B
1265 #define I40E_SR_OCP_ENABLED BIT(15)
1266
1267 /* Shadow RAM related */
1268 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1269 #define I40E_SR_WORDS_IN_1KB 512
1270 /* Checksum should be calculated such that after adding all the words,
1271 * including the checksum word itself, the sum should be 0xBABA.
1272 */
1273 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1274
1275 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1276
1277 enum i40e_switch_element_types {
1278 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1279 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1280 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1281 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1282 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1283 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1284 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1285 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1286 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1287 };
1288
1289 /* Supported EtherType filters */
1290 enum i40e_ether_type_index {
1291 I40E_ETHER_TYPE_1588 = 0,
1292 I40E_ETHER_TYPE_FIP = 1,
1293 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1294 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1295 I40E_ETHER_TYPE_LLDP = 4,
1296 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1297 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1298 I40E_ETHER_TYPE_QCN_CNM = 7,
1299 I40E_ETHER_TYPE_8021X = 8,
1300 I40E_ETHER_TYPE_ARP = 9,
1301 I40E_ETHER_TYPE_RSV1 = 10,
1302 I40E_ETHER_TYPE_RSV2 = 11,
1303 };
1304
1305 /* Filter context base size is 1K */
1306 #define I40E_HASH_FILTER_BASE_SIZE 1024
1307 /* Supported Hash filter values */
1308 enum i40e_hash_filter_size {
1309 I40E_HASH_FILTER_SIZE_1K = 0,
1310 I40E_HASH_FILTER_SIZE_2K = 1,
1311 I40E_HASH_FILTER_SIZE_4K = 2,
1312 I40E_HASH_FILTER_SIZE_8K = 3,
1313 I40E_HASH_FILTER_SIZE_16K = 4,
1314 I40E_HASH_FILTER_SIZE_32K = 5,
1315 I40E_HASH_FILTER_SIZE_64K = 6,
1316 I40E_HASH_FILTER_SIZE_128K = 7,
1317 I40E_HASH_FILTER_SIZE_256K = 8,
1318 I40E_HASH_FILTER_SIZE_512K = 9,
1319 I40E_HASH_FILTER_SIZE_1M = 10,
1320 };
1321
1322 /* DMA context base size is 0.5K */
1323 #define I40E_DMA_CNTX_BASE_SIZE 512
1324 /* Supported DMA context values */
1325 enum i40e_dma_cntx_size {
1326 I40E_DMA_CNTX_SIZE_512 = 0,
1327 I40E_DMA_CNTX_SIZE_1K = 1,
1328 I40E_DMA_CNTX_SIZE_2K = 2,
1329 I40E_DMA_CNTX_SIZE_4K = 3,
1330 I40E_DMA_CNTX_SIZE_8K = 4,
1331 I40E_DMA_CNTX_SIZE_16K = 5,
1332 I40E_DMA_CNTX_SIZE_32K = 6,
1333 I40E_DMA_CNTX_SIZE_64K = 7,
1334 I40E_DMA_CNTX_SIZE_128K = 8,
1335 I40E_DMA_CNTX_SIZE_256K = 9,
1336 };
1337
1338 /* Supported Hash look up table (LUT) sizes */
1339 enum i40e_hash_lut_size {
1340 I40E_HASH_LUT_SIZE_128 = 0,
1341 I40E_HASH_LUT_SIZE_512 = 1,
1342 };
1343
1344 /* Structure to hold a per PF filter control settings */
1345 struct i40e_filter_control_settings {
1346 /* number of PE Quad Hash filter buckets */
1347 enum i40e_hash_filter_size pe_filt_num;
1348 /* number of PE Quad Hash contexts */
1349 enum i40e_dma_cntx_size pe_cntx_num;
1350 /* number of FCoE filter buckets */
1351 enum i40e_hash_filter_size fcoe_filt_num;
1352 /* number of FCoE DDP contexts */
1353 enum i40e_dma_cntx_size fcoe_cntx_num;
1354 /* size of the Hash LUT */
1355 enum i40e_hash_lut_size hash_lut_size;
1356 /* enable FDIR filters for PF and its VFs */
1357 bool enable_fdir;
1358 /* enable Ethertype filters for PF and its VFs */
1359 bool enable_ethtype;
1360 /* enable MAC/VLAN filters for PF and its VFs */
1361 bool enable_macvlan;
1362 };
1363
1364 /* Structure to hold device level control filter counts */
1365 struct i40e_control_filter_stats {
1366 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1367 u16 etype_used; /* Used perfect EtherType filters */
1368 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1369 u16 etype_free; /* Un-used perfect EtherType filters */
1370 };
1371
1372 enum i40e_reset_type {
1373 I40E_RESET_POR = 0,
1374 I40E_RESET_CORER = 1,
1375 I40E_RESET_GLOBR = 2,
1376 I40E_RESET_EMPR = 3,
1377 };
1378
1379 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1380 #define I40E_NVM_LLDP_CFG_PTR 0x06
1381 #define I40E_SR_LLDP_CFG_PTR 0x31
1382 struct i40e_lldp_variables {
1383 u16 length;
1384 u16 adminstatus;
1385 u16 msgfasttx;
1386 u16 msgtxinterval;
1387 u16 txparams;
1388 u16 timers;
1389 u16 crc8;
1390 };
1391
1392 /* Offsets into Alternate Ram */
1393 #define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */
1394 #define I40E_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */
1395 #define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */
1396 #define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */
1397
1398 /* Alternate Ram Bandwidth Masks */
1399 #define I40E_ALT_BW_VALUE_MASK 0xFF
1400 #define I40E_ALT_BW_VALID_MASK 0x80000000
1401
1402 /* RSS Hash Table Size */
1403 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1404
1405 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1406 #define I40E_L3_SRC_SHIFT 47
1407 #define I40E_L3_SRC_MASK (0x3ULL << I40E_L3_SRC_SHIFT)
1408 #define I40E_L3_V6_SRC_SHIFT 43
1409 #define I40E_L3_V6_SRC_MASK (0xFFULL << I40E_L3_V6_SRC_SHIFT)
1410 #define I40E_L3_DST_SHIFT 35
1411 #define I40E_L3_DST_MASK (0x3ULL << I40E_L3_DST_SHIFT)
1412 #define I40E_L3_V6_DST_SHIFT 35
1413 #define I40E_L3_V6_DST_MASK (0xFFULL << I40E_L3_V6_DST_SHIFT)
1414 #define I40E_L4_SRC_SHIFT 34
1415 #define I40E_L4_SRC_MASK (0x1ULL << I40E_L4_SRC_SHIFT)
1416 #define I40E_L4_DST_SHIFT 33
1417 #define I40E_L4_DST_MASK (0x1ULL << I40E_L4_DST_SHIFT)
1418 #define I40E_VERIFY_TAG_SHIFT 31
1419 #define I40E_VERIFY_TAG_MASK (0x3ULL << I40E_VERIFY_TAG_SHIFT)
1420 #define I40E_VLAN_SRC_SHIFT 55
1421 #define I40E_VLAN_SRC_MASK (0x1ULL << I40E_VLAN_SRC_SHIFT)
1422
1423 #define I40E_FLEX_50_SHIFT 13
1424 #define I40E_FLEX_50_MASK (0x1ULL << I40E_FLEX_50_SHIFT)
1425 #define I40E_FLEX_51_SHIFT 12
1426 #define I40E_FLEX_51_MASK (0x1ULL << I40E_FLEX_51_SHIFT)
1427 #define I40E_FLEX_52_SHIFT 11
1428 #define I40E_FLEX_52_MASK (0x1ULL << I40E_FLEX_52_SHIFT)
1429 #define I40E_FLEX_53_SHIFT 10
1430 #define I40E_FLEX_53_MASK (0x1ULL << I40E_FLEX_53_SHIFT)
1431 #define I40E_FLEX_54_SHIFT 9
1432 #define I40E_FLEX_54_MASK (0x1ULL << I40E_FLEX_54_SHIFT)
1433 #define I40E_FLEX_55_SHIFT 8
1434 #define I40E_FLEX_55_MASK (0x1ULL << I40E_FLEX_55_SHIFT)
1435 #define I40E_FLEX_56_SHIFT 7
1436 #define I40E_FLEX_56_MASK (0x1ULL << I40E_FLEX_56_SHIFT)
1437 #define I40E_FLEX_57_SHIFT 6
1438 #define I40E_FLEX_57_MASK (0x1ULL << I40E_FLEX_57_SHIFT)
1439
1440 /* Version format for Dynamic Device Personalization(DDP) */
1441 struct i40e_ddp_version {
1442 u8 major;
1443 u8 minor;
1444 u8 update;
1445 u8 draft;
1446 };
1447
1448 #define I40E_DDP_NAME_SIZE 32
1449
1450 /* Package header */
1451 struct i40e_package_header {
1452 struct i40e_ddp_version version;
1453 u32 segment_count;
1454 u32 segment_offset[1];
1455 };
1456
1457 /* Generic segment header */
1458 struct i40e_generic_seg_header {
1459 #define SEGMENT_TYPE_METADATA 0x00000001
1460 #define SEGMENT_TYPE_I40E 0x00000011
1461 u32 type;
1462 struct i40e_ddp_version version;
1463 u32 size;
1464 char name[I40E_DDP_NAME_SIZE];
1465 };
1466
1467 struct i40e_metadata_segment {
1468 struct i40e_generic_seg_header header;
1469 struct i40e_ddp_version version;
1470 #define I40E_DDP_TRACKID_INVALID 0xFFFFFFFF
1471 u32 track_id;
1472 char name[I40E_DDP_NAME_SIZE];
1473 };
1474
1475 struct i40e_device_id_entry {
1476 u32 vendor_dev_id;
1477 u32 sub_vendor_dev_id;
1478 };
1479
1480 struct i40e_profile_segment {
1481 struct i40e_generic_seg_header header;
1482 struct i40e_ddp_version version;
1483 char name[I40E_DDP_NAME_SIZE];
1484 u32 device_table_count;
1485 struct i40e_device_id_entry device_table[1];
1486 };
1487
1488 struct i40e_section_table {
1489 u32 section_count;
1490 u32 section_offset[1];
1491 };
1492
1493 struct i40e_profile_section_header {
1494 u16 tbl_size;
1495 u16 data_end;
1496 struct {
1497 #define SECTION_TYPE_INFO 0x00000010
1498 #define SECTION_TYPE_MMIO 0x00000800
1499 #define SECTION_TYPE_RB_MMIO 0x00001800
1500 #define SECTION_TYPE_AQ 0x00000801
1501 #define SECTION_TYPE_RB_AQ 0x00001801
1502 #define SECTION_TYPE_NOTE 0x80000000
1503 u32 type;
1504 u32 offset;
1505 u32 size;
1506 } section;
1507 };
1508
1509 struct i40e_profile_tlv_section_record {
1510 u8 rtype;
1511 u8 type;
1512 u16 len;
1513 u8 data[12];
1514 };
1515
1516 /* Generic AQ section in proflie */
1517 struct i40e_profile_aq_section {
1518 u16 opcode;
1519 u16 flags;
1520 u8 param[16];
1521 u16 datalen;
1522 u8 data[1];
1523 };
1524
1525 struct i40e_profile_info {
1526 u32 track_id;
1527 struct i40e_ddp_version version;
1528 u8 op;
1529 #define I40E_DDP_ADD_TRACKID 0x01
1530 #define I40E_DDP_REMOVE_TRACKID 0x02
1531 u8 reserved[7];
1532 u8 name[I40E_DDP_NAME_SIZE];
1533 };
1534 #endif /* _I40E_TYPE_H_ */
1535
