1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2011 Realtek Corporation. */
3
4 #define _RTL8188E_MP_C_
5
6 #include "../include/drv_types.h"
7 #include "../include/rtw_mp.h"
8 #include "../include/rtl8188e_hal.h"
9 #include "../include/rtl8188e_dm.h"
10
Hal_SetPowerTracking(struct adapter * padapter,u8 enable)11 s32 Hal_SetPowerTracking(struct adapter *padapter, u8 enable)
12 {
13 struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
14 struct odm_dm_struct *pDM_Odm = &pHalData->odmpriv;
15
16 if (!netif_running(padapter->pnetdev))
17 return _FAIL;
18
19 if (!check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE))
20 return _FAIL;
21
22 if (enable)
23 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = true;
24 else
25 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = false;
26
27 return _SUCCESS;
28 }
29
Hal_GetPowerTracking(struct adapter * padapter,u8 * enable)30 void Hal_GetPowerTracking(struct adapter *padapter, u8 *enable)
31 {
32 struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
33 struct odm_dm_struct *pDM_Odm = &pHalData->odmpriv;
34
35 *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl;
36 }
37
38 /*-----------------------------------------------------------------------------
39 * Function: mpt_SwitchRfSetting
40 *
41 * Overview: Change RF Setting when we siwthc channel/rate/BW for MP.
42 *
43 * Input: struct adapter * pAdapter
44 *
45 * Output: NONE
46 *
47 * Return: NONE
48 *
49 * Revised History:
50 * When Who Remark
51 * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series.
52 * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
53 *
54 *---------------------------------------------------------------------------*/
Hal_mpt_SwitchRfSetting(struct adapter * pAdapter)55 void Hal_mpt_SwitchRfSetting(struct adapter *pAdapter)
56 {
57 struct mp_priv *pmp = &pAdapter->mppriv;
58
59 /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis. */
60 pmp->MptCtx.backup0x52_RF_A = (u8)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
61 pmp->MptCtx.backup0x52_RF_B = (u8)PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
62 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0, 0xD);
63 PHY_SetRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0, 0xD);
64 }
65 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
66
67 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
Hal_MPT_CCKTxPowerAdjust(struct adapter * Adapter,bool bInCH14)68 void Hal_MPT_CCKTxPowerAdjust(struct adapter *Adapter, bool bInCH14)
69 {
70 u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
71 u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
72 u8 i;
73
74 /* get current cck swing value and check 0xa22 & 0xa23 later to match the table. */
75 CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
76
77 if (!bInCH14) {
78 /* Readback the current bb cck swing value and compare with the table to */
79 /* get the current swing index */
80 for (i = 0; i < CCK_TABLE_SIZE; i++) {
81 if (((CurrCCKSwingVal & 0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
82 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) {
83 CCKSwingIndex = i;
84 break;
85 }
86 }
87
88 /* Write 0xa22 0xa23 */
89 TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
90 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1] << 8);
91
92 /* Write 0xa24 ~ 0xa27 */
93 TempVal2 = 0;
94 TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
95 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3] << 8) +
96 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4] << 16) +
97 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5] << 24);
98
99 /* Write 0xa28 0xa29 */
100 TempVal3 = 0;
101 TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
102 (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7] << 8);
103 } else {
104 for (i = 0; i < CCK_TABLE_SIZE; i++) {
105 if (((CurrCCKSwingVal & 0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
106 (((CurrCCKSwingVal & 0xff00) >> 8) == (u32)CCKSwingTable_Ch14[i][1])) {
107 CCKSwingIndex = i;
108 break;
109 }
110 }
111
112 /* Write 0xa22 0xa23 */
113 TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
114 (CCKSwingTable_Ch14[CCKSwingIndex][1] << 8);
115
116 /* Write 0xa24 ~ 0xa27 */
117 TempVal2 = 0;
118 TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
119 (CCKSwingTable_Ch14[CCKSwingIndex][3] << 8) +
120 (CCKSwingTable_Ch14[CCKSwingIndex][4] << 16) +
121 (CCKSwingTable_Ch14[CCKSwingIndex][5] << 24);
122
123 /* Write 0xa28 0xa29 */
124 TempVal3 = 0;
125 TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
126 (CCKSwingTable_Ch14[CCKSwingIndex][7] << 8);
127 }
128
129 write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
130 write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
131 write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
132 }
133
Hal_MPT_CCKTxPowerAdjustbyIndex(struct adapter * pAdapter,bool beven)134 void Hal_MPT_CCKTxPowerAdjustbyIndex(struct adapter *pAdapter, bool beven)
135 {
136 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
137 struct mpt_context *pMptCtx = &pAdapter->mppriv.MptCtx;
138 struct odm_dm_struct *pDM_Odm = &pHalData->odmpriv;
139 s32 TempCCk;
140 u8 CCK_index, CCK_index_old = 0;
141 u8 Action = 0; /* 0: no action, 1: even->odd, 2:odd->even */
142 s32 i = 0;
143
144 if (!IS_92C_SERIAL(pHalData->VersionID))
145 return;
146 if (beven && !pMptCtx->bMptIndexEven) {
147 /* odd->even */
148 Action = 2;
149 pMptCtx->bMptIndexEven = true;
150 } else if (!beven && pMptCtx->bMptIndexEven) {
151 /* even->odd */
152 Action = 1;
153 pMptCtx->bMptIndexEven = false;
154 }
155
156 if (Action != 0) {
157 /* Query CCK default setting From 0xa24 */
158 TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;
159 for (i = 0; i < CCK_TABLE_SIZE; i++) {
160 if (pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
161 if (!memcmp((void *)&TempCCk, (void *)&CCKSwingTable_Ch14[i][2], 4)) {
162 CCK_index_old = (u8)i;
163 break;
164 }
165 } else {
166 if (!memcmp((void *)&TempCCk, (void *)&CCKSwingTable_Ch1_Ch13[i][2], 4)) {
167 CCK_index_old = (u8)i;
168 break;
169 }
170 }
171 }
172
173 if (Action == 1)
174 CCK_index = CCK_index_old - 1;
175 else
176 CCK_index = CCK_index_old + 1;
177
178 /* Adjust CCK according to gain index */
179 if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
180 rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);
181 rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);
182 rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);
183 rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);
184 rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);
185 rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);
186 rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);
187 rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);
188 } else {
189 rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);
190 rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);
191 rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);
192 rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);
193 rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);
194 rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);
195 rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);
196 rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);
197 }
198 }
199 }
200 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
201
202 /*
203 * SetChannel
204 * Description
205 * Use H2C command to change channel,
206 * not only modify rf register, but also other setting need to be done.
207 */
Hal_SetChannel(struct adapter * pAdapter)208 void Hal_SetChannel(struct adapter *pAdapter)
209 {
210 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
211 struct mp_priv *pmp = &pAdapter->mppriv;
212 struct odm_dm_struct *pDM_Odm = &pHalData->odmpriv;
213 u8 eRFPath;
214 u8 channel = pmp->channel;
215
216 /* set RF channel register */
217 for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
218 _write_rfreg(pAdapter, eRFPath, ODM_CHANNEL, 0x3FF, channel);
219 Hal_mpt_SwitchRfSetting(pAdapter);
220
221 SelectChannel(pAdapter, channel);
222
223 if (pHalData->CurrentChannel == 14 && !pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
224 pDM_Odm->RFCalibrateInfo.bCCKinCH14 = true;
225 Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
226 } else if (pHalData->CurrentChannel != 14 && pDM_Odm->RFCalibrateInfo.bCCKinCH14) {
227 pDM_Odm->RFCalibrateInfo.bCCKinCH14 = false;
228 Hal_MPT_CCKTxPowerAdjust(pAdapter, pDM_Odm->RFCalibrateInfo.bCCKinCH14);
229 }
230 }
231
232 /*
233 * Notice
234 * Switch bandwitdth may change center frequency(channel)
235 */
Hal_SetBandwidth(struct adapter * pAdapter)236 void Hal_SetBandwidth(struct adapter *pAdapter)
237 {
238 struct mp_priv *pmp = &pAdapter->mppriv;
239
240 SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);
241 Hal_mpt_SwitchRfSetting(pAdapter);
242 }
243
Hal_SetCCKTxPower(struct adapter * pAdapter,u8 * TxPower)244 void Hal_SetCCKTxPower(struct adapter *pAdapter, u8 *TxPower)
245 {
246 u32 tmpval = 0;
247
248 /* rf-A cck tx power */
249 write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);
250 tmpval = (TxPower[RF_PATH_A] << 16) | (TxPower[RF_PATH_A] << 8) | TxPower[RF_PATH_A];
251 write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
252
253 /* rf-B cck tx power */
254 write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);
255 tmpval = (TxPower[RF_PATH_B] << 16) | (TxPower[RF_PATH_B] << 8) | TxPower[RF_PATH_B];
256 write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
257 }
258
Hal_SetOFDMTxPower(struct adapter * pAdapter,u8 * TxPower)259 void Hal_SetOFDMTxPower(struct adapter *pAdapter, u8 *TxPower)
260 {
261 u32 TxAGC = 0;
262 u8 tmpval = 0;
263
264 /* HT Tx-rf(A) */
265 tmpval = TxPower[RF_PATH_A];
266 TxAGC = (tmpval << 24) | (tmpval << 16) | (tmpval << 8) | tmpval;
267
268 write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
269 write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
270 write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
271 write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
272 write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
273 write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
274
275 /* HT Tx-rf(B) */
276 tmpval = TxPower[RF_PATH_B];
277 TxAGC = (tmpval << 24) | (tmpval << 16) | (tmpval << 8) | tmpval;
278
279 write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
280 write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
281 write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
282 write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
283 write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
284 write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
285 }
286
Hal_SetAntennaPathPower(struct adapter * pAdapter)287 void Hal_SetAntennaPathPower(struct adapter *pAdapter)
288 {
289 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
290 u8 TxPowerLevel[RF_PATH_MAX];
291 u8 rfPath;
292
293 TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;
294 TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;
295
296 switch (pAdapter->mppriv.antenna_tx) {
297 case ANTENNA_A:
298 default:
299 rfPath = RF_PATH_A;
300 break;
301 case ANTENNA_B:
302 rfPath = RF_PATH_B;
303 break;
304 case ANTENNA_C:
305 rfPath = RF_PATH_C;
306 break;
307 }
308
309 switch (pHalData->rf_chip) {
310 case RF_8225:
311 case RF_8256:
312 case RF_6052:
313 Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
314 if (pAdapter->mppriv.rateidx < MPT_RATE_6M) /* CCK rate */
315 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath] % 2 == 0);
316 Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
317 break;
318 default:
319 break;
320 }
321 }
322
Hal_SetTxPower(struct adapter * pAdapter)323 void Hal_SetTxPower(struct adapter *pAdapter)
324 {
325 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
326 u8 TxPower = pAdapter->mppriv.txpoweridx;
327 u8 TxPowerLevel[RF_PATH_MAX];
328 u8 rf, rfPath;
329
330 for (rf = 0; rf < RF_PATH_MAX; rf++)
331 TxPowerLevel[rf] = TxPower;
332
333 switch (pAdapter->mppriv.antenna_tx) {
334 case ANTENNA_A:
335 default:
336 rfPath = RF_PATH_A;
337 break;
338 case ANTENNA_B:
339 rfPath = RF_PATH_B;
340 break;
341 case ANTENNA_C:
342 rfPath = RF_PATH_C;
343 break;
344 }
345
346 switch (pHalData->rf_chip) {
347 /* 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!! */
348 /* We should call normal driver API later!! */
349 case RF_8225:
350 case RF_8256:
351 case RF_6052:
352 Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
353 if (pAdapter->mppriv.rateidx < MPT_RATE_6M) /* CCK rate */
354 Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath] % 2 == 0);
355 Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
356 break;
357 default:
358 break;
359 }
360 }
361
Hal_SetDataRate(struct adapter * pAdapter)362 void Hal_SetDataRate(struct adapter *pAdapter)
363 {
364 Hal_mpt_SwitchRfSetting(pAdapter);
365 }
366
Hal_SetAntenna(struct adapter * pAdapter)367 void Hal_SetAntenna(struct adapter *pAdapter)
368 {
369 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
370
371 struct ant_sel_ofdm *p_ofdm_tx; /* OFDM Tx register */
372 struct ant_sel_cck *p_cck_txrx;
373 u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
374 u8 chgTx = 0, chgRx = 0;
375 u32 r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
376
377 p_ofdm_tx = (struct ant_sel_ofdm *)&r_ant_select_ofdm_val;
378 p_cck_txrx = (struct ant_sel_cck *)&r_ant_select_cck_val;
379
380 p_ofdm_tx->r_ant_ht1 = 0x1;
381 p_ofdm_tx->r_ant_ht2 = 0x2; /* Second TX RF path is A */
382 p_ofdm_tx->r_ant_non_ht = 0x3; /* 0x1+0x2=0x3 */
383
384 switch (pAdapter->mppriv.antenna_tx) {
385 case ANTENNA_A:
386 p_ofdm_tx->r_tx_antenna = 0x1;
387 r_ofdm_tx_en_val = 0x1;
388 p_ofdm_tx->r_ant_l = 0x1;
389 p_ofdm_tx->r_ant_ht_s1 = 0x1;
390 p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
391 p_cck_txrx->r_ccktx_enable = 0x8;
392 chgTx = 1;
393
394 /* From SD3 Willis suggestion !!! Set RF A=TX and B as standby */
395 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
396 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
397 r_ofdm_tx_en_val = 0x3;
398
399 /* Power save */
400
401 /* We need to close RFB by SW control */
402 if (pHalData->rf_type == RF_2T2R) {
403 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0);
404 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT(26), 1);
405 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT(10), 0);
406 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT(1), 1);
407 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT(17), 0);
408 }
409 break;
410 case ANTENNA_B:
411 p_ofdm_tx->r_tx_antenna = 0x2;
412 r_ofdm_tx_en_val = 0x2;
413 p_ofdm_tx->r_ant_l = 0x2;
414 p_ofdm_tx->r_ant_ht_s1 = 0x2;
415 p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
416 p_cck_txrx->r_ccktx_enable = 0x4;
417 chgTx = 1;
418 /* From SD3 Willis suggestion !!! Set RF A as standby */
419 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
420 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
421
422 /* Power save */
423 /* cosa r_ant_select_ofdm_val = 0x22222222; */
424
425 /* 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table. */
426 /* 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control */
427 if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) {
428 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT(10), 1);
429 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT(10), 0);
430 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0);
431 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT(1), 0);
432 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT(17), 1);
433 }
434 break;
435 case ANTENNA_AB: /* For 8192S */
436 p_ofdm_tx->r_tx_antenna = 0x3;
437 r_ofdm_tx_en_val = 0x3;
438 p_ofdm_tx->r_ant_l = 0x3;
439 p_ofdm_tx->r_ant_ht_s1 = 0x3;
440 p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
441 p_cck_txrx->r_ccktx_enable = 0xC;
442 chgTx = 1;
443
444 /* From SD3 Willis suggestion !!! Set RF B as standby */
445 PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
446 PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
447
448 /* Disable Power save */
449 /* cosa r_ant_select_ofdm_val = 0x3321333; */
450 /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control */
451 if (pHalData->rf_type == RF_2T2R) {
452 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0);
453 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0);
454 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT(1), 1);
455 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT(17), 1);
456 }
457 break;
458 default:
459 break;
460 }
461
462 /* r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D */
463 /* r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D */
464 /* r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */
465 switch (pAdapter->mppriv.antenna_rx) {
466 case ANTENNA_A:
467 r_rx_antenna_ofdm = 0x1; /* A */
468 p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
469 p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
470 chgRx = 1;
471 break;
472 case ANTENNA_B:
473 r_rx_antenna_ofdm = 0x2; /* B */
474 p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
475 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
476 chgRx = 1;
477 break;
478 case ANTENNA_AB:
479 r_rx_antenna_ofdm = 0x3; /* AB */
480 p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
481 p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
482 chgRx = 1;
483 break;
484 default:
485 break;
486 }
487
488 if (chgTx && chgRx) {
489 switch (pHalData->rf_chip) {
490 case RF_8225:
491 case RF_8256:
492 case RF_6052:
493 /* r_ant_sel_cck_val = r_ant_select_cck_val; */
494 PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /* OFDM Tx */
495 PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /* OFDM Tx */
496 PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /* OFDM Rx */
497 PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /* OFDM Rx */
498 PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val); /* CCK TxRx */
499
500 break;
501 default:
502 break;
503 }
504 }
505 }
506
Hal_SetThermalMeter(struct adapter * pAdapter,u8 target_ther)507 s32 Hal_SetThermalMeter(struct adapter *pAdapter, u8 target_ther)
508 {
509 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
510
511 if (!netif_running(pAdapter->pnetdev))
512 return _FAIL;
513
514 if (!check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE))
515 return _FAIL;
516
517 target_ther &= 0xff;
518 if (target_ther < 0x07)
519 target_ther = 0x07;
520 else if (target_ther > 0x1d)
521 target_ther = 0x1d;
522
523 pHalData->EEPROMThermalMeter = target_ther;
524
525 return _SUCCESS;
526 }
527
Hal_TriggerRFThermalMeter(struct adapter * pAdapter)528 void Hal_TriggerRFThermalMeter(struct adapter *pAdapter)
529 {
530 _write_rfreg(pAdapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
531 }
532
Hal_ReadRFThermalMeter(struct adapter * pAdapter)533 u8 Hal_ReadRFThermalMeter(struct adapter *pAdapter)
534 {
535 u32 ThermalValue = 0;
536
537 ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER_88E, 0xfc00);
538 return (u8)ThermalValue;
539 }
540
Hal_GetThermalMeter(struct adapter * pAdapter,u8 * value)541 void Hal_GetThermalMeter(struct adapter *pAdapter, u8 *value)
542 {
543 Hal_TriggerRFThermalMeter(pAdapter);
544 msleep(1000);
545 *value = Hal_ReadRFThermalMeter(pAdapter);
546 }
547
Hal_SetSingleCarrierTx(struct adapter * pAdapter,u8 bStart)548 void Hal_SetSingleCarrierTx(struct adapter *pAdapter, u8 bStart)
549 {
550 pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
551 if (bStart) {
552 /* Start Single Carrier. */
553 /* 1. if OFDM block on? */
554 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
555 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
556
557 /* 2. set CCK test mode off, set to CCK normal mode */
558 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
559 /* 3. turn on scramble setting */
560 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
561 /* 4. Turn On Single Carrier Tx and turn off the other test modes. */
562 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
563 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
564 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
565 /* for dynamic set Power index. */
566 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
567 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
568 } else {
569 /* Stop Single Carrier. */
570 /* Turn off all test modes. */
571 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
572 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
573 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
574 msleep(10);
575
576 /* BB Reset */
577 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
578 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
579
580 /* Stop for dynamic set Power index. */
581 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
582 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
583 }
584 }
585
Hal_SetSingleToneTx(struct adapter * pAdapter,u8 bStart)586 void Hal_SetSingleToneTx(struct adapter *pAdapter, u8 bStart)
587 {
588 struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
589 bool is92C = IS_92C_SERIAL(pHalData->VersionID);
590
591 u8 rfPath;
592 u32 reg58 = 0x0;
593 switch (pAdapter->mppriv.antenna_tx) {
594 case ANTENNA_A:
595 default:
596 rfPath = RF_PATH_A;
597 break;
598 case ANTENNA_B:
599 rfPath = RF_PATH_B;
600 break;
601 case ANTENNA_C:
602 rfPath = RF_PATH_C;
603 break;
604 }
605
606 pAdapter->mppriv.MptCtx.bSingleTone = bStart;
607 if (bStart) {
608 /* Start Single Tone. */
609 /* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
610 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
611 reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
612 reg58 &= 0xFFFFFFF0;
613 reg58 += 2;
614 PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);
615 }
616 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
617 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
618
619 if (is92C) {
620 _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT(19), 0x01);
621 rtw_usleep_os(100);
622 if (rfPath == RF_PATH_A)
623 write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); /* PAD all on. */
624 else if (rfPath == RF_PATH_B)
625 write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); /* PAD all on. */
626 write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */
627 rtw_usleep_os(100);
628 } else {
629 write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);
630 rtw_usleep_os(100);
631 write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); /* PAD all on. */
632 rtw_usleep_os(100);
633 }
634
635 /* for dynamic set Power index. */
636 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
637 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
638
639 } else {
640 /* Stop Single Tone. */
641 /* <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu) */
642 /* <20120326, Kordan> Only in single tone mode. (asked by Edlu) */
643 if (IS_HARDWARE_TYPE_8188E(pAdapter)) {
644 reg58 = PHY_QueryRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask);
645 reg58 &= 0xFFFFFFF0;
646 PHY_SetRFReg(pAdapter, RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, reg58);
647 }
648 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
649 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
650 if (is92C) {
651 _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT(19), 0x00);
652 rtw_usleep_os(100);
653 write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); /* PAD all on. */
654 write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); /* PAD all on. */
655 rtw_usleep_os(100);
656 } else {
657 write_rfreg(pAdapter, rfPath, 0x21, 0x54000);
658 rtw_usleep_os(100);
659 write_rfreg(pAdapter, rfPath, 0x00, 0x30000); /* PAD all on. */
660 rtw_usleep_os(100);
661 }
662
663 /* Stop for dynamic set Power index. */
664 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
665 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
666 }
667 }
668
Hal_SetCarrierSuppressionTx(struct adapter * pAdapter,u8 bStart)669 void Hal_SetCarrierSuppressionTx(struct adapter *pAdapter, u8 bStart)
670 {
671 pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
672 if (bStart) {
673 /* Start Carrier Suppression. */
674 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
675 /* 1. if CCK block on? */
676 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
677 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
678
679 /* Turn Off All Test Mode */
680 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
681 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
682 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
683
684 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /* transmit mode */
685 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /* turn off scramble setting */
686
687 /* Set CCK Tx Test Rate */
688 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /* Set FTxRate to 1Mbps */
689 }
690
691 /* for dynamic set Power index. */
692 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
693 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
694 } else {
695 /* Stop Carrier Suppression. */
696 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) {
697 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /* normal mode */
698 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /* turn on scramble setting */
699
700 /* BB Reset */
701 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
702 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
703 }
704
705 /* Stop for dynamic set Power index. */
706 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
707 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
708 }
709 }
710
Hal_SetCCKContinuousTx(struct adapter * pAdapter,u8 bStart)711 void Hal_SetCCKContinuousTx(struct adapter *pAdapter, u8 bStart)
712 {
713 u32 cckrate;
714
715 if (bStart) {
716 /* 1. if CCK block on? */
717 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
718 write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/* set CCK block on */
719
720 /* Turn Off All Test Mode */
721 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
722 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
723 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
724 /* Set CCK Tx Test Rate */
725 cckrate = pAdapter->mppriv.rateidx;
726 write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
727 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /* transmit mode */
728 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /* turn on scramble setting */
729
730 /* for dynamic set Power index. */
731 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
732 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
733 } else {
734 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /* normal mode */
735 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /* turn on scramble setting */
736
737 /* BB Reset */
738 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
739 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
740
741 /* Stop for dynamic set Power index. */
742 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
743 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
744 }
745
746 pAdapter->mppriv.MptCtx.bCckContTx = bStart;
747 pAdapter->mppriv.MptCtx.bOfdmContTx = false;
748 } /* mpt_StartCckContTx */
749
Hal_SetOFDMContinuousTx(struct adapter * pAdapter,u8 bStart)750 void Hal_SetOFDMContinuousTx(struct adapter *pAdapter, u8 bStart)
751 {
752 if (bStart) {
753 /* 1. if OFDM block on? */
754 if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
755 write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);/* set OFDM block on */
756
757 /* 2. set CCK test mode off, set to CCK normal mode */
758 write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
759
760 /* 3. turn on scramble setting */
761 write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
762 /* 4. Turn On Continue Tx and turn off the other test modes. */
763 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
764 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
765 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
766
767 /* for dynamic set Power index. */
768 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
769 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
770
771 } else {
772 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
773 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
774 write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
775 /* Delay 10 ms */
776 msleep(10);
777 /* BB Reset */
778 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
779 write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
780
781 /* Stop for dynamic set Power index. */
782 write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
783 write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
784 }
785
786 pAdapter->mppriv.MptCtx.bCckContTx = false;
787 pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
788 } /* mpt_StartOfdmContTx */
789
Hal_SetContinuousTx(struct adapter * pAdapter,u8 bStart)790 void Hal_SetContinuousTx(struct adapter *pAdapter, u8 bStart)
791 {
792 pAdapter->mppriv.MptCtx.bStartContTx = bStart;
793 if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
794 Hal_SetCCKContinuousTx(pAdapter, bStart);
795 else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&
796 (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))
797 Hal_SetOFDMContinuousTx(pAdapter, bStart);
798 }
799