1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H
3 #define _ASM_POWERPC_BOOK3S_64_HASH_4K_H
4
5 #define H_PTE_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 4KB = 2MB
6 #define H_PMD_INDEX_SIZE 7 // size: 8B << 7 = 1KB, maps: 2^7 x 2MB = 256MB
7 #define H_PUD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 256MB = 128GB
8 #define H_PGD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 128GB = 64TB
9
10 /*
11 * Each context is 512TB. But on 4k we restrict our max TASK size to 64TB
12 * Hence also limit max EA bits to 64TB.
13 */
14 #define MAX_EA_BITS_PER_CONTEXT 46
15
16 #define REGION_SHIFT (MAX_EA_BITS_PER_CONTEXT - 2)
17
18 /*
19 * Our page table limit us to 64TB. Hence for the kernel mapping,
20 * each MAP area is limited to 16 TB.
21 * The four map areas are: linear mapping, vmap, IO and vmemmap
22 */
23 #define H_KERN_MAP_SIZE (ASM_CONST(1) << REGION_SHIFT)
24
25 /*
26 * Define the address range of the kernel non-linear virtual area
27 * 16TB
28 */
29 #define H_KERN_VIRT_START ASM_CONST(0xc000100000000000)
30
31 #ifndef __ASSEMBLY__
32 #define H_PTE_TABLE_SIZE (sizeof(pte_t) << H_PTE_INDEX_SIZE)
33 #define H_PMD_TABLE_SIZE (sizeof(pmd_t) << H_PMD_INDEX_SIZE)
34 #define H_PUD_TABLE_SIZE (sizeof(pud_t) << H_PUD_INDEX_SIZE)
35 #define H_PGD_TABLE_SIZE (sizeof(pgd_t) << H_PGD_INDEX_SIZE)
36
37 #define H_PAGE_F_GIX_SHIFT 53
38 #define H_PAGE_F_SECOND _RPAGE_RPN44 /* HPTE is in 2ndary HPTEG */
39 #define H_PAGE_F_GIX (_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41)
40 #define H_PAGE_BUSY _RPAGE_RSV1 /* software: PTE & hash are busy */
41 #define H_PAGE_HASHPTE _RPAGE_RSV2 /* software: PTE & hash are busy */
42
43 /* PTE flags to conserve for HPTE identification */
44 #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \
45 H_PAGE_F_SECOND | H_PAGE_F_GIX)
46 /*
47 * Not supported by 4k linux page size
48 */
49 #define H_PAGE_4K_PFN 0x0
50 #define H_PAGE_THP_HUGE 0x0
51 #define H_PAGE_COMBO 0x0
52
53 /* 8 bytes per each pte entry */
54 #define H_PTE_FRAG_SIZE_SHIFT (H_PTE_INDEX_SIZE + 3)
55 #define H_PTE_FRAG_NR (PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT)
56 #define H_PMD_FRAG_SIZE_SHIFT (H_PMD_INDEX_SIZE + 3)
57 #define H_PMD_FRAG_NR (PAGE_SIZE >> H_PMD_FRAG_SIZE_SHIFT)
58
59 /* memory key bits, only 8 keys supported */
60 #define H_PTE_PKEY_BIT0 0
61 #define H_PTE_PKEY_BIT1 0
62 #define H_PTE_PKEY_BIT2 _RPAGE_RSV3
63 #define H_PTE_PKEY_BIT3 _RPAGE_RSV4
64 #define H_PTE_PKEY_BIT4 _RPAGE_RSV5
65
66 /*
67 * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()
68 */
69 #define remap_4k_pfn(vma, addr, pfn, prot) \
70 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
71
72 #ifdef CONFIG_HUGETLB_PAGE
hash__hugepd_ok(hugepd_t hpd)73 static inline int hash__hugepd_ok(hugepd_t hpd)
74 {
75 unsigned long hpdval = hpd_val(hpd);
76 /*
77 * if it is not a pte and have hugepd shift mask
78 * set, then it is a hugepd directory pointer
79 */
80 if (!(hpdval & _PAGE_PTE) && (hpdval & _PAGE_PRESENT) &&
81 ((hpdval & HUGEPD_SHIFT_MASK) != 0))
82 return true;
83 return false;
84 }
85 #endif
86
87 /*
88 * 4K PTE format is different from 64K PTE format. Saving the hash_slot is just
89 * a matter of returning the PTE bits that need to be modified. On 64K PTE,
90 * things are a little more involved and hence needs many more parameters to
91 * accomplish the same. However we want to abstract this out from the caller by
92 * keeping the prototype consistent across the two formats.
93 */
pte_set_hidx(pte_t * ptep,real_pte_t rpte,unsigned int subpg_index,unsigned long hidx,int offset)94 static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte,
95 unsigned int subpg_index, unsigned long hidx,
96 int offset)
97 {
98 return (hidx << H_PAGE_F_GIX_SHIFT) &
99 (H_PAGE_F_SECOND | H_PAGE_F_GIX);
100 }
101
102 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
103
get_hpte_slot_array(pmd_t * pmdp)104 static inline char *get_hpte_slot_array(pmd_t *pmdp)
105 {
106 BUG();
107 return NULL;
108 }
109
hpte_valid(unsigned char * hpte_slot_array,int index)110 static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)
111 {
112 BUG();
113 return 0;
114 }
115
hpte_hash_index(unsigned char * hpte_slot_array,int index)116 static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array,
117 int index)
118 {
119 BUG();
120 return 0;
121 }
122
mark_hpte_slot_valid(unsigned char * hpte_slot_array,unsigned int index,unsigned int hidx)123 static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array,
124 unsigned int index, unsigned int hidx)
125 {
126 BUG();
127 }
128
hash__pmd_trans_huge(pmd_t pmd)129 static inline int hash__pmd_trans_huge(pmd_t pmd)
130 {
131 return 0;
132 }
133
hash__pmd_same(pmd_t pmd_a,pmd_t pmd_b)134 static inline int hash__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
135 {
136 BUG();
137 return 0;
138 }
139
hash__pmd_mkhuge(pmd_t pmd)140 static inline pmd_t hash__pmd_mkhuge(pmd_t pmd)
141 {
142 BUG();
143 return pmd;
144 }
145
146 extern unsigned long hash__pmd_hugepage_update(struct mm_struct *mm,
147 unsigned long addr, pmd_t *pmdp,
148 unsigned long clr, unsigned long set);
149 extern pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma,
150 unsigned long address, pmd_t *pmdp);
151 extern void hash__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
152 pgtable_t pgtable);
153 extern pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
154 extern pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm,
155 unsigned long addr, pmd_t *pmdp);
156 extern int hash__has_transparent_hugepage(void);
157 #endif
158
159 #endif /* !__ASSEMBLY__ */
160
161 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_4K_H */
162
