1 /*
2 * Generic EDAC defs
3 *
4 * Author: Dave Jiang <djiang@mvista.com>
5 *
6 * 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 */
12 #ifndef _LINUX_EDAC_H_
13 #define _LINUX_EDAC_H_
14
15 #include <linux/atomic.h>
16 #include <linux/device.h>
17 #include <linux/completion.h>
18 #include <linux/workqueue.h>
19 #include <linux/debugfs.h>
20
21 #define EDAC_DEVICE_NAME_LEN 31
22
23 struct device;
24
25 #define EDAC_OPSTATE_INVAL -1
26 #define EDAC_OPSTATE_POLL 0
27 #define EDAC_OPSTATE_NMI 1
28 #define EDAC_OPSTATE_INT 2
29
30 extern int edac_op_state;
31
32 struct bus_type *edac_get_sysfs_subsys(void);
33 int edac_get_report_status(void);
34 void edac_set_report_status(int new);
35
36 enum {
37 EDAC_REPORTING_ENABLED,
38 EDAC_REPORTING_DISABLED,
39 EDAC_REPORTING_FORCE
40 };
41
opstate_init(void)42 static inline void opstate_init(void)
43 {
44 switch (edac_op_state) {
45 case EDAC_OPSTATE_POLL:
46 case EDAC_OPSTATE_NMI:
47 break;
48 default:
49 edac_op_state = EDAC_OPSTATE_POLL;
50 }
51 return;
52 }
53
54 /* Max length of a DIMM label*/
55 #define EDAC_MC_LABEL_LEN 31
56
57 /* Maximum size of the location string */
58 #define LOCATION_SIZE 256
59
60 /* Defines the maximum number of labels that can be reported */
61 #define EDAC_MAX_LABELS 8
62
63 /* String used to join two or more labels */
64 #define OTHER_LABEL " or "
65
66 /**
67 * enum dev_type - describe the type of memory DRAM chips used at the stick
68 * @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
69 * @DEV_X1: 1 bit for data
70 * @DEV_X2: 2 bits for data
71 * @DEV_X4: 4 bits for data
72 * @DEV_X8: 8 bits for data
73 * @DEV_X16: 16 bits for data
74 * @DEV_X32: 32 bits for data
75 * @DEV_X64: 64 bits for data
76 *
77 * Typical values are x4 and x8.
78 */
79 enum dev_type {
80 DEV_UNKNOWN = 0,
81 DEV_X1,
82 DEV_X2,
83 DEV_X4,
84 DEV_X8,
85 DEV_X16,
86 DEV_X32, /* Do these parts exist? */
87 DEV_X64 /* Do these parts exist? */
88 };
89
90 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
91 #define DEV_FLAG_X1 BIT(DEV_X1)
92 #define DEV_FLAG_X2 BIT(DEV_X2)
93 #define DEV_FLAG_X4 BIT(DEV_X4)
94 #define DEV_FLAG_X8 BIT(DEV_X8)
95 #define DEV_FLAG_X16 BIT(DEV_X16)
96 #define DEV_FLAG_X32 BIT(DEV_X32)
97 #define DEV_FLAG_X64 BIT(DEV_X64)
98
99 /**
100 * enum hw_event_mc_err_type - type of the detected error
101 *
102 * @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
103 * corrected error was detected
104 * @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
105 * can't be corrected by ECC, but it is not
106 * fatal (maybe it is on an unused memory area,
107 * or the memory controller could recover from
108 * it for example, by re-trying the operation).
109 * @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
110 * error whose handling is not urgent. This could
111 * be due to hardware data poisoning where the
112 * system can continue operation until the poisoned
113 * data is consumed. Preemptive measures may also
114 * be taken, e.g. offlining pages, etc.
115 * @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
116 * be recovered.
117 * @HW_EVENT_ERR_INFO: Informational - The CPER spec defines a forth
118 * type of error: informational logs.
119 */
120 enum hw_event_mc_err_type {
121 HW_EVENT_ERR_CORRECTED,
122 HW_EVENT_ERR_UNCORRECTED,
123 HW_EVENT_ERR_DEFERRED,
124 HW_EVENT_ERR_FATAL,
125 HW_EVENT_ERR_INFO,
126 };
127
mc_event_error_type(const unsigned int err_type)128 static inline char *mc_event_error_type(const unsigned int err_type)
129 {
130 switch (err_type) {
131 case HW_EVENT_ERR_CORRECTED:
132 return "Corrected";
133 case HW_EVENT_ERR_UNCORRECTED:
134 return "Uncorrected";
135 case HW_EVENT_ERR_DEFERRED:
136 return "Deferred";
137 case HW_EVENT_ERR_FATAL:
138 return "Fatal";
139 default:
140 case HW_EVENT_ERR_INFO:
141 return "Info";
142 }
143 }
144
145 /**
146 * enum mem_type - memory types. For a more detailed reference, please see
147 * http://en.wikipedia.org/wiki/DRAM
148 *
149 * @MEM_EMPTY: Empty csrow
150 * @MEM_RESERVED: Reserved csrow type
151 * @MEM_UNKNOWN: Unknown csrow type
152 * @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
153 * @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
154 * @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
155 * @MEM_SDR: SDR - Single data rate SDRAM
156 * http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
157 * They use 3 pins for chip select: Pins 0 and 2 are
158 * for rank 0; pins 1 and 3 are for rank 1, if the memory
159 * is dual-rank.
160 * @MEM_RDR: Registered SDR SDRAM
161 * @MEM_DDR: Double data rate SDRAM
162 * http://en.wikipedia.org/wiki/DDR_SDRAM
163 * @MEM_RDDR: Registered Double data rate SDRAM
164 * This is a variant of the DDR memories.
165 * A registered memory has a buffer inside it, hiding
166 * part of the memory details to the memory controller.
167 * @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
168 * @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
169 * Those memories are labeled as "PC2-" instead of "PC" to
170 * differentiate from DDR.
171 * @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
172 * and JESD206.
173 * Those memories are accessed per DIMM slot, and not by
174 * a chip select signal.
175 * @MEM_RDDR2: Registered DDR2 RAM
176 * This is a variant of the DDR2 memories.
177 * @MEM_XDR: Rambus XDR
178 * It is an evolution of the original RAMBUS memories,
179 * created to compete with DDR2. Weren't used on any
180 * x86 arch, but cell_edac PPC memory controller uses it.
181 * @MEM_DDR3: DDR3 RAM
182 * @MEM_RDDR3: Registered DDR3 RAM
183 * This is a variant of the DDR3 memories.
184 * @MEM_LRDDR3: Load-Reduced DDR3 memory.
185 * @MEM_DDR4: Unbuffered DDR4 RAM
186 * @MEM_RDDR4: Registered DDR4 RAM
187 * This is a variant of the DDR4 memories.
188 * @MEM_LRDDR4: Load-Reduced DDR4 memory.
189 * @MEM_NVDIMM: Non-volatile RAM
190 */
191 enum mem_type {
192 MEM_EMPTY = 0,
193 MEM_RESERVED,
194 MEM_UNKNOWN,
195 MEM_FPM,
196 MEM_EDO,
197 MEM_BEDO,
198 MEM_SDR,
199 MEM_RDR,
200 MEM_DDR,
201 MEM_RDDR,
202 MEM_RMBS,
203 MEM_DDR2,
204 MEM_FB_DDR2,
205 MEM_RDDR2,
206 MEM_XDR,
207 MEM_DDR3,
208 MEM_RDDR3,
209 MEM_LRDDR3,
210 MEM_DDR4,
211 MEM_RDDR4,
212 MEM_LRDDR4,
213 MEM_NVDIMM,
214 };
215
216 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
217 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
218 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
219 #define MEM_FLAG_FPM BIT(MEM_FPM)
220 #define MEM_FLAG_EDO BIT(MEM_EDO)
221 #define MEM_FLAG_BEDO BIT(MEM_BEDO)
222 #define MEM_FLAG_SDR BIT(MEM_SDR)
223 #define MEM_FLAG_RDR BIT(MEM_RDR)
224 #define MEM_FLAG_DDR BIT(MEM_DDR)
225 #define MEM_FLAG_RDDR BIT(MEM_RDDR)
226 #define MEM_FLAG_RMBS BIT(MEM_RMBS)
227 #define MEM_FLAG_DDR2 BIT(MEM_DDR2)
228 #define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
229 #define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
230 #define MEM_FLAG_XDR BIT(MEM_XDR)
231 #define MEM_FLAG_DDR3 BIT(MEM_DDR3)
232 #define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
233 #define MEM_FLAG_DDR4 BIT(MEM_DDR4)
234 #define MEM_FLAG_RDDR4 BIT(MEM_RDDR4)
235 #define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4)
236 #define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM)
237
238 /**
239 * enum edac-type - Error Detection and Correction capabilities and mode
240 * @EDAC_UNKNOWN: Unknown if ECC is available
241 * @EDAC_NONE: Doesn't support ECC
242 * @EDAC_RESERVED: Reserved ECC type
243 * @EDAC_PARITY: Detects parity errors
244 * @EDAC_EC: Error Checking - no correction
245 * @EDAC_SECDED: Single bit error correction, Double detection
246 * @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
247 * @EDAC_S4ECD4ED: Chipkill x4 devices
248 * @EDAC_S8ECD8ED: Chipkill x8 devices
249 * @EDAC_S16ECD16ED: Chipkill x16 devices
250 */
251 enum edac_type {
252 EDAC_UNKNOWN = 0,
253 EDAC_NONE,
254 EDAC_RESERVED,
255 EDAC_PARITY,
256 EDAC_EC,
257 EDAC_SECDED,
258 EDAC_S2ECD2ED,
259 EDAC_S4ECD4ED,
260 EDAC_S8ECD8ED,
261 EDAC_S16ECD16ED,
262 };
263
264 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
265 #define EDAC_FLAG_NONE BIT(EDAC_NONE)
266 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
267 #define EDAC_FLAG_EC BIT(EDAC_EC)
268 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
269 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
270 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
271 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
272 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
273
274 /**
275 * enum scrub_type - scrubbing capabilities
276 * @SCRUB_UNKNOWN: Unknown if scrubber is available
277 * @SCRUB_NONE: No scrubber
278 * @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
279 * @SCRUB_SW_SRC: Software scrub only errors
280 * @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
281 * @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
282 * @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
283 * @SCRUB_HW_SRC: Hardware scrub only errors
284 * @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
285 * @SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
286 */
287 enum scrub_type {
288 SCRUB_UNKNOWN = 0,
289 SCRUB_NONE,
290 SCRUB_SW_PROG,
291 SCRUB_SW_SRC,
292 SCRUB_SW_PROG_SRC,
293 SCRUB_SW_TUNABLE,
294 SCRUB_HW_PROG,
295 SCRUB_HW_SRC,
296 SCRUB_HW_PROG_SRC,
297 SCRUB_HW_TUNABLE
298 };
299
300 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
301 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
302 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
303 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
304 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
305 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
306 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
307 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
308
309 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
310
311 /* EDAC internal operation states */
312 #define OP_ALLOC 0x100
313 #define OP_RUNNING_POLL 0x201
314 #define OP_RUNNING_INTERRUPT 0x202
315 #define OP_RUNNING_POLL_INTR 0x203
316 #define OP_OFFLINE 0x300
317
318 /**
319 * enum edac_mc_layer - memory controller hierarchy layer
320 *
321 * @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
322 * @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
323 * @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
324 * @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
325 * @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
326 * as a single memory area. This is used when
327 * retrieving errors from a firmware driven driver.
328 *
329 * This enum is used by the drivers to tell edac_mc_sysfs what name should
330 * be used when describing a memory stick location.
331 */
332 enum edac_mc_layer_type {
333 EDAC_MC_LAYER_BRANCH,
334 EDAC_MC_LAYER_CHANNEL,
335 EDAC_MC_LAYER_SLOT,
336 EDAC_MC_LAYER_CHIP_SELECT,
337 EDAC_MC_LAYER_ALL_MEM,
338 };
339
340 /**
341 * struct edac_mc_layer - describes the memory controller hierarchy
342 * @type: layer type
343 * @size: number of components per layer. For example,
344 * if the channel layer has two channels, size = 2
345 * @is_virt_csrow: This layer is part of the "csrow" when old API
346 * compatibility mode is enabled. Otherwise, it is
347 * a channel
348 */
349 struct edac_mc_layer {
350 enum edac_mc_layer_type type;
351 unsigned size;
352 bool is_virt_csrow;
353 };
354
355 /*
356 * Maximum number of layers used by the memory controller to uniquely
357 * identify a single memory stick.
358 * NOTE: Changing this constant requires not only to change the constant
359 * below, but also to change the existing code at the core, as there are
360 * some code there that are optimized for 3 layers.
361 */
362 #define EDAC_MAX_LAYERS 3
363
364 /**
365 * EDAC_DIMM_OFF - Macro responsible to get a pointer offset inside a pointer
366 * array for the element given by [layer0,layer1,layer2]
367 * position
368 *
369 * @layers: a struct edac_mc_layer array, describing how many elements
370 * were allocated for each layer
371 * @nlayers: Number of layers at the @layers array
372 * @layer0: layer0 position
373 * @layer1: layer1 position. Unused if n_layers < 2
374 * @layer2: layer2 position. Unused if n_layers < 3
375 *
376 * For 1 layer, this macro returns "var[layer0] - var";
377 *
378 * For 2 layers, this macro is similar to allocate a bi-dimensional array
379 * and to return "var[layer0][layer1] - var";
380 *
381 * For 3 layers, this macro is similar to allocate a tri-dimensional array
382 * and to return "var[layer0][layer1][layer2] - var".
383 *
384 * A loop could be used here to make it more generic, but, as we only have
385 * 3 layers, this is a little faster.
386 *
387 * By design, layers can never be 0 or more than 3. If that ever happens,
388 * a NULL is returned, causing an OOPS during the memory allocation routine,
389 * with would point to the developer that he's doing something wrong.
390 */
391 #define EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2) ({ \
392 int __i; \
393 if ((nlayers) == 1) \
394 __i = layer0; \
395 else if ((nlayers) == 2) \
396 __i = (layer1) + ((layers[1]).size * (layer0)); \
397 else if ((nlayers) == 3) \
398 __i = (layer2) + ((layers[2]).size * ((layer1) + \
399 ((layers[1]).size * (layer0)))); \
400 else \
401 __i = -EINVAL; \
402 __i; \
403 })
404
405 /**
406 * EDAC_DIMM_PTR - Macro responsible to get a pointer inside a pointer array
407 * for the element given by [layer0,layer1,layer2] position
408 *
409 * @layers: a struct edac_mc_layer array, describing how many elements
410 * were allocated for each layer
411 * @var: name of the var where we want to get the pointer
412 * (like mci->dimms)
413 * @nlayers: Number of layers at the @layers array
414 * @layer0: layer0 position
415 * @layer1: layer1 position. Unused if n_layers < 2
416 * @layer2: layer2 position. Unused if n_layers < 3
417 *
418 * For 1 layer, this macro returns "var[layer0]";
419 *
420 * For 2 layers, this macro is similar to allocate a bi-dimensional array
421 * and to return "var[layer0][layer1]";
422 *
423 * For 3 layers, this macro is similar to allocate a tri-dimensional array
424 * and to return "var[layer0][layer1][layer2]";
425 */
426 #define EDAC_DIMM_PTR(layers, var, nlayers, layer0, layer1, layer2) ({ \
427 typeof(*var) __p; \
428 int ___i = EDAC_DIMM_OFF(layers, nlayers, layer0, layer1, layer2); \
429 if (___i < 0) \
430 __p = NULL; \
431 else \
432 __p = (var)[___i]; \
433 __p; \
434 })
435
436 struct dimm_info {
437 struct device dev;
438
439 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
440
441 /* Memory location data */
442 unsigned location[EDAC_MAX_LAYERS];
443
444 struct mem_ctl_info *mci; /* the parent */
445
446 u32 grain; /* granularity of reported error in bytes */
447 enum dev_type dtype; /* memory device type */
448 enum mem_type mtype; /* memory dimm type */
449 enum edac_type edac_mode; /* EDAC mode for this dimm */
450
451 u32 nr_pages; /* number of pages on this dimm */
452
453 unsigned csrow, cschannel; /* Points to the old API data */
454 };
455
456 /**
457 * struct rank_info - contains the information for one DIMM rank
458 *
459 * @chan_idx: channel number where the rank is (typically, 0 or 1)
460 * @ce_count: number of correctable errors for this rank
461 * @csrow: A pointer to the chip select row structure (the parent
462 * structure). The location of the rank is given by
463 * the (csrow->csrow_idx, chan_idx) vector.
464 * @dimm: A pointer to the DIMM structure, where the DIMM label
465 * information is stored.
466 *
467 * FIXME: Currently, the EDAC core model will assume one DIMM per rank.
468 * This is a bad assumption, but it makes this patch easier. Later
469 * patches in this series will fix this issue.
470 */
471 struct rank_info {
472 int chan_idx;
473 struct csrow_info *csrow;
474 struct dimm_info *dimm;
475
476 u32 ce_count; /* Correctable Errors for this csrow */
477 };
478
479 struct csrow_info {
480 struct device dev;
481
482 /* Used only by edac_mc_find_csrow_by_page() */
483 unsigned long first_page; /* first page number in csrow */
484 unsigned long last_page; /* last page number in csrow */
485 unsigned long page_mask; /* used for interleaving -
486 * 0UL for non intlv */
487
488 int csrow_idx; /* the chip-select row */
489
490 u32 ue_count; /* Uncorrectable Errors for this csrow */
491 u32 ce_count; /* Correctable Errors for this csrow */
492
493 struct mem_ctl_info *mci; /* the parent */
494
495 /* channel information for this csrow */
496 u32 nr_channels;
497 struct rank_info **channels;
498 };
499
500 /*
501 * struct errcount_attribute - used to store the several error counts
502 */
503 struct errcount_attribute_data {
504 int n_layers;
505 int pos[EDAC_MAX_LAYERS];
506 int layer0, layer1, layer2;
507 };
508
509 /**
510 * struct edac_raw_error_desc - Raw error report structure
511 * @grain: minimum granularity for an error report, in bytes
512 * @error_count: number of errors of the same type
513 * @top_layer: top layer of the error (layer[0])
514 * @mid_layer: middle layer of the error (layer[1])
515 * @low_layer: low layer of the error (layer[2])
516 * @page_frame_number: page where the error happened
517 * @offset_in_page: page offset
518 * @syndrome: syndrome of the error (or 0 if unknown or if
519 * the syndrome is not applicable)
520 * @msg: error message
521 * @location: location of the error
522 * @label: label of the affected DIMM(s)
523 * @other_detail: other driver-specific detail about the error
524 * @enable_per_layer_report: if false, the error affects all layers
525 * (typically, a memory controller error)
526 */
527 struct edac_raw_error_desc {
528 /*
529 * NOTE: everything before grain won't be cleaned by
530 * edac_raw_error_desc_clean()
531 */
532 char location[LOCATION_SIZE];
533 char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
534 long grain;
535
536 /* the vars below and grain will be cleaned on every new error report */
537 u16 error_count;
538 int top_layer;
539 int mid_layer;
540 int low_layer;
541 unsigned long page_frame_number;
542 unsigned long offset_in_page;
543 unsigned long syndrome;
544 const char *msg;
545 const char *other_detail;
546 bool enable_per_layer_report;
547 };
548
549 /* MEMORY controller information structure
550 */
551 struct mem_ctl_info {
552 struct device dev;
553 struct bus_type *bus;
554
555 struct list_head link; /* for global list of mem_ctl_info structs */
556
557 struct module *owner; /* Module owner of this control struct */
558
559 unsigned long mtype_cap; /* memory types supported by mc */
560 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
561 unsigned long edac_cap; /* configuration capabilities - this is
562 * closely related to edac_ctl_cap. The
563 * difference is that the controller may be
564 * capable of s4ecd4ed which would be listed
565 * in edac_ctl_cap, but if channels aren't
566 * capable of s4ecd4ed then the edac_cap would
567 * not have that capability.
568 */
569 unsigned long scrub_cap; /* chipset scrub capabilities */
570 enum scrub_type scrub_mode; /* current scrub mode */
571
572 /* Translates sdram memory scrub rate given in bytes/sec to the
573 internal representation and configures whatever else needs
574 to be configured.
575 */
576 int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
577
578 /* Get the current sdram memory scrub rate from the internal
579 representation and converts it to the closest matching
580 bandwidth in bytes/sec.
581 */
582 int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
583
584
585 /* pointer to edac checking routine */
586 void (*edac_check) (struct mem_ctl_info * mci);
587
588 /*
589 * Remaps memory pages: controller pages to physical pages.
590 * For most MC's, this will be NULL.
591 */
592 /* FIXME - why not send the phys page to begin with? */
593 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
594 unsigned long page);
595 int mc_idx;
596 struct csrow_info **csrows;
597 unsigned nr_csrows, num_cschannel;
598
599 /*
600 * Memory Controller hierarchy
601 *
602 * There are basically two types of memory controller: the ones that
603 * sees memory sticks ("dimms"), and the ones that sees memory ranks.
604 * All old memory controllers enumerate memories per rank, but most
605 * of the recent drivers enumerate memories per DIMM, instead.
606 * When the memory controller is per rank, csbased is true.
607 */
608 unsigned n_layers;
609 struct edac_mc_layer *layers;
610 bool csbased;
611
612 /*
613 * DIMM info. Will eventually remove the entire csrows_info some day
614 */
615 unsigned tot_dimms;
616 struct dimm_info **dimms;
617
618 /*
619 * FIXME - what about controllers on other busses? - IDs must be
620 * unique. dev pointer should be sufficiently unique, but
621 * BUS:SLOT.FUNC numbers may not be unique.
622 */
623 struct device *pdev;
624 const char *mod_name;
625 const char *ctl_name;
626 const char *dev_name;
627 void *pvt_info;
628 unsigned long start_time; /* mci load start time (in jiffies) */
629
630 /*
631 * drivers shouldn't access those fields directly, as the core
632 * already handles that.
633 */
634 u32 ce_noinfo_count, ue_noinfo_count;
635 u32 ue_mc, ce_mc;
636 u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
637
638 struct completion complete;
639
640 /* Additional top controller level attributes, but specified
641 * by the low level driver.
642 *
643 * Set by the low level driver to provide attributes at the
644 * controller level.
645 * An array of structures, NULL terminated
646 *
647 * If attributes are desired, then set to array of attributes
648 * If no attributes are desired, leave NULL
649 */
650 const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
651
652 /* work struct for this MC */
653 struct delayed_work work;
654
655 /*
656 * Used to report an error - by being at the global struct
657 * makes the memory allocated by the EDAC core
658 */
659 struct edac_raw_error_desc error_desc;
660
661 /* the internal state of this controller instance */
662 int op_state;
663
664 struct dentry *debugfs;
665 u8 fake_inject_layer[EDAC_MAX_LAYERS];
666 bool fake_inject_ue;
667 u16 fake_inject_count;
668 };
669
670 /*
671 * Maximum number of memory controllers in the coherent fabric.
672 */
673 #define EDAC_MAX_MCS 16
674
675 #endif
676
