1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * aQuantia Corporation Network Driver 4 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 5 */ 6 7 /* File hw_atl_llh_internal.h: Preprocessor definitions 8 * for Atlantic registers. 9 */ 10 11 #ifndef HW_ATL_LLH_INTERNAL_H 12 #define HW_ATL_LLH_INTERNAL_H 13 14 /* global microprocessor semaphore definitions 15 * base address: 0x000003a0 16 * parameter: semaphore {s} | stride size 0x4 | range [0, 15] 17 */ 18 #define HW_ATL_GLB_CPU_SEM_ADR(semaphore) (0x000003a0u + (semaphore) * 0x4) 19 /* register address for bitfield rx dma good octet counter lsw [1f:0] */ 20 #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808 21 /* register address for bitfield rx dma good packet counter lsw [1f:0] */ 22 #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800 23 /* register address for bitfield tx dma good octet counter lsw [1f:0] */ 24 #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808 25 /* register address for bitfield tx dma good packet counter lsw [1f:0] */ 26 #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800 27 28 /* register address for bitfield rx dma good octet counter msw [3f:20] */ 29 #define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c 30 /* register address for bitfield rx dma good packet counter msw [3f:20] */ 31 #define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804 32 /* register address for bitfield tx dma good octet counter msw [3f:20] */ 33 #define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c 34 /* register address for bitfield tx dma good packet counter msw [3f:20] */ 35 #define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804 36 37 /* preprocessor definitions for msm rx errors counter register */ 38 #define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u 39 40 /* preprocessor definitions for msm rx unicast frames counter register */ 41 #define HW_ATL_MAC_MSM_RX_UCST_FRM_CNT_ADR 0x000000e0u 42 43 /* preprocessor definitions for msm rx multicast frames counter register */ 44 #define HW_ATL_MAC_MSM_RX_MCST_FRM_CNT_ADR 0x000000e8u 45 46 /* preprocessor definitions for msm rx broadcast frames counter register */ 47 #define HW_ATL_MAC_MSM_RX_BCST_FRM_CNT_ADR 0x000000f0u 48 49 /* preprocessor definitions for msm rx broadcast octets counter register 1 */ 50 #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER1_ADR 0x000001b0u 51 52 /* preprocessor definitions for msm rx broadcast octets counter register 2 */ 53 #define HW_ATL_MAC_MSM_RX_BCST_OCTETS_COUNTER2_ADR 0x000001b4u 54 55 /* preprocessor definitions for msm rx unicast octets counter register 0 */ 56 #define HW_ATL_MAC_MSM_RX_UCST_OCTETS_COUNTER0_ADR 0x000001b8u 57 58 /* preprocessor definitions for msm tx unicast frames counter register */ 59 #define HW_ATL_MAC_MSM_TX_UCST_FRM_CNT_ADR 0x00000108u 60 61 /* preprocessor definitions for msm tx multicast frames counter register */ 62 #define HW_ATL_MAC_MSM_TX_MCST_FRM_CNT_ADR 0x00000110u 63 64 /* preprocessor definitions for global mif identification */ 65 #define HW_ATL_GLB_MIF_ID_ADR 0x0000001cu 66 67 /* register address for bitfield iamr_lsw[1f:0] */ 68 #define HW_ATL_ITR_IAMRLSW_ADR 0x00002090 69 /* register address for bitfield rx dma drop packet counter [1f:0] */ 70 #define HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR 0x00006818 71 72 /* register address for bitfield imcr_lsw[1f:0] */ 73 #define HW_ATL_ITR_IMCRLSW_ADR 0x00002070 74 /* register address for bitfield imsr_lsw[1f:0] */ 75 #define HW_ATL_ITR_IMSRLSW_ADR 0x00002060 76 /* register address for bitfield itr_reg_res_dsbl */ 77 #define HW_ATL_ITR_REG_RES_DSBL_ADR 0x00002300 78 /* bitmask for bitfield itr_reg_res_dsbl */ 79 #define HW_ATL_ITR_REG_RES_DSBL_MSK 0x20000000 80 /* lower bit position of bitfield itr_reg_res_dsbl */ 81 #define HW_ATL_ITR_REG_RES_DSBL_SHIFT 29 82 /* register address for bitfield iscr_lsw[1f:0] */ 83 #define HW_ATL_ITR_ISCRLSW_ADR 0x00002050 84 /* register address for bitfield isr_lsw[1f:0] */ 85 #define HW_ATL_ITR_ISRLSW_ADR 0x00002000 86 /* register address for bitfield itr_reset */ 87 #define HW_ATL_ITR_RES_ADR 0x00002300 88 /* bitmask for bitfield itr_reset */ 89 #define HW_ATL_ITR_RES_MSK 0x80000000 90 /* lower bit position of bitfield itr_reset */ 91 #define HW_ATL_ITR_RES_SHIFT 31 92 93 /* register address for bitfield rsc_en */ 94 #define HW_ATL_ITR_RSC_EN_ADR 0x00002200 95 96 /* register address for bitfield rsc_delay */ 97 #define HW_ATL_ITR_RSC_DELAY_ADR 0x00002204 98 /* bitmask for bitfield rsc_delay */ 99 #define HW_ATL_ITR_RSC_DELAY_MSK 0x0000000f 100 /* width of bitfield rsc_delay */ 101 #define HW_ATL_ITR_RSC_DELAY_WIDTH 4 102 /* lower bit position of bitfield rsc_delay */ 103 #define HW_ATL_ITR_RSC_DELAY_SHIFT 0 104 105 /* register address for bitfield dca{d}_cpuid[7:0] */ 106 #define HW_ATL_RDM_DCADCPUID_ADR(dca) (0x00006100 + (dca) * 0x4) 107 /* bitmask for bitfield dca{d}_cpuid[7:0] */ 108 #define HW_ATL_RDM_DCADCPUID_MSK 0x000000ff 109 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ 110 #define HW_ATL_RDM_DCADCPUID_SHIFT 0 111 /* register address for bitfield dca_en */ 112 #define HW_ATL_RDM_DCA_EN_ADR 0x00006180 113 114 /* rx dca_en bitfield definitions 115 * preprocessor definitions for the bitfield "dca_en". 116 * port="pif_rdm_dca_en_i" 117 */ 118 119 /* register address for bitfield dca_en */ 120 #define HW_ATL_RDM_DCA_EN_ADR 0x00006180 121 /* bitmask for bitfield dca_en */ 122 #define HW_ATL_RDM_DCA_EN_MSK 0x80000000 123 /* inverted bitmask for bitfield dca_en */ 124 #define HW_ATL_RDM_DCA_EN_MSKN 0x7fffffff 125 /* lower bit position of bitfield dca_en */ 126 #define HW_ATL_RDM_DCA_EN_SHIFT 31 127 /* width of bitfield dca_en */ 128 #define HW_ATL_RDM_DCA_EN_WIDTH 1 129 /* default value of bitfield dca_en */ 130 #define HW_ATL_RDM_DCA_EN_DEFAULT 0x1 131 132 /* rx dca_mode[3:0] bitfield definitions 133 * preprocessor definitions for the bitfield "dca_mode[3:0]". 134 * port="pif_rdm_dca_mode_i[3:0]" 135 */ 136 137 /* register address for bitfield dca_mode[3:0] */ 138 #define HW_ATL_RDM_DCA_MODE_ADR 0x00006180 139 /* bitmask for bitfield dca_mode[3:0] */ 140 #define HW_ATL_RDM_DCA_MODE_MSK 0x0000000f 141 /* inverted bitmask for bitfield dca_mode[3:0] */ 142 #define HW_ATL_RDM_DCA_MODE_MSKN 0xfffffff0 143 /* lower bit position of bitfield dca_mode[3:0] */ 144 #define HW_ATL_RDM_DCA_MODE_SHIFT 0 145 /* width of bitfield dca_mode[3:0] */ 146 #define HW_ATL_RDM_DCA_MODE_WIDTH 4 147 /* default value of bitfield dca_mode[3:0] */ 148 #define HW_ATL_RDM_DCA_MODE_DEFAULT 0x0 149 150 /* rx desc{d}_data_size[4:0] bitfield definitions 151 * preprocessor definitions for the bitfield "desc{d}_data_size[4:0]". 152 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 153 * port="pif_rdm_desc0_data_size_i[4:0]" 154 */ 155 156 /* register address for bitfield desc{d}_data_size[4:0] */ 157 #define HW_ATL_RDM_DESCDDATA_SIZE_ADR(descriptor) \ 158 (0x00005b18 + (descriptor) * 0x20) 159 /* bitmask for bitfield desc{d}_data_size[4:0] */ 160 #define HW_ATL_RDM_DESCDDATA_SIZE_MSK 0x0000001f 161 /* inverted bitmask for bitfield desc{d}_data_size[4:0] */ 162 #define HW_ATL_RDM_DESCDDATA_SIZE_MSKN 0xffffffe0 163 /* lower bit position of bitfield desc{d}_data_size[4:0] */ 164 #define HW_ATL_RDM_DESCDDATA_SIZE_SHIFT 0 165 /* width of bitfield desc{d}_data_size[4:0] */ 166 #define HW_ATL_RDM_DESCDDATA_SIZE_WIDTH 5 167 /* default value of bitfield desc{d}_data_size[4:0] */ 168 #define HW_ATL_RDM_DESCDDATA_SIZE_DEFAULT 0x0 169 170 /* rx dca{d}_desc_en bitfield definitions 171 * preprocessor definitions for the bitfield "dca{d}_desc_en". 172 * parameter: dca {d} | stride size 0x4 | range [0, 31] 173 * port="pif_rdm_dca_desc_en_i[0]" 174 */ 175 176 /* register address for bitfield dca{d}_desc_en */ 177 #define HW_ATL_RDM_DCADDESC_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 178 /* bitmask for bitfield dca{d}_desc_en */ 179 #define HW_ATL_RDM_DCADDESC_EN_MSK 0x80000000 180 /* inverted bitmask for bitfield dca{d}_desc_en */ 181 #define HW_ATL_RDM_DCADDESC_EN_MSKN 0x7fffffff 182 /* lower bit position of bitfield dca{d}_desc_en */ 183 #define HW_ATL_RDM_DCADDESC_EN_SHIFT 31 184 /* width of bitfield dca{d}_desc_en */ 185 #define HW_ATL_RDM_DCADDESC_EN_WIDTH 1 186 /* default value of bitfield dca{d}_desc_en */ 187 #define HW_ATL_RDM_DCADDESC_EN_DEFAULT 0x0 188 189 /* rx desc{d}_en bitfield definitions 190 * preprocessor definitions for the bitfield "desc{d}_en". 191 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 192 * port="pif_rdm_desc_en_i[0]" 193 */ 194 195 /* register address for bitfield desc{d}_en */ 196 #define HW_ATL_RDM_DESCDEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 197 /* bitmask for bitfield desc{d}_en */ 198 #define HW_ATL_RDM_DESCDEN_MSK 0x80000000 199 /* inverted bitmask for bitfield desc{d}_en */ 200 #define HW_ATL_RDM_DESCDEN_MSKN 0x7fffffff 201 /* lower bit position of bitfield desc{d}_en */ 202 #define HW_ATL_RDM_DESCDEN_SHIFT 31 203 /* width of bitfield desc{d}_en */ 204 #define HW_ATL_RDM_DESCDEN_WIDTH 1 205 /* default value of bitfield desc{d}_en */ 206 #define HW_ATL_RDM_DESCDEN_DEFAULT 0x0 207 208 /* rx desc{d}_hdr_size[4:0] bitfield definitions 209 * preprocessor definitions for the bitfield "desc{d}_hdr_size[4:0]". 210 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 211 * port="pif_rdm_desc0_hdr_size_i[4:0]" 212 */ 213 214 /* register address for bitfield desc{d}_hdr_size[4:0] */ 215 #define HW_ATL_RDM_DESCDHDR_SIZE_ADR(descriptor) \ 216 (0x00005b18 + (descriptor) * 0x20) 217 /* bitmask for bitfield desc{d}_hdr_size[4:0] */ 218 #define HW_ATL_RDM_DESCDHDR_SIZE_MSK 0x00001f00 219 /* inverted bitmask for bitfield desc{d}_hdr_size[4:0] */ 220 #define HW_ATL_RDM_DESCDHDR_SIZE_MSKN 0xffffe0ff 221 /* lower bit position of bitfield desc{d}_hdr_size[4:0] */ 222 #define HW_ATL_RDM_DESCDHDR_SIZE_SHIFT 8 223 /* width of bitfield desc{d}_hdr_size[4:0] */ 224 #define HW_ATL_RDM_DESCDHDR_SIZE_WIDTH 5 225 /* default value of bitfield desc{d}_hdr_size[4:0] */ 226 #define HW_ATL_RDM_DESCDHDR_SIZE_DEFAULT 0x0 227 228 /* rx desc{d}_hdr_split bitfield definitions 229 * preprocessor definitions for the bitfield "desc{d}_hdr_split". 230 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 231 * port="pif_rdm_desc_hdr_split_i[0]" 232 */ 233 234 /* register address for bitfield desc{d}_hdr_split */ 235 #define HW_ATL_RDM_DESCDHDR_SPLIT_ADR(descriptor) \ 236 (0x00005b08 + (descriptor) * 0x20) 237 /* bitmask for bitfield desc{d}_hdr_split */ 238 #define HW_ATL_RDM_DESCDHDR_SPLIT_MSK 0x10000000 239 /* inverted bitmask for bitfield desc{d}_hdr_split */ 240 #define HW_ATL_RDM_DESCDHDR_SPLIT_MSKN 0xefffffff 241 /* lower bit position of bitfield desc{d}_hdr_split */ 242 #define HW_ATL_RDM_DESCDHDR_SPLIT_SHIFT 28 243 /* width of bitfield desc{d}_hdr_split */ 244 #define HW_ATL_RDM_DESCDHDR_SPLIT_WIDTH 1 245 /* default value of bitfield desc{d}_hdr_split */ 246 #define HW_ATL_RDM_DESCDHDR_SPLIT_DEFAULT 0x0 247 248 /* rx desc{d}_hd[c:0] bitfield definitions 249 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 250 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 251 * port="rdm_pif_desc0_hd_o[12:0]" 252 */ 253 254 /* register address for bitfield desc{d}_hd[c:0] */ 255 #define HW_ATL_RDM_DESCDHD_ADR(descriptor) (0x00005b0c + (descriptor) * 0x20) 256 /* bitmask for bitfield desc{d}_hd[c:0] */ 257 #define HW_ATL_RDM_DESCDHD_MSK 0x00001fff 258 /* inverted bitmask for bitfield desc{d}_hd[c:0] */ 259 #define HW_ATL_RDM_DESCDHD_MSKN 0xffffe000 260 /* lower bit position of bitfield desc{d}_hd[c:0] */ 261 #define HW_ATL_RDM_DESCDHD_SHIFT 0 262 /* width of bitfield desc{d}_hd[c:0] */ 263 #define HW_ATL_RDM_DESCDHD_WIDTH 13 264 265 /* rx desc{d}_len[9:0] bitfield definitions 266 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 267 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 268 * port="pif_rdm_desc0_len_i[9:0]" 269 */ 270 271 /* register address for bitfield desc{d}_len[9:0] */ 272 #define HW_ATL_RDM_DESCDLEN_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 273 /* bitmask for bitfield desc{d}_len[9:0] */ 274 #define HW_ATL_RDM_DESCDLEN_MSK 0x00001ff8 275 /* inverted bitmask for bitfield desc{d}_len[9:0] */ 276 #define HW_ATL_RDM_DESCDLEN_MSKN 0xffffe007 277 /* lower bit position of bitfield desc{d}_len[9:0] */ 278 #define HW_ATL_RDM_DESCDLEN_SHIFT 3 279 /* width of bitfield desc{d}_len[9:0] */ 280 #define HW_ATL_RDM_DESCDLEN_WIDTH 10 281 /* default value of bitfield desc{d}_len[9:0] */ 282 #define HW_ATL_RDM_DESCDLEN_DEFAULT 0x0 283 284 /* rx desc{d}_reset bitfield definitions 285 * preprocessor definitions for the bitfield "desc{d}_reset". 286 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 287 * port="pif_rdm_q_pf_res_i[0]" 288 */ 289 290 /* register address for bitfield desc{d}_reset */ 291 #define HW_ATL_RDM_DESCDRESET_ADR(descriptor) (0x00005b08 + (descriptor) * 0x20) 292 /* bitmask for bitfield desc{d}_reset */ 293 #define HW_ATL_RDM_DESCDRESET_MSK 0x02000000 294 /* inverted bitmask for bitfield desc{d}_reset */ 295 #define HW_ATL_RDM_DESCDRESET_MSKN 0xfdffffff 296 /* lower bit position of bitfield desc{d}_reset */ 297 #define HW_ATL_RDM_DESCDRESET_SHIFT 25 298 /* width of bitfield desc{d}_reset */ 299 #define HW_ATL_RDM_DESCDRESET_WIDTH 1 300 /* default value of bitfield desc{d}_reset */ 301 #define HW_ATL_RDM_DESCDRESET_DEFAULT 0x0 302 303 /* rdm_desc_init_i bitfield definitions 304 * preprocessor definitions for the bitfield rdm_desc_init_i. 305 * port="pif_rdm_desc_init_i" 306 */ 307 308 /* register address for bitfield rdm_desc_init_i */ 309 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_ADR 0x00005a00 310 /* bitmask for bitfield rdm_desc_init_i */ 311 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSK 0xffffffff 312 /* inverted bitmask for bitfield rdm_desc_init_i */ 313 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_MSKN 0x00000000 314 /* lower bit position of bitfield rdm_desc_init_i */ 315 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_SHIFT 0 316 /* width of bitfield rdm_desc_init_i */ 317 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_WIDTH 32 318 /* default value of bitfield rdm_desc_init_i */ 319 #define HW_ATL_RDM_RX_DMA_DESC_CACHE_INIT_DEFAULT 0x0 320 321 /* rdm_desc_init_done_i bitfield definitions 322 * preprocessor definitions for the bitfield rdm_desc_init_done_i. 323 * port="pif_rdm_desc_init_done_i" 324 */ 325 326 /* register address for bitfield rdm_desc_init_done_i */ 327 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_ADR 0x00005a10 328 /* bitmask for bitfield rdm_desc_init_done_i */ 329 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSK 0x00000001U 330 /* inverted bitmask for bitfield rdm_desc_init_done_i */ 331 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_MSKN 0xfffffffe 332 /* lower bit position of bitfield rdm_desc_init_done_i */ 333 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_SHIFT 0U 334 /* width of bitfield rdm_desc_init_done_i */ 335 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_WIDTH 1 336 /* default value of bitfield rdm_desc_init_done_i */ 337 #define RDM_RX_DMA_DESC_CACHE_INIT_DONE_DEFAULT 0x0 338 339 340 /* rx int_desc_wrb_en bitfield definitions 341 * preprocessor definitions for the bitfield "int_desc_wrb_en". 342 * port="pif_rdm_int_desc_wrb_en_i" 343 */ 344 345 /* register address for bitfield int_desc_wrb_en */ 346 #define HW_ATL_RDM_INT_DESC_WRB_EN_ADR 0x00005a30 347 /* bitmask for bitfield int_desc_wrb_en */ 348 #define HW_ATL_RDM_INT_DESC_WRB_EN_MSK 0x00000004 349 /* inverted bitmask for bitfield int_desc_wrb_en */ 350 #define HW_ATL_RDM_INT_DESC_WRB_EN_MSKN 0xfffffffb 351 /* lower bit position of bitfield int_desc_wrb_en */ 352 #define HW_ATL_RDM_INT_DESC_WRB_EN_SHIFT 2 353 /* width of bitfield int_desc_wrb_en */ 354 #define HW_ATL_RDM_INT_DESC_WRB_EN_WIDTH 1 355 /* default value of bitfield int_desc_wrb_en */ 356 #define HW_ATL_RDM_INT_DESC_WRB_EN_DEFAULT 0x0 357 358 /* rx dca{d}_hdr_en bitfield definitions 359 * preprocessor definitions for the bitfield "dca{d}_hdr_en". 360 * parameter: dca {d} | stride size 0x4 | range [0, 31] 361 * port="pif_rdm_dca_hdr_en_i[0]" 362 */ 363 364 /* register address for bitfield dca{d}_hdr_en */ 365 #define HW_ATL_RDM_DCADHDR_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 366 /* bitmask for bitfield dca{d}_hdr_en */ 367 #define HW_ATL_RDM_DCADHDR_EN_MSK 0x40000000 368 /* inverted bitmask for bitfield dca{d}_hdr_en */ 369 #define HW_ATL_RDM_DCADHDR_EN_MSKN 0xbfffffff 370 /* lower bit position of bitfield dca{d}_hdr_en */ 371 #define HW_ATL_RDM_DCADHDR_EN_SHIFT 30 372 /* width of bitfield dca{d}_hdr_en */ 373 #define HW_ATL_RDM_DCADHDR_EN_WIDTH 1 374 /* default value of bitfield dca{d}_hdr_en */ 375 #define HW_ATL_RDM_DCADHDR_EN_DEFAULT 0x0 376 377 /* rx dca{d}_pay_en bitfield definitions 378 * preprocessor definitions for the bitfield "dca{d}_pay_en". 379 * parameter: dca {d} | stride size 0x4 | range [0, 31] 380 * port="pif_rdm_dca_pay_en_i[0]" 381 */ 382 383 /* register address for bitfield dca{d}_pay_en */ 384 #define HW_ATL_RDM_DCADPAY_EN_ADR(dca) (0x00006100 + (dca) * 0x4) 385 /* bitmask for bitfield dca{d}_pay_en */ 386 #define HW_ATL_RDM_DCADPAY_EN_MSK 0x20000000 387 /* inverted bitmask for bitfield dca{d}_pay_en */ 388 #define HW_ATL_RDM_DCADPAY_EN_MSKN 0xdfffffff 389 /* lower bit position of bitfield dca{d}_pay_en */ 390 #define HW_ATL_RDM_DCADPAY_EN_SHIFT 29 391 /* width of bitfield dca{d}_pay_en */ 392 #define HW_ATL_RDM_DCADPAY_EN_WIDTH 1 393 /* default value of bitfield dca{d}_pay_en */ 394 #define HW_ATL_RDM_DCADPAY_EN_DEFAULT 0x0 395 396 /* RX rdm_int_rim_en Bitfield Definitions 397 * Preprocessor definitions for the bitfield "rdm_int_rim_en". 398 * PORT="pif_rdm_int_rim_en_i" 399 */ 400 401 /* Register address for bitfield rdm_int_rim_en */ 402 #define HW_ATL_RDM_INT_RIM_EN_ADR 0x00005A30 403 /* Bitmask for bitfield rdm_int_rim_en */ 404 #define HW_ATL_RDM_INT_RIM_EN_MSK 0x00000008 405 /* Inverted bitmask for bitfield rdm_int_rim_en */ 406 #define HW_ATL_RDM_INT_RIM_EN_MSKN 0xFFFFFFF7 407 /* Lower bit position of bitfield rdm_int_rim_en */ 408 #define HW_ATL_RDM_INT_RIM_EN_SHIFT 3 409 /* Width of bitfield rdm_int_rim_en */ 410 #define HW_ATL_RDM_INT_RIM_EN_WIDTH 1 411 /* Default value of bitfield rdm_int_rim_en */ 412 #define HW_ATL_RDM_INT_RIM_EN_DEFAULT 0x0 413 414 /* general interrupt mapping register definitions 415 * preprocessor definitions for general interrupt mapping register 416 * base address: 0x00002180 417 * parameter: regidx {f} | stride size 0x4 | range [0, 3] 418 */ 419 #define HW_ATL_GEN_INTR_MAP_ADR(regidx) (0x00002180u + (regidx) * 0x4) 420 421 /* general interrupt status register definitions 422 * preprocessor definitions for general interrupt status register 423 * address: 0x000021A0 424 */ 425 426 #define HW_ATL_GEN_INTR_STAT_ADR 0x000021A4U 427 428 /* interrupt global control register definitions 429 * preprocessor definitions for interrupt global control register 430 * address: 0x00002300 431 */ 432 #define HW_ATL_INTR_GLB_CTL_ADR 0x00002300u 433 434 /* interrupt throttle register definitions 435 * preprocessor definitions for interrupt throttle register 436 * base address: 0x00002800 437 * parameter: throttle {t} | stride size 0x4 | range [0, 31] 438 */ 439 #define HW_ATL_INTR_THR_ADR(throttle) (0x00002800u + (throttle) * 0x4) 440 441 /* rx dma descriptor base address lsw definitions 442 * preprocessor definitions for rx dma descriptor base address lsw 443 * base address: 0x00005b00 444 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 445 */ 446 #define HW_ATL_RX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ 447 (0x00005b00u + (descriptor) * 0x20) 448 449 /* rx dma descriptor base address msw definitions 450 * preprocessor definitions for rx dma descriptor base address msw 451 * base address: 0x00005b04 452 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 453 */ 454 #define HW_ATL_RX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ 455 (0x00005b04u + (descriptor) * 0x20) 456 457 /* rx dma descriptor status register definitions 458 * preprocessor definitions for rx dma descriptor status register 459 * base address: 0x00005b14 460 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 461 */ 462 #define HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor) \ 463 (0x00005b14u + (descriptor) * 0x20) 464 465 /* rx dma descriptor tail pointer register definitions 466 * preprocessor definitions for rx dma descriptor tail pointer register 467 * base address: 0x00005b10 468 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 469 */ 470 #define HW_ATL_RX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ 471 (0x00005b10u + (descriptor) * 0x20) 472 473 /* rx interrupt moderation control register definitions 474 * Preprocessor definitions for RX Interrupt Moderation Control Register 475 * Base Address: 0x00005A40 476 * Parameter: RIM {R} | stride size 0x4 | range [0, 31] 477 */ 478 #define HW_ATL_RX_INTR_MODERATION_CTL_ADR(rim) (0x00005A40u + (rim) * 0x4) 479 480 /* rx filter multicast filter mask register definitions 481 * preprocessor definitions for rx filter multicast filter mask register 482 * address: 0x00005270 483 */ 484 #define HW_ATL_RX_FLR_MCST_FLR_MSK_ADR 0x00005270u 485 486 /* rx filter multicast filter register definitions 487 * preprocessor definitions for rx filter multicast filter register 488 * base address: 0x00005250 489 * parameter: filter {f} | stride size 0x4 | range [0, 7] 490 */ 491 #define HW_ATL_RX_FLR_MCST_FLR_ADR(filter) (0x00005250u + (filter) * 0x4) 492 493 /* RX Filter RSS Control Register 1 Definitions 494 * Preprocessor definitions for RX Filter RSS Control Register 1 495 * Address: 0x000054C0 496 */ 497 #define HW_ATL_RX_FLR_RSS_CONTROL1_ADR 0x000054C0u 498 499 /* RX Filter Control Register 2 Definitions 500 * Preprocessor definitions for RX Filter Control Register 2 501 * Address: 0x00005104 502 */ 503 #define HW_ATL_RX_FLR_CONTROL2_ADR 0x00005104u 504 505 /* tx tx dma debug control [1f:0] bitfield definitions 506 * preprocessor definitions for the bitfield "tx dma debug control [1f:0]". 507 * port="pif_tdm_debug_cntl_i[31:0]" 508 */ 509 510 /* register address for bitfield tx dma debug control [1f:0] */ 511 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_ADR 0x00008920 512 /* bitmask for bitfield tx dma debug control [1f:0] */ 513 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSK 0xffffffff 514 /* inverted bitmask for bitfield tx dma debug control [1f:0] */ 515 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_MSKN 0x00000000 516 /* lower bit position of bitfield tx dma debug control [1f:0] */ 517 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_SHIFT 0 518 /* width of bitfield tx dma debug control [1f:0] */ 519 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_WIDTH 32 520 /* default value of bitfield tx dma debug control [1f:0] */ 521 #define HW_ATL_TDM_TX_DMA_DEBUG_CTL_DEFAULT 0x0 522 523 /* tx dma descriptor base address lsw definitions 524 * preprocessor definitions for tx dma descriptor base address lsw 525 * base address: 0x00007c00 526 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 527 */ 528 #define HW_ATL_TX_DMA_DESC_BASE_ADDRLSW_ADR(descriptor) \ 529 (0x00007c00u + (descriptor) * 0x40) 530 531 /* tx dma descriptor tail pointer register definitions 532 * preprocessor definitions for tx dma descriptor tail pointer register 533 * base address: 0x00007c10 534 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 535 */ 536 #define HW_ATL_TX_DMA_DESC_TAIL_PTR_ADR(descriptor) \ 537 (0x00007c10u + (descriptor) * 0x40) 538 539 /* rx dma_sys_loopback bitfield definitions 540 * preprocessor definitions for the bitfield "dma_sys_loopback". 541 * port="pif_rpb_dma_sys_lbk_i" 542 */ 543 544 /* register address for bitfield dma_sys_loopback */ 545 #define HW_ATL_RPB_DMA_SYS_LBK_ADR 0x00005000 546 /* bitmask for bitfield dma_sys_loopback */ 547 #define HW_ATL_RPB_DMA_SYS_LBK_MSK 0x00000040 548 /* inverted bitmask for bitfield dma_sys_loopback */ 549 #define HW_ATL_RPB_DMA_SYS_LBK_MSKN 0xffffffbf 550 /* lower bit position of bitfield dma_sys_loopback */ 551 #define HW_ATL_RPB_DMA_SYS_LBK_SHIFT 6 552 /* width of bitfield dma_sys_loopback */ 553 #define HW_ATL_RPB_DMA_SYS_LBK_WIDTH 1 554 /* default value of bitfield dma_sys_loopback */ 555 #define HW_ATL_RPB_DMA_SYS_LBK_DEFAULT 0x0 556 557 /* rx rx_tc_mode bitfield definitions 558 * preprocessor definitions for the bitfield "rx_tc_mode". 559 * port="pif_rpb_rx_tc_mode_i,pif_rpf_rx_tc_mode_i" 560 */ 561 562 /* register address for bitfield rx_tc_mode */ 563 #define HW_ATL_RPB_RPF_RX_TC_MODE_ADR 0x00005700 564 /* bitmask for bitfield rx_tc_mode */ 565 #define HW_ATL_RPB_RPF_RX_TC_MODE_MSK 0x00000100 566 /* inverted bitmask for bitfield rx_tc_mode */ 567 #define HW_ATL_RPB_RPF_RX_TC_MODE_MSKN 0xfffffeff 568 /* lower bit position of bitfield rx_tc_mode */ 569 #define HW_ATL_RPB_RPF_RX_TC_MODE_SHIFT 8 570 /* width of bitfield rx_tc_mode */ 571 #define HW_ATL_RPB_RPF_RX_TC_MODE_WIDTH 1 572 /* default value of bitfield rx_tc_mode */ 573 #define HW_ATL_RPB_RPF_RX_TC_MODE_DEFAULT 0x0 574 575 /* rx rx_buf_en bitfield definitions 576 * preprocessor definitions for the bitfield "rx_buf_en". 577 * port="pif_rpb_rx_buf_en_i" 578 */ 579 580 /* register address for bitfield rx_buf_en */ 581 #define HW_ATL_RPB_RX_BUF_EN_ADR 0x00005700 582 /* bitmask for bitfield rx_buf_en */ 583 #define HW_ATL_RPB_RX_BUF_EN_MSK 0x00000001 584 /* inverted bitmask for bitfield rx_buf_en */ 585 #define HW_ATL_RPB_RX_BUF_EN_MSKN 0xfffffffe 586 /* lower bit position of bitfield rx_buf_en */ 587 #define HW_ATL_RPB_RX_BUF_EN_SHIFT 0 588 /* width of bitfield rx_buf_en */ 589 #define HW_ATL_RPB_RX_BUF_EN_WIDTH 1 590 /* default value of bitfield rx_buf_en */ 591 #define HW_ATL_RPB_RX_BUF_EN_DEFAULT 0x0 592 593 /* rx rx{b}_hi_thresh[d:0] bitfield definitions 594 * preprocessor definitions for the bitfield "rx{b}_hi_thresh[d:0]". 595 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 596 * port="pif_rpb_rx0_hi_thresh_i[13:0]" 597 */ 598 599 /* register address for bitfield rx{b}_hi_thresh[d:0] */ 600 #define HW_ATL_RPB_RXBHI_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) 601 /* bitmask for bitfield rx{b}_hi_thresh[d:0] */ 602 #define HW_ATL_RPB_RXBHI_THRESH_MSK 0x3fff0000 603 /* inverted bitmask for bitfield rx{b}_hi_thresh[d:0] */ 604 #define HW_ATL_RPB_RXBHI_THRESH_MSKN 0xc000ffff 605 /* lower bit position of bitfield rx{b}_hi_thresh[d:0] */ 606 #define HW_ATL_RPB_RXBHI_THRESH_SHIFT 16 607 /* width of bitfield rx{b}_hi_thresh[d:0] */ 608 #define HW_ATL_RPB_RXBHI_THRESH_WIDTH 14 609 /* default value of bitfield rx{b}_hi_thresh[d:0] */ 610 #define HW_ATL_RPB_RXBHI_THRESH_DEFAULT 0x0 611 612 /* rx rx{b}_lo_thresh[d:0] bitfield definitions 613 * preprocessor definitions for the bitfield "rx{b}_lo_thresh[d:0]". 614 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 615 * port="pif_rpb_rx0_lo_thresh_i[13:0]" 616 */ 617 618 /* register address for bitfield rx{b}_lo_thresh[d:0] */ 619 #define HW_ATL_RPB_RXBLO_THRESH_ADR(buffer) (0x00005714 + (buffer) * 0x10) 620 /* bitmask for bitfield rx{b}_lo_thresh[d:0] */ 621 #define HW_ATL_RPB_RXBLO_THRESH_MSK 0x00003fff 622 /* inverted bitmask for bitfield rx{b}_lo_thresh[d:0] */ 623 #define HW_ATL_RPB_RXBLO_THRESH_MSKN 0xffffc000 624 /* lower bit position of bitfield rx{b}_lo_thresh[d:0] */ 625 #define HW_ATL_RPB_RXBLO_THRESH_SHIFT 0 626 /* width of bitfield rx{b}_lo_thresh[d:0] */ 627 #define HW_ATL_RPB_RXBLO_THRESH_WIDTH 14 628 /* default value of bitfield rx{b}_lo_thresh[d:0] */ 629 #define HW_ATL_RPB_RXBLO_THRESH_DEFAULT 0x0 630 631 /* rx rx_fc_mode[1:0] bitfield definitions 632 * preprocessor definitions for the bitfield "rx_fc_mode[1:0]". 633 * port="pif_rpb_rx_fc_mode_i[1:0]" 634 */ 635 636 /* register address for bitfield rx_fc_mode[1:0] */ 637 #define HW_ATL_RPB_RX_FC_MODE_ADR 0x00005700 638 /* bitmask for bitfield rx_fc_mode[1:0] */ 639 #define HW_ATL_RPB_RX_FC_MODE_MSK 0x00000030 640 /* inverted bitmask for bitfield rx_fc_mode[1:0] */ 641 #define HW_ATL_RPB_RX_FC_MODE_MSKN 0xffffffcf 642 /* lower bit position of bitfield rx_fc_mode[1:0] */ 643 #define HW_ATL_RPB_RX_FC_MODE_SHIFT 4 644 /* width of bitfield rx_fc_mode[1:0] */ 645 #define HW_ATL_RPB_RX_FC_MODE_WIDTH 2 646 /* default value of bitfield rx_fc_mode[1:0] */ 647 #define HW_ATL_RPB_RX_FC_MODE_DEFAULT 0x0 648 649 /* rx rx{b}_buf_size[8:0] bitfield definitions 650 * preprocessor definitions for the bitfield "rx{b}_buf_size[8:0]". 651 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 652 * port="pif_rpb_rx0_buf_size_i[8:0]" 653 */ 654 655 /* register address for bitfield rx{b}_buf_size[8:0] */ 656 #define HW_ATL_RPB_RXBBUF_SIZE_ADR(buffer) (0x00005710 + (buffer) * 0x10) 657 /* bitmask for bitfield rx{b}_buf_size[8:0] */ 658 #define HW_ATL_RPB_RXBBUF_SIZE_MSK 0x000001ff 659 /* inverted bitmask for bitfield rx{b}_buf_size[8:0] */ 660 #define HW_ATL_RPB_RXBBUF_SIZE_MSKN 0xfffffe00 661 /* lower bit position of bitfield rx{b}_buf_size[8:0] */ 662 #define HW_ATL_RPB_RXBBUF_SIZE_SHIFT 0 663 /* width of bitfield rx{b}_buf_size[8:0] */ 664 #define HW_ATL_RPB_RXBBUF_SIZE_WIDTH 9 665 /* default value of bitfield rx{b}_buf_size[8:0] */ 666 #define HW_ATL_RPB_RXBBUF_SIZE_DEFAULT 0x0 667 668 /* rx rx{b}_xoff_en bitfield definitions 669 * preprocessor definitions for the bitfield "rx{b}_xoff_en". 670 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 671 * port="pif_rpb_rx_xoff_en_i[0]" 672 */ 673 674 /* register address for bitfield rx{b}_xoff_en */ 675 #define HW_ATL_RPB_RXBXOFF_EN_ADR(buffer) (0x00005714 + (buffer) * 0x10) 676 /* bitmask for bitfield rx{b}_xoff_en */ 677 #define HW_ATL_RPB_RXBXOFF_EN_MSK 0x80000000 678 /* inverted bitmask for bitfield rx{b}_xoff_en */ 679 #define HW_ATL_RPB_RXBXOFF_EN_MSKN 0x7fffffff 680 /* lower bit position of bitfield rx{b}_xoff_en */ 681 #define HW_ATL_RPB_RXBXOFF_EN_SHIFT 31 682 /* width of bitfield rx{b}_xoff_en */ 683 #define HW_ATL_RPB_RXBXOFF_EN_WIDTH 1 684 /* default value of bitfield rx{b}_xoff_en */ 685 #define HW_ATL_RPB_RXBXOFF_EN_DEFAULT 0x0 686 687 /* rx l2_bc_thresh[f:0] bitfield definitions 688 * preprocessor definitions for the bitfield "l2_bc_thresh[f:0]". 689 * port="pif_rpf_l2_bc_thresh_i[15:0]" 690 */ 691 692 /* register address for bitfield l2_bc_thresh[f:0] */ 693 #define HW_ATL_RPFL2BC_THRESH_ADR 0x00005100 694 /* bitmask for bitfield l2_bc_thresh[f:0] */ 695 #define HW_ATL_RPFL2BC_THRESH_MSK 0xffff0000 696 /* inverted bitmask for bitfield l2_bc_thresh[f:0] */ 697 #define HW_ATL_RPFL2BC_THRESH_MSKN 0x0000ffff 698 /* lower bit position of bitfield l2_bc_thresh[f:0] */ 699 #define HW_ATL_RPFL2BC_THRESH_SHIFT 16 700 /* width of bitfield l2_bc_thresh[f:0] */ 701 #define HW_ATL_RPFL2BC_THRESH_WIDTH 16 702 /* default value of bitfield l2_bc_thresh[f:0] */ 703 #define HW_ATL_RPFL2BC_THRESH_DEFAULT 0x0 704 705 /* rx l2_bc_en bitfield definitions 706 * preprocessor definitions for the bitfield "l2_bc_en". 707 * port="pif_rpf_l2_bc_en_i" 708 */ 709 710 /* register address for bitfield l2_bc_en */ 711 #define HW_ATL_RPFL2BC_EN_ADR 0x00005100 712 /* bitmask for bitfield l2_bc_en */ 713 #define HW_ATL_RPFL2BC_EN_MSK 0x00000001 714 /* inverted bitmask for bitfield l2_bc_en */ 715 #define HW_ATL_RPFL2BC_EN_MSKN 0xfffffffe 716 /* lower bit position of bitfield l2_bc_en */ 717 #define HW_ATL_RPFL2BC_EN_SHIFT 0 718 /* width of bitfield l2_bc_en */ 719 #define HW_ATL_RPFL2BC_EN_WIDTH 1 720 /* default value of bitfield l2_bc_en */ 721 #define HW_ATL_RPFL2BC_EN_DEFAULT 0x0 722 723 /* rx l2_bc_act[2:0] bitfield definitions 724 * preprocessor definitions for the bitfield "l2_bc_act[2:0]". 725 * port="pif_rpf_l2_bc_act_i[2:0]" 726 */ 727 728 /* register address for bitfield l2_bc_act[2:0] */ 729 #define HW_ATL_RPFL2BC_ACT_ADR 0x00005100 730 /* bitmask for bitfield l2_bc_act[2:0] */ 731 #define HW_ATL_RPFL2BC_ACT_MSK 0x00007000 732 /* inverted bitmask for bitfield l2_bc_act[2:0] */ 733 #define HW_ATL_RPFL2BC_ACT_MSKN 0xffff8fff 734 /* lower bit position of bitfield l2_bc_act[2:0] */ 735 #define HW_ATL_RPFL2BC_ACT_SHIFT 12 736 /* width of bitfield l2_bc_act[2:0] */ 737 #define HW_ATL_RPFL2BC_ACT_WIDTH 3 738 /* default value of bitfield l2_bc_act[2:0] */ 739 #define HW_ATL_RPFL2BC_ACT_DEFAULT 0x0 740 741 /* rx l2_mc_en{f} bitfield definitions 742 * preprocessor definitions for the bitfield "l2_mc_en{f}". 743 * parameter: filter {f} | stride size 0x4 | range [0, 7] 744 * port="pif_rpf_l2_mc_en_i[0]" 745 */ 746 747 /* register address for bitfield l2_mc_en{f} */ 748 #define HW_ATL_RPFL2MC_ENF_ADR(filter) (0x00005250 + (filter) * 0x4) 749 /* bitmask for bitfield l2_mc_en{f} */ 750 #define HW_ATL_RPFL2MC_ENF_MSK 0x80000000 751 /* inverted bitmask for bitfield l2_mc_en{f} */ 752 #define HW_ATL_RPFL2MC_ENF_MSKN 0x7fffffff 753 /* lower bit position of bitfield l2_mc_en{f} */ 754 #define HW_ATL_RPFL2MC_ENF_SHIFT 31 755 /* width of bitfield l2_mc_en{f} */ 756 #define HW_ATL_RPFL2MC_ENF_WIDTH 1 757 /* default value of bitfield l2_mc_en{f} */ 758 #define HW_ATL_RPFL2MC_ENF_DEFAULT 0x0 759 760 /* rx l2_promis_mode bitfield definitions 761 * preprocessor definitions for the bitfield "l2_promis_mode". 762 * port="pif_rpf_l2_promis_mode_i" 763 */ 764 765 /* register address for bitfield l2_promis_mode */ 766 #define HW_ATL_RPFL2PROMIS_MODE_ADR 0x00005100 767 /* bitmask for bitfield l2_promis_mode */ 768 #define HW_ATL_RPFL2PROMIS_MODE_MSK 0x00000008 769 /* inverted bitmask for bitfield l2_promis_mode */ 770 #define HW_ATL_RPFL2PROMIS_MODE_MSKN 0xfffffff7 771 /* lower bit position of bitfield l2_promis_mode */ 772 #define HW_ATL_RPFL2PROMIS_MODE_SHIFT 3 773 /* width of bitfield l2_promis_mode */ 774 #define HW_ATL_RPFL2PROMIS_MODE_WIDTH 1 775 /* default value of bitfield l2_promis_mode */ 776 #define HW_ATL_RPFL2PROMIS_MODE_DEFAULT 0x0 777 778 /* rx l2_uc_act{f}[2:0] bitfield definitions 779 * preprocessor definitions for the bitfield "l2_uc_act{f}[2:0]". 780 * parameter: filter {f} | stride size 0x8 | range [0, 37] 781 * port="pif_rpf_l2_uc_act0_i[2:0]" 782 */ 783 784 /* register address for bitfield l2_uc_act{f}[2:0] */ 785 #define HW_ATL_RPFL2UC_ACTF_ADR(filter) (0x00005114 + (filter) * 0x8) 786 /* bitmask for bitfield l2_uc_act{f}[2:0] */ 787 #define HW_ATL_RPFL2UC_ACTF_MSK 0x00070000 788 /* inverted bitmask for bitfield l2_uc_act{f}[2:0] */ 789 #define HW_ATL_RPFL2UC_ACTF_MSKN 0xfff8ffff 790 /* lower bit position of bitfield l2_uc_act{f}[2:0] */ 791 #define HW_ATL_RPFL2UC_ACTF_SHIFT 16 792 /* width of bitfield l2_uc_act{f}[2:0] */ 793 #define HW_ATL_RPFL2UC_ACTF_WIDTH 3 794 /* default value of bitfield l2_uc_act{f}[2:0] */ 795 #define HW_ATL_RPFL2UC_ACTF_DEFAULT 0x0 796 797 /* rx l2_uc_en{f} bitfield definitions 798 * preprocessor definitions for the bitfield "l2_uc_en{f}". 799 * parameter: filter {f} | stride size 0x8 | range [0, 37] 800 * port="pif_rpf_l2_uc_en_i[0]" 801 */ 802 803 /* register address for bitfield l2_uc_en{f} */ 804 #define HW_ATL_RPFL2UC_ENF_ADR(filter) (0x00005114 + (filter) * 0x8) 805 /* bitmask for bitfield l2_uc_en{f} */ 806 #define HW_ATL_RPFL2UC_ENF_MSK 0x80000000 807 /* inverted bitmask for bitfield l2_uc_en{f} */ 808 #define HW_ATL_RPFL2UC_ENF_MSKN 0x7fffffff 809 /* lower bit position of bitfield l2_uc_en{f} */ 810 #define HW_ATL_RPFL2UC_ENF_SHIFT 31 811 /* width of bitfield l2_uc_en{f} */ 812 #define HW_ATL_RPFL2UC_ENF_WIDTH 1 813 /* default value of bitfield l2_uc_en{f} */ 814 #define HW_ATL_RPFL2UC_ENF_DEFAULT 0x0 815 816 /* register address for bitfield l2_uc_da{f}_lsw[1f:0] */ 817 #define HW_ATL_RPFL2UC_DAFLSW_ADR(filter) (0x00005110 + (filter) * 0x8) 818 /* register address for bitfield l2_uc_da{f}_msw[f:0] */ 819 #define HW_ATL_RPFL2UC_DAFMSW_ADR(filter) (0x00005114 + (filter) * 0x8) 820 /* bitmask for bitfield l2_uc_da{f}_msw[f:0] */ 821 #define HW_ATL_RPFL2UC_DAFMSW_MSK 0x0000ffff 822 /* lower bit position of bitfield l2_uc_da{f}_msw[f:0] */ 823 #define HW_ATL_RPFL2UC_DAFMSW_SHIFT 0 824 825 /* rx l2_mc_accept_all bitfield definitions 826 * Preprocessor definitions for the bitfield "l2_mc_accept_all". 827 * PORT="pif_rpf_l2_mc_all_accept_i" 828 */ 829 830 /* Register address for bitfield l2_mc_accept_all */ 831 #define HW_ATL_RPFL2MC_ACCEPT_ALL_ADR 0x00005270 832 /* Bitmask for bitfield l2_mc_accept_all */ 833 #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSK 0x00004000 834 /* Inverted bitmask for bitfield l2_mc_accept_all */ 835 #define HW_ATL_RPFL2MC_ACCEPT_ALL_MSKN 0xFFFFBFFF 836 /* Lower bit position of bitfield l2_mc_accept_all */ 837 #define HW_ATL_RPFL2MC_ACCEPT_ALL_SHIFT 14 838 /* Width of bitfield l2_mc_accept_all */ 839 #define HW_ATL_RPFL2MC_ACCEPT_ALL_WIDTH 1 840 /* Default value of bitfield l2_mc_accept_all */ 841 #define HW_ATL_RPFL2MC_ACCEPT_ALL_DEFAULT 0x0 842 843 /* width of bitfield rx_tc_up{t}[2:0] */ 844 #define HW_ATL_RPF_RPB_RX_TC_UPT_WIDTH 3 845 /* default value of bitfield rx_tc_up{t}[2:0] */ 846 #define HW_ATL_RPF_RPB_RX_TC_UPT_DEFAULT 0x0 847 848 /* rx rss_key_addr[4:0] bitfield definitions 849 * preprocessor definitions for the bitfield "rss_key_addr[4:0]". 850 * port="pif_rpf_rss_key_addr_i[4:0]" 851 */ 852 853 /* register address for bitfield rss_key_addr[4:0] */ 854 #define HW_ATL_RPF_RSS_KEY_ADDR_ADR 0x000054d0 855 /* bitmask for bitfield rss_key_addr[4:0] */ 856 #define HW_ATL_RPF_RSS_KEY_ADDR_MSK 0x0000001f 857 /* inverted bitmask for bitfield rss_key_addr[4:0] */ 858 #define HW_ATL_RPF_RSS_KEY_ADDR_MSKN 0xffffffe0 859 /* lower bit position of bitfield rss_key_addr[4:0] */ 860 #define HW_ATL_RPF_RSS_KEY_ADDR_SHIFT 0 861 /* width of bitfield rss_key_addr[4:0] */ 862 #define HW_ATL_RPF_RSS_KEY_ADDR_WIDTH 5 863 /* default value of bitfield rss_key_addr[4:0] */ 864 #define HW_ATL_RPF_RSS_KEY_ADDR_DEFAULT 0x0 865 866 /* rx rss_key_wr_data[1f:0] bitfield definitions 867 * preprocessor definitions for the bitfield "rss_key_wr_data[1f:0]". 868 * port="pif_rpf_rss_key_wr_data_i[31:0]" 869 */ 870 871 /* register address for bitfield rss_key_wr_data[1f:0] */ 872 #define HW_ATL_RPF_RSS_KEY_WR_DATA_ADR 0x000054d4 873 /* bitmask for bitfield rss_key_wr_data[1f:0] */ 874 #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSK 0xffffffff 875 /* inverted bitmask for bitfield rss_key_wr_data[1f:0] */ 876 #define HW_ATL_RPF_RSS_KEY_WR_DATA_MSKN 0x00000000 877 /* lower bit position of bitfield rss_key_wr_data[1f:0] */ 878 #define HW_ATL_RPF_RSS_KEY_WR_DATA_SHIFT 0 879 /* width of bitfield rss_key_wr_data[1f:0] */ 880 #define HW_ATL_RPF_RSS_KEY_WR_DATA_WIDTH 32 881 /* default value of bitfield rss_key_wr_data[1f:0] */ 882 #define HW_ATL_RPF_RSS_KEY_WR_DATA_DEFAULT 0x0 883 884 /* rx rss_key_wr_en_i bitfield definitions 885 * preprocessor definitions for the bitfield "rss_key_wr_en_i". 886 * port="pif_rpf_rss_key_wr_en_i" 887 */ 888 889 /* register address for bitfield rss_key_wr_en_i */ 890 #define HW_ATL_RPF_RSS_KEY_WR_ENI_ADR 0x000054d0 891 /* bitmask for bitfield rss_key_wr_en_i */ 892 #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSK 0x00000020 893 /* inverted bitmask for bitfield rss_key_wr_en_i */ 894 #define HW_ATL_RPF_RSS_KEY_WR_ENI_MSKN 0xffffffdf 895 /* lower bit position of bitfield rss_key_wr_en_i */ 896 #define HW_ATL_RPF_RSS_KEY_WR_ENI_SHIFT 5 897 /* width of bitfield rss_key_wr_en_i */ 898 #define HW_ATL_RPF_RSS_KEY_WR_ENI_WIDTH 1 899 /* default value of bitfield rss_key_wr_en_i */ 900 #define HW_ATL_RPF_RSS_KEY_WR_ENI_DEFAULT 0x0 901 902 /* rx rss_redir_addr[3:0] bitfield definitions 903 * preprocessor definitions for the bitfield "rss_redir_addr[3:0]". 904 * port="pif_rpf_rss_redir_addr_i[3:0]" 905 */ 906 907 /* register address for bitfield rss_redir_addr[3:0] */ 908 #define HW_ATL_RPF_RSS_REDIR_ADDR_ADR 0x000054e0 909 /* bitmask for bitfield rss_redir_addr[3:0] */ 910 #define HW_ATL_RPF_RSS_REDIR_ADDR_MSK 0x0000000f 911 /* inverted bitmask for bitfield rss_redir_addr[3:0] */ 912 #define HW_ATL_RPF_RSS_REDIR_ADDR_MSKN 0xfffffff0 913 /* lower bit position of bitfield rss_redir_addr[3:0] */ 914 #define HW_ATL_RPF_RSS_REDIR_ADDR_SHIFT 0 915 /* width of bitfield rss_redir_addr[3:0] */ 916 #define HW_ATL_RPF_RSS_REDIR_ADDR_WIDTH 4 917 /* default value of bitfield rss_redir_addr[3:0] */ 918 #define HW_ATL_RPF_RSS_REDIR_ADDR_DEFAULT 0x0 919 920 /* rx rss_redir_wr_data[f:0] bitfield definitions 921 * preprocessor definitions for the bitfield "rss_redir_wr_data[f:0]". 922 * port="pif_rpf_rss_redir_wr_data_i[15:0]" 923 */ 924 925 /* register address for bitfield rss_redir_wr_data[f:0] */ 926 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_ADR 0x000054e4 927 /* bitmask for bitfield rss_redir_wr_data[f:0] */ 928 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSK 0x0000ffff 929 /* inverted bitmask for bitfield rss_redir_wr_data[f:0] */ 930 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_MSKN 0xffff0000 931 /* lower bit position of bitfield rss_redir_wr_data[f:0] */ 932 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_SHIFT 0 933 /* width of bitfield rss_redir_wr_data[f:0] */ 934 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_WIDTH 16 935 /* default value of bitfield rss_redir_wr_data[f:0] */ 936 #define HW_ATL_RPF_RSS_REDIR_WR_DATA_DEFAULT 0x0 937 938 /* rx rss_redir_wr_en_i bitfield definitions 939 * preprocessor definitions for the bitfield "rss_redir_wr_en_i". 940 * port="pif_rpf_rss_redir_wr_en_i" 941 */ 942 943 /* register address for bitfield rss_redir_wr_en_i */ 944 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_ADR 0x000054e0 945 /* bitmask for bitfield rss_redir_wr_en_i */ 946 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSK 0x00000010 947 /* inverted bitmask for bitfield rss_redir_wr_en_i */ 948 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_MSKN 0xffffffef 949 /* lower bit position of bitfield rss_redir_wr_en_i */ 950 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_SHIFT 4 951 /* width of bitfield rss_redir_wr_en_i */ 952 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_WIDTH 1 953 /* default value of bitfield rss_redir_wr_en_i */ 954 #define HW_ATL_RPF_RSS_REDIR_WR_ENI_DEFAULT 0x0 955 956 /* rx tpo_rpf_sys_loopback bitfield definitions 957 * preprocessor definitions for the bitfield "tpo_rpf_sys_loopback". 958 * port="pif_rpf_tpo_pkt_sys_lbk_i" 959 */ 960 961 /* register address for bitfield tpo_rpf_sys_loopback */ 962 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_ADR 0x00005000 963 /* bitmask for bitfield tpo_rpf_sys_loopback */ 964 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSK 0x00000100 965 /* inverted bitmask for bitfield tpo_rpf_sys_loopback */ 966 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_MSKN 0xfffffeff 967 /* lower bit position of bitfield tpo_rpf_sys_loopback */ 968 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_SHIFT 8 969 /* width of bitfield tpo_rpf_sys_loopback */ 970 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_WIDTH 1 971 /* default value of bitfield tpo_rpf_sys_loopback */ 972 #define HW_ATL_RPF_TPO_RPF_SYS_LBK_DEFAULT 0x0 973 974 /* rx vl_inner_tpid[f:0] bitfield definitions 975 * preprocessor definitions for the bitfield "vl_inner_tpid[f:0]". 976 * port="pif_rpf_vl_inner_tpid_i[15:0]" 977 */ 978 979 /* register address for bitfield vl_inner_tpid[f:0] */ 980 #define HW_ATL_RPF_VL_INNER_TPID_ADR 0x00005284 981 /* bitmask for bitfield vl_inner_tpid[f:0] */ 982 #define HW_ATL_RPF_VL_INNER_TPID_MSK 0x0000ffff 983 /* inverted bitmask for bitfield vl_inner_tpid[f:0] */ 984 #define HW_ATL_RPF_VL_INNER_TPID_MSKN 0xffff0000 985 /* lower bit position of bitfield vl_inner_tpid[f:0] */ 986 #define HW_ATL_RPF_VL_INNER_TPID_SHIFT 0 987 /* width of bitfield vl_inner_tpid[f:0] */ 988 #define HW_ATL_RPF_VL_INNER_TPID_WIDTH 16 989 /* default value of bitfield vl_inner_tpid[f:0] */ 990 #define HW_ATL_RPF_VL_INNER_TPID_DEFAULT 0x8100 991 992 /* rx vl_outer_tpid[f:0] bitfield definitions 993 * preprocessor definitions for the bitfield "vl_outer_tpid[f:0]". 994 * port="pif_rpf_vl_outer_tpid_i[15:0]" 995 */ 996 997 /* register address for bitfield vl_outer_tpid[f:0] */ 998 #define HW_ATL_RPF_VL_OUTER_TPID_ADR 0x00005284 999 /* bitmask for bitfield vl_outer_tpid[f:0] */ 1000 #define HW_ATL_RPF_VL_OUTER_TPID_MSK 0xffff0000 1001 /* inverted bitmask for bitfield vl_outer_tpid[f:0] */ 1002 #define HW_ATL_RPF_VL_OUTER_TPID_MSKN 0x0000ffff 1003 /* lower bit position of bitfield vl_outer_tpid[f:0] */ 1004 #define HW_ATL_RPF_VL_OUTER_TPID_SHIFT 16 1005 /* width of bitfield vl_outer_tpid[f:0] */ 1006 #define HW_ATL_RPF_VL_OUTER_TPID_WIDTH 16 1007 /* default value of bitfield vl_outer_tpid[f:0] */ 1008 #define HW_ATL_RPF_VL_OUTER_TPID_DEFAULT 0x88a8 1009 1010 /* rx vl_promis_mode bitfield definitions 1011 * preprocessor definitions for the bitfield "vl_promis_mode". 1012 * port="pif_rpf_vl_promis_mode_i" 1013 */ 1014 1015 /* register address for bitfield vl_promis_mode */ 1016 #define HW_ATL_RPF_VL_PROMIS_MODE_ADR 0x00005280 1017 /* bitmask for bitfield vl_promis_mode */ 1018 #define HW_ATL_RPF_VL_PROMIS_MODE_MSK 0x00000002 1019 /* inverted bitmask for bitfield vl_promis_mode */ 1020 #define HW_ATL_RPF_VL_PROMIS_MODE_MSKN 0xfffffffd 1021 /* lower bit position of bitfield vl_promis_mode */ 1022 #define HW_ATL_RPF_VL_PROMIS_MODE_SHIFT 1 1023 /* width of bitfield vl_promis_mode */ 1024 #define HW_ATL_RPF_VL_PROMIS_MODE_WIDTH 1 1025 /* default value of bitfield vl_promis_mode */ 1026 #define HW_ATL_RPF_VL_PROMIS_MODE_DEFAULT 0x0 1027 1028 /* RX vl_accept_untagged_mode Bitfield Definitions 1029 * Preprocessor definitions for the bitfield "vl_accept_untagged_mode". 1030 * PORT="pif_rpf_vl_accept_untagged_i" 1031 */ 1032 1033 /* Register address for bitfield vl_accept_untagged_mode */ 1034 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_ADR 0x00005280 1035 /* Bitmask for bitfield vl_accept_untagged_mode */ 1036 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSK 0x00000004 1037 /* Inverted bitmask for bitfield vl_accept_untagged_mode */ 1038 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_MSKN 0xFFFFFFFB 1039 /* Lower bit position of bitfield vl_accept_untagged_mode */ 1040 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_SHIFT 2 1041 /* Width of bitfield vl_accept_untagged_mode */ 1042 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_WIDTH 1 1043 /* Default value of bitfield vl_accept_untagged_mode */ 1044 #define HW_ATL_RPF_VL_ACCEPT_UNTAGGED_MODE_DEFAULT 0x0 1045 1046 /* rX vl_untagged_act[2:0] Bitfield Definitions 1047 * Preprocessor definitions for the bitfield "vl_untagged_act[2:0]". 1048 * PORT="pif_rpf_vl_untagged_act_i[2:0]" 1049 */ 1050 1051 /* Register address for bitfield vl_untagged_act[2:0] */ 1052 #define HW_ATL_RPF_VL_UNTAGGED_ACT_ADR 0x00005280 1053 /* Bitmask for bitfield vl_untagged_act[2:0] */ 1054 #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSK 0x00000038 1055 /* Inverted bitmask for bitfield vl_untagged_act[2:0] */ 1056 #define HW_ATL_RPF_VL_UNTAGGED_ACT_MSKN 0xFFFFFFC7 1057 /* Lower bit position of bitfield vl_untagged_act[2:0] */ 1058 #define HW_ATL_RPF_VL_UNTAGGED_ACT_SHIFT 3 1059 /* Width of bitfield vl_untagged_act[2:0] */ 1060 #define HW_ATL_RPF_VL_UNTAGGED_ACT_WIDTH 3 1061 /* Default value of bitfield vl_untagged_act[2:0] */ 1062 #define HW_ATL_RPF_VL_UNTAGGED_ACT_DEFAULT 0x0 1063 1064 /* RX vl_en{F} Bitfield Definitions 1065 * Preprocessor definitions for the bitfield "vl_en{F}". 1066 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1067 * PORT="pif_rpf_vl_en_i[0]" 1068 */ 1069 1070 /* Register address for bitfield vl_en{F} */ 1071 #define HW_ATL_RPF_VL_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1072 /* Bitmask for bitfield vl_en{F} */ 1073 #define HW_ATL_RPF_VL_EN_F_MSK 0x80000000 1074 /* Inverted bitmask for bitfield vl_en{F} */ 1075 #define HW_ATL_RPF_VL_EN_F_MSKN 0x7FFFFFFF 1076 /* Lower bit position of bitfield vl_en{F} */ 1077 #define HW_ATL_RPF_VL_EN_F_SHIFT 31 1078 /* Width of bitfield vl_en{F} */ 1079 #define HW_ATL_RPF_VL_EN_F_WIDTH 1 1080 /* Default value of bitfield vl_en{F} */ 1081 #define HW_ATL_RPF_VL_EN_F_DEFAULT 0x0 1082 1083 /* RX vl_act{F}[2:0] Bitfield Definitions 1084 * Preprocessor definitions for the bitfield "vl_act{F}[2:0]". 1085 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1086 * PORT="pif_rpf_vl_act0_i[2:0]" 1087 */ 1088 1089 /* Register address for bitfield vl_act{F}[2:0] */ 1090 #define HW_ATL_RPF_VL_ACT_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1091 /* Bitmask for bitfield vl_act{F}[2:0] */ 1092 #define HW_ATL_RPF_VL_ACT_F_MSK 0x00070000 1093 /* Inverted bitmask for bitfield vl_act{F}[2:0] */ 1094 #define HW_ATL_RPF_VL_ACT_F_MSKN 0xFFF8FFFF 1095 /* Lower bit position of bitfield vl_act{F}[2:0] */ 1096 #define HW_ATL_RPF_VL_ACT_F_SHIFT 16 1097 /* Width of bitfield vl_act{F}[2:0] */ 1098 #define HW_ATL_RPF_VL_ACT_F_WIDTH 3 1099 /* Default value of bitfield vl_act{F}[2:0] */ 1100 #define HW_ATL_RPF_VL_ACT_F_DEFAULT 0x0 1101 1102 /* RX vl_id{F}[B:0] Bitfield Definitions 1103 * Preprocessor definitions for the bitfield "vl_id{F}[B:0]". 1104 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1105 * PORT="pif_rpf_vl_id0_i[11:0]" 1106 */ 1107 1108 /* Register address for bitfield vl_id{F}[B:0] */ 1109 #define HW_ATL_RPF_VL_ID_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1110 /* Bitmask for bitfield vl_id{F}[B:0] */ 1111 #define HW_ATL_RPF_VL_ID_F_MSK 0x00000FFF 1112 /* Inverted bitmask for bitfield vl_id{F}[B:0] */ 1113 #define HW_ATL_RPF_VL_ID_F_MSKN 0xFFFFF000 1114 /* Lower bit position of bitfield vl_id{F}[B:0] */ 1115 #define HW_ATL_RPF_VL_ID_F_SHIFT 0 1116 /* Width of bitfield vl_id{F}[B:0] */ 1117 #define HW_ATL_RPF_VL_ID_F_WIDTH 12 1118 /* Default value of bitfield vl_id{F}[B:0] */ 1119 #define HW_ATL_RPF_VL_ID_F_DEFAULT 0x0 1120 1121 /* RX vl_rxq_en{F} Bitfield Definitions 1122 * Preprocessor definitions for the bitfield "vl_rxq{F}". 1123 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1124 * PORT="pif_rpf_vl_rxq_en_i" 1125 */ 1126 1127 /* Register address for bitfield vl_rxq_en{F} */ 1128 #define HW_ATL_RPF_VL_RXQ_EN_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1129 /* Bitmask for bitfield vl_rxq_en{F} */ 1130 #define HW_ATL_RPF_VL_RXQ_EN_F_MSK 0x10000000 1131 /* Inverted bitmask for bitfield vl_rxq_en{F}[ */ 1132 #define HW_ATL_RPF_VL_RXQ_EN_F_MSKN 0xEFFFFFFF 1133 /* Lower bit position of bitfield vl_rxq_en{F} */ 1134 #define HW_ATL_RPF_VL_RXQ_EN_F_SHIFT 28 1135 /* Width of bitfield vl_rxq_en{F} */ 1136 #define HW_ATL_RPF_VL_RXQ_EN_F_WIDTH 1 1137 /* Default value of bitfield vl_rxq_en{F} */ 1138 #define HW_ATL_RPF_VL_RXQ_EN_F_DEFAULT 0x0 1139 1140 /* RX vl_rxq{F}[4:0] Bitfield Definitions 1141 * Preprocessor definitions for the bitfield "vl_rxq{F}[4:0]". 1142 * Parameter: filter {F} | stride size 0x4 | range [0, 15] 1143 * PORT="pif_rpf_vl_rxq0_i[4:0]" 1144 */ 1145 1146 /* Register address for bitfield vl_rxq{F}[4:0] */ 1147 #define HW_ATL_RPF_VL_RXQ_F_ADR(filter) (0x00005290 + (filter) * 0x4) 1148 /* Bitmask for bitfield vl_rxq{F}[4:0] */ 1149 #define HW_ATL_RPF_VL_RXQ_F_MSK 0x01F00000 1150 /* Inverted bitmask for bitfield vl_rxq{F}[4:0] */ 1151 #define HW_ATL_RPF_VL_RXQ_F_MSKN 0xFE0FFFFF 1152 /* Lower bit position of bitfield vl_rxq{F}[4:0] */ 1153 #define HW_ATL_RPF_VL_RXQ_F_SHIFT 20 1154 /* Width of bitfield vl_rxw{F}[4:0] */ 1155 #define HW_ATL_RPF_VL_RXQ_F_WIDTH 5 1156 /* Default value of bitfield vl_rxq{F}[4:0] */ 1157 #define HW_ATL_RPF_VL_RXQ_F_DEFAULT 0x0 1158 1159 /* rx et_en{f} bitfield definitions 1160 * preprocessor definitions for the bitfield "et_en{f}". 1161 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1162 * port="pif_rpf_et_en_i[0]" 1163 */ 1164 1165 /* register address for bitfield et_en{f} */ 1166 #define HW_ATL_RPF_ET_ENF_ADR(filter) (0x00005300 + (filter) * 0x4) 1167 /* bitmask for bitfield et_en{f} */ 1168 #define HW_ATL_RPF_ET_ENF_MSK 0x80000000 1169 /* inverted bitmask for bitfield et_en{f} */ 1170 #define HW_ATL_RPF_ET_ENF_MSKN 0x7fffffff 1171 /* lower bit position of bitfield et_en{f} */ 1172 #define HW_ATL_RPF_ET_ENF_SHIFT 31 1173 /* width of bitfield et_en{f} */ 1174 #define HW_ATL_RPF_ET_ENF_WIDTH 1 1175 /* default value of bitfield et_en{f} */ 1176 #define HW_ATL_RPF_ET_ENF_DEFAULT 0x0 1177 1178 /* rx et_up{f}_en bitfield definitions 1179 * preprocessor definitions for the bitfield "et_up{f}_en". 1180 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1181 * port="pif_rpf_et_up_en_i[0]" 1182 */ 1183 1184 /* register address for bitfield et_up{f}_en */ 1185 #define HW_ATL_RPF_ET_UPFEN_ADR(filter) (0x00005300 + (filter) * 0x4) 1186 /* bitmask for bitfield et_up{f}_en */ 1187 #define HW_ATL_RPF_ET_UPFEN_MSK 0x40000000 1188 /* inverted bitmask for bitfield et_up{f}_en */ 1189 #define HW_ATL_RPF_ET_UPFEN_MSKN 0xbfffffff 1190 /* lower bit position of bitfield et_up{f}_en */ 1191 #define HW_ATL_RPF_ET_UPFEN_SHIFT 30 1192 /* width of bitfield et_up{f}_en */ 1193 #define HW_ATL_RPF_ET_UPFEN_WIDTH 1 1194 /* default value of bitfield et_up{f}_en */ 1195 #define HW_ATL_RPF_ET_UPFEN_DEFAULT 0x0 1196 1197 /* rx et_rxq{f}_en bitfield definitions 1198 * preprocessor definitions for the bitfield "et_rxq{f}_en". 1199 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1200 * port="pif_rpf_et_rxq_en_i[0]" 1201 */ 1202 1203 /* register address for bitfield et_rxq{f}_en */ 1204 #define HW_ATL_RPF_ET_RXQFEN_ADR(filter) (0x00005300 + (filter) * 0x4) 1205 /* bitmask for bitfield et_rxq{f}_en */ 1206 #define HW_ATL_RPF_ET_RXQFEN_MSK 0x20000000 1207 /* inverted bitmask for bitfield et_rxq{f}_en */ 1208 #define HW_ATL_RPF_ET_RXQFEN_MSKN 0xdfffffff 1209 /* lower bit position of bitfield et_rxq{f}_en */ 1210 #define HW_ATL_RPF_ET_RXQFEN_SHIFT 29 1211 /* width of bitfield et_rxq{f}_en */ 1212 #define HW_ATL_RPF_ET_RXQFEN_WIDTH 1 1213 /* default value of bitfield et_rxq{f}_en */ 1214 #define HW_ATL_RPF_ET_RXQFEN_DEFAULT 0x0 1215 1216 /* rx et_up{f}[2:0] bitfield definitions 1217 * preprocessor definitions for the bitfield "et_up{f}[2:0]". 1218 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1219 * port="pif_rpf_et_up0_i[2:0]" 1220 */ 1221 1222 /* register address for bitfield et_up{f}[2:0] */ 1223 #define HW_ATL_RPF_ET_UPF_ADR(filter) (0x00005300 + (filter) * 0x4) 1224 /* bitmask for bitfield et_up{f}[2:0] */ 1225 #define HW_ATL_RPF_ET_UPF_MSK 0x1c000000 1226 /* inverted bitmask for bitfield et_up{f}[2:0] */ 1227 #define HW_ATL_RPF_ET_UPF_MSKN 0xe3ffffff 1228 /* lower bit position of bitfield et_up{f}[2:0] */ 1229 #define HW_ATL_RPF_ET_UPF_SHIFT 26 1230 /* width of bitfield et_up{f}[2:0] */ 1231 #define HW_ATL_RPF_ET_UPF_WIDTH 3 1232 /* default value of bitfield et_up{f}[2:0] */ 1233 #define HW_ATL_RPF_ET_UPF_DEFAULT 0x0 1234 1235 /* rx et_rxq{f}[4:0] bitfield definitions 1236 * preprocessor definitions for the bitfield "et_rxq{f}[4:0]". 1237 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1238 * port="pif_rpf_et_rxq0_i[4:0]" 1239 */ 1240 1241 /* register address for bitfield et_rxq{f}[4:0] */ 1242 #define HW_ATL_RPF_ET_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) 1243 /* bitmask for bitfield et_rxq{f}[4:0] */ 1244 #define HW_ATL_RPF_ET_RXQF_MSK 0x01f00000 1245 /* inverted bitmask for bitfield et_rxq{f}[4:0] */ 1246 #define HW_ATL_RPF_ET_RXQF_MSKN 0xfe0fffff 1247 /* lower bit position of bitfield et_rxq{f}[4:0] */ 1248 #define HW_ATL_RPF_ET_RXQF_SHIFT 20 1249 /* width of bitfield et_rxq{f}[4:0] */ 1250 #define HW_ATL_RPF_ET_RXQF_WIDTH 5 1251 /* default value of bitfield et_rxq{f}[4:0] */ 1252 #define HW_ATL_RPF_ET_RXQF_DEFAULT 0x0 1253 1254 /* rx et_mng_rxq{f} bitfield definitions 1255 * preprocessor definitions for the bitfield "et_mng_rxq{f}". 1256 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1257 * port="pif_rpf_et_mng_rxq_i[0]" 1258 */ 1259 1260 /* register address for bitfield et_mng_rxq{f} */ 1261 #define HW_ATL_RPF_ET_MNG_RXQF_ADR(filter) (0x00005300 + (filter) * 0x4) 1262 /* bitmask for bitfield et_mng_rxq{f} */ 1263 #define HW_ATL_RPF_ET_MNG_RXQF_MSK 0x00080000 1264 /* inverted bitmask for bitfield et_mng_rxq{f} */ 1265 #define HW_ATL_RPF_ET_MNG_RXQF_MSKN 0xfff7ffff 1266 /* lower bit position of bitfield et_mng_rxq{f} */ 1267 #define HW_ATL_RPF_ET_MNG_RXQF_SHIFT 19 1268 /* width of bitfield et_mng_rxq{f} */ 1269 #define HW_ATL_RPF_ET_MNG_RXQF_WIDTH 1 1270 /* default value of bitfield et_mng_rxq{f} */ 1271 #define HW_ATL_RPF_ET_MNG_RXQF_DEFAULT 0x0 1272 1273 /* rx et_act{f}[2:0] bitfield definitions 1274 * preprocessor definitions for the bitfield "et_act{f}[2:0]". 1275 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1276 * port="pif_rpf_et_act0_i[2:0]" 1277 */ 1278 1279 /* register address for bitfield et_act{f}[2:0] */ 1280 #define HW_ATL_RPF_ET_ACTF_ADR(filter) (0x00005300 + (filter) * 0x4) 1281 /* bitmask for bitfield et_act{f}[2:0] */ 1282 #define HW_ATL_RPF_ET_ACTF_MSK 0x00070000 1283 /* inverted bitmask for bitfield et_act{f}[2:0] */ 1284 #define HW_ATL_RPF_ET_ACTF_MSKN 0xfff8ffff 1285 /* lower bit position of bitfield et_act{f}[2:0] */ 1286 #define HW_ATL_RPF_ET_ACTF_SHIFT 16 1287 /* width of bitfield et_act{f}[2:0] */ 1288 #define HW_ATL_RPF_ET_ACTF_WIDTH 3 1289 /* default value of bitfield et_act{f}[2:0] */ 1290 #define HW_ATL_RPF_ET_ACTF_DEFAULT 0x0 1291 1292 /* rx et_val{f}[f:0] bitfield definitions 1293 * preprocessor definitions for the bitfield "et_val{f}[f:0]". 1294 * parameter: filter {f} | stride size 0x4 | range [0, 15] 1295 * port="pif_rpf_et_val0_i[15:0]" 1296 */ 1297 1298 /* register address for bitfield et_val{f}[f:0] */ 1299 #define HW_ATL_RPF_ET_VALF_ADR(filter) (0x00005300 + (filter) * 0x4) 1300 /* bitmask for bitfield et_val{f}[f:0] */ 1301 #define HW_ATL_RPF_ET_VALF_MSK 0x0000ffff 1302 /* inverted bitmask for bitfield et_val{f}[f:0] */ 1303 #define HW_ATL_RPF_ET_VALF_MSKN 0xffff0000 1304 /* lower bit position of bitfield et_val{f}[f:0] */ 1305 #define HW_ATL_RPF_ET_VALF_SHIFT 0 1306 /* width of bitfield et_val{f}[f:0] */ 1307 #define HW_ATL_RPF_ET_VALF_WIDTH 16 1308 /* default value of bitfield et_val{f}[f:0] */ 1309 #define HW_ATL_RPF_ET_VALF_DEFAULT 0x0 1310 1311 /* RX l4_sp{D}[F:0] Bitfield Definitions 1312 * Preprocessor definitions for the bitfield "l4_sp{D}[F:0]". 1313 * Parameter: srcport {D} | stride size 0x4 | range [0, 7] 1314 * PORT="pif_rpf_l4_sp0_i[15:0]" 1315 */ 1316 1317 /* Register address for bitfield l4_sp{D}[F:0] */ 1318 #define HW_ATL_RPF_L4_SPD_ADR(srcport) (0x00005400u + (srcport) * 0x4) 1319 /* Bitmask for bitfield l4_sp{D}[F:0] */ 1320 #define HW_ATL_RPF_L4_SPD_MSK 0x0000FFFFu 1321 /* Inverted bitmask for bitfield l4_sp{D}[F:0] */ 1322 #define HW_ATL_RPF_L4_SPD_MSKN 0xFFFF0000u 1323 /* Lower bit position of bitfield l4_sp{D}[F:0] */ 1324 #define HW_ATL_RPF_L4_SPD_SHIFT 0 1325 /* Width of bitfield l4_sp{D}[F:0] */ 1326 #define HW_ATL_RPF_L4_SPD_WIDTH 16 1327 /* Default value of bitfield l4_sp{D}[F:0] */ 1328 #define HW_ATL_RPF_L4_SPD_DEFAULT 0x0 1329 1330 /* RX l4_dp{D}[F:0] Bitfield Definitions 1331 * Preprocessor definitions for the bitfield "l4_dp{D}[F:0]". 1332 * Parameter: destport {D} | stride size 0x4 | range [0, 7] 1333 * PORT="pif_rpf_l4_dp0_i[15:0]" 1334 */ 1335 1336 /* Register address for bitfield l4_dp{D}[F:0] */ 1337 #define HW_ATL_RPF_L4_DPD_ADR(destport) (0x00005420u + (destport) * 0x4) 1338 /* Bitmask for bitfield l4_dp{D}[F:0] */ 1339 #define HW_ATL_RPF_L4_DPD_MSK 0x0000FFFFu 1340 /* Inverted bitmask for bitfield l4_dp{D}[F:0] */ 1341 #define HW_ATL_RPF_L4_DPD_MSKN 0xFFFF0000u 1342 /* Lower bit position of bitfield l4_dp{D}[F:0] */ 1343 #define HW_ATL_RPF_L4_DPD_SHIFT 0 1344 /* Width of bitfield l4_dp{D}[F:0] */ 1345 #define HW_ATL_RPF_L4_DPD_WIDTH 16 1346 /* Default value of bitfield l4_dp{D}[F:0] */ 1347 #define HW_ATL_RPF_L4_DPD_DEFAULT 0x0 1348 1349 /* rx ipv4_chk_en bitfield definitions 1350 * preprocessor definitions for the bitfield "ipv4_chk_en". 1351 * port="pif_rpo_ipv4_chk_en_i" 1352 */ 1353 1354 /* register address for bitfield ipv4_chk_en */ 1355 #define HW_ATL_RPO_IPV4CHK_EN_ADR 0x00005580 1356 /* bitmask for bitfield ipv4_chk_en */ 1357 #define HW_ATL_RPO_IPV4CHK_EN_MSK 0x00000002 1358 /* inverted bitmask for bitfield ipv4_chk_en */ 1359 #define HW_ATL_RPO_IPV4CHK_EN_MSKN 0xfffffffd 1360 /* lower bit position of bitfield ipv4_chk_en */ 1361 #define HW_ATL_RPO_IPV4CHK_EN_SHIFT 1 1362 /* width of bitfield ipv4_chk_en */ 1363 #define HW_ATL_RPO_IPV4CHK_EN_WIDTH 1 1364 /* default value of bitfield ipv4_chk_en */ 1365 #define HW_ATL_RPO_IPV4CHK_EN_DEFAULT 0x0 1366 1367 /* rx desc{d}_vl_strip bitfield definitions 1368 * preprocessor definitions for the bitfield "desc{d}_vl_strip". 1369 * parameter: descriptor {d} | stride size 0x20 | range [0, 31] 1370 * port="pif_rpo_desc_vl_strip_i[0]" 1371 */ 1372 1373 /* register address for bitfield desc{d}_vl_strip */ 1374 #define HW_ATL_RPO_DESCDVL_STRIP_ADR(descriptor) \ 1375 (0x00005b08 + (descriptor) * 0x20) 1376 /* bitmask for bitfield desc{d}_vl_strip */ 1377 #define HW_ATL_RPO_DESCDVL_STRIP_MSK 0x20000000 1378 /* inverted bitmask for bitfield desc{d}_vl_strip */ 1379 #define HW_ATL_RPO_DESCDVL_STRIP_MSKN 0xdfffffff 1380 /* lower bit position of bitfield desc{d}_vl_strip */ 1381 #define HW_ATL_RPO_DESCDVL_STRIP_SHIFT 29 1382 /* width of bitfield desc{d}_vl_strip */ 1383 #define HW_ATL_RPO_DESCDVL_STRIP_WIDTH 1 1384 /* default value of bitfield desc{d}_vl_strip */ 1385 #define HW_ATL_RPO_DESCDVL_STRIP_DEFAULT 0x0 1386 1387 /* rx l4_chk_en bitfield definitions 1388 * preprocessor definitions for the bitfield "l4_chk_en". 1389 * port="pif_rpo_l4_chk_en_i" 1390 */ 1391 1392 /* register address for bitfield l4_chk_en */ 1393 #define HW_ATL_RPOL4CHK_EN_ADR 0x00005580 1394 /* bitmask for bitfield l4_chk_en */ 1395 #define HW_ATL_RPOL4CHK_EN_MSK 0x00000001 1396 /* inverted bitmask for bitfield l4_chk_en */ 1397 #define HW_ATL_RPOL4CHK_EN_MSKN 0xfffffffe 1398 /* lower bit position of bitfield l4_chk_en */ 1399 #define HW_ATL_RPOL4CHK_EN_SHIFT 0 1400 /* width of bitfield l4_chk_en */ 1401 #define HW_ATL_RPOL4CHK_EN_WIDTH 1 1402 /* default value of bitfield l4_chk_en */ 1403 #define HW_ATL_RPOL4CHK_EN_DEFAULT 0x0 1404 1405 /* RX outer_vl_ins_mode Bitfield Definitions 1406 * Preprocessor definitions for the bitfield "outer_vl_ins_mode". 1407 * PORT="pif_rpo_outer_vl_mode_i" 1408 */ 1409 1410 /* Register address for bitfield outer_vl_ins_mode */ 1411 #define HW_ATL_RPO_OUTER_VL_INS_MODE_ADR 0x00005580 1412 /* Bitmask for bitfield outer_vl_ins_mode */ 1413 #define HW_ATL_RPO_OUTER_VL_INS_MODE_MSK 0x00000004 1414 /* Inverted bitmask for bitfield outer_vl_ins_mode */ 1415 #define HW_ATL_RPO_OUTER_VL_INS_MODE_MSKN 0xFFFFFFFB 1416 /* Lower bit position of bitfield outer_vl_ins_mode */ 1417 #define HW_ATL_RPO_OUTER_VL_INS_MODE_SHIFT 2 1418 /* Width of bitfield outer_vl_ins_mode */ 1419 #define HW_ATL_RPO_OUTER_VL_INS_MODE_WIDTH 1 1420 /* Default value of bitfield outer_vl_ins_mode */ 1421 #define HW_ATL_RPO_OUTER_VL_INS_MODE_DEFAULT 0x0 1422 1423 /* rx reg_res_dsbl bitfield definitions 1424 * preprocessor definitions for the bitfield "reg_res_dsbl". 1425 * port="pif_rx_reg_res_dsbl_i" 1426 */ 1427 1428 /* register address for bitfield reg_res_dsbl */ 1429 #define HW_ATL_RX_REG_RES_DSBL_ADR 0x00005000 1430 /* bitmask for bitfield reg_res_dsbl */ 1431 #define HW_ATL_RX_REG_RES_DSBL_MSK 0x20000000 1432 /* inverted bitmask for bitfield reg_res_dsbl */ 1433 #define HW_ATL_RX_REG_RES_DSBL_MSKN 0xdfffffff 1434 /* lower bit position of bitfield reg_res_dsbl */ 1435 #define HW_ATL_RX_REG_RES_DSBL_SHIFT 29 1436 /* width of bitfield reg_res_dsbl */ 1437 #define HW_ATL_RX_REG_RES_DSBL_WIDTH 1 1438 /* default value of bitfield reg_res_dsbl */ 1439 #define HW_ATL_RX_REG_RES_DSBL_DEFAULT 0x1 1440 1441 /* tx dca{d}_cpuid[7:0] bitfield definitions 1442 * preprocessor definitions for the bitfield "dca{d}_cpuid[7:0]". 1443 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1444 * port="pif_tdm_dca0_cpuid_i[7:0]" 1445 */ 1446 1447 /* register address for bitfield dca{d}_cpuid[7:0] */ 1448 #define HW_ATL_TDM_DCADCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) 1449 /* bitmask for bitfield dca{d}_cpuid[7:0] */ 1450 #define HW_ATL_TDM_DCADCPUID_MSK 0x000000ff 1451 /* inverted bitmask for bitfield dca{d}_cpuid[7:0] */ 1452 #define HW_ATL_TDM_DCADCPUID_MSKN 0xffffff00 1453 /* lower bit position of bitfield dca{d}_cpuid[7:0] */ 1454 #define HW_ATL_TDM_DCADCPUID_SHIFT 0 1455 /* width of bitfield dca{d}_cpuid[7:0] */ 1456 #define HW_ATL_TDM_DCADCPUID_WIDTH 8 1457 /* default value of bitfield dca{d}_cpuid[7:0] */ 1458 #define HW_ATL_TDM_DCADCPUID_DEFAULT 0x0 1459 1460 /* tx lso_en[1f:0] bitfield definitions 1461 * preprocessor definitions for the bitfield "lso_en[1f:0]". 1462 * port="pif_tdm_lso_en_i[31:0]" 1463 */ 1464 1465 /* register address for bitfield lso_en[1f:0] */ 1466 #define HW_ATL_TDM_LSO_EN_ADR 0x00007810 1467 /* bitmask for bitfield lso_en[1f:0] */ 1468 #define HW_ATL_TDM_LSO_EN_MSK 0xffffffff 1469 /* inverted bitmask for bitfield lso_en[1f:0] */ 1470 #define HW_ATL_TDM_LSO_EN_MSKN 0x00000000 1471 /* lower bit position of bitfield lso_en[1f:0] */ 1472 #define HW_ATL_TDM_LSO_EN_SHIFT 0 1473 /* width of bitfield lso_en[1f:0] */ 1474 #define HW_ATL_TDM_LSO_EN_WIDTH 32 1475 /* default value of bitfield lso_en[1f:0] */ 1476 #define HW_ATL_TDM_LSO_EN_DEFAULT 0x0 1477 1478 /* tx dca_en bitfield definitions 1479 * preprocessor definitions for the bitfield "dca_en". 1480 * port="pif_tdm_dca_en_i" 1481 */ 1482 1483 /* register address for bitfield dca_en */ 1484 #define HW_ATL_TDM_DCA_EN_ADR 0x00008480 1485 /* bitmask for bitfield dca_en */ 1486 #define HW_ATL_TDM_DCA_EN_MSK 0x80000000 1487 /* inverted bitmask for bitfield dca_en */ 1488 #define HW_ATL_TDM_DCA_EN_MSKN 0x7fffffff 1489 /* lower bit position of bitfield dca_en */ 1490 #define HW_ATL_TDM_DCA_EN_SHIFT 31 1491 /* width of bitfield dca_en */ 1492 #define HW_ATL_TDM_DCA_EN_WIDTH 1 1493 /* default value of bitfield dca_en */ 1494 #define HW_ATL_TDM_DCA_EN_DEFAULT 0x1 1495 1496 /* tx dca_mode[3:0] bitfield definitions 1497 * preprocessor definitions for the bitfield "dca_mode[3:0]". 1498 * port="pif_tdm_dca_mode_i[3:0]" 1499 */ 1500 1501 /* register address for bitfield dca_mode[3:0] */ 1502 #define HW_ATL_TDM_DCA_MODE_ADR 0x00008480 1503 /* bitmask for bitfield dca_mode[3:0] */ 1504 #define HW_ATL_TDM_DCA_MODE_MSK 0x0000000f 1505 /* inverted bitmask for bitfield dca_mode[3:0] */ 1506 #define HW_ATL_TDM_DCA_MODE_MSKN 0xfffffff0 1507 /* lower bit position of bitfield dca_mode[3:0] */ 1508 #define HW_ATL_TDM_DCA_MODE_SHIFT 0 1509 /* width of bitfield dca_mode[3:0] */ 1510 #define HW_ATL_TDM_DCA_MODE_WIDTH 4 1511 /* default value of bitfield dca_mode[3:0] */ 1512 #define HW_ATL_TDM_DCA_MODE_DEFAULT 0x0 1513 1514 /* tx dca{d}_desc_en bitfield definitions 1515 * preprocessor definitions for the bitfield "dca{d}_desc_en". 1516 * parameter: dca {d} | stride size 0x4 | range [0, 31] 1517 * port="pif_tdm_dca_desc_en_i[0]" 1518 */ 1519 1520 /* register address for bitfield dca{d}_desc_en */ 1521 #define HW_ATL_TDM_DCADDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) 1522 /* bitmask for bitfield dca{d}_desc_en */ 1523 #define HW_ATL_TDM_DCADDESC_EN_MSK 0x80000000 1524 /* inverted bitmask for bitfield dca{d}_desc_en */ 1525 #define HW_ATL_TDM_DCADDESC_EN_MSKN 0x7fffffff 1526 /* lower bit position of bitfield dca{d}_desc_en */ 1527 #define HW_ATL_TDM_DCADDESC_EN_SHIFT 31 1528 /* width of bitfield dca{d}_desc_en */ 1529 #define HW_ATL_TDM_DCADDESC_EN_WIDTH 1 1530 /* default value of bitfield dca{d}_desc_en */ 1531 #define HW_ATL_TDM_DCADDESC_EN_DEFAULT 0x0 1532 1533 /* tx desc{d}_en bitfield definitions 1534 * preprocessor definitions for the bitfield "desc{d}_en". 1535 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1536 * port="pif_tdm_desc_en_i[0]" 1537 */ 1538 1539 /* register address for bitfield desc{d}_en */ 1540 #define HW_ATL_TDM_DESCDEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) 1541 /* bitmask for bitfield desc{d}_en */ 1542 #define HW_ATL_TDM_DESCDEN_MSK 0x80000000 1543 /* inverted bitmask for bitfield desc{d}_en */ 1544 #define HW_ATL_TDM_DESCDEN_MSKN 0x7fffffff 1545 /* lower bit position of bitfield desc{d}_en */ 1546 #define HW_ATL_TDM_DESCDEN_SHIFT 31 1547 /* width of bitfield desc{d}_en */ 1548 #define HW_ATL_TDM_DESCDEN_WIDTH 1 1549 /* default value of bitfield desc{d}_en */ 1550 #define HW_ATL_TDM_DESCDEN_DEFAULT 0x0 1551 1552 /* tx desc{d}_hd[c:0] bitfield definitions 1553 * preprocessor definitions for the bitfield "desc{d}_hd[c:0]". 1554 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1555 * port="tdm_pif_desc0_hd_o[12:0]" 1556 */ 1557 1558 /* register address for bitfield desc{d}_hd[c:0] */ 1559 #define HW_ATL_TDM_DESCDHD_ADR(descriptor) (0x00007c0c + (descriptor) * 0x40) 1560 /* bitmask for bitfield desc{d}_hd[c:0] */ 1561 #define HW_ATL_TDM_DESCDHD_MSK 0x00001fff 1562 /* inverted bitmask for bitfield desc{d}_hd[c:0] */ 1563 #define HW_ATL_TDM_DESCDHD_MSKN 0xffffe000 1564 /* lower bit position of bitfield desc{d}_hd[c:0] */ 1565 #define HW_ATL_TDM_DESCDHD_SHIFT 0 1566 /* width of bitfield desc{d}_hd[c:0] */ 1567 #define HW_ATL_TDM_DESCDHD_WIDTH 13 1568 1569 /* tx desc{d}_len[9:0] bitfield definitions 1570 * preprocessor definitions for the bitfield "desc{d}_len[9:0]". 1571 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1572 * port="pif_tdm_desc0_len_i[9:0]" 1573 */ 1574 1575 /* register address for bitfield desc{d}_len[9:0] */ 1576 #define HW_ATL_TDM_DESCDLEN_ADR(descriptor) (0x00007c08 + (descriptor) * 0x40) 1577 /* bitmask for bitfield desc{d}_len[9:0] */ 1578 #define HW_ATL_TDM_DESCDLEN_MSK 0x00001ff8 1579 /* inverted bitmask for bitfield desc{d}_len[9:0] */ 1580 #define HW_ATL_TDM_DESCDLEN_MSKN 0xffffe007 1581 /* lower bit position of bitfield desc{d}_len[9:0] */ 1582 #define HW_ATL_TDM_DESCDLEN_SHIFT 3 1583 /* width of bitfield desc{d}_len[9:0] */ 1584 #define HW_ATL_TDM_DESCDLEN_WIDTH 10 1585 /* default value of bitfield desc{d}_len[9:0] */ 1586 #define HW_ATL_TDM_DESCDLEN_DEFAULT 0x0 1587 1588 /* tx int_desc_wrb_en bitfield definitions 1589 * preprocessor definitions for the bitfield "int_desc_wrb_en". 1590 * port="pif_tdm_int_desc_wrb_en_i" 1591 */ 1592 1593 /* register address for bitfield int_desc_wrb_en */ 1594 #define HW_ATL_TDM_INT_DESC_WRB_EN_ADR 0x00007b40 1595 /* bitmask for bitfield int_desc_wrb_en */ 1596 #define HW_ATL_TDM_INT_DESC_WRB_EN_MSK 0x00000002 1597 /* inverted bitmask for bitfield int_desc_wrb_en */ 1598 #define HW_ATL_TDM_INT_DESC_WRB_EN_MSKN 0xfffffffd 1599 /* lower bit position of bitfield int_desc_wrb_en */ 1600 #define HW_ATL_TDM_INT_DESC_WRB_EN_SHIFT 1 1601 /* width of bitfield int_desc_wrb_en */ 1602 #define HW_ATL_TDM_INT_DESC_WRB_EN_WIDTH 1 1603 /* default value of bitfield int_desc_wrb_en */ 1604 #define HW_ATL_TDM_INT_DESC_WRB_EN_DEFAULT 0x0 1605 1606 /* tx desc{d}_wrb_thresh[6:0] bitfield definitions 1607 * preprocessor definitions for the bitfield "desc{d}_wrb_thresh[6:0]". 1608 * parameter: descriptor {d} | stride size 0x40 | range [0, 31] 1609 * port="pif_tdm_desc0_wrb_thresh_i[6:0]" 1610 */ 1611 1612 /* register address for bitfield desc{d}_wrb_thresh[6:0] */ 1613 #define HW_ATL_TDM_DESCDWRB_THRESH_ADR(descriptor) \ 1614 (0x00007c18 + (descriptor) * 0x40) 1615 /* bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1616 #define HW_ATL_TDM_DESCDWRB_THRESH_MSK 0x00007f00 1617 /* inverted bitmask for bitfield desc{d}_wrb_thresh[6:0] */ 1618 #define HW_ATL_TDM_DESCDWRB_THRESH_MSKN 0xffff80ff 1619 /* lower bit position of bitfield desc{d}_wrb_thresh[6:0] */ 1620 #define HW_ATL_TDM_DESCDWRB_THRESH_SHIFT 8 1621 /* width of bitfield desc{d}_wrb_thresh[6:0] */ 1622 #define HW_ATL_TDM_DESCDWRB_THRESH_WIDTH 7 1623 /* default value of bitfield desc{d}_wrb_thresh[6:0] */ 1624 #define HW_ATL_TDM_DESCDWRB_THRESH_DEFAULT 0x0 1625 1626 /* tx lso_tcp_flag_first[b:0] bitfield definitions 1627 * preprocessor definitions for the bitfield "lso_tcp_flag_first[b:0]". 1628 * port="pif_thm_lso_tcp_flag_first_i[11:0]" 1629 */ 1630 1631 /* register address for bitfield lso_tcp_flag_first[b:0] */ 1632 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_ADR 0x00007820 1633 /* bitmask for bitfield lso_tcp_flag_first[b:0] */ 1634 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSK 0x00000fff 1635 /* inverted bitmask for bitfield lso_tcp_flag_first[b:0] */ 1636 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_MSKN 0xfffff000 1637 /* lower bit position of bitfield lso_tcp_flag_first[b:0] */ 1638 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_SHIFT 0 1639 /* width of bitfield lso_tcp_flag_first[b:0] */ 1640 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_WIDTH 12 1641 /* default value of bitfield lso_tcp_flag_first[b:0] */ 1642 #define HW_ATL_THM_LSO_TCP_FLAG_FIRST_DEFAULT 0x0 1643 1644 /* tx lso_tcp_flag_last[b:0] bitfield definitions 1645 * preprocessor definitions for the bitfield "lso_tcp_flag_last[b:0]". 1646 * port="pif_thm_lso_tcp_flag_last_i[11:0]" 1647 */ 1648 1649 /* register address for bitfield lso_tcp_flag_last[b:0] */ 1650 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_ADR 0x00007824 1651 /* bitmask for bitfield lso_tcp_flag_last[b:0] */ 1652 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSK 0x00000fff 1653 /* inverted bitmask for bitfield lso_tcp_flag_last[b:0] */ 1654 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_MSKN 0xfffff000 1655 /* lower bit position of bitfield lso_tcp_flag_last[b:0] */ 1656 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_SHIFT 0 1657 /* width of bitfield lso_tcp_flag_last[b:0] */ 1658 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_WIDTH 12 1659 /* default value of bitfield lso_tcp_flag_last[b:0] */ 1660 #define HW_ATL_THM_LSO_TCP_FLAG_LAST_DEFAULT 0x0 1661 1662 /* tx lso_tcp_flag_mid[b:0] bitfield definitions 1663 * preprocessor definitions for the bitfield "lso_tcp_flag_mid[b:0]". 1664 * port="pif_thm_lso_tcp_flag_mid_i[11:0]" 1665 */ 1666 1667 /* Register address for bitfield lro_rsc_max[1F:0] */ 1668 #define HW_ATL_RPO_LRO_RSC_MAX_ADR 0x00005598 1669 /* Bitmask for bitfield lro_rsc_max[1F:0] */ 1670 #define HW_ATL_RPO_LRO_RSC_MAX_MSK 0xFFFFFFFF 1671 /* Inverted bitmask for bitfield lro_rsc_max[1F:0] */ 1672 #define HW_ATL_RPO_LRO_RSC_MAX_MSKN 0x00000000 1673 /* Lower bit position of bitfield lro_rsc_max[1F:0] */ 1674 #define HW_ATL_RPO_LRO_RSC_MAX_SHIFT 0 1675 /* Width of bitfield lro_rsc_max[1F:0] */ 1676 #define HW_ATL_RPO_LRO_RSC_MAX_WIDTH 32 1677 /* Default value of bitfield lro_rsc_max[1F:0] */ 1678 #define HW_ATL_RPO_LRO_RSC_MAX_DEFAULT 0x0 1679 1680 /* RX lro_en[1F:0] Bitfield Definitions 1681 * Preprocessor definitions for the bitfield "lro_en[1F:0]". 1682 * PORT="pif_rpo_lro_en_i[31:0]" 1683 */ 1684 1685 /* Register address for bitfield lro_en[1F:0] */ 1686 #define HW_ATL_RPO_LRO_EN_ADR 0x00005590 1687 /* Bitmask for bitfield lro_en[1F:0] */ 1688 #define HW_ATL_RPO_LRO_EN_MSK 0xFFFFFFFF 1689 /* Inverted bitmask for bitfield lro_en[1F:0] */ 1690 #define HW_ATL_RPO_LRO_EN_MSKN 0x00000000 1691 /* Lower bit position of bitfield lro_en[1F:0] */ 1692 #define HW_ATL_RPO_LRO_EN_SHIFT 0 1693 /* Width of bitfield lro_en[1F:0] */ 1694 #define HW_ATL_RPO_LRO_EN_WIDTH 32 1695 /* Default value of bitfield lro_en[1F:0] */ 1696 #define HW_ATL_RPO_LRO_EN_DEFAULT 0x0 1697 1698 /* RX lro_ptopt_en Bitfield Definitions 1699 * Preprocessor definitions for the bitfield "lro_ptopt_en". 1700 * PORT="pif_rpo_lro_ptopt_en_i" 1701 */ 1702 1703 /* Register address for bitfield lro_ptopt_en */ 1704 #define HW_ATL_RPO_LRO_PTOPT_EN_ADR 0x00005594 1705 /* Bitmask for bitfield lro_ptopt_en */ 1706 #define HW_ATL_RPO_LRO_PTOPT_EN_MSK 0x00008000 1707 /* Inverted bitmask for bitfield lro_ptopt_en */ 1708 #define HW_ATL_RPO_LRO_PTOPT_EN_MSKN 0xFFFF7FFF 1709 /* Lower bit position of bitfield lro_ptopt_en */ 1710 #define HW_ATL_RPO_LRO_PTOPT_EN_SHIFT 15 1711 /* Width of bitfield lro_ptopt_en */ 1712 #define HW_ATL_RPO_LRO_PTOPT_EN_WIDTH 1 1713 /* Default value of bitfield lro_ptopt_en */ 1714 #define HW_ATL_RPO_LRO_PTOPT_EN_DEFALT 0x1 1715 1716 /* RX lro_q_ses_lmt Bitfield Definitions 1717 * Preprocessor definitions for the bitfield "lro_q_ses_lmt". 1718 * PORT="pif_rpo_lro_q_ses_lmt_i[1:0]" 1719 */ 1720 1721 /* Register address for bitfield lro_q_ses_lmt */ 1722 #define HW_ATL_RPO_LRO_QSES_LMT_ADR 0x00005594 1723 /* Bitmask for bitfield lro_q_ses_lmt */ 1724 #define HW_ATL_RPO_LRO_QSES_LMT_MSK 0x00003000 1725 /* Inverted bitmask for bitfield lro_q_ses_lmt */ 1726 #define HW_ATL_RPO_LRO_QSES_LMT_MSKN 0xFFFFCFFF 1727 /* Lower bit position of bitfield lro_q_ses_lmt */ 1728 #define HW_ATL_RPO_LRO_QSES_LMT_SHIFT 12 1729 /* Width of bitfield lro_q_ses_lmt */ 1730 #define HW_ATL_RPO_LRO_QSES_LMT_WIDTH 2 1731 /* Default value of bitfield lro_q_ses_lmt */ 1732 #define HW_ATL_RPO_LRO_QSES_LMT_DEFAULT 0x1 1733 1734 /* RX lro_tot_dsc_lmt[1:0] Bitfield Definitions 1735 * Preprocessor definitions for the bitfield "lro_tot_dsc_lmt[1:0]". 1736 * PORT="pif_rpo_lro_tot_dsc_lmt_i[1:0]" 1737 */ 1738 1739 /* Register address for bitfield lro_tot_dsc_lmt[1:0] */ 1740 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_ADR 0x00005594 1741 /* Bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1742 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSK 0x00000060 1743 /* Inverted bitmask for bitfield lro_tot_dsc_lmt[1:0] */ 1744 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_MSKN 0xFFFFFF9F 1745 /* Lower bit position of bitfield lro_tot_dsc_lmt[1:0] */ 1746 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_SHIFT 5 1747 /* Width of bitfield lro_tot_dsc_lmt[1:0] */ 1748 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_WIDTH 2 1749 /* Default value of bitfield lro_tot_dsc_lmt[1:0] */ 1750 #define HW_ATL_RPO_LRO_TOT_DSC_LMT_DEFALT 0x1 1751 1752 /* RX lro_pkt_min[4:0] Bitfield Definitions 1753 * Preprocessor definitions for the bitfield "lro_pkt_min[4:0]". 1754 * PORT="pif_rpo_lro_pkt_min_i[4:0]" 1755 */ 1756 1757 /* Register address for bitfield lro_pkt_min[4:0] */ 1758 #define HW_ATL_RPO_LRO_PKT_MIN_ADR 0x00005594 1759 /* Bitmask for bitfield lro_pkt_min[4:0] */ 1760 #define HW_ATL_RPO_LRO_PKT_MIN_MSK 0x0000001F 1761 /* Inverted bitmask for bitfield lro_pkt_min[4:0] */ 1762 #define HW_ATL_RPO_LRO_PKT_MIN_MSKN 0xFFFFFFE0 1763 /* Lower bit position of bitfield lro_pkt_min[4:0] */ 1764 #define HW_ATL_RPO_LRO_PKT_MIN_SHIFT 0 1765 /* Width of bitfield lro_pkt_min[4:0] */ 1766 #define HW_ATL_RPO_LRO_PKT_MIN_WIDTH 5 1767 /* Default value of bitfield lro_pkt_min[4:0] */ 1768 #define HW_ATL_RPO_LRO_PKT_MIN_DEFAULT 0x8 1769 1770 /* Width of bitfield lro{L}_des_max[1:0] */ 1771 #define HW_ATL_RPO_LRO_LDES_MAX_WIDTH 2 1772 /* Default value of bitfield lro{L}_des_max[1:0] */ 1773 #define HW_ATL_RPO_LRO_LDES_MAX_DEFAULT 0x0 1774 1775 /* RX lro_tb_div[11:0] Bitfield Definitions 1776 * Preprocessor definitions for the bitfield "lro_tb_div[11:0]". 1777 * PORT="pif_rpo_lro_tb_div_i[11:0]" 1778 */ 1779 1780 /* Register address for bitfield lro_tb_div[11:0] */ 1781 #define HW_ATL_RPO_LRO_TB_DIV_ADR 0x00005620 1782 /* Bitmask for bitfield lro_tb_div[11:0] */ 1783 #define HW_ATL_RPO_LRO_TB_DIV_MSK 0xFFF00000 1784 /* Inverted bitmask for bitfield lro_tb_div[11:0] */ 1785 #define HW_ATL_RPO_LRO_TB_DIV_MSKN 0x000FFFFF 1786 /* Lower bit position of bitfield lro_tb_div[11:0] */ 1787 #define HW_ATL_RPO_LRO_TB_DIV_SHIFT 20 1788 /* Width of bitfield lro_tb_div[11:0] */ 1789 #define HW_ATL_RPO_LRO_TB_DIV_WIDTH 12 1790 /* Default value of bitfield lro_tb_div[11:0] */ 1791 #define HW_ATL_RPO_LRO_TB_DIV_DEFAULT 0xC35 1792 1793 /* RX lro_ina_ival[9:0] Bitfield Definitions 1794 * Preprocessor definitions for the bitfield "lro_ina_ival[9:0]". 1795 * PORT="pif_rpo_lro_ina_ival_i[9:0]" 1796 */ 1797 1798 /* Register address for bitfield lro_ina_ival[9:0] */ 1799 #define HW_ATL_RPO_LRO_INA_IVAL_ADR 0x00005620 1800 /* Bitmask for bitfield lro_ina_ival[9:0] */ 1801 #define HW_ATL_RPO_LRO_INA_IVAL_MSK 0x000FFC00 1802 /* Inverted bitmask for bitfield lro_ina_ival[9:0] */ 1803 #define HW_ATL_RPO_LRO_INA_IVAL_MSKN 0xFFF003FF 1804 /* Lower bit position of bitfield lro_ina_ival[9:0] */ 1805 #define HW_ATL_RPO_LRO_INA_IVAL_SHIFT 10 1806 /* Width of bitfield lro_ina_ival[9:0] */ 1807 #define HW_ATL_RPO_LRO_INA_IVAL_WIDTH 10 1808 /* Default value of bitfield lro_ina_ival[9:0] */ 1809 #define HW_ATL_RPO_LRO_INA_IVAL_DEFAULT 0xA 1810 1811 /* RX lro_max_ival[9:0] Bitfield Definitions 1812 * Preprocessor definitions for the bitfield "lro_max_ival[9:0]". 1813 * PORT="pif_rpo_lro_max_ival_i[9:0]" 1814 */ 1815 1816 /* Register address for bitfield lro_max_ival[9:0] */ 1817 #define HW_ATL_RPO_LRO_MAX_IVAL_ADR 0x00005620 1818 /* Bitmask for bitfield lro_max_ival[9:0] */ 1819 #define HW_ATL_RPO_LRO_MAX_IVAL_MSK 0x000003FF 1820 /* Inverted bitmask for bitfield lro_max_ival[9:0] */ 1821 #define HW_ATL_RPO_LRO_MAX_IVAL_MSKN 0xFFFFFC00 1822 /* Lower bit position of bitfield lro_max_ival[9:0] */ 1823 #define HW_ATL_RPO_LRO_MAX_IVAL_SHIFT 0 1824 /* Width of bitfield lro_max_ival[9:0] */ 1825 #define HW_ATL_RPO_LRO_MAX_IVAL_WIDTH 10 1826 /* Default value of bitfield lro_max_ival[9:0] */ 1827 #define HW_ATL_RPO_LRO_MAX_IVAL_DEFAULT 0x19 1828 1829 /* TX dca{D}_cpuid[7:0] Bitfield Definitions 1830 * Preprocessor definitions for the bitfield "dca{D}_cpuid[7:0]". 1831 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1832 * PORT="pif_tdm_dca0_cpuid_i[7:0]" 1833 */ 1834 1835 /* Register address for bitfield dca{D}_cpuid[7:0] */ 1836 #define HW_ATL_TDM_DCA_DCPUID_ADR(dca) (0x00008400 + (dca) * 0x4) 1837 /* Bitmask for bitfield dca{D}_cpuid[7:0] */ 1838 #define HW_ATL_TDM_DCA_DCPUID_MSK 0x000000FF 1839 /* Inverted bitmask for bitfield dca{D}_cpuid[7:0] */ 1840 #define HW_ATL_TDM_DCA_DCPUID_MSKN 0xFFFFFF00 1841 /* Lower bit position of bitfield dca{D}_cpuid[7:0] */ 1842 #define HW_ATL_TDM_DCA_DCPUID_SHIFT 0 1843 /* Width of bitfield dca{D}_cpuid[7:0] */ 1844 #define HW_ATL_TDM_DCA_DCPUID_WIDTH 8 1845 /* Default value of bitfield dca{D}_cpuid[7:0] */ 1846 #define HW_ATL_TDM_DCA_DCPUID_DEFAULT 0x0 1847 1848 /* TX dca{D}_desc_en Bitfield Definitions 1849 * Preprocessor definitions for the bitfield "dca{D}_desc_en". 1850 * Parameter: DCA {D} | stride size 0x4 | range [0, 31] 1851 * PORT="pif_tdm_dca_desc_en_i[0]" 1852 */ 1853 1854 /* Register address for bitfield dca{D}_desc_en */ 1855 #define HW_ATL_TDM_DCA_DDESC_EN_ADR(dca) (0x00008400 + (dca) * 0x4) 1856 /* Bitmask for bitfield dca{D}_desc_en */ 1857 #define HW_ATL_TDM_DCA_DDESC_EN_MSK 0x80000000 1858 /* Inverted bitmask for bitfield dca{D}_desc_en */ 1859 #define HW_ATL_TDM_DCA_DDESC_EN_MSKN 0x7FFFFFFF 1860 /* Lower bit position of bitfield dca{D}_desc_en */ 1861 #define HW_ATL_TDM_DCA_DDESC_EN_SHIFT 31 1862 /* Width of bitfield dca{D}_desc_en */ 1863 #define HW_ATL_TDM_DCA_DDESC_EN_WIDTH 1 1864 /* Default value of bitfield dca{D}_desc_en */ 1865 #define HW_ATL_TDM_DCA_DDESC_EN_DEFAULT 0x0 1866 1867 /* TX desc{D}_en Bitfield Definitions 1868 * Preprocessor definitions for the bitfield "desc{D}_en". 1869 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1870 * PORT="pif_tdm_desc_en_i[0]" 1871 */ 1872 1873 /* Register address for bitfield desc{D}_en */ 1874 #define HW_ATL_TDM_DESC_DEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) 1875 /* Bitmask for bitfield desc{D}_en */ 1876 #define HW_ATL_TDM_DESC_DEN_MSK 0x80000000 1877 /* Inverted bitmask for bitfield desc{D}_en */ 1878 #define HW_ATL_TDM_DESC_DEN_MSKN 0x7FFFFFFF 1879 /* Lower bit position of bitfield desc{D}_en */ 1880 #define HW_ATL_TDM_DESC_DEN_SHIFT 31 1881 /* Width of bitfield desc{D}_en */ 1882 #define HW_ATL_TDM_DESC_DEN_WIDTH 1 1883 /* Default value of bitfield desc{D}_en */ 1884 #define HW_ATL_TDM_DESC_DEN_DEFAULT 0x0 1885 1886 /* TX desc{D}_hd[C:0] Bitfield Definitions 1887 * Preprocessor definitions for the bitfield "desc{D}_hd[C:0]". 1888 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1889 * PORT="tdm_pif_desc0_hd_o[12:0]" 1890 */ 1891 1892 /* Register address for bitfield desc{D}_hd[C:0] */ 1893 #define HW_ATL_TDM_DESC_DHD_ADR(descriptor) (0x00007C0C + (descriptor) * 0x40) 1894 /* Bitmask for bitfield desc{D}_hd[C:0] */ 1895 #define HW_ATL_TDM_DESC_DHD_MSK 0x00001FFF 1896 /* Inverted bitmask for bitfield desc{D}_hd[C:0] */ 1897 #define HW_ATL_TDM_DESC_DHD_MSKN 0xFFFFE000 1898 /* Lower bit position of bitfield desc{D}_hd[C:0] */ 1899 #define HW_ATL_TDM_DESC_DHD_SHIFT 0 1900 /* Width of bitfield desc{D}_hd[C:0] */ 1901 #define HW_ATL_TDM_DESC_DHD_WIDTH 13 1902 1903 /* TX desc{D}_len[9:0] Bitfield Definitions 1904 * Preprocessor definitions for the bitfield "desc{D}_len[9:0]". 1905 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1906 * PORT="pif_tdm_desc0_len_i[9:0]" 1907 */ 1908 1909 /* Register address for bitfield desc{D}_len[9:0] */ 1910 #define HW_ATL_TDM_DESC_DLEN_ADR(descriptor) (0x00007C08 + (descriptor) * 0x40) 1911 /* Bitmask for bitfield desc{D}_len[9:0] */ 1912 #define HW_ATL_TDM_DESC_DLEN_MSK 0x00001FF8 1913 /* Inverted bitmask for bitfield desc{D}_len[9:0] */ 1914 #define HW_ATL_TDM_DESC_DLEN_MSKN 0xFFFFE007 1915 /* Lower bit position of bitfield desc{D}_len[9:0] */ 1916 #define HW_ATL_TDM_DESC_DLEN_SHIFT 3 1917 /* Width of bitfield desc{D}_len[9:0] */ 1918 #define HW_ATL_TDM_DESC_DLEN_WIDTH 10 1919 /* Default value of bitfield desc{D}_len[9:0] */ 1920 #define HW_ATL_TDM_DESC_DLEN_DEFAULT 0x0 1921 1922 /* TX desc{D}_wrb_thresh[6:0] Bitfield Definitions 1923 * Preprocessor definitions for the bitfield "desc{D}_wrb_thresh[6:0]". 1924 * Parameter: descriptor {D} | stride size 0x40 | range [0, 31] 1925 * PORT="pif_tdm_desc0_wrb_thresh_i[6:0]" 1926 */ 1927 1928 /* Register address for bitfield desc{D}_wrb_thresh[6:0] */ 1929 #define HW_ATL_TDM_DESC_DWRB_THRESH_ADR(descriptor) \ 1930 (0x00007C18 + (descriptor) * 0x40) 1931 /* Bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 1932 #define HW_ATL_TDM_DESC_DWRB_THRESH_MSK 0x00007F00 1933 /* Inverted bitmask for bitfield desc{D}_wrb_thresh[6:0] */ 1934 #define HW_ATL_TDM_DESC_DWRB_THRESH_MSKN 0xFFFF80FF 1935 /* Lower bit position of bitfield desc{D}_wrb_thresh[6:0] */ 1936 #define HW_ATL_TDM_DESC_DWRB_THRESH_SHIFT 8 1937 /* Width of bitfield desc{D}_wrb_thresh[6:0] */ 1938 #define HW_ATL_TDM_DESC_DWRB_THRESH_WIDTH 7 1939 /* Default value of bitfield desc{D}_wrb_thresh[6:0] */ 1940 #define HW_ATL_TDM_DESC_DWRB_THRESH_DEFAULT 0x0 1941 1942 /* TX tdm_int_mod_en Bitfield Definitions 1943 * Preprocessor definitions for the bitfield "tdm_int_mod_en". 1944 * PORT="pif_tdm_int_mod_en_i" 1945 */ 1946 1947 /* Register address for bitfield tdm_int_mod_en */ 1948 #define HW_ATL_TDM_INT_MOD_EN_ADR 0x00007B40 1949 /* Bitmask for bitfield tdm_int_mod_en */ 1950 #define HW_ATL_TDM_INT_MOD_EN_MSK 0x00000010 1951 /* Inverted bitmask for bitfield tdm_int_mod_en */ 1952 #define HW_ATL_TDM_INT_MOD_EN_MSKN 0xFFFFFFEF 1953 /* Lower bit position of bitfield tdm_int_mod_en */ 1954 #define HW_ATL_TDM_INT_MOD_EN_SHIFT 4 1955 /* Width of bitfield tdm_int_mod_en */ 1956 #define HW_ATL_TDM_INT_MOD_EN_WIDTH 1 1957 /* Default value of bitfield tdm_int_mod_en */ 1958 #define HW_ATL_TDM_INT_MOD_EN_DEFAULT 0x0 1959 1960 /* TX lso_tcp_flag_mid[B:0] Bitfield Definitions 1961 * Preprocessor definitions for the bitfield "lso_tcp_flag_mid[B:0]". 1962 * PORT="pif_thm_lso_tcp_flag_mid_i[11:0]" 1963 */ 1964 /* register address for bitfield lso_tcp_flag_mid[b:0] */ 1965 #define HW_ATL_THM_LSO_TCP_FLAG_MID_ADR 0x00007820 1966 /* bitmask for bitfield lso_tcp_flag_mid[b:0] */ 1967 #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSK 0x0fff0000 1968 /* inverted bitmask for bitfield lso_tcp_flag_mid[b:0] */ 1969 #define HW_ATL_THM_LSO_TCP_FLAG_MID_MSKN 0xf000ffff 1970 /* lower bit position of bitfield lso_tcp_flag_mid[b:0] */ 1971 #define HW_ATL_THM_LSO_TCP_FLAG_MID_SHIFT 16 1972 /* width of bitfield lso_tcp_flag_mid[b:0] */ 1973 #define HW_ATL_THM_LSO_TCP_FLAG_MID_WIDTH 12 1974 /* default value of bitfield lso_tcp_flag_mid[b:0] */ 1975 #define HW_ATL_THM_LSO_TCP_FLAG_MID_DEFAULT 0x0 1976 1977 /* tx tx_buf_en bitfield definitions 1978 * preprocessor definitions for the bitfield "tx_buf_en". 1979 * port="pif_tpb_tx_buf_en_i" 1980 */ 1981 1982 /* register address for bitfield tx_buf_en */ 1983 #define HW_ATL_TPB_TX_BUF_EN_ADR 0x00007900 1984 /* bitmask for bitfield tx_buf_en */ 1985 #define HW_ATL_TPB_TX_BUF_EN_MSK 0x00000001 1986 /* inverted bitmask for bitfield tx_buf_en */ 1987 #define HW_ATL_TPB_TX_BUF_EN_MSKN 0xfffffffe 1988 /* lower bit position of bitfield tx_buf_en */ 1989 #define HW_ATL_TPB_TX_BUF_EN_SHIFT 0 1990 /* width of bitfield tx_buf_en */ 1991 #define HW_ATL_TPB_TX_BUF_EN_WIDTH 1 1992 /* default value of bitfield tx_buf_en */ 1993 #define HW_ATL_TPB_TX_BUF_EN_DEFAULT 0x0 1994 1995 /* register address for bitfield tx_tc_mode */ 1996 #define HW_ATL_TPB_TX_TC_MODE_ADDR 0x00007900 1997 /* bitmask for bitfield tx_tc_mode */ 1998 #define HW_ATL_TPB_TX_TC_MODE_MSK 0x00000100 1999 /* inverted bitmask for bitfield tx_tc_mode */ 2000 #define HW_ATL_TPB_TX_TC_MODE_MSKN 0xFFFFFEFF 2001 /* lower bit position of bitfield tx_tc_mode */ 2002 #define HW_ATL_TPB_TX_TC_MODE_SHIFT 8 2003 /* width of bitfield tx_tc_mode */ 2004 #define HW_ATL_TPB_TX_TC_MODE_WIDTH 1 2005 /* default value of bitfield tx_tc_mode */ 2006 #define HW_ATL_TPB_TX_TC_MODE_DEFAULT 0x0 2007 2008 /* tx tx{b}_hi_thresh[c:0] bitfield definitions 2009 * preprocessor definitions for the bitfield "tx{b}_hi_thresh[c:0]". 2010 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 2011 * port="pif_tpb_tx0_hi_thresh_i[12:0]" 2012 */ 2013 2014 /* register address for bitfield tx{b}_hi_thresh[c:0] */ 2015 #define HW_ATL_TPB_TXBHI_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) 2016 /* bitmask for bitfield tx{b}_hi_thresh[c:0] */ 2017 #define HW_ATL_TPB_TXBHI_THRESH_MSK 0x1fff0000 2018 /* inverted bitmask for bitfield tx{b}_hi_thresh[c:0] */ 2019 #define HW_ATL_TPB_TXBHI_THRESH_MSKN 0xe000ffff 2020 /* lower bit position of bitfield tx{b}_hi_thresh[c:0] */ 2021 #define HW_ATL_TPB_TXBHI_THRESH_SHIFT 16 2022 /* width of bitfield tx{b}_hi_thresh[c:0] */ 2023 #define HW_ATL_TPB_TXBHI_THRESH_WIDTH 13 2024 /* default value of bitfield tx{b}_hi_thresh[c:0] */ 2025 #define HW_ATL_TPB_TXBHI_THRESH_DEFAULT 0x0 2026 2027 /* tx tx{b}_lo_thresh[c:0] bitfield definitions 2028 * preprocessor definitions for the bitfield "tx{b}_lo_thresh[c:0]". 2029 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 2030 * port="pif_tpb_tx0_lo_thresh_i[12:0]" 2031 */ 2032 2033 /* register address for bitfield tx{b}_lo_thresh[c:0] */ 2034 #define HW_ATL_TPB_TXBLO_THRESH_ADR(buffer) (0x00007914 + (buffer) * 0x10) 2035 /* bitmask for bitfield tx{b}_lo_thresh[c:0] */ 2036 #define HW_ATL_TPB_TXBLO_THRESH_MSK 0x00001fff 2037 /* inverted bitmask for bitfield tx{b}_lo_thresh[c:0] */ 2038 #define HW_ATL_TPB_TXBLO_THRESH_MSKN 0xffffe000 2039 /* lower bit position of bitfield tx{b}_lo_thresh[c:0] */ 2040 #define HW_ATL_TPB_TXBLO_THRESH_SHIFT 0 2041 /* width of bitfield tx{b}_lo_thresh[c:0] */ 2042 #define HW_ATL_TPB_TXBLO_THRESH_WIDTH 13 2043 /* default value of bitfield tx{b}_lo_thresh[c:0] */ 2044 #define HW_ATL_TPB_TXBLO_THRESH_DEFAULT 0x0 2045 2046 /* tx dma_sys_loopback bitfield definitions 2047 * preprocessor definitions for the bitfield "dma_sys_loopback". 2048 * port="pif_tpb_dma_sys_lbk_i" 2049 */ 2050 2051 /* register address for bitfield dma_sys_loopback */ 2052 #define HW_ATL_TPB_DMA_SYS_LBK_ADR 0x00007000 2053 /* bitmask for bitfield dma_sys_loopback */ 2054 #define HW_ATL_TPB_DMA_SYS_LBK_MSK 0x00000040 2055 /* inverted bitmask for bitfield dma_sys_loopback */ 2056 #define HW_ATL_TPB_DMA_SYS_LBK_MSKN 0xffffffbf 2057 /* lower bit position of bitfield dma_sys_loopback */ 2058 #define HW_ATL_TPB_DMA_SYS_LBK_SHIFT 6 2059 /* width of bitfield dma_sys_loopback */ 2060 #define HW_ATL_TPB_DMA_SYS_LBK_WIDTH 1 2061 /* default value of bitfield dma_sys_loopback */ 2062 #define HW_ATL_TPB_DMA_SYS_LBK_DEFAULT 0x0 2063 2064 /* tx tx{b}_buf_size[7:0] bitfield definitions 2065 * preprocessor definitions for the bitfield "tx{b}_buf_size[7:0]". 2066 * parameter: buffer {b} | stride size 0x10 | range [0, 7] 2067 * port="pif_tpb_tx0_buf_size_i[7:0]" 2068 */ 2069 2070 /* register address for bitfield tx{b}_buf_size[7:0] */ 2071 #define HW_ATL_TPB_TXBBUF_SIZE_ADR(buffer) (0x00007910 + (buffer) * 0x10) 2072 /* bitmask for bitfield tx{b}_buf_size[7:0] */ 2073 #define HW_ATL_TPB_TXBBUF_SIZE_MSK 0x000000ff 2074 /* inverted bitmask for bitfield tx{b}_buf_size[7:0] */ 2075 #define HW_ATL_TPB_TXBBUF_SIZE_MSKN 0xffffff00 2076 /* lower bit position of bitfield tx{b}_buf_size[7:0] */ 2077 #define HW_ATL_TPB_TXBBUF_SIZE_SHIFT 0 2078 /* width of bitfield tx{b}_buf_size[7:0] */ 2079 #define HW_ATL_TPB_TXBBUF_SIZE_WIDTH 8 2080 /* default value of bitfield tx{b}_buf_size[7:0] */ 2081 #define HW_ATL_TPB_TXBBUF_SIZE_DEFAULT 0x0 2082 2083 /* tx tx_scp_ins_en bitfield definitions 2084 * preprocessor definitions for the bitfield "tx_scp_ins_en". 2085 * port="pif_tpb_scp_ins_en_i" 2086 */ 2087 2088 /* register address for bitfield tx_scp_ins_en */ 2089 #define HW_ATL_TPB_TX_SCP_INS_EN_ADR 0x00007900 2090 /* bitmask for bitfield tx_scp_ins_en */ 2091 #define HW_ATL_TPB_TX_SCP_INS_EN_MSK 0x00000004 2092 /* inverted bitmask for bitfield tx_scp_ins_en */ 2093 #define HW_ATL_TPB_TX_SCP_INS_EN_MSKN 0xfffffffb 2094 /* lower bit position of bitfield tx_scp_ins_en */ 2095 #define HW_ATL_TPB_TX_SCP_INS_EN_SHIFT 2 2096 /* width of bitfield tx_scp_ins_en */ 2097 #define HW_ATL_TPB_TX_SCP_INS_EN_WIDTH 1 2098 /* default value of bitfield tx_scp_ins_en */ 2099 #define HW_ATL_TPB_TX_SCP_INS_EN_DEFAULT 0x0 2100 2101 /* tx ipv4_chk_en bitfield definitions 2102 * preprocessor definitions for the bitfield "ipv4_chk_en". 2103 * port="pif_tpo_ipv4_chk_en_i" 2104 */ 2105 2106 /* register address for bitfield ipv4_chk_en */ 2107 #define HW_ATL_TPO_IPV4CHK_EN_ADR 0x00007800 2108 /* bitmask for bitfield ipv4_chk_en */ 2109 #define HW_ATL_TPO_IPV4CHK_EN_MSK 0x00000002 2110 /* inverted bitmask for bitfield ipv4_chk_en */ 2111 #define HW_ATL_TPO_IPV4CHK_EN_MSKN 0xfffffffd 2112 /* lower bit position of bitfield ipv4_chk_en */ 2113 #define HW_ATL_TPO_IPV4CHK_EN_SHIFT 1 2114 /* width of bitfield ipv4_chk_en */ 2115 #define HW_ATL_TPO_IPV4CHK_EN_WIDTH 1 2116 /* default value of bitfield ipv4_chk_en */ 2117 #define HW_ATL_TPO_IPV4CHK_EN_DEFAULT 0x0 2118 2119 /* tx l4_chk_en bitfield definitions 2120 * preprocessor definitions for the bitfield "l4_chk_en". 2121 * port="pif_tpo_l4_chk_en_i" 2122 */ 2123 2124 /* register address for bitfield l4_chk_en */ 2125 #define HW_ATL_TPOL4CHK_EN_ADR 0x00007800 2126 /* bitmask for bitfield l4_chk_en */ 2127 #define HW_ATL_TPOL4CHK_EN_MSK 0x00000001 2128 /* inverted bitmask for bitfield l4_chk_en */ 2129 #define HW_ATL_TPOL4CHK_EN_MSKN 0xfffffffe 2130 /* lower bit position of bitfield l4_chk_en */ 2131 #define HW_ATL_TPOL4CHK_EN_SHIFT 0 2132 /* width of bitfield l4_chk_en */ 2133 #define HW_ATL_TPOL4CHK_EN_WIDTH 1 2134 /* default value of bitfield l4_chk_en */ 2135 #define HW_ATL_TPOL4CHK_EN_DEFAULT 0x0 2136 2137 /* tx pkt_sys_loopback bitfield definitions 2138 * preprocessor definitions for the bitfield "pkt_sys_loopback". 2139 * port="pif_tpo_pkt_sys_lbk_i" 2140 */ 2141 2142 /* register address for bitfield pkt_sys_loopback */ 2143 #define HW_ATL_TPO_PKT_SYS_LBK_ADR 0x00007000 2144 /* bitmask for bitfield pkt_sys_loopback */ 2145 #define HW_ATL_TPO_PKT_SYS_LBK_MSK 0x00000080 2146 /* inverted bitmask for bitfield pkt_sys_loopback */ 2147 #define HW_ATL_TPO_PKT_SYS_LBK_MSKN 0xffffff7f 2148 /* lower bit position of bitfield pkt_sys_loopback */ 2149 #define HW_ATL_TPO_PKT_SYS_LBK_SHIFT 7 2150 /* width of bitfield pkt_sys_loopback */ 2151 #define HW_ATL_TPO_PKT_SYS_LBK_WIDTH 1 2152 /* default value of bitfield pkt_sys_loopback */ 2153 #define HW_ATL_TPO_PKT_SYS_LBK_DEFAULT 0x0 2154 2155 /* tx data_tc_arb_mode bitfield definitions 2156 * preprocessor definitions for the bitfield "data_tc_arb_mode". 2157 * port="pif_tps_data_tc_arb_mode_i" 2158 */ 2159 2160 /* register address for bitfield data_tc_arb_mode */ 2161 #define HW_ATL_TPS_DATA_TC_ARB_MODE_ADR 0x00007100 2162 /* bitmask for bitfield data_tc_arb_mode */ 2163 #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSK 0x00000001 2164 /* inverted bitmask for bitfield data_tc_arb_mode */ 2165 #define HW_ATL_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffe 2166 /* lower bit position of bitfield data_tc_arb_mode */ 2167 #define HW_ATL_TPS_DATA_TC_ARB_MODE_SHIFT 0 2168 /* width of bitfield data_tc_arb_mode */ 2169 #define HW_ATL_TPS_DATA_TC_ARB_MODE_WIDTH 1 2170 /* default value of bitfield data_tc_arb_mode */ 2171 #define HW_ATL_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0 2172 2173 /* tx desc_rate_ta_rst bitfield definitions 2174 * preprocessor definitions for the bitfield "desc_rate_ta_rst". 2175 * port="pif_tps_desc_rate_ta_rst_i" 2176 */ 2177 2178 /* register address for bitfield desc_rate_ta_rst */ 2179 #define HW_ATL_TPS_DESC_RATE_TA_RST_ADR 0x00007310 2180 /* bitmask for bitfield desc_rate_ta_rst */ 2181 #define HW_ATL_TPS_DESC_RATE_TA_RST_MSK 0x80000000 2182 /* inverted bitmask for bitfield desc_rate_ta_rst */ 2183 #define HW_ATL_TPS_DESC_RATE_TA_RST_MSKN 0x7fffffff 2184 /* lower bit position of bitfield desc_rate_ta_rst */ 2185 #define HW_ATL_TPS_DESC_RATE_TA_RST_SHIFT 31 2186 /* width of bitfield desc_rate_ta_rst */ 2187 #define HW_ATL_TPS_DESC_RATE_TA_RST_WIDTH 1 2188 /* default value of bitfield desc_rate_ta_rst */ 2189 #define HW_ATL_TPS_DESC_RATE_TA_RST_DEFAULT 0x0 2190 2191 /* tx desc_rate_limit[a:0] bitfield definitions 2192 * preprocessor definitions for the bitfield "desc_rate_limit[a:0]". 2193 * port="pif_tps_desc_rate_lim_i[10:0]" 2194 */ 2195 2196 /* register address for bitfield desc_rate_limit[a:0] */ 2197 #define HW_ATL_TPS_DESC_RATE_LIM_ADR 0x00007310 2198 /* bitmask for bitfield desc_rate_limit[a:0] */ 2199 #define HW_ATL_TPS_DESC_RATE_LIM_MSK 0x000007ff 2200 /* inverted bitmask for bitfield desc_rate_limit[a:0] */ 2201 #define HW_ATL_TPS_DESC_RATE_LIM_MSKN 0xfffff800 2202 /* lower bit position of bitfield desc_rate_limit[a:0] */ 2203 #define HW_ATL_TPS_DESC_RATE_LIM_SHIFT 0 2204 /* width of bitfield desc_rate_limit[a:0] */ 2205 #define HW_ATL_TPS_DESC_RATE_LIM_WIDTH 11 2206 /* default value of bitfield desc_rate_limit[a:0] */ 2207 #define HW_ATL_TPS_DESC_RATE_LIM_DEFAULT 0x0 2208 2209 /* tx desc_tc_arb_mode[1:0] bitfield definitions 2210 * preprocessor definitions for the bitfield "desc_tc_arb_mode[1:0]". 2211 * port="pif_tps_desc_tc_arb_mode_i[1:0]" 2212 */ 2213 2214 /* register address for bitfield desc_tc_arb_mode[1:0] */ 2215 #define HW_ATL_TPS_DESC_TC_ARB_MODE_ADR 0x00007200 2216 /* bitmask for bitfield desc_tc_arb_mode[1:0] */ 2217 #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSK 0x00000003 2218 /* inverted bitmask for bitfield desc_tc_arb_mode[1:0] */ 2219 #define HW_ATL_TPS_DESC_TC_ARB_MODE_MSKN 0xfffffffc 2220 /* lower bit position of bitfield desc_tc_arb_mode[1:0] */ 2221 #define HW_ATL_TPS_DESC_TC_ARB_MODE_SHIFT 0 2222 /* width of bitfield desc_tc_arb_mode[1:0] */ 2223 #define HW_ATL_TPS_DESC_TC_ARB_MODE_WIDTH 2 2224 /* default value of bitfield desc_tc_arb_mode[1:0] */ 2225 #define HW_ATL_TPS_DESC_TC_ARB_MODE_DEFAULT 0x0 2226 2227 /* tx desc_tc{t}_credit_max[b:0] bitfield definitions 2228 * preprocessor definitions for the bitfield "desc_tc{t}_credit_max[b:0]". 2229 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2230 * port="pif_tps_desc_tc0_credit_max_i[11:0]" 2231 */ 2232 2233 /* register address for bitfield desc_tc{t}_credit_max[b:0] */ 2234 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_ADR(tc) (0x00007210 + (tc) * 0x4) 2235 /* bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2236 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSK 0x0fff0000 2237 /* inverted bitmask for bitfield desc_tc{t}_credit_max[b:0] */ 2238 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_MSKN 0xf000ffff 2239 /* lower bit position of bitfield desc_tc{t}_credit_max[b:0] */ 2240 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_SHIFT 16 2241 /* width of bitfield desc_tc{t}_credit_max[b:0] */ 2242 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_WIDTH 12 2243 /* default value of bitfield desc_tc{t}_credit_max[b:0] */ 2244 #define HW_ATL_TPS_DESC_TCTCREDIT_MAX_DEFAULT 0x0 2245 2246 /* tx desc_tc{t}_weight[8:0] bitfield definitions 2247 * preprocessor definitions for the bitfield "desc_tc{t}_weight[8:0]". 2248 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2249 * port="pif_tps_desc_tc0_weight_i[8:0]" 2250 */ 2251 2252 /* register address for bitfield desc_tc{t}_weight[8:0] */ 2253 #define HW_ATL_TPS_DESC_TCTWEIGHT_ADR(tc) (0x00007210 + (tc) * 0x4) 2254 /* bitmask for bitfield desc_tc{t}_weight[8:0] */ 2255 #define HW_ATL_TPS_DESC_TCTWEIGHT_MSK 0x000001ff 2256 /* inverted bitmask for bitfield desc_tc{t}_weight[8:0] */ 2257 #define HW_ATL_TPS_DESC_TCTWEIGHT_MSKN 0xfffffe00 2258 /* lower bit position of bitfield desc_tc{t}_weight[8:0] */ 2259 #define HW_ATL_TPS_DESC_TCTWEIGHT_SHIFT 0 2260 /* width of bitfield desc_tc{t}_weight[8:0] */ 2261 #define HW_ATL_TPS_DESC_TCTWEIGHT_WIDTH 9 2262 /* default value of bitfield desc_tc{t}_weight[8:0] */ 2263 #define HW_ATL_TPS_DESC_TCTWEIGHT_DEFAULT 0x0 2264 2265 /* tx desc_vm_arb_mode bitfield definitions 2266 * preprocessor definitions for the bitfield "desc_vm_arb_mode". 2267 * port="pif_tps_desc_vm_arb_mode_i" 2268 */ 2269 2270 /* register address for bitfield desc_vm_arb_mode */ 2271 #define HW_ATL_TPS_DESC_VM_ARB_MODE_ADR 0x00007300 2272 /* bitmask for bitfield desc_vm_arb_mode */ 2273 #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSK 0x00000001 2274 /* inverted bitmask for bitfield desc_vm_arb_mode */ 2275 #define HW_ATL_TPS_DESC_VM_ARB_MODE_MSKN 0xfffffffe 2276 /* lower bit position of bitfield desc_vm_arb_mode */ 2277 #define HW_ATL_TPS_DESC_VM_ARB_MODE_SHIFT 0 2278 /* width of bitfield desc_vm_arb_mode */ 2279 #define HW_ATL_TPS_DESC_VM_ARB_MODE_WIDTH 1 2280 /* default value of bitfield desc_vm_arb_mode */ 2281 #define HW_ATL_TPS_DESC_VM_ARB_MODE_DEFAULT 0x0 2282 2283 /* tx data_tc{t}_credit_max[b:0] bitfield definitions 2284 * preprocessor definitions for the bitfield "data_tc{t}_credit_max[b:0]". 2285 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2286 * port="pif_tps_data_tc0_credit_max_i[11:0]" 2287 */ 2288 2289 /* register address for bitfield data_tc{t}_credit_max[b:0] */ 2290 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4) 2291 /* bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2292 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000 2293 /* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */ 2294 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff 2295 /* lower bit position of bitfield data_tc{t}_credit_max[b:0] */ 2296 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_SHIFT 16 2297 /* width of bitfield data_tc{t}_credit_max[b:0] */ 2298 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_WIDTH 12 2299 /* default value of bitfield data_tc{t}_credit_max[b:0] */ 2300 #define HW_ATL_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0 2301 2302 /* tx data_tc{t}_weight[8:0] bitfield definitions 2303 * preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]". 2304 * parameter: tc {t} | stride size 0x4 | range [0, 7] 2305 * port="pif_tps_data_tc0_weight_i[8:0]" 2306 */ 2307 2308 /* register address for bitfield data_tc{t}_weight[8:0] */ 2309 #define HW_ATL_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4) 2310 /* bitmask for bitfield data_tc{t}_weight[8:0] */ 2311 #define HW_ATL_TPS_DATA_TCTWEIGHT_MSK 0x000001ff 2312 /* inverted bitmask for bitfield data_tc{t}_weight[8:0] */ 2313 #define HW_ATL_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00 2314 /* lower bit position of bitfield data_tc{t}_weight[8:0] */ 2315 #define HW_ATL_TPS_DATA_TCTWEIGHT_SHIFT 0 2316 /* width of bitfield data_tc{t}_weight[8:0] */ 2317 #define HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH 9 2318 /* default value of bitfield data_tc{t}_weight[8:0] */ 2319 #define HW_ATL_TPS_DATA_TCTWEIGHT_DEFAULT 0x0 2320 2321 /* tx reg_res_dsbl bitfield definitions 2322 * preprocessor definitions for the bitfield "reg_res_dsbl". 2323 * port="pif_tx_reg_res_dsbl_i" 2324 */ 2325 2326 /* register address for bitfield reg_res_dsbl */ 2327 #define HW_ATL_TX_REG_RES_DSBL_ADR 0x00007000 2328 /* bitmask for bitfield reg_res_dsbl */ 2329 #define HW_ATL_TX_REG_RES_DSBL_MSK 0x20000000 2330 /* inverted bitmask for bitfield reg_res_dsbl */ 2331 #define HW_ATL_TX_REG_RES_DSBL_MSKN 0xdfffffff 2332 /* lower bit position of bitfield reg_res_dsbl */ 2333 #define HW_ATL_TX_REG_RES_DSBL_SHIFT 29 2334 /* width of bitfield reg_res_dsbl */ 2335 #define HW_ATL_TX_REG_RES_DSBL_WIDTH 1 2336 /* default value of bitfield reg_res_dsbl */ 2337 #define HW_ATL_TX_REG_RES_DSBL_DEFAULT 0x1 2338 2339 /* mac_phy register access busy bitfield definitions 2340 * preprocessor definitions for the bitfield "register access busy". 2341 * port="msm_pif_reg_busy_o" 2342 */ 2343 2344 /* register address for bitfield register access busy */ 2345 #define HW_ATL_MSM_REG_ACCESS_BUSY_ADR 0x00004400 2346 /* bitmask for bitfield register access busy */ 2347 #define HW_ATL_MSM_REG_ACCESS_BUSY_MSK 0x00001000 2348 /* inverted bitmask for bitfield register access busy */ 2349 #define HW_ATL_MSM_REG_ACCESS_BUSY_MSKN 0xffffefff 2350 /* lower bit position of bitfield register access busy */ 2351 #define HW_ATL_MSM_REG_ACCESS_BUSY_SHIFT 12 2352 /* width of bitfield register access busy */ 2353 #define HW_ATL_MSM_REG_ACCESS_BUSY_WIDTH 1 2354 2355 /* mac_phy msm register address[7:0] bitfield definitions 2356 * preprocessor definitions for the bitfield "msm register address[7:0]". 2357 * port="pif_msm_reg_addr_i[7:0]" 2358 */ 2359 2360 /* register address for bitfield msm register address[7:0] */ 2361 #define HW_ATL_MSM_REG_ADDR_ADR 0x00004400 2362 /* bitmask for bitfield msm register address[7:0] */ 2363 #define HW_ATL_MSM_REG_ADDR_MSK 0x000000ff 2364 /* inverted bitmask for bitfield msm register address[7:0] */ 2365 #define HW_ATL_MSM_REG_ADDR_MSKN 0xffffff00 2366 /* lower bit position of bitfield msm register address[7:0] */ 2367 #define HW_ATL_MSM_REG_ADDR_SHIFT 0 2368 /* width of bitfield msm register address[7:0] */ 2369 #define HW_ATL_MSM_REG_ADDR_WIDTH 8 2370 /* default value of bitfield msm register address[7:0] */ 2371 #define HW_ATL_MSM_REG_ADDR_DEFAULT 0x0 2372 2373 /* mac_phy register read strobe bitfield definitions 2374 * preprocessor definitions for the bitfield "register read strobe". 2375 * port="pif_msm_reg_rden_i" 2376 */ 2377 2378 /* register address for bitfield register read strobe */ 2379 #define HW_ATL_MSM_REG_RD_STROBE_ADR 0x00004400 2380 /* bitmask for bitfield register read strobe */ 2381 #define HW_ATL_MSM_REG_RD_STROBE_MSK 0x00000200 2382 /* inverted bitmask for bitfield register read strobe */ 2383 #define HW_ATL_MSM_REG_RD_STROBE_MSKN 0xfffffdff 2384 /* lower bit position of bitfield register read strobe */ 2385 #define HW_ATL_MSM_REG_RD_STROBE_SHIFT 9 2386 /* width of bitfield register read strobe */ 2387 #define HW_ATL_MSM_REG_RD_STROBE_WIDTH 1 2388 /* default value of bitfield register read strobe */ 2389 #define HW_ATL_MSM_REG_RD_STROBE_DEFAULT 0x0 2390 2391 /* mac_phy msm register read data[31:0] bitfield definitions 2392 * preprocessor definitions for the bitfield "msm register read data[31:0]". 2393 * port="msm_pif_reg_rd_data_o[31:0]" 2394 */ 2395 2396 /* register address for bitfield msm register read data[31:0] */ 2397 #define HW_ATL_MSM_REG_RD_DATA_ADR 0x00004408 2398 /* bitmask for bitfield msm register read data[31:0] */ 2399 #define HW_ATL_MSM_REG_RD_DATA_MSK 0xffffffff 2400 /* inverted bitmask for bitfield msm register read data[31:0] */ 2401 #define HW_ATL_MSM_REG_RD_DATA_MSKN 0x00000000 2402 /* lower bit position of bitfield msm register read data[31:0] */ 2403 #define HW_ATL_MSM_REG_RD_DATA_SHIFT 0 2404 /* width of bitfield msm register read data[31:0] */ 2405 #define HW_ATL_MSM_REG_RD_DATA_WIDTH 32 2406 2407 /* mac_phy msm register write data[31:0] bitfield definitions 2408 * preprocessor definitions for the bitfield "msm register write data[31:0]". 2409 * port="pif_msm_reg_wr_data_i[31:0]" 2410 */ 2411 2412 /* register address for bitfield msm register write data[31:0] */ 2413 #define HW_ATL_MSM_REG_WR_DATA_ADR 0x00004404 2414 /* bitmask for bitfield msm register write data[31:0] */ 2415 #define HW_ATL_MSM_REG_WR_DATA_MSK 0xffffffff 2416 /* inverted bitmask for bitfield msm register write data[31:0] */ 2417 #define HW_ATL_MSM_REG_WR_DATA_MSKN 0x00000000 2418 /* lower bit position of bitfield msm register write data[31:0] */ 2419 #define HW_ATL_MSM_REG_WR_DATA_SHIFT 0 2420 /* width of bitfield msm register write data[31:0] */ 2421 #define HW_ATL_MSM_REG_WR_DATA_WIDTH 32 2422 /* default value of bitfield msm register write data[31:0] */ 2423 #define HW_ATL_MSM_REG_WR_DATA_DEFAULT 0x0 2424 2425 /* mac_phy register write strobe bitfield definitions 2426 * preprocessor definitions for the bitfield "register write strobe". 2427 * port="pif_msm_reg_wren_i" 2428 */ 2429 2430 /* register address for bitfield register write strobe */ 2431 #define HW_ATL_MSM_REG_WR_STROBE_ADR 0x00004400 2432 /* bitmask for bitfield register write strobe */ 2433 #define HW_ATL_MSM_REG_WR_STROBE_MSK 0x00000100 2434 /* inverted bitmask for bitfield register write strobe */ 2435 #define HW_ATL_MSM_REG_WR_STROBE_MSKN 0xfffffeff 2436 /* lower bit position of bitfield register write strobe */ 2437 #define HW_ATL_MSM_REG_WR_STROBE_SHIFT 8 2438 /* width of bitfield register write strobe */ 2439 #define HW_ATL_MSM_REG_WR_STROBE_WIDTH 1 2440 /* default value of bitfield register write strobe */ 2441 #define HW_ATL_MSM_REG_WR_STROBE_DEFAULT 0x0 2442 2443 /* mif soft reset bitfield definitions 2444 * preprocessor definitions for the bitfield "soft reset". 2445 * port="pif_glb_res_i" 2446 */ 2447 2448 /* register address for bitfield soft reset */ 2449 #define HW_ATL_GLB_SOFT_RES_ADR 0x00000000 2450 /* bitmask for bitfield soft reset */ 2451 #define HW_ATL_GLB_SOFT_RES_MSK 0x00008000 2452 /* inverted bitmask for bitfield soft reset */ 2453 #define HW_ATL_GLB_SOFT_RES_MSKN 0xffff7fff 2454 /* lower bit position of bitfield soft reset */ 2455 #define HW_ATL_GLB_SOFT_RES_SHIFT 15 2456 /* width of bitfield soft reset */ 2457 #define HW_ATL_GLB_SOFT_RES_WIDTH 1 2458 /* default value of bitfield soft reset */ 2459 #define HW_ATL_GLB_SOFT_RES_DEFAULT 0x0 2460 2461 /* mif register reset disable bitfield definitions 2462 * preprocessor definitions for the bitfield "register reset disable". 2463 * port="pif_glb_reg_res_dsbl_i" 2464 */ 2465 2466 /* register address for bitfield register reset disable */ 2467 #define HW_ATL_GLB_REG_RES_DIS_ADR 0x00000000 2468 /* bitmask for bitfield register reset disable */ 2469 #define HW_ATL_GLB_REG_RES_DIS_MSK 0x00004000 2470 /* inverted bitmask for bitfield register reset disable */ 2471 #define HW_ATL_GLB_REG_RES_DIS_MSKN 0xffffbfff 2472 /* lower bit position of bitfield register reset disable */ 2473 #define HW_ATL_GLB_REG_RES_DIS_SHIFT 14 2474 /* width of bitfield register reset disable */ 2475 #define HW_ATL_GLB_REG_RES_DIS_WIDTH 1 2476 /* default value of bitfield register reset disable */ 2477 #define HW_ATL_GLB_REG_RES_DIS_DEFAULT 0x1 2478 2479 /* tx dma debug control definitions */ 2480 #define HW_ATL_TX_DMA_DEBUG_CTL_ADR 0x00008920u 2481 2482 /* tx dma descriptor base address msw definitions */ 2483 #define HW_ATL_TX_DMA_DESC_BASE_ADDRMSW_ADR(descriptor) \ 2484 (0x00007c04u + (descriptor) * 0x40) 2485 2486 /* tx dma total request limit */ 2487 #define HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20u 2488 2489 /* tx interrupt moderation control register definitions 2490 * Preprocessor definitions for TX Interrupt Moderation Control Register 2491 * Base Address: 0x00008980 2492 * Parameter: queue {Q} | stride size 0x4 | range [0, 31] 2493 */ 2494 2495 #define HW_ATL_TX_INTR_MODERATION_CTL_ADR(queue) (0x00008980u + (queue) * 0x4) 2496 2497 /* pcie reg_res_dsbl bitfield definitions 2498 * preprocessor definitions for the bitfield "reg_res_dsbl". 2499 * port="pif_pci_reg_res_dsbl_i" 2500 */ 2501 2502 /* register address for bitfield reg_res_dsbl */ 2503 #define HW_ATL_PCI_REG_RES_DSBL_ADR 0x00001000 2504 /* bitmask for bitfield reg_res_dsbl */ 2505 #define HW_ATL_PCI_REG_RES_DSBL_MSK 0x20000000 2506 /* inverted bitmask for bitfield reg_res_dsbl */ 2507 #define HW_ATL_PCI_REG_RES_DSBL_MSKN 0xdfffffff 2508 /* lower bit position of bitfield reg_res_dsbl */ 2509 #define HW_ATL_PCI_REG_RES_DSBL_SHIFT 29 2510 /* width of bitfield reg_res_dsbl */ 2511 #define HW_ATL_PCI_REG_RES_DSBL_WIDTH 1 2512 /* default value of bitfield reg_res_dsbl */ 2513 #define HW_ATL_PCI_REG_RES_DSBL_DEFAULT 0x1 2514 2515 /* PCI core control register */ 2516 #define HW_ATL_PCI_REG_CONTROL6_ADR 0x1014u 2517 2518 /* global microprocessor scratch pad definitions */ 2519 #define HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp) \ 2520 (0x00000300u + (scratch_scp) * 0x4) 2521 2522 /* register address for bitfield uP Force Interrupt */ 2523 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_ADR 0x00000404 2524 /* bitmask for bitfield uP Force Interrupt */ 2525 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSK 0x00000002 2526 /* inverted bitmask for bitfield uP Force Interrupt */ 2527 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_MSKN 0xFFFFFFFD 2528 /* lower bit position of bitfield uP Force Interrupt */ 2529 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_SHIFT 1 2530 /* width of bitfield uP Force Interrupt */ 2531 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_WIDTH 1 2532 /* default value of bitfield uP Force Interrupt */ 2533 #define HW_ATL_MCP_UP_FORCE_INTERRUPT_DEFAULT 0x0 2534 2535 #define HW_ATL_RX_CTRL_ADDR_BEGIN_FL3L4 0x00005380 2536 #define HW_ATL_RX_SRCA_ADDR_BEGIN_FL3L4 0x000053B0 2537 #define HW_ATL_RX_DESTA_ADDR_BEGIN_FL3L4 0x000053D0 2538 2539 #define HW_ATL_RPF_L3_REG_CTRL_ADR(location) (0x00005380 + (location) * 0x4) 2540 2541 /* RX rpf_l3_sa{D}[1F:0] Bitfield Definitions 2542 * Preprocessor definitions for the bitfield "l3_sa{D}[1F:0]". 2543 * Parameter: location {D} | stride size 0x4 | range [0, 7] 2544 * PORT="pif_rpf_l3_sa0_i[31:0]" 2545 */ 2546 2547 /* Register address for bitfield pif_rpf_l3_sa0_i[31:0] */ 2548 #define HW_ATL_RPF_L3_SRCA_ADR(location) (0x000053B0 + (location) * 0x4) 2549 /* Bitmask for bitfield l3_sa0[1F:0] */ 2550 #define HW_ATL_RPF_L3_SRCA_MSK 0xFFFFFFFFu 2551 /* Inverted bitmask for bitfield l3_sa0[1F:0] */ 2552 #define HW_ATL_RPF_L3_SRCA_MSKN 0xFFFFFFFFu 2553 /* Lower bit position of bitfield l3_sa0[1F:0] */ 2554 #define HW_ATL_RPF_L3_SRCA_SHIFT 0 2555 /* Width of bitfield l3_sa0[1F:0] */ 2556 #define HW_ATL_RPF_L3_SRCA_WIDTH 32 2557 /* Default value of bitfield l3_sa0[1F:0] */ 2558 #define HW_ATL_RPF_L3_SRCA_DEFAULT 0x0 2559 2560 /* RX rpf_l3_da{D}[1F:0] Bitfield Definitions 2561 * Preprocessor definitions for the bitfield "l3_da{D}[1F:0]". 2562 * Parameter: location {D} | stride size 0x4 | range [0, 7] 2563 * PORT="pif_rpf_l3_da0_i[31:0]" 2564 */ 2565 2566 /* Register address for bitfield pif_rpf_l3_da0_i[31:0] */ 2567 #define HW_ATL_RPF_L3_DSTA_ADR(location) (0x000053B0 + (location) * 0x4) 2568 /* Bitmask for bitfield l3_da0[1F:0] */ 2569 #define HW_ATL_RPF_L3_DSTA_MSK 0xFFFFFFFFu 2570 /* Inverted bitmask for bitfield l3_da0[1F:0] */ 2571 #define HW_ATL_RPF_L3_DSTA_MSKN 0xFFFFFFFFu 2572 /* Lower bit position of bitfield l3_da0[1F:0] */ 2573 #define HW_ATL_RPF_L3_DSTA_SHIFT 0 2574 /* Width of bitfield l3_da0[1F:0] */ 2575 #define HW_ATL_RPF_L3_DSTA_WIDTH 32 2576 /* Default value of bitfield l3_da0[1F:0] */ 2577 #define HW_ATL_RPF_L3_DSTA_DEFAULT 0x0 2578 2579 #define HW_ATL_FW_SM_RAM 0x2U 2580 2581 #endif /* HW_ATL_LLH_INTERNAL_H */ 2582
