1 /* 2 * aQuantia Corporation Network Driver 3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 */ 9 10 /* File hw_atl_a0_internal.h: Definition of Atlantic A0 chip specific 11 * constants. 12 */ 13 14 #ifndef HW_ATL_A0_INTERNAL_H 15 #define HW_ATL_A0_INTERNAL_H 16 17 #include "../aq_common.h" 18 19 #define HW_ATL_A0_MTU_JUMBO 9014U 20 21 #define HW_ATL_A0_TX_RINGS 4U 22 #define HW_ATL_A0_RX_RINGS 4U 23 24 #define HW_ATL_A0_RINGS_MAX 32U 25 #define HW_ATL_A0_TXD_SIZE 16U 26 #define HW_ATL_A0_RXD_SIZE 16U 27 28 #define HW_ATL_A0_MAC 0U 29 #define HW_ATL_A0_MAC_MIN 1U 30 #define HW_ATL_A0_MAC_MAX 33U 31 32 /* interrupts */ 33 #define HW_ATL_A0_ERR_INT 8U 34 #define HW_ATL_A0_INT_MASK 0xFFFFFFFFU 35 36 #define HW_ATL_A0_TXD_CTL2_LEN 0xFFFFC000U 37 #define HW_ATL_A0_TXD_CTL2_CTX_EN 0x00002000U 38 #define HW_ATL_A0_TXD_CTL2_CTX_IDX 0x00001000U 39 40 #define HW_ATL_A0_TXD_CTL_DESC_TYPE_TXD 0x00000001U 41 #define HW_ATL_A0_TXD_CTL_DESC_TYPE_TXC 0x00000002U 42 #define HW_ATL_A0_TXD_CTL_BLEN 0x000FFFF0U 43 #define HW_ATL_A0_TXD_CTL_DD 0x00100000U 44 #define HW_ATL_A0_TXD_CTL_EOP 0x00200000U 45 46 #define HW_ATL_A0_TXD_CTL_CMD_X 0x3FC00000U 47 48 #define HW_ATL_A0_TXD_CTL_CMD_VLAN BIT(22) 49 #define HW_ATL_A0_TXD_CTL_CMD_FCS BIT(23) 50 #define HW_ATL_A0_TXD_CTL_CMD_IPCSO BIT(24) 51 #define HW_ATL_A0_TXD_CTL_CMD_TUCSO BIT(25) 52 #define HW_ATL_A0_TXD_CTL_CMD_LSO BIT(26) 53 #define HW_ATL_A0_TXD_CTL_CMD_WB BIT(27) 54 #define HW_ATL_A0_TXD_CTL_CMD_VXLAN BIT(28) 55 56 #define HW_ATL_A0_TXD_CTL_CMD_IPV6 BIT(21) 57 #define HW_ATL_A0_TXD_CTL_CMD_TCP BIT(22) 58 59 #define HW_ATL_A0_MPI_CONTROL_ADR 0x0368U 60 #define HW_ATL_A0_MPI_STATE_ADR 0x036CU 61 62 #define HW_ATL_A0_MPI_SPEED_MSK 0xFFFFU 63 #define HW_ATL_A0_MPI_SPEED_SHIFT 16U 64 65 #define HW_ATL_A0_RATE_10G BIT(0) 66 #define HW_ATL_A0_RATE_5G BIT(1) 67 #define HW_ATL_A0_RATE_2G5 BIT(3) 68 #define HW_ATL_A0_RATE_1G BIT(4) 69 #define HW_ATL_A0_RATE_100M BIT(5) 70 71 #define HW_ATL_A0_TXBUF_MAX 160U 72 #define HW_ATL_A0_RXBUF_MAX 320U 73 74 #define HW_ATL_A0_RSS_REDIRECTION_MAX 64U 75 #define HW_ATL_A0_RSS_REDIRECTION_BITS 3U 76 77 #define HW_ATL_A0_TC_MAX 1U 78 #define HW_ATL_A0_RSS_MAX 8U 79 80 #define HW_ATL_A0_FW_SEMA_RAM 0x2U 81 82 #define HW_ATL_A0_RXD_DD 0x1U 83 #define HW_ATL_A0_RXD_NCEA0 0x1U 84 85 #define HW_ATL_A0_RXD_WB_STAT2_EOP 0x0002U 86 87 #define HW_ATL_A0_UCP_0X370_REG 0x370U 88 89 #define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U 90 91 #define HW_ATL_A0_MIN_RXD \ 92 (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE)) 93 #define HW_ATL_A0_MIN_TXD \ 94 (ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE)) 95 96 #define HW_ATL_A0_MAX_RXD 8184U 97 #define HW_ATL_A0_MAX_TXD 8184U 98 99 #endif /* HW_ATL_A0_INTERNAL_H */ 100
